Electronic device with ohmic contacts

Abstract

The invention relates to an electronic device with ohmic contacts. The contacts are obtained by forming one or more insulating layers in the electronic device on top of a semiconductor layer, wherein the insulating layer has a sufficient charge density to attract charge carriers to the top surface of the semiconductor layer. The ohmic contacts between the conductive layer and the semiconductor layer are achieved without the need for heavily doping the surface of the semiconductor layer.

Description

[0001] ELECTRONIC DEVICE WITH OHMIC CONTACTS

[0002] FIELD OF THE DISCLOSURE

[0003] This disclosure relates to electronic devices and more particularly to contacts in electronic devices. The present disclosure further concerns ohmic contacts in electronic devices.

[0004] BACKGROUND OF THE DISCLOSURE

[0005] Metal-semiconductor (MS) junctions are widely used in all electronics to conduct electricity in and out of a semiconducting material. High-quality MS junctions are crucial to ensure high performance in integrated circuits and electronic devices such as transistors, diodes, resistors, photodetectors and solar cells. In order to achieve high-performance devices, the resistance of MS contacts has to be low to minimize ohmic losses and to maximize current flow. This is accomplished with low-resistance ohmic contacts.

[0006] Ohmic contacts are metal-semiconductor contacts with resistance independent of the applied voltage. Ohmic contacts can be achieved if the potential barrier in the metal-semiconductor interface, called the Schottky barrier, is either zero or negative. In such case, the resistance across the contact is minimized and the current flow is maximized. Zero or negative Schottky barrier height can be achieved with correct metal and semiconductor selections. However, achieving a zero or negative Schottky barrier is often infeasible in the real world, as there are very few material combinations that allow this. Nevertheless, ohmic contacts can also be achieved by increasing the carrier concentration by heavily doping the semiconductor under the contact area. Higher carrier concentrations narrow the Schottky barrier, enabling current to tunnel through it. Heavy doping is a straight-forward process that can be done for any semiconductor substrate and has thus become the industry standard for the fabrication of ohmic MS contacts. Although low-resistivity ohmic contacts can be achieved with heavy doping, it is not problem-free. For instance, the insertion of external atoms can cause damage to the crystal lattice, thus hindering device performance. Moreover, the increased number of charge carriers increases the probability of recombination. When an electron-hole pair recombines, the charges are lost, and energy is released e.g. as a photon or transferred to a nearby charge carrier, generating excess heat. The evanescence of charge carriers results in lower current, in turn reducing the performance of the devices. Doping is also expensive and time-consuming, and its elimination would thereby facilitate the production of certain semiconductor devices.

[0007] BRIEF DESCRIPTION OF THE DISCLOSURE

[0008] An object of the present disclosure is to provide a solution to the problem described above.

[0009] The disclosed solution proposes an alternative way of achieving ohmic contacts. Examples provided in this disclosure describe ways to implement the solution. The solution is achieved by features of an electronic device.

[0010] The object of the disclosure is achieved by an electronic device and a fabrication method which are characterized by what is stated in the independent claims. The preferred embodiments of the disclosure are disclosed in the dependent claims.

[0011] The disclosure is based on the idea of forming one or more insulating layers on top of the semiconductor layer; the one or more insulating layers having a sufficient charge density to attract charge carriers in the semiconductor layer to the top surface of the semiconductor layer thus generating high carrier concentration. These carriers reach the conductive layer from the semiconductor layer enabling an ohmic contact between the conductive layer and the semiconductor layer without the need for heavily doping the surface of the semiconductor layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] In the following, the disclosure will be described in greater detail by means of preferred embodiments with reference to the accompanying drawings, in which :

[0013] Figure 1 illustrates a vertical cross-section of an ohmic contact in an electronic device in accordance with one embodiment of the invention;

[0014] Figures 2a-b illustrate a vertical cross-section of ohmic contacts in electronic devices in accordance with further embodiments of the invention;

[0015] Figure 3a illustrates a schematic representation of a semiconductor / insulating layer interface;

[0016] Figure 3b illustrates a schematic representation of carriers drifting under a conductive layer;

[0017] Figures 4a-c illustrate vertical cross-sections of ohmic contacts in electronic devices in accordance with further embodiments of the invention;

[0018] Figure 5a illustrates a vertical cross-section of two ohmic contacts in an electronic device comprising two conductive layers;

[0019] Figure 5b illustrates a schematic representation of a top view of the ohmic contacts shown in figure 5a;

[0020] Figure 6 illustrates a schematic representation of a top view of ohmic contacts in an electronic component comprising a matrix shaped conductive layer;

[0021] Figures 7a-c illustrate an example method for the fabrication of ohmic contacts in accordance with one embodiment of the disclosure;

[0022] Figures 8a-f illustrate the example method for the fabrication of ohmic contacts in accordance with another embodiment of the disclosure;

[0023] DETAILED DESCRIPTION OF THE DISCLOSURE

[0024] The disclosure describes an electronic device. The electronic device comprises a semiconductor layer having a top surface, wherein the semiconductor layer defines an xy-plane, and there is a z-direction which is perpendicular the xy- plane. The electronic device further comprises one or more insulating layers positioned on the top surface of the semiconductor layer and at least one conductive layer. The at least one conductive layer is on the top surface of the one or more insulating layers, or the at least one conductive layer is on the top surface of the semiconductor layer, adjacent to the one or more insulating layers. The at least one conductive layer defines a contact region in the xy- plane. The contact region further extends in the z-direction from the at least one conductive layer to the semiconductor layer, and there is at least one contact between the at least one conductive layer and the semiconductor layer in the contact region. The one or more insulating layers have a sufficient charge density to attract charge carriers in the semiconductor layer to the top surface of the semiconductor layer so that the at least one contact is an ohmic contact.

[0025] The sufficient charge density of the one or more insulating layers depends at least on the semiconductor layer material being used, and possibly on other parameters such as the semiconductor layer type (n-type or p-type), the conductive layer's work function, and the Schottky barrier height. In practice, the charge density may be optimized by experimentation to achieve an ohmic contact.

[0026] Any direction or plane which is parallel to the xy-plane can be called horizontal. The direction which is perpendicular to the xy-plane can be called the vertical direction. Expressions such as "top", "bottom", "above", "below", "up" and "down" refer in this disclosure to differences in the vertical z-coordinate. These expressions do not refer to the orientation of the electronic device with regard to the direction of earth's gravitational field either when the electronic device is manufactured or when it is in use.

[0027] Figure 1 illustrates a vertical cross-section of an ohmic contact in an electronic device in accordance with one embodiment of the invention. The electronic device comprises a semiconductor layer 101 having a top surface and an insulating layer 102 positioned on the top surface of the semiconductor layer

[0028] 101. The electronic device further comprises one conductive layer 103. The conductive layer 103 is in attached to the top surface of the insulating layer

[0029] 102. The conductive layer 103 defines a contact region in the xy-plane. The contact region further extends in the z-direction from the at least one conductive layer to the semiconductor layer. The contact region is illustrated by the dash lines in the figure. In this example, there is a contact 100 between the conductive layer 103 and the semiconductor layer 101 in the contact region. The insulating layer 102 has a sufficient charge density to attract charge carriers in the semiconductor layer 101 to the top surface of the semiconductor layer 101 so that the contact 100 is an ohmic contact. The ohmic contact 100 is a tunnelling ohmic contact and the current flow is enabled between the conductive layer 103 and the semiconductor layer 101 due to the low thickness of the insulating layer 102 in the contact region. Charge carriers tunnel from the semiconductor layer 101 through the insulating layer 102 directly into the conductive layer 103.

[0030] The electronic device may further comprise one or more openings in the contact region wherein the one or more openings extend in the z-direction in the one or more insulating layers and the at least one conductive layer extends in the z-direction in the one or more openings. The one or more openings may extend through the full thickness of the one or more insulating layers. Alternatively, the one or more openings may extend through a portion of the thickness of one or more insulating layers.

[0031] Figure 2a illustrates a vertical cross section of an ohmic contact 200 in an electronic device in accordance with another embodiment of the invention. The electronic device comprises a semiconductor layer 201 having a top surface and an insulating layer 202 positioned on the top surface of the semiconductor layer 201. The electronic device further comprises an opening and a conductive layer 203 in the contact region (dash lines). In this example, the opening extends in the z-direction through the full thickness of the insulating layer 202. The conductive layer 203 extends in the z-direction through the opening so that it is touches the semiconductor layer 201. In other words, the conductive layer 203 is on the top surface of the semiconductor layer 201, adjacent to the to the insulating layers 202.

[0032] Figure 2b illustrates a vertical cross section of an ohmic contact 210 in an electronic device in accordance with another embodiment of the invention. The electronic device comprises a semiconductor layer 211 and an insulating layer 212 on the top surface of the semiconductor layer 211. In this example, the electronic device further comprises an opening which extends in the z-direction through a portion of the thickness of the insulating layer 212. The electronic device further comprises a conductive layer 213 which extends in the z- direction in the opening. In this embodiment, the ohmic contact is a tunnelling ohmic contact and the current flow is enabled between the conductive layer

[0033] 213 and the semiconductor layer 211 due to the low thickness of the insulating layer 212 in the contact region.

[0034] The one or more openings may have a circular shape, a square shape, or a rectangular shape. Each of the openings may have an area in the xy-plane in the range of [1-1000] nm2, or [1-50] pm2, or [50-200] pm2. The area in the xy-plane of the one or more openings may preferably be less than 1 pm2. Multiple openings may be aligned in any way, for example, rectangular openings may be arranged parallel to each other. The distance between two neighbouring openings may be in the range of [1-1000] nm, or [5-50] pm, or [15-50] pm, or [10-25] pm. The one or more openings may be formed using etching, or lift-off. These options may apply to any embodiment in this disclosure.

[0035] The semiconductor layer may comprise silicon. For example, the semiconductor layer may be a Si wafer. The semiconductor layer may have a surface dopant density below 1019cm-3, or below 1017cm-3, or below 1015cm-3, or below 1013cm-3, or below 1011cm-3. Alternatively, the semiconductor may be Ge, GaN or SiC.

[0036] The insulating layer has a charge density, and the charge density is used to attract carriers to the surface of the semiconductor thus generating high carrier concentration (the same order of magnitude that is possible to have when using external doping of the semiconductor layer) to the semiconductor surface. An interface is thus created by depositing the insulating layer on top of the semiconductor layer. Depending on the type of the semiconductor layer, the interface may be a p-n interface, a p-p+interface or a n-n+interface. When a thin insulating layer is left between the opening and the semiconductor layer, it needs to be thin enough to allow tunnelling of the carriers from the semiconductor layer to the conductive layer. However, when the one or more openings extend through the full thickness of the insulating layer, the current flows from the semiconductor layer to the conductive layer through the one or more openings.

[0037] Figure 3a illustrates a schematic representation a semiconductor / insulating layer interface. In this example, the semiconductor layer 301 is an n-type semiconductor such as silicon. The surface charge of the insulating layer 302 repels electrons and accumulates holes towards the surface of the semiconductor layer 301, increasing the semiconductor surface carrier concentration. The separation of holes and electrons induces a junction in the semiconductor layer.

[0038] The ohmic contact 300 as shown in figure 3b comprises at least one conductive layer 303 located on the top surface of the semiconductor layer 301, adjacent to the insulating layers 302. In other words, the electronic device comprises an opening and the conductive layer 303 extends through the whole depth of the opening so that it reaches the semiconductor layer 301. The at least one conductive layer 303 may comprise a metal such as Al, Cu, Ag, Au, Pt, Pd, Mo or metal alloys. The metals may be formed by a variety of deposition methods such as sputtering, chemical vapor deposition, molecular beam epitaxy, electron beam, physical vapor evaporation, or laser metal deposition. Because the one or more insulating layers have a sufficient charge density to attract charge carriers from the bulk of the semiconductor layer to the top surface of the semiconductor layer, the contact is an ohmic contact without the need for heavily doping the semiconductor under the conductive layer 303. Thus, an ohmic contact may be obtained with a low semiconductor surface dopant density, below 1019cm-3, or below 1017cm-3, or below 1015cm-3, or below 1013cm-3, or below 1011cm-3.

[0039] The one or more insulating layers may be dielectric layers. The one or more dielectric layers may comprise a nitride material such as SiN, or AIN. Alternatively, the one or more dielectric layers may comprise an oxide material. For example, the one or more dielectric layers may comprise aluminium oxide, or silicon oxide, or hafnium oxide, or silicon oxide / aluminium oxide stack. Alternatively, the one or more dielectric layers may comprise an oxynitride material such as SiON, or AION. The one or more insulating layer may have a thickness in the range of [1-1000] nm, or [10-500] nm, or [10-100] nm, or [10-50] nm, or [1-5] nm. The one or more insulating layers may be formed by methods such as atomic layer deposition (ALD) or, thermal oxidation, sputtering, chemical vapor deposition (CVD), spin coating. These options may apply to any embodiment in this disclosure.

[0040] Figures 4a illustrates a vertical cross-section of an ohmic contact 400 in an electronic device in accordance with a further embodiment of the invention. In this example, the electronic device comprises several insulating layers 402 arranged on top of each other. The insulating layers 402 are positioned on top of the semiconductor layer 401. The electronic device further comprises a conductive layer 403. The conductive layer 403 is located on the top surface of the insulating layers 402.

[0041] Figures 4b illustrates a vertical cross-section of an ohmic contact 410 in an electronic device in accordance with another embodiment of the invention. In this example, the electronic device comprises several insulating layers 412 arranged on top of each other. The insulating layers 412 are positioned on top of the semiconductor layer 411. The electronic device further comprises an opening extending in the z-direction through the full thickness of the insulating layers 412 and a conductive layer 413 extending in the z-direction inside the opening.

[0042] Figures 4c illustrates a vertical cross-section of an ohmic contact 420 in an electronic device in accordance with another embodiment of the invention. In this example, the ohmic contact is a tunneling ohmic contact, and the electronic device comprises several insulating layers 422 arranged on top of each other. The device further comprises an opening extending in the z-direction through only a few insulating layers. The conductive layer 423 extends in the z-direction inside the opening.

[0043] The electrical component may comprise a plurality of conductive layers. The conductive layers may have different shapes such as rectangle, square, circle, matrix shape. A conductive layer may have a surface area in the xy-plane which is the same or greater than the surface area in the xy-plane of the opening in which it sits. In other words, the surface area in the xy-plane of a conductive layer may be at least in the range of [1-1000] nm2, or [1-50] m2, or [50-200] pm2. These options may apply to any embodiment in this disclosure.

[0044] Figure 5a illustrates a vertical cross-section of two ohmic contacts 500 in an electronic device comprising two conductive layers 503 which are arranged adjacent to each other. The semiconductor layer 501 may for example be a n- type Si wafer. The device further comprises two openings which extend in the z-direction through the full thickness of the insulating layer 502. The insulating layer may for example be a thin film of AI2O3. The insulating layer 502 may induce one or more regions with a high concentration of holes in the n-type Si semiconductor layer 501 leading to one or more p+-type Si regions 505 near the Si / AhOs interface. Each conductive layer 503 extends in the z-direction through an opening so that it meets the semiconductor layer 501. A portion of each conductive layer 503 also extends in the xy-plane on top of the insulating layer 502.

[0045] Figure 5b illustrates a schematic representation of a top view of the ohmic contacts shown in figure 5a. In this example, the conductive layers 503 have a rectangular shape. The conductive layers 503 are openings-free but in the figure parts of the conductive layer are highlighted in different colors to indicate the materials beneath them: the parts drawn in black are in touch with the insulating layer 502, whereas the parts drawn in light grey (5030) are the parts of the conductive layer 503 which extend in the z-direction in the openings and are in touch with the semiconductor layer 501.

[0046] Figure 6 illustrates a schematic representation of a top view of ohmic contacts in an electronic component comprising a matrix shaped conductive layer 603. In this disclosure, "matrix shaped conductive layer" refers to an openings-free square or rectangular conductive layer underneath which the one or more insulating layers comprise a matrix of openings. In this example, the insulating layer 602 comprises a plurality of small openings. In the figure, parts of the conductive layer are highlighted in different colors to indicate the materials beneath them: the parts drawn in black are in touch with the insulating layer 602, whereas the parts drawn in light grey (6030) are the parts of the conductive layer which extend in the z-direction in the openings and are in touch with the semiconductor layer. The openings may have a surface area in the xy-plane in the range of [1-1000] nm2, or [1-10] pm2. These options may apply to any embodiment in this disclosure. For example, the small openings may have a square shape (as shown in this figure) with an area in the xy-plane of 1.4 x 1.4 pm2, or 2.2 x 2.2 pm2. Alternatively, the openings may have other shapes such as a circular shape, or rectangular shape. When a conductive layer such as a metal pad is arranged on top of the insulating layer all the openings contribute to the current flow.

[0047] Figures 7a-c illustrate an example method for the fabrication of ohmic contacts in accordance with one embodiment of the disclosure. The method comprises: (1) providing a semiconductor layer having a top surface. The semiconductor layer defines an xy-plane, and there is a z-direction which is perpendicular the xy-plane, (2) forming one or more insulating layers on the top surface of the semiconductor layer, (3) forming at least one conductive layer on the top surface of the one or more insulating layers or on the top surface of the semiconductor layer, adjacent to the one or more insulating layers. The at least one conductive layer defines a contact region in the xy-plane, and the contact region further extends in the z-direction from the semiconductor layer to the at least one conductive layer so that there is at least one contact between the at least one conductive layer and the semiconductor layer in the contact region.

[0048] The one or more insulating layers have a sufficient charge density to attract charge carriers in the semiconductor layer to the top surface of the semiconductor layer so that the at least one contact is an ohmic contact.

[0049] Figure 7a illustrates the first step of the method. This step comprises providing a semiconductor layer 701.

[0050] Figure 7b illustrates another step of the method. This step comprises forming one or more insulating layers 702 on the top surface of the semiconductor layer 701.

[0051] Figure 7c illustrates a further step of the method. This step comprises forming a conductive layer 703 on the top surface of the insulating layer 702. The conductive layer 703 defines a contact region in the xy-plane. The contact region further extends in the z-direction from the semiconductor layer to the at least one conductive layer as shown by the dash line in the figure. There is a contact 700 between the conductive layer 703 and the semiconductor layer

[0052] 701 in the contact region.

[0053] The insulating layer has a sufficient charge density to attract charge carriers in the semiconductor layer to the top surface of the semiconductor layer so that the contact 700 is an ohmic contact. In this example, the insulating layer must be thin enough to allow tunnelling of the carriers from the semiconductor layer to the conductive layer. The ohmic contact 700 is then a tunnelling ohmic contact and the current flow is enabled between the conductive layer 703 and the semiconductor layer 701 due to the low thickness of the insulating layer

[0054] 702 in the contact region.

[0055] The method may further comprise forming one or more openings in the contact region so that the one or more openings extend in the z-direction in the one or more insulating layers and that the at least one conductive layer extends in the z-direction in the one or more openings before forming the at least one conductive layer.

[0056] Figures 8a-f illustrate the example method for the fabrication of ohmic contacts in accordance with another embodiment of the disclosure. Figure 8a illustrates the first step of the method. This step comprises providing a semiconductor layer 801. The semiconductor layer 801 has a top surface. In this example, the semiconductor layer 801 comprises native oxides 804 on its surface. For example, the semiconductor layer may be a Si wafer, and the oxide layer may be a SiOz native oxide.

[0057] Figure 8b illustrate another step of the method. This step comprises forming one or more insulating layers 802 on the top surface of the semiconductor layer. Because the surface of the semiconductor layer 801 comprises native oxides 804, in this example, the one or more insulating layers 802 are formed on the top surface of the native oxide layer 804.

[0058] The one or more insulating layers may be dielectric layers. The one or more dielectric layers may comprise a nitride material such as SiN, AIN. Alternatively, the one or more dielectric layers may comprise an oxide material. For example, the one or more dielectric layers may comprise aluminium oxide, or silicon oxide, or hafnium oxide, or silicon oxide / aluminium oxide stack. Alternatively, the one or more dielectric layers may comprise an oxynitride material such as SiON, or AION. The one or more insulating layer may have a thickness in the range of [1-1000] nm, or [10-500] nm, or [10-100] nm, or [10-50] nm, or [1- 5] nm. The one or more insulating layers may be formed by methods such as atomic layer deposition (ALD) or, thermal oxidation, sputtering, chemical vapor deposition (CVD), spin coating. These options may apply to any embodiment in this disclosure.

[0059] The one or more insulating layers 802 may induce one or more regions with a high concentration of carriers near the surface of the semiconductor layer 801. In other words, the semiconductor type near the semiconductor / insulating layer interface may be changed by the one or more insulating layers 802. For example, an insulating layer 802 comprising an oxide material such as AI2O3 may induce one or more regions with a high concentration of holes in a n-type Si semiconductor layer 801 leading to one or more p+-type Si regions 805 near the Si / AhOs interface.

[0060] Figure 8c illustrate a further step of the method. This step comprises forming one or more openings 816 by patterning the one or more insulating layers 812 so that the one or more openings 816 extend in the z-direction in the one or more insulating layers 812. The opening may be formed by several methods such as chemical etching, or lift-off. These options may apply to any embodiment in this disclosure. Induced p+-type Si regions 815 remain only in areas where AI2O3 portions are maintained

[0061] The method may further comprise the step of patterning the native oxide layer 824 so that the one or more openings 826 extend in the z-direction through the one or more insulating layer 812 and the native oxide layer 824 as illustrated in figure 8d.

[0062] Figure 8e illustrates the step of forming at least one conductive layer 833 on the top surface of the semiconductor layer 801 adjacent to the one or more insulating layers 812, so that the at least one conductive layer 833 extends in the z-direction in the one or more openings 826. In this example, the conductive layer 833 extends in the z-direction through the full depth of the openings 826 so that it is in direct contact with semiconductor layer 801. At this stage, the conductive layer 833 further extends in the xy-plane so that it covers the one or more insulating layers 812.

[0063] Figure 8e illustrates a further step of the method. This step comprises forming a plurality of conductive layers 843 by patterning the at least one conductive layer 833 in the z-direction so that portions of insulating layer 812 are exposed between the conductive layers 843.

[0064] The method may further comprise the step of etching the top surface of the semiconductor layer 801 before forming the one or more insulating layers 802. This etching step removes native oxides 804 from the surface of the semiconductor layer 801.

Claims

CLAIMS1. An electronic device comprising :- a semiconductor layer having a top surface, wherein the semiconductor layer defines an xy-plane, and there is a z-direction which is perpendicular the xy-plane,- one or more insulating layers positioned on the top surface of the semiconductor layer,- at least one conductive layer, wherein the at least one conductive layer is on the top surface of the one or more insulating layers, or the at least one conductive layer is on the top surface of the semiconductor layer, adjacent to the one or more insulating layers, and wherein the at least one conductive layer defines a contact region in the xy-plane, and wherein the contact region further extends in the z-direction from the at least one conductive layer to the semiconductor layer, and wherein there is at least one contact between the at least one conductive layer and the semiconductor layer in the contact region, characterized in that the one or more insulating layers have a sufficient charge density to attract charge carriers in the semiconductor layer to the top surface of the semiconductor layer so that the at least one contact is an ohmic contact.

2. An electronic device according to claim 1, wherein the electronic device further comprises one or more openings in the contact region, wherein the one or more openings extend in the z-direction in the one or more insulating layers, and wherein the at least one conductive layer extends in the z-direction in the one or more openings.

3. An electronic device according to any of claims 1-2, wherein the one or more insulating layers are dielectric layers.

4. An electronic device according to claim 3, wherein the one or more dielectric layers comprise a nitride material.

5. An electronic device according to claim 3, wherein the one or more dielectric layers comprise an oxynitride material.

6. An electronic device according to claim 3, wherein the one or more dielectric layers comprise an oxide material.

7. An electronic device according to claim 6, wherein the one or more dielectric layers comprise aluminium oxide.

8. An electronic device according to any of claims 1-7 wherein each of the one or more openings have an area in the xy-plane in the range of [1- 1000] nm2, or [1-50] pm2, or [50-200] pm2.

9. An electronic device according to claim 8, wherein the area in the xy- plane of the one or more openings is preferably less than 1 pm2.

10. An electronic device according to any of the previous claims, wherein the semiconductor layer comprises silicon.

11. An electronic device according to claim 10, wherein the semiconductor layer has a surface dopant density below 1019cm-3, or below 1017cm-3, or below 1015cm-3, or below 1013cm-3, or below 1011cm-3.

12. A method for fabricating an ohmic contact, wherein the method comprises:- providing a semiconductor layer having a top surface, wherein the semiconductor layer defines an xy-plane, and there is a z-direction which is perpendicular the xy-plane,- forming one or more insulating layers on the top surface of the semiconductor layer, forming at least one conductive layer on the top surface of the one or more insulating layers or on the top surface of the semiconductorlayer, adjacent to the one or more insulating layers, wherein the at least one conductive layer defines a contact region in the xy-plane, and the contact region further extends in the z-direction from the semiconductor layer to the at least one conductive layer so that there is at least one contact between the at least one conductive layer and the semiconductor layer in the contact region, characterized in that the one or more insulating layers have a sufficient charge density to attract charge carriers in the semiconductor layer to the top surface of the semiconductor layer so that the at least one contact is an ohmic contact.

13. A method according to claim 12, wherein the method further comprises forming one or more openings in the contact region so that the one or more openings extend in the z-direction in the one or more insulating layers and that the at least one conductive layer extends in the z-direction in the one or more openings, before forming at least one conductive layer.

14. A method according to any of claims 12-13, wherein the method further comprises etching the top surface of the semiconductor layer before forming the one or more insulating layers.

15. A method according to any of claims 12-14, wherein the one or more insulating layers are dielectric layers.

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