Optical semiconductor device

Abstract

The purpose of the present disclosure is to provide an optical semiconductor device that can reduce the capacitance of a pad electrode. This optical semiconductor device comprises a semiconductor substrate, an optical semiconductor element that is formed on the semiconductor substrate, and a pad electrode that is formed on the optical semiconductor element and is electrically connected to a top surface electrode of the optical semiconductor element. The pad electrode has a first electrode that is formed on the optical semiconductor element with an insulating film therebetween and a second electrode that is formed on the first electrode. A plurality of holes or a groove that is mesh-shaped as seen from above penetrate / s the insulating film from the surface of the first electrode toward the back surface of the semiconductor substrate.

Description

Optical semiconductor device

[0001] The present disclosure relates to optical semiconductor devices.

[0002] An Electro Absorption Modulated Laser (EML) is a device that integrates a semiconductor laser and an optical modulator, which absorbs part of the incident light when an electric field is applied, on the same semiconductor substrate. Compared to direct modulation methods that directly modulate the light intensity, EMLs have less signal waveform degradation and are therefore capable of high-speed, long-distance optical fiber transmission.

[0003] As data traffic expands, EML is required to operate at even higher speeds. Since the upper limit of modulation speed is inversely proportional to the capacitance of the optical modulator, it is desirable for the capacitance of the optical modulator to be extremely small. Therefore, it is desirable for the area of ​​the pad electrode that inputs the modulation signal to the optical modulator to be small.

[0004] On the other hand, in the characteristic inspection of the EML using a probe contact, and in the wire bonding for mounting the EML chip on an optical transmission device such as a transceiver, it is desirable that the area of ​​the pad electrode be large from the viewpoint of workability.

[0005] In view of these circumstances, Patent Document 1 discloses a technique for reducing the capacitance of a pad electrode by providing a plurality of mesh holes in the pad electrode, which makes it possible to reduce the effective area of ​​the pad electrode while ensuring a contact area.

[0006] JP 2012-23065 A

[0007] However, in the above-mentioned method, only the pad electrode is made to have a mesh shape, and the insulating film and semiconductor layer formed below the pad electrode are not made to have a mesh shape, which increases the capacitance of the pad electrode.

[0008] In order to solve the above-mentioned problems, an object of the present disclosure is to provide an optical semiconductor device that can reduce the electrostatic capacitance of a pad electrode.

[0009] A first aspect of the present disclosure is preferably an optical semiconductor device comprising: a semiconductor substrate; an optical semiconductor element formed on the semiconductor substrate; and a pad electrode formed on the optical semiconductor element and electrically connected to an upper surface electrode of the optical semiconductor element, wherein the pad electrode has a first electrode formed on the optical semiconductor element via an insulating film and a second electrode formed on the first electrode, and a mesh-shaped groove or a plurality of holes is provided in a top view that penetrates the insulating film from the front surface of the first electrode toward the back surface of the semiconductor substrate.

[0010] A second aspect is an optical semiconductor device comprising: a semiconductor substrate; an optical semiconductor element formed on the semiconductor substrate; and a pad electrode formed on the optical semiconductor element via an insulating film and electrically connected to an upper surface electrode of the optical semiconductor element, wherein a mesh-shaped groove or a plurality of holes is provided in a top view, penetrating the insulating film from the surface of the insulating film formed below the pad electrode toward the back surface of the semiconductor substrate.

[0011] According to the present disclosure, it is possible to reduce the capacitance of the pad electrode by providing a region occupied by air with a low dielectric constant below the pad electrode.

[0012] 1 is a top view of an optical semiconductor device according to a first embodiment of the present disclosure; FIG. 2 is a cross-sectional view taken along line A-A of FIG. 1 , showing a cross-section of a mesa stripe; FIG. 3 is a cross-sectional view taken along line B-B of FIG. 1 , showing a cross-section of a semiconductor laser; FIG. 4 is a cross-sectional view taken along line C-C of FIG. 1 , showing a cross-section of an optical modulator; FIG. 5 is a schematic diagram for calculating the capacitance of a pad electrode according to the first embodiment of the present disclosure; FIG. 6 is a schematic diagram for calculating the capacitance of a pad electrode in a general prior art; FIG. 7 is a schematic diagram for calculating the capacitance of a pad electrode in Patent Document 1; FIG. 8 is a cross-sectional view of an optical modulator according to a second embodiment of the present disclosure; FIG. 9 is a cross-sectional view of an optical modulator according to a third embodiment of the present disclosure; FIG. 10 is a schematic diagram for calculating the capacitance of a pad electrode according to the third embodiment of the present disclosure; FIG. 11 is a top view of an optical semiconductor device according to a fourth embodiment of the present disclosure; FIG. 12 is a cross-sectional view of an optical modulator according to a fourth embodiment of the present disclosure; FIG. 13 is a schematic diagram for calculating the capacitance of a pad electrode according to the fourth embodiment of the present disclosure; FIG. 14 is a cross-sectional view of an optical modulator according to a fifth embodiment of the present disclosure; FIG. 15 is a schematic diagram for calculating the capacitance of a pad electrode according to the fifth embodiment of the present disclosure; 17 is a top view of the optical semiconductor device 1 according to a modified example of the first embodiment of the present disclosure, and is a cross-sectional view taken along line DD of FIG.

[0013] Embodiments of the present disclosure will be described with reference to the drawings. The same or corresponding components will be designated by the same reference numerals, and repeated description may be omitted.

[0014] 1 is a top view of an optical semiconductor device 1 according to a first embodiment of the present disclosure. In this disclosure, the optical axis direction of the laser light emitted by the semiconductor laser 2 is defined as the z-direction. The thickness direction of the stacked semiconductor layers is defined as the y-direction. Furthermore, the direction perpendicular to the z-direction and the y-direction is defined as the x-direction.

[0015] In the optical semiconductor device 1, a semiconductor laser 2 and an optical modulator 4 are integrated on an InP substrate 9 (not shown).

[0016] The semiconductor laser 2 is, for example, a distributed feedback laser. The wavelength band of the laser light is not limited, but the 1.3 μm band and the 1.55 μm band are used as long wavelength bands in optical communications. An anode electrode 5 is formed on the surface of the semiconductor laser 2.

[0017] The optical modulator 4 is an electro-absorption modulator. An anode electrode 6 is formed on the upper surface of the optical modulator 4. The anode electrode 6 is electrically connected to a pad electrode 7 via a wire bonding metal 28 (not shown). When an electric field or current is input from the pad electrode 7 to the anode electrode 6, the optical modulator 4 absorbs and modulates the laser light emitted from the semiconductor laser 2.

[0018] The semiconductor laser 2 and the optical modulator 4 are separated by a separation section 3 .

[0019] FIG. 2 is a cross-sectional view taken along line A-A in FIG. 1, showing a cross section of the mesa stripe 8. As shown in FIG.

[0020] The mesa stripe 8 is formed across the semiconductor laser 2, the separator 3, and the optical modulator 4. The mesa stripe 8 has a waveguide that propagates light generated in the semiconductor laser 2 to the optical modulator 4. The mesa stripe 8 in the semiconductor laser 2 region has an n-type guide layer 10, an i-type active layer 11, a diffraction grating 13, a p-type guide layer 14, an InP p-type cladding layer 15, and a p-type contact layer 16, which are stacked in this order on an InP substrate 9. The n-type guide layer 10, the i-type active layer 11, the diffraction grating 13, and the p-type guide layer 14 are made of III-V group mixed crystal semiconductors such as InAlGaAs and InGaAsP. The p-type contact layer 16 is made of InGaAs or the like. The i-type active layer 11 has a multiple quantum well (MQW) structure.

[0021] An insulating film 17 and an anode electrode 5 are formed on the p-type contact layer 16 in the semiconductor laser 2 region. An opening is provided in the insulating film 17, and the anode electrode 5 is electrically connected to the p-type contact layer 16 through the opening. The anode electrode 5 includes a first anode electrode 18 connected to the p-type contact layer 16, and a second anode electrode 19 formed on the first anode electrode 18. The first anode electrode 18 not only improves adhesion to the p-type contact layer 16, but also serves as a barrier metal that suppresses diffusion of the metal of the second anode electrode 19 into the p-type contact layer 16. The first anode electrode 18 and the second anode electrode 19 are made of Ti, Au, or the like.

[0022] The mesa stripe 8 in the optical modulator 4 region includes an n-type guide layer 10, an i-type light absorbing layer 12, a p-type guide layer 14, a p-type cladding layer 15, and a p-type contact layer 16, which are stacked in this order on an InP substrate 9. The i-type light absorbing layer 12 has an MQW structure using a III-V group mixed crystal semiconductor such as InAlGaAs or InGaAsP.

[0023] An insulating film 17 and an anode electrode 6 are formed on the p-type contact layer 16 in the optical modulator 4 region. An opening is provided in the insulating film 17, and the anode electrode 6 is electrically connected to the p-type contact layer 16 through the opening. The anode electrode 6 includes an anode first electrode 18 and an anode second electrode 19.

[0024] A cathode electrode 20 is provided on the entire or part of the back surface of the InP substrate 9. The cathode electrode 20 includes a first cathode electrode 21 and a second cathode electrode 22. The first cathode electrode 21 not only improves adhesion to the InP substrate 9, but also serves as a barrier metal that suppresses diffusion of the metal of the second cathode electrode 22 into the InP substrate 9. The first cathode electrode 21 and the second cathode electrode 22 are made of AuGe, Au, or the like.

[0025] The structure of the mesa stripe 8 in the isolation portion 3 region is the same as that of the mesa stripe 8 in the optical modulator 4 region, except that an insulating film 17 is formed on the p-type cladding layer 15. The insulating film 17 is formed between the p-type contact layer 16 in the semiconductor laser 2 region and the p-type contact layer 16 in the optical modulator 4 region. This electrically insulates the semiconductor laser 2 from the optical modulator 4.

[0026] 3 is a cross-sectional view taken along line B-B in FIG. 1, showing a cross section of the semiconductor laser 2. The ridge structure 23 of the semiconductor laser 2 is provided on an InP substrate 9. In the ridge structure 23, an n-type guide layer 10, an i-type active layer 11, a diffraction grating 13, and a p-type guide layer 14 are formed.

[0027] The semiconductor burying layer 24 buries the side surfaces of the ridge structure 23. The semiconductor burying layer 24 is made of Fe-doped semi-insulating InP or the like.

[0028] The side surfaces of the mesa stripe 8 including the ridge structure 23 and the semiconductor buried layer 24 are covered with an insulating film 17 .

[0029] 4 is a cross-sectional view taken along the line CC in FIG. 1 , showing the cross section of the optical modulator 4. A ridge structure 23 is provided on an InP substrate 9. In the ridge structure 23, an n-type guide layer 10, an i-type optical absorption layer 12, and a p-type guide layer 14 are formed. The side surfaces of the ridge structure 23 are buried with a semiconductor burying layer 24.

[0030] The anode electrode 6 on the mesa stripe 8 is extended to the surface of the p-type contact layer 16 in a portion not including the mesa stripe 8, and serves as a pad electrode 7. This is because the width of the mesa stripe 8 of the optical modulator 4 must be narrowed to reduce capacitance, and therefore the width of the anode electrode 6 formed on the mesa stripe 8 must also be narrowed. The pad electrode 7 is used to input a modulated signal to the optical modulator 4. It is also used in EML characteristic testing using a probe contact, and in wire bonding to mount the EML chip on an optical transmission device such as a transceiver. The pad electrode 7 has an area secured in consideration of the ease of these operations.

[0031] The capacitance of the optical modulator 4 is the sum of the capacitance of the mesa stripe 8 of the optical modulator 4 and the capacitance of the pad electrode 7. Generally, when the capacitance of the mesa stripe 8 is reduced by, for example, shortening the length of the mesa stripe 8, there is a trade-off with the extinction characteristics, etc., so it is important to reduce the capacitance of the pad electrode 7.

[0032] In the present disclosure, mesh-like grooves 25 are provided in a top view in the pad electrode 7 and the insulating film 17 formed below the pad electrode 7. This is based on the finding of the present disclosure that the capacitance of the pad electrode 7 can be reduced by providing a region occupied by air with a low dielectric constant in the pad electrode 7 and in the layer below the pad electrode 7.

[0033] Below, the results of calculating the capacitance of the pad electrode 7 in the present disclosure, the general prior art, and Patent Document 1 will be described using the schematic diagrams in Figures 5 to 7. In order to calculate the capacitance taking into account the groove 25, a simulation was performed taking into account the edge effect at the electrode end of the pad electrode 7. Note that the shape, dimensions, and relative dielectric constant of each component used in the calculation are examples. Furthermore, the number of pillars of the pad electrode 7 and the insulating film 17, which will be described later, is also an example and is not limited thereto.

[0034] 5 is a schematic diagram for calculating the capacitance of the pad electrode 7 according to the first embodiment of the present disclosure. In calculating the capacitance, a simplified structure as shown in FIG. 5 was considered. That is, the structure is composed of a metal 28, a pad electrode 7, an insulating film 17, an i-type light absorbing layer 12, and a cathode electrode 20. Note that the metal 28 is assumed to be the wire used in the above-mentioned wire bonding.

[0035] The thickness of each component was 1.0 μm for the metal 28, 2.5 μm for the pad electrode 7, 1.5 μm for the insulating film 17, 0.5 μm for the i-type light absorbing layer 12, and 1.0 μm for the cathode electrode 20.

[0036] The dimensions of the metal 28, i-type light absorption layer 12, and cathode electrode 20 in top view are 50 μm × 50 μm. On the other hand, the pad electrode 7 and insulating film 17 are 50 μm × 50 μm, but a groove 25 with a width of 10 μm is provided. In this case, the pad electrode 7 and insulating film 17 are configured as nine 10 μm × 10 μm pillars lined up. Note that the width here refers to the width in side view of the optical semiconductor device 1.

[0037] The ambient environment including the groove 25 is air, the relative dielectric constant of the i-type light absorbing layer 12 is 12.25, and the relative dielectric constant of the insulating film 17 is 2.28.

[0038] As a result of calculation, the capacitance of the pad electrode 7 of the present disclosure was approximately 19.9 fF.

[0039] On the other hand, Figure 6 is a schematic diagram for calculating the capacitance of the pad electrode 7 in a general prior art. In the prior art, neither the pad electrode 7 nor the insulating film 17 has a mesh shape. Therefore, except that the pad electrode 7 and the insulating film 17 do not have the groove 25, the shape and relative dielectric constant of each component are the same as those in Figure 5. As a result of the calculation, the capacitance of the pad electrode 7 was approximately 39.2 [fF]. From this result, it is clear that the capacitance of the pad electrode 7 in the prior art is larger than that in the present disclosure.

[0040] On the other hand, Figure 7 is a schematic diagram for calculating the capacitance of the pad electrode 7 in Patent Document 1. In Patent Document 1, the insulating film 17 is not mesh-shaped. Therefore, the shape and relative dielectric constant of each component are the same as those in Figure 5, except that the insulating film 17 does not have grooves 25. As a result of the calculation, the capacitance was approximately 24.2 [fF]. Because the insulating film 17 is a material with a higher dielectric constant than air, it can be said that the capacitance of the pad electrode 7 in Patent Document 1 is larger than that of the present disclosure.

[0041] 7, the lower layer of the pad electrode 7 is the insulating film 17, but even if any semiconductor layer is used, the capacitance will be larger than that of the present disclosure. This is because the relative dielectric constant of the semiconductor material is higher than that of air.

[0042] As described above, in the present disclosure, mesh-like grooves 25 are provided in a top view that penetrate from the surface of the pad electrode 7 through the insulating film 17. This allows an area occupied by air with a low dielectric constant to be provided in the insulating film 17, making it possible to reduce the capacitance of the pad electrode 7.

[0043] Next, an example of the operation of the optical semiconductor device 1 of this embodiment will be described.

[0044] First, a current is injected from the anode electrode 5 to the cathode electrode 20 of the semiconductor laser 2, causing electrons and holes to recombine and emit light. The generated light is reflected by the diffraction grating 13 and travels back and forth within the semiconductor laser 2. Stimulated emission occurs during the travel, amplifying the light intensity. When a certain threshold is reached, laser oscillation occurs, and laser light is emitted from the semiconductor laser 2 toward the optical modulator 4.

[0045] Furthermore, in the optical modulator 4, a negative voltage is applied from the anode electrode 6 to the cathode electrode 20 via the pad electrode 7. This causes the absorption spectrum of the i-type optical absorption layer 12 to change due to the quantum confined Stark effect, resulting in optical absorption. In other words, the intensity of the laser light emitted from the optical modulator 4 is modulated in accordance with the voltage value applied to the optical modulator 4. The modulated laser light is emitted to the outside of the optical semiconductor device 1 and is used as signal light in optical communications, etc.

[0046] Next, a method for manufacturing the optical semiconductor device 1 of this embodiment will be described. For example, the n-type guide layer 10 is crystal-grown on the surface of the InP substrate 9 by MOCVD (metal organic chemical vapor deposition). Next, target semiconductor layers are crystal-grown in the regions of the semiconductor laser 2, the separator 3, and the optical modulator 4 by MOCVD. Further, SiO ２ Dry etching is performed using the mask of FIG. 1 to pattern the i-type active layer 11, the i-type light absorption layer 12, the diffraction grating 13, and the p-type guide layer 14.

[0047] Furthermore, SiO ２ A mask is formed on the ridge structure 23, and dry etching is performed to pattern the ridge structure 23. Then, a semiconductor burying layer 24 is grown on the side surface of the ridge structure 23 by crystal growth. ２ After removing the mask, the p-type cladding layer 15 and the p-type contact layer 16 are successively grown by crystal growth on the surfaces of the semiconductor buried layer 24 and the ridge structure 23. Next, SiO ２ A mask is formed on the surface of the semiconductor laser 2, the separation section 3, and the optical modulator 4, and then dry etching is performed to pattern the mesa stripe 8. Next, the p-type contact layer 16 on the separation section 3 is removed by wet etching using a photoresist mask. Next, SiO 2 is deposited on the surfaces of the semiconductor laser 2, the separation section 3, and the optical modulator 4 by plasma CVD or the like. ２ The insulating film 17 is formed as follows.

[0048] Next, in the region where the anode electrodes 5 and 6 are to be formed, an opening is formed in the insulating film 17 by combining photolithography and etching using hydrofluoric acid or the like. Furthermore, by these techniques, a groove 25 is formed in the insulating film 17 below the pad electrode 7.

[0049] Thereafter, a first anode electrode 18 and a second anode electrode 19 are formed in the regions where the anode electrodes 5 and 6 are to be formed. Examples of the formation method include electron beam evaporation and plating. Unnecessary portions are lifted off together with the photoresist film. The pad electrode 7 is also formed simultaneously with the anode electrodes 5 and 6. During the lift-off of the first anode electrode 18 and the second anode electrode 19, the photoresist film in the region where the pad electrode 7 is to be formed is patterned into a mesh shape, thereby forming grooves 25 in the first anode electrode 18 and the second anode electrode 19. The rear surface of the InP substrate 9 is then polished, and a cathode electrode 20 including a first cathode electrode 21 and a second cathode electrode 22 is formed on the rear surface of the InP substrate 9. The optical semiconductor device 1 of this embodiment is manufactured through the above steps. However, the manufacturing method is not limited to this. For example, although the p-type cladding layer 15 and the p-type contact layer 16 are simultaneously formed in the regions of the semiconductor laser 2, the separator 3, and the optical modulator 4 in the above-described embodiment, they may each be formed in separate processes.

[0050] <Modifications> The materials for the n-type guide layer 10, i-type active layer 11, i-type light absorption layer 12, diffraction grating 13, and p-type guide layer 14 are not limited to III-V mixed crystal semiconductors, and other semiconductor materials may be used. Furthermore, although the i-type active layer 11 and i-type light absorption layer 12 have an MQW structure, they may have a single quantum well structure or may not have a quantum well structure. Furthermore, the type of substrate is not limited to InP.

[0051] Although FIG. 1 shows a case where the width of the mesa stripe 8 is uniform in each of the regions of the semiconductor laser 2, the separator 3, and the optical modulator 4, the width does not have to be uniform.

[0052] 2 shows a case where the structures of the mesa stripes 8 of the separator 3 and the optical modulator 4 are the same, but they do not necessarily have to be the same. Also, while Fig. 2 shows an example where the diffraction grating 13 is formed on the i-type active layer 11, the diffraction grating 13 may be formed below the i-type active layer 11. Also, the semiconductor laser 2, separator 3, and optical modulator 4 have the same structure except for the i-type active layer 11, diffraction grating 13, and i-type light absorption layer 12, but they do not necessarily have to be the same.

[0053] 3 and 4, the semiconductor laser 2 and the optical modulator 4 have a buried structure, but they may have a ridge structure or other structure. The optical modulator 4 is not limited to a high mesa structure, and may have a buried waveguide or a low mesa ridge structure.

[0054] Second Embodiment Figure 8 is a cross-section of an optical modulator 4 according to a second embodiment of the present disclosure. The cross-section shown here is the same as that shown in Figure 4 of the first embodiment. This embodiment differs from the first embodiment in that the groove 25 penetrates from the surface of the pad electrode 7 to the back surface of the n-type guide layer 10. Among the optical modulators 4, the i-type light absorption layer 12 has a particularly high relative dielectric constant, which contributes to an increase in the capacitance of the pad electrode 7. In this embodiment, a region occupied by air can also be provided in the i-type light absorption layer 12, making it possible to reduce the capacitance of the pad electrode 7 compared to the first embodiment.

[0055] 9 is a schematic diagram for calculating the capacitance of the pad electrode 7 according to the second embodiment of the present disclosure. Except for the fact that the groove 25 penetrates from the front surface of the pad electrode 7 to the rear surface of the i-type light absorbing layer 12, the shape and relative dielectric constant of each component are the same as those of FIG. 5 in the first embodiment. As a result of the calculation, the capacitance of the pad electrode 7 was approximately 19.2 fF. It is clear from this result that the capacitance of the pad electrode 7 can be made smaller than that of the first embodiment.

[0056] Next, a method for manufacturing the optical semiconductor device 1 of this embodiment will be described. Only the changes from the first embodiment will be described here. For example, when patterning the mesa stripe 8 in the first embodiment, a mesh-shaped SiO ２Then, the grooves 25 are patterned so as to reach the n-type guide layer 10 by dry etching simultaneously with the mesa stripe 8. However, the manufacturing method is not limited to this. For example, the grooves 25 and the mesa stripe 8 may be formed by dry etching in separate steps.

[0057] In this embodiment, the groove 25 is formed to penetrate from the surface of the pad electrode 7 to the back surface of the n-type guide layer 10, but the depth of the groove 25 is not limited to this. Since the deeper the groove 25 is, the smaller the capacitance of the pad electrode 7 can be, the groove 25 may penetrate, for example, from the surface of the pad electrode 7 to the back surface of the InP substrate 9.

[0058] 10 is a cross-section of an optical modulator 4 according to a third embodiment of the present disclosure. The cross-section shown here is the same as that shown in FIG. 4 of the first embodiment. In this embodiment, the width of the groove 25 is larger below the pad electrode 7 than in the pad electrode 7. This allows the proportion of air below the pad electrode 7 to be larger than in the second embodiment, while ensuring the same area for the pad electrode 7 as in the second embodiment. Therefore, the capacitance of the pad electrode 7 can be smaller than in the second embodiment.

[0059] 11 is a schematic diagram for calculating the capacitance of the pad electrode 7 according to the third embodiment of the present disclosure. Here, the width of the groove 25 is set to 10 μm in the pad electrode 7 and 15 μm in the insulating film 17 and the i-type light absorbing layer 12. In this case, the pillars of the pad electrode 7 are each 10 μm × 10 μm, and the pillars of the insulating film 17 and the i-type light absorbing layer 12 are each 5 μm × 5 μm. The shapes and relative dielectric constants of the other components are the same as those of the second embodiment. As a result of the calculation, the capacitance of the pad electrode 7 was found to be approximately 13.4 fF. This result clearly shows that the capacitance of the pad electrode 7 can be reduced compared to the second embodiment.

[0060] Next, a method for manufacturing the optical semiconductor device 1 of this embodiment will be described. Note that only the changes from the second embodiment will be described here. For example, after forming the anode first electrode 18 and the anode second electrode 19 in the area of ​​the pad electrode 7, the area other than the pad electrode 7 is covered with a photoresist film. Furthermore, wet etching is performed using a chemical such as BHF, which has different etching rates, on the first group consisting of the anode first electrode 18 and the anode second electrode 19 and the second group consisting of the insulating film 17, the p-type contact layer 16, the p-type cladding layer 15, the p-type guide layer 14, the i-type light absorption layer 12, and the n-type guide layer 10. This selectively etches only the second group.

[0061] The width of the groove 25 does not necessarily have to be increased from within the insulating film 17, but may be increased from within any of the p-type contact layer 16, the p-type cladding layer 15, the p-type guide layer 14, the i-type light absorption layer 12, and the n-type guide layer 10.

[0062] 12 is a top view of an optical semiconductor device 1 according to a fourth embodiment of the present disclosure. The optical semiconductor device 1 of this embodiment includes a shield electrode 26 electrically insulated from the pad electrode 7 within the groove 25 of the pad electrode 7. A pad electrode 27 extending from the shield electrode 26 is formed next to the pad electrode 7. The shield electrode 26 is set to the ground potential via the pad electrode 27.

[0063] 13 is a cross-sectional view of an optical modulator 4 according to a fourth embodiment of the present disclosure. The cross-section shown here is the same as that shown in FIG. 4 of the first embodiment. The shield electrode 26 includes an anode first electrode 18 connected to the p-type contact layer 16, and an anode second electrode 19 formed on the anode first electrode 18.

[0064] In the case where there is no shield electrode 26 as in the first embodiment, all of the electric lines of force emanating from the pad electrode 7 are directed toward the cathode electrode 20, resulting in an increase in capacitance. By providing the shield electrode 26 as in this embodiment, it is possible to direct some of the electric lines of force toward the shield electrode 26, thereby making it possible to reduce the capacitance compared to the first embodiment.

[0065] The capacitance reduction effect increases as the width in side view of the shield electrode 26 increases. However, it should be noted that the shield electrode 26 cannot come into contact with the pad electrode 7 and the insulating film 17 in order to ensure insulation.

[0066] 14 is a schematic diagram for calculating the capacitance of the pad electrode 7 according to the fourth embodiment of the present disclosure. Here, the width of the shield electrode 26 is set to 6 μm and the thickness to 2.5 μm. The shapes and relative dielectric constants of the other components are set to the same as those in FIG. 5 of the first embodiment. As a result of the calculation, the capacitance of the pad electrode 7 was found to be approximately 14.5 fF. It is clear from this result that the capacitance of the pad electrode 7 can be made smaller than that of the first embodiment.

[0067] Next, a method for manufacturing the optical semiconductor device 1 of this embodiment will be described. Note that only the changes from the first embodiment will be described here. For example, only the region of the shield electrode 26 is patterned with a photoresist film, and the first anode electrode 18 and the second anode electrode 19 are formed in the regions that will become the pad electrode 7 and the shield electrode 26 using electron beam evaporation, plating, or the like. By repeatedly lifting off the unnecessary portions together with the photoresist film, it is possible to simultaneously form the pad electrode 7 and the shield electrode 26 of the desired thickness.

[0068] 15 is a cross-section of an optical modulator 4 according to a fifth embodiment of the present disclosure. The cross-section shown here is the same as that shown in FIG. 4 of the first embodiment. Here, changes from the third embodiment will be explained. In this embodiment, the pad electrode 7 is uniform. A groove 25 penetrates from the surface of the insulating film 17 to the back surface of the n-type guide layer 10.

[0069] By making the pad electrode 7 uniform without providing the groove 25, the contact property of the pad electrode 7 can be improved compared to the third embodiment.

[0070] 16 is a schematic diagram for calculating the capacitance of the pad electrode 7 according to the fifth embodiment of the present disclosure. Here, the shape and relative dielectric constant of each component are the same as those of the third embodiment, except that the pad electrode 7 does not have the groove 25. As a result of the calculation, the capacitance of the pad electrode 7 is approximately 16.2 fF. Although the capacitance is larger than that of the third embodiment, the capacitance of the pad electrode 7 can be made smaller than that of the general prior art shown in FIG. 6 and Patent Document 1 shown in FIG. 7. This is the effect of providing the groove 25 that penetrates from the surface of the insulating film 17 to the underside of the i-type light absorption layer 12.

[0071] Next, a method for manufacturing the optical semiconductor device 1 of this embodiment will be described. Note that only the changes from the third embodiment will be described here. For example, before forming the anode first electrode 18 and the anode second electrode 19 in the region that will become the pad electrode 7, the portion that will become the groove 25 is covered with a photoresist film. Dry etching is then performed to form the groove 25 and expose the insulating film 17. Then, electron beam evaporation, plating, or the like is used to form the anode first electrode 18 and the anode second electrode 19 in the region of the pad electrode 7. By lifting off the unnecessary portions together with the photoresist film, a uniform pad electrode 7 can be formed on the mesh-shaped insulating film 17.

[0072] The present disclosure is not limited to the above-described embodiments, and various modifications can be made in the implementation stage without departing from the spirit and scope of the present disclosure. For example, the present disclosure is not limited to EMLs, but can also be applied to optical semiconductor devices having pad electrodes for applying an electric field or injecting a current to optical semiconductor elements such as directly modulated semiconductor lasers, Mach-Zehnder optical modulators, optical resonators, and optical phase shifters. Furthermore, the respective embodiments may be implemented in appropriate combination, in which case the combined effects can be obtained.

[0073] <Modification> Figure 17 is a top view of an optical semiconductor device 1 according to a modification of the first embodiment of the present disclosure. Here, instead of the grooves 25, a plurality of holes 30 in a mesh shape when viewed from above are formed. Even in this case, a region occupied by air with a low dielectric constant can be provided below the pad electrode 7, and the same effect as described above can be obtained. Figure 18 is a cross section taken along the line D-D in Figure 17. Here, a plurality of holes 30 are provided that penetrate the pad electrode 7 and the insulating film 17.

[0074] <Explanation of terms used in claims> In claim 1, the pad electrode 7 is referred to as the first electrode, the metal 28 is referred to as the second electrode, and the pad electrode has the first electrode and the second electrode. Also, in claims 1 and 5, the anode electrode 6 is referred to as the upper electrode.

[0075] REFERENCE SIGNS LIST 1 Optical semiconductor device, 2 Semiconductor laser, 3 Separation portion, 4 Optical modulator (optical semiconductor element), 5 Anode electrode, 6 Anode electrode (upper electrode), 7 Pad electrode, 8 Mesa stripe, 9 InP substrate (semiconductor substrate), 10 n-type guide layer, 11 i-type active layer, 12 i-type optical absorption layer, 13 Diffraction grating, 14 p-type guide layer, 15 p-type cladding layer, 16 p-type contact layer, 17 Insulating film, 18 Anode first electrode, 19 Anode second electrode, 20 Cathode electrode, 21 Cathode first electrode, 22 Cathode second electrode, 23 Ridge structure, 24 Semiconductor buried layer, 25 Groove, 26 Shield electrode, 27 Pad electrode, 28 Metal, 30 Hole

Claims

1. A semiconductor device comprising: a semiconductor substrate; an optical semiconductor element formed on the semiconductor substrate; and a pad electrode formed on the optical semiconductor element and electrically connected to the upper surface electrode of the optical semiconductor element, wherein the pad electrode has a first electrode formed on the optical semiconductor element with an insulating film interposed therebetween, and a second electrode formed on the first electrode, and the insulating film is penetrated from the surface of the first electrode toward the back surface of the semiconductor substrate, and a mesh-shaped groove or a plurality of holes are provided in a top view.

2. The optical semiconductor device according to claim 1, wherein a width of the groove or the hole in a side view is larger in the insulating film than in the pad electrode.

3. The optical semiconductor device according to claim 1 or 2, wherein a width of the groove or the hole in a side view is larger in the optical semiconductor element than in the pad electrode.

4. The optical semiconductor device according to any one of claims 1 to 3, further comprising a shield electrode formed in the groove and electrically insulated from the pad electrode.

5. A semiconductor device comprising: a semiconductor substrate; an optical semiconductor element formed on the semiconductor substrate; and a pad electrode formed on the optical semiconductor element with an insulating film interposed therebetween and electrically connected to the upper surface electrode of the optical semiconductor element, wherein the insulating film is penetrated from the surface of the insulating film formed under the pad electrode toward the back surface of the semiconductor substrate, and a mesh-shaped groove or a plurality of holes are provided in a top view.

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