Semiconductor laminate and method for manufacturing semiconductor device

Abstract

A semiconductor laminate (laminated wafer) 100 has: a growth substrate 111 as a substrate; a holding layer 114 as a first layer laminated above the growth substrate 111; a sacrificial layer 115 as a second layer laminated on the holding layer 114; an upper barrier layer 116 as a third layer laminated on the sacrificial layer 115; and a functional layer 133 laminated on the upper barrier layer 116 and serving as a semiconductor layer in contact with the upper barrier layer 116. A cladding layer 117 in the functional layer 133 that is in contact with at least the upper barrier layer 116 is composed of the same material as the sacrificial layer 115. The etching selection ratio of the sacrificial layer 115 with respect to the upper barrier layer 116 is larger than the etching selection ratio of the sacrificial layer 115 with respect to the holding layer 114.

Description

Semiconductor laminate and method for manufacturing semiconductor device

[0001] The present disclosure relates to a method for manufacturing a semiconductor stack and a semiconductor device.

[0002] A technique has been known in the past in which a semiconductor thin film is grown on a substrate via a sacrificial layer, the sacrificial layer is removed by etching, the semiconductor thin film is peeled off from the substrate, and the semiconductor thin film is transferred to another substrate (see, for example, Patent Document 1).

[0003] JP 2009-290232 A (page 10, FIG. 5)

[0004] However, in the conventional technology, the back surface of the semiconductor layer may become rough when the semiconductor layer is exposed to the etching solution, which may make it difficult to bond the semiconductor layer to the transfer substrate.

[0005] A semiconductor laminate according to the present disclosure comprises a substrate, a first layer laminated above the substrate, a second layer laminated on the first layer, a third layer laminated on the second layer, and a semiconductor layer laminated on the third layer, at least a layer in contact with the third layer being made of the same material as the second layer, and is characterized in that, when a predetermined etchant is used, the etching selectivity of the second layer to the third layer is greater than the etching selectivity of the second layer to the first layer.

[0006] A method for manufacturing a semiconductor device according to the present disclosure includes the steps of: removing a semiconductor layer structure having a first layer stacked above a substrate, a second layer stacked on the first layer, a third layer stacked on the second layer, and a semiconductor layer stacked on the third layer, the semiconductor layer being at least in contact with the third layer and made of the same material as the second layer, using a predetermined etchant; separating the semiconductor layer and the third layer from the substrate; removing the third layer; and transferring the semiconductor layer to a transfer substrate different from the substrate.

[0007] According to the present disclosure, when transferring a semiconductor layer, it is easy to separate the semiconductor layer from the substrate from which it is transferred, and further, the flatness of the lower surface of the semiconductor layer can be maintained, making it easy to bond the semiconductor layer to the transfer substrate.

[0008] 1A to 1C are diagrams schematically illustrating a stacked structure of a laminated wafer according to a first embodiment having a semiconductor laminate configuration according to the present disclosure. (A) to (C) are diagrams illustrating a predetermined region of the laminated wafer of FIG. 1 patterned into 4×4, where (A) is a plan view and (B) is a side view. (C) is a partially enlarged view of one block shown in (B). (A) to (C) are diagrams illustrating a state in which the laminated wafer of FIGS. 2A to 2C has been further patterned, where (A) is a plan view and (B) is a side view. (C) is a partially enlarged view of one block shown in (B). (A) to (C) are diagrams illustrating a state in which a protective film has been formed on each laminate, where (A) is a plan view and (B) is a side view. (C) is a partially enlarged view of one block shown in (B). 7A to 7C are diagrams showing the state in which a holding structure has been formed from the protective film formed on each laminate to the lower barrier layer, where (A) is a plan view and (B) is a side view. Also, (C) is a partially enlarged view of one block shown in (B). This is a plan view of one block of the laminate shown in FIG. 5C. (A) to (C) are diagrams for explaining the progress of etching of the sacrificial layer and the holding layer, where (A) shows the state before etching progresses, (B) and (C) show the process of etching progressing, and (D) shows the state after etching has ended. This is a partially enlarged view showing the vicinity of the end of the holding layer shown in FIG. 7C, where etching has progressed in a tapered shape. This is a diagram showing the state in which the sacrificial layer has been removed by etching in a laminated wafer on which the holding structure shown in FIG. 5 has been formed, and further the holding layer has also been removed except for the central portion. This is a diagram showing the state in which the holding structure has been further removed from the state shown in FIG. 9. This is a diagram for supplementary explanation of FIG. 10. This is a diagram showing the state in which a stamp has been attached to the semiconductor thin film shown in FIG. 10 or 11. 1A to 1C are diagrams showing the state in which the semiconductor thin film has been peeled off from the support layer by a stamp, and illustrate the process in which the upper barrier layer of the semiconductor thin film peeled off by the stamp is removed by etching, where 1A shows the state before etching, 1B shows the state while etching is in progress, and 1C shows the state after etching has been completed.20A to 20C are diagrams illustrating the process of attaching a semiconductor thin film from which the upper barrier layer has been removed to a transfer substrate and forming electrodes at predetermined positions, where (A) is a diagram illustrating the state in which the semiconductor thin film has been transferred to the transfer substrate, (B) is a diagram illustrating the state in which the protective film has been removed, and (C) is a diagram illustrating the state in which two electrodes have been formed at each predetermined location.

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[110] 21(A) to 21(C) are views showing the state after further patterning, where (A) is a plan view and (B) is a side view. Also, (C) is a partially enlarged view showing multiple blocks shown in (B). (A) to (C) are views showing a state after a protective film has been formed on each divided laminate, where (A) is a plan view and (B) is a side view. Also, (C) is a partially enlarged view showing multiple blocks shown in (B). (A) to (C) are views showing a state in which elongated holes have been provided in the protective film and part of the upper barrier layer of each groove portion shown in FIGS. 23(A) to 23(C), where (A) is a plan view and (B) is a side view. Also, (C) is a partially enlarged view showing multiple blocks shown in (B). (A) to (D) are views for explaining the progress of etching of the sacrificial layer and the retention layer, and correspond to, for example, the area surrounded by the dotted line in FIG. 24(B). (A) shows the state before etching progresses, (B) and (C) show the states as etching progresses, and (D) shows the state after etching has finished. Fig. 25(C) is a partially enlarged view showing the vicinity of the end of the retention layer where etching has progressed in a tapered shape. Fig. 25(D) shows the state in which the sacrificial layer has been removed by etching and the retention layer has also been removed except for the center portion in the stacked wafers with the elongated holes formed therein shown in Figs. 24(A) to (C), corresponding to the stage shown in Fig. 25(D).30(A) is a plan view thereof, and (B) is a side view thereof. Also, (C) is a partially enlarged view of a plurality of blocks shown in (B). It is a top view corresponding to FIG. 27(C). It is a diagram showing a state in which a stamp is attached to the semiconductor thin film shown in FIG. 27(C). It is a diagram showing a state in which the semiconductor thin film is peeled off from the holding layer by the stamp. It is a diagram showing a state in which the upper barrier layer has been removed from the semiconductor thin film held by the stamp shown in FIG. 30. It is a diagram showing a state in which the semiconductor thin film from which the upper barrier layer has been removed is attached to a transfer substrate. It is a diagram showing a state in which the protective film has been removed and an electrode has been formed.

[0009] First Embodiment Fig. 1 is a diagram schematically showing a stacked structure of a stacked wafer 100 according to a first embodiment, which has the configuration of a semiconductor stack according to the present disclosure.

[0010] In the laminated wafer 100 shown in Fig. 1, a growth substrate 111 is an InP layer on whose upper surface (main surface) an epitaxial layer is grown. A buffer layer 112, which is an InP layer, a lower barrier layer 113, which is an InGaAs layer and serves as a fourth layer, a retention layer 114, which is an InGaAsP layer and serves as a first layer, and a sacrificial layer 115, which is an InP layer, are sequentially formed by epitaxial growth on the growth substrate (InP) 111. The thickness of the retention layer (InGaAsP) 114 is thicker than the thickness of the sacrificial layer (InP) 115, preferably at least twice as thick; the reason for this will be explained later.

[0011] In this embodiment, the thickness of the retention layer (InGaAsP) 114 is 100 nm to 600 nm, and the thickness of the sacrificial layer (InP) 115 is 50 nm to 300 nm. Preferably, the thickness of the retention layer (InGaAsP) 114 is 300 nm, and the thickness of the sacrificial layer (InP) 115 is 150 nm. Because the three layers of the upper barrier layer 116, the sacrificial layer (InP) 115, and the retention layer (InGaAsP) 114 are etched by dry etching and the dry etching must be stopped midway through the lower barrier layer 113, the thickness of the lower barrier layer 113 is desirably 700 nm or more.

[0012] Furthermore, on the sacrificial layer (InP) 115, an upper barrier layer 116 as a third layer, which is an InGaAs layer, a cladding layer 117 which is an n-InP layer, a light absorption layer 118 which is an i-InGaAs layer, a cladding layer 119 which is a p-InP layer, and a contact layer 120 which is a p-InGaAs layer are formed. For example, the thickness of the upper barrier layer 116 is 100 nm to 600 nm, preferably 300 nm. Regarding the composition ratio of each InGaAs layer in this embodiment, when the In concentration is 0.53, the Ga concentration is 0.47, and the As concentration is 1.

[0013] Next, a description will be given of a method for manufacturing a semiconductor device according to this embodiment, which is carried out by preparing the above-described laminated wafer 100. Note that the laminated wafer 100 shown in each figure is assumed to be positioned so that the stacking direction is vertically upward.

[0014] 2A to 2C are diagrams showing a predetermined area patterned into 4 × 4 on the laminated wafer 100 of FIG. 1, where FIG. 2A is a plan view and FIG. 2B is a side view. Also, FIG. 3C is an enlarged view of one block (area P1 enclosed by a dotted line) shown in FIG. 2B.

[0015] As shown in FIG. 2A, in order to separate the laminated wafer 100 into 16 (4×4) stacks 130 down to the lower barrier layer (InGaAs) 113 (FIG. 2C), etching is performed along the separation regions set in a grid pattern, forming grid-shaped grooves 131a. The lower barrier layer (InGaAs) 113 is set to a thickness that ensures a margin that prevents penetration even if the upper part is removed by this etching. The thickness of the lower barrier layer (InGaAs) 113 is desirably thicker than the thicknesses of the retention layer (InGaAsP) 114, the sacrificial layer (InP) 115, and the upper barrier layer (InGaAs) 116.

[0016] 3A to 3C are diagrams showing the state in which the laminated wafer 100 of Fig. 2A to 2C has been further patterned, Fig. 3A being a plan view and Fig. 3B being a side view, and Fig. 3C being a partially enlarged view of one block (area P1 enclosed by a dotted line) shown in Fig. 3B.

[0017] As shown in Figure 3C, the four layers of each laminate 130, from the cladding layer (n-InP) 117 to the contact layer (p-InGaAs) 120, are patterned by etching to remove a predetermined step width L1 from the periphery of each layer. As a result, grooves 131b wider than grooves 131a are formed around these four layers. Hereinafter, these four layers may be referred to as functional layers 133 as semiconductor layers.

[0018] Here, the cladding layer (n-InP) 117, which is the bottom layer of the functional layer 133 and is in contact with the upper barrier layer (InGaAs) 116, is made of the same material as the sacrificial layer (InP) 115. The term "same material" as used here means that both layers are made of indium phosphide (InP), and therefore the composition ratios of these layers may be the same or different.

[0019] The relationship between the step width L1, which is the length in the first direction of the step portion 116a generated on the top surface of the upper barrier layer (InGaAs) 116, and the thickness L2, which is the thickness in the second direction of the upper barrier layer 116, is formed to satisfy the following: L1≧L2 (1) Note that, because FIG. 3 is a schematic diagram, inequality (1) is not satisfied, but in reality it is satisfied. The reason why inequality (1) is satisfied will be described later.

[0020] 4A to 4C are diagrams showing the state in which the protective film 121 has been formed on each laminate 130, with Fig. 4A being a plan view and Fig. 4B being a side view, and Fig. 4C being a partially enlarged view of one block (area P1 enclosed by a dotted line) shown in Fig. 4B.

[0021] 4A to 4C, the protective film 121 is formed so as to cover the functional layer 133, which is the four layers from the cladding layer (n-InP) 117 to the contact layer (p-InGaAs) 120 of each etched laminated body 130, and the step portion 116a of the upper barrier layer (InGaAs) 116. The protective film 121 is made of a material that is resistant to an etchant capable of removing the sacrificial layer (InP) 115 (i.e., is not removed by the etchant). Specific examples of the material for the protective film 121 include Al ２ O ３ , SiN, SiO２ The protective film 121 has resistance to the etchant so long as it is resistant to the etchant to such an extent that the functional layer 133 is not removed to an extent that it can be sufficiently protected until the sacrificial layer (InP) 115 is removed. This makes it possible to prevent the top and side surfaces of the functional layer 133, which is made up of four layers from the cladding layer (n-InP) 117 to the contact layer (p-InGaAs) 120 of each stacked body 130, from being etched when the sacrificial layer (InP) 115 is removed.

[0022] 5A to 5C are diagrams showing the state in which the holding structure 122 is formed from the protective film 121 formed on each laminate 130 to the lower barrier layer (InGaAs) 113, with Fig. 5A being a plan view and Fig. 5B being a side view. Fig. 5C is a partial enlarged view of one block (area P1 surrounded by a dotted line) shown in Fig. 5B.

[0023] 5C, a holding structure 122 is formed from a resist or the like from a protective film 121 covering the step portion 116a of the upper barrier layer (InGaAs) 116 to a groove portion 131a of the lower barrier layer (InGaAs) 113. This holding structure 122 is formed by applying a resist made of an inorganic insulating film or an organic insulating film to each layer and then removing unnecessary portions of the resist.

[0024] Fig. 6 is a plan view of one block of the laminate 130 shown in Fig. 5(C) . As shown in Fig. 6 and Fig. 5(C) , the holding structure 122 is formed in the shape of an L-shaped extended plate at the center of each of two opposing side walls of the four side walls of each laminate 130.

[0025] 7A to 7D are diagrams for explaining the progress of etching of the sacrificial layer (InP) 115 and the retention layer (InGaAsP) 114. Fig. 7A shows the state before etching begins, Figs. 7B and 7C show the process of etching, and Fig. 7D shows the state after etching has finished. Note that the growth substrate 111, the buffer layer 112, and the functional layer 133 above the upper barrier layer 116 are not shown here for simplicity.

[0026] The etchant used here is hydrochloric acid, a mixture of hydrochloric acid and phosphoric acid, or a mixture of hydrochloric acid and nitric acid. In this etching, the etching rate of the sacrificial layer (InP) 115 is faster than that of the upper barrier layer (InGaAs) 116, and the difference between the two is large, so the upper barrier layer (InGaAs) 116 is hardly etched.

[0027] Here, with regard to the etching rate of each layer, the etching rate of the sacrificial layer (InP) 115 is higher than the etching rate of the retention layer (InGaAsP) 114, and the etching rate of the sacrificial layer (InP) 115 is also higher than the etching rate of the upper barrier layer (InGaAs) 116.

[0028] With the etchant used here, the etching rate of the sacrificial layer (InP) 115 is 1000 times or more the etching rate of the upper barrier layer (InGaAs) 116 (i.e., a selectivity ratio of 1000 or more), and the etching rate of the sacrificial layer (InP) 115 is 2 times or more but less than 1000 times the etching rate of the retention layer (InGaAsP) 114 (i.e., a selectivity ratio of 2 or more but less than 1000). Here, the etching rate of the sacrificial layer (InP) 115 is preferably 2 to 4 times the etching rate of the retention layer (InGaAsP) 114 (i.e., a selectivity ratio of 2 to 4).

[0029] Furthermore, since the lower barrier layer (InGaAs) 113 is formed of the same material as the upper barrier layer (InGaAs) 116, the etching rate of the sacrificial layer (InP) 115 is similarly 1000 times or more the etching rate of the lower barrier layer (InGaAs) 113. Therefore, the sacrificial layer (InP) 115 is hardly etched while the upper retention layer (InGaAsP) 114 is being etched. This also protects the buffer layer (InP) 112 and growth substrate (InP) 111 below the lower barrier layer (InGaAs) 113 from etching.

[0030] That is, when a predetermined etchant is used, the etching selectivity of the sacrificial layer (InP) 115 to the upper barrier layer (InGaAs) 116 is greater than the etching selectivity of the sacrificial layer (InP) 115 to the retention layer (InGaAsP) 114. Also, the etching selectivity of the sacrificial layer (InP) 115 to the lower barrier layer (InGaAs) 113 is greater than the etching selectivity of the sacrificial layer (InP) 115 to the retention layer (InGaAsP) 114.

[0031] Therefore, as the etching of the sacrificial layer (InP) 115 progresses, the retention layer (InGaAsP) 114 is also etched, but because the etching of the sacrificial layer (InP) 115 progresses first, it is also etched from its upper surface. However, the retention layer (InGaAsP) 114 is not etched from its lower surface because the lower barrier layer (InGaAs) 113 is not etched. As a result, the retention layer (InGaAsP) 114 is etched in a tapered shape on both sides, as shown in Figures 7(A) to 7(C).

[0032] FIG. 8 is a partially enlarged view of the vicinity of the end (area P2 surrounded by a dotted line) of the retention layer (InGaAsP) 114 shown in FIG. 7C, where etching has progressed in a tapered shape.

[0033] The ratio of the thickness L4 of the retention layer (InGaAsP) 114 to the depth L3 of the tapered etching at the end of the retention layer (InGaAsP) 114 shown in FIG. 8, i.e., tan(θ1) of the angle θ1 at the tip, varies depending on the thickness of the sacrificial layer (InP) 115 and the patterning size.

[0034] The angle θ1 increases by adjusting x and y in the composition of the retention layer (InGaAsP) 114, In(x)Ga(1-x)As(y)P(1-y), within the ranges of 0<x<1 (2) and 0<y<1 (3) to increase the In and P concentrations (composition ratios). Specifically, 0.7≦x is desirable (to increase the In concentration), and y≦0.5 is desirable (to increase the P concentration). Within these ranges (x is 0.7 or more and y is 0.5 or less), the angle θ1 of the retention layer (InGaAsP) 114 becomes greater than 0. That is, the retention layer 114 has a triangular shape, allowing the semiconductor thin film 135 (described below) to be releasably held with a smaller area (vertex). However, in this embodiment, the In and P composition ratio of the retention layer (InGaAsP) 114 may be close to 0, and the angle θ1 may be close to 0.

[0035] In addition, the angle θ1 can be reduced by increasing the thickness of the sacrificial layer (InP) 115, but if the thickness of the retention layer (InGaAsP) 114 is less than twice the thickness of the sacrificial layer (InP) 115, there is a possibility that the retention layer (InGaAsP) 114 will not remain to the required height.

[0036] Fig. 9 is a diagram showing a state in which the sacrificial layer (InP) 115 has been removed by etching from the laminated wafer 100 on which the holding structure 122 shown in Fig. 5(A) to (C) has been formed, and furthermore, the holding layer (InGaAsP) 114 has also been removed except for the central portion. Fig. 10 is a diagram showing a state in which the holding structure 122 has been further removed from the state shown in Fig. 9, and Fig. 11 is a diagram for supplementary explanation of Fig. 10.

[0037] 9, when the etching described with reference to Figures 7A to 7D is performed on the laminated wafer 100 on which the holding structure 122 shown in Figure 5 is formed, a gap is generated between the upper barrier layer (InGaAs) 116 supported by the holding structure 122 and the lower barrier layer (InGaAs) 113. Note that the laminated structure from the upper barrier layer (InGaAs) 116 above the gap to the protective film 121 may be referred to as a semiconductor thin film 135.

[0038] Next, when the retaining structure 122 is removed by dry etching, the upper barrier layer (InGaAs) 116 and the retaining layer (InGaAsP) 114 are partially in contact with each other, as shown in Fig. 10. At this time, the lower surface of the upper barrier layer (InGaAs) 116 and the upper surface of the retaining layer (InGaAsP) 114 are bonded with a force weaker than a covalent bond and with a sufficiently small contact area.

[0039] Therefore, in the step of removing the sacrificial layer (InP) 115 by etching, the area of ​​the upper surface of the retention layer (InGaAsP) 114, which serves as a second surface in contact with the upper barrier layer (InGaAs) 116, is made smaller than the area of ​​the lower surface, which serves as a first surface in contact with the lower barrier layer (InGaAs) 113.

[0040] Furthermore, when the semiconductor thin film 135 is tilted as shown in FIG. 11, the lower surface of the upper barrier layer (InGaAs) 116 bonds to the upper surface of the retention layer (InGaAsP) 114 and a part of the upper surface of the lower barrier layer (InGaAs) 113 with a force weaker than a covalent bond and with a sufficiently small contact area.

[0041] 11, the semiconductor thin film 135 is shown as tilted because the retention layer (InGaAsP) 114 is shown larger than its actual size relative to the size of the semiconductor thin film 135. The actual thickness of the retention layer (InGaAsP) 114 is sufficiently small compared to the size of the semiconductor thin film 135. For example, the thickness (height) of the retention layer (InGaAsP) 114 is 0.5 μm or less and the width L5 of the semiconductor thin film 135 is 100 μm, so the tilt angle θ2 is θ2 < arctan(0.5 / 50) ≈ 0.57°, and therefore no problems will arise due to the tilt of the semiconductor thin film 135 in the next process described below.

[0042] Here, an example in which the semiconductor thin film 135 is tilted as shown in Figure 11 has been shown, but as shown in Figure 10, depending on the remaining shape of the retention layer (InGaAsP) 114, the semiconductor thin film 135 may not be tilted. For example, this may be the case when the top of the retention layer 114 remains flat. Furthermore, even if the semiconductor thin film 135 is tilted, for the reasons described above, this tilt will not cause any problems in the subsequent process described below.

[0043] As described above, before etching, the thickness of the retention layer (InGaAsP) 114 is preferably at least twice as thick as the thickness of the sacrificial layer (InP) 115. This allows the retention layer (InGaAsP) 114 to remain with a height necessary to support the semiconductor thin film 135 after the sacrificial layer (InP) 115 is removed by etching, as shown in FIG.

[0044] Fig. 12 is a diagram showing a state in which a stamp 140 is attached to the semiconductor thin film 135 shown in Fig. 10 or 11. Fig. 13 is a diagram showing a state in which the semiconductor thin film 135 has been peeled off from the retention layer (InGaAsP) 114 by the stamp 140.

[0045] In order to peel and move the semiconductor thin film 135 from the holding layer (InGaAsP) 114, a stamp 140 is attached to the upper surface of the protective film 121 of the semiconductor thin film 135 as shown in FIG. 12, and the semiconductor thin film 135 is peeled from the holding layer (InGaAsP) 114 using the stamp 140 as shown in FIG.

[0046] 11, the upper barrier layer (InGaAs) 116 is bonded to the upper surface of the retention layer (InGaAsP) 114 and, if the semiconductor thin film 135 is slightly tilted as shown in Fig. 11, also to a portion of the upper surface of the lower barrier layer (InGaAs) 113 by a force weaker than a covalent bond and over a sufficiently small contact area, so that it can be easily peeled off when separating the semiconductor thin film 135. The lower surface of the retention layer (InGaAsP) 114 is covalently bonded to the lower barrier layer (InGaAs) 113.

[0047] 14(A) to 14(C) are diagrams showing the process of removing the upper barrier layer (InGaAs) 116 of the semiconductor thin film 135 peeled off by the stamp 140 by etching, where FIG. 14(A) shows the state before etching, FIG. 14(B) shows the state while etching is in progress, and FIG. 14(C) shows the state after etching has finished.

[0048] As shown in FIG. 14B, the upper barrier layer (InGaAs) 116 of the separated semiconductor thin film 135 is etched both vertically and horizontally (in the directions of the arrows).

[0049] As described above, in practice, the step width L1 of the step portion 116a on the upper surface of the upper barrier layer (InGaAs) 116 and the thickness L2 of the upper barrier layer 116 satisfy the above-described inequality (1). Therefore, as etching progresses, etching from below in the vertical direction is completed before reaching the cladding layer (n-InP) 117 from the horizontal direction. As a result, at least the portion of the upper barrier layer (InGaAs) 116 that is in contact with the lower surface of the cladding layer (n-InP) 117 is removed only by etching from below in the vertical direction, allowing for uniform removal of this portion. This allows for the upper barrier layer (InGaAs) 116 to be removed by etching while maintaining the rear surface (lower surface) of the cladding layer (n-InP) 117 flat.

[0050] 15(A) to 15(C) are diagrams for explaining the process from attaching the semiconductor thin film 135 from which the upper barrier layer (InGaAs) 116 has been removed to a transfer substrate 141 to forming electrodes at predetermined positions, with FIG. 15(A) showing the state in which the semiconductor thin film 135 has been transferred to the transfer substrate 141, FIG. 15(B) showing the state in which the protective film 121 has been removed, and FIG. 15(C) showing the state in which a first electrode 142 and a second electrode 143 have been formed at each predetermined position.

[0051] 15(A), the semiconductor thin film 135 from which the upper barrier layer (InGaAs) 116 has been etched is attached by intermolecular forces to a transfer substrate 141, which is a Si substrate separate from the growth substrate (InP) 111. Next, as shown in FIG. 15(B), the stamp 140 and the protective film 121 are removed, and a functional layer 133 consisting of a cladding layer (n-InP) 117, a light absorption layer (i-InGaAs) 118, a cladding layer (p-InP) 119, and a contact layer (p-InGaAs) 120 is formed on the transfer substrate (Si) 141.

[0052] 15C, a first electrode 142 is formed on the contact layer (p-InGaAs) 120 of the functional layer 133, and a second electrode 143 is formed on the cladding layer (n-InP) 117. In this way, a semiconductor device including the transfer substrate 141, the functional layer 133, the first electrode 142, and the second electrode 143 is formed.

[0053] The semiconductor device here is, for example, a photodiode or an LED (Light Emitting Diode), which is used in, for example, an image sensor, an LED print head, an LED display, etc.

[0054] Fig. 16 is a top view of the laminated wafer 100 processed to the state shown in Fig. 9. Fig. 19 is a diagram for explaining the progress of etching of the sacrificial layer (InP) 115 and the retention layer (InGaAsP) 114.

[0055] The etching of the sacrificial layer (InP) 115 and the retention layer (InGaAsP) 114 described in FIG. 7 progresses from all directions toward the center of each of the rectangularly patterned stacked layers 130, as shown in FIG. 5(A).

[0056] At this time, the etching rate of the retention layer (InGaAsP) 114 is smaller than that of the sacrificial layer (InP) 115, but the retention layer (InGaAsP) 114 forms a wedge-shaped opening (region 150 in FIG. 19 ) by being etched from above as the etching of the sacrificial layer (InP) 115 progresses. This maintains the penetration of the etching solution inward, and the sacrificial layer (InP) 115 is completely removed.

[0057] Therefore, when etching is performed on each stacked body 130 (FIG. 5A) that has been patterned into a square shape as shown in FIG. 5A, the remaining retention layer (InGaAsP) 114 also has a substantially square planar shape and a shape close to a square pyramid or a truncated square pyramid as shown in FIG. 16.

[0058] FIG. 17 is a diagram for explaining the progress of etching in another example, and FIG. 18 is a diagram for explaining the progress of etching in yet another example.

[0059] As shown in FIG. 17, when each laminate 130 is patterned so that its planar shape is circular, and the sacrificial layer (InP) 115 and the retention layer (InGaAsP) 114 are etched from all directions, the retention layer (InGaAsP) 114 remaining in the center has a shape resembling a cone or a truncated cone.

[0060] Furthermore, as shown in Figure 18, in each laminate 130 (Figure 5(A)) that has been patterned to have a square planar shape, if resist that constitutes the holding structure 122 is formed over the entire area of ​​each of the two opposing sides (the left and right sides in Figure 18) of each laminate 130 and then similar etching is performed, the etching solution is prevented from penetrating from each side on which the resist is formed.

[0061] In this case, etching proceeds only from both sides (the top and bottom sides in Figure 18) on which the retention structure 122 (resist) is not formed, so the remaining retention layer 114 is formed in the shape of an approximately triangular prism extending in the same direction at the center equidistant from both sides.

[0062] As described above, according to the configuration of the semiconductor laminate of this embodiment, even if the semiconductor layer is exposed to an etching solution, the back surface of the semiconductor layer (the lower surface of the cladding layer (n-InP) 117) is not roughened, and the semiconductor layer can be satisfactorily bonded to the transfer substrate. Furthermore, when removing the sacrificial layer (InP) 115, the underlying holding layer (InGaAsP) 114 can be left in a tapered shape that tapers toward the top. This makes it possible to completely remove the sacrificial layer (InP) 115 down to the center of the laminate 130, facilitating peeling of the semiconductor thin film 135.

[0063] Furthermore, while the lower surface of the upper barrier layer (InGaAs) 116, which is the bottom layer of the semiconductor thin film 135, is kept flat with a roughness of, for example, 10 nm or less, the remaining tapered layer retention layer (InGaAsP) 114 can stably hold the semiconductor thin film 135 until peeling. Furthermore, since the upper barrier layer (InGaAs) 116 can be etched in the vertical direction after separation (peeling), the lower surface of the cladding layer (n-InP) 117, which is attached to the transfer substrate 141 by intermolecular forces, can be kept flat.

[0064] Second Embodiment Fig. 20 is a diagram schematically showing a stacked structure of a stacked wafer 200 according to a second embodiment having the configuration of a semiconductor stack according to the present disclosure.

[0065] In the laminated wafer 200 shown in Fig. 20, a growth substrate 211 is an InP layer on whose upper surface (main surface) an epitaxial layer is grown. On this growth substrate (InP) 211, a buffer layer 212, which is an InP layer, a lower barrier layer 213, which is an InGaAs layer and serves as a fourth layer, a retention layer 214, which is an InGaAsP layer and serves as a first layer, and a sacrificial layer 215, which is an InP layer and serves as a second layer, are sequentially formed by epitaxial growth. The thickness of the retention layer (InGaAsP) 214 is thicker than the thickness of the sacrificial layer (InP) 215, and in this case, it is preferably at least twice as thick.

[0066] Furthermore, on the sacrificial layer (InP) 215, an upper barrier layer 216 as a third layer which is an InGaAs layer, a cladding layer 217 which is an n-InP layer, a light absorption layer 218 which is an i-InGaAs layer, a cladding layer 219 which is a p-InP layer, and a contact layer 220 which is a p-InGaAs layer are sequentially formed by epitaxial growth.

[0067] Next, a description will be given of a method for manufacturing a semiconductor device according to this embodiment, which is carried out by preparing the above-described laminated wafer 200. Note that the laminated wafer 200 shown in each figure is assumed to be arranged so that the stacking direction is vertically upward.

[0068] 21A to 21C are diagrams showing a predetermined area obtained by patterning the laminated wafer 200 of Fig. 20 into a 4 × 4 pattern, with Fig. 21A being a plan view and Fig. 21B being a side view, and Fig. 21C being a partially enlarged view of one block (area P5 enclosed by a dotted line) shown in Fig. 21B.

[0069] 21A, etching is performed along the separation regions set in a lattice pattern to form lattice-shaped grooves 230a in order to separate the laminated wafer 200 up to the interface between the cladding layer (n-InP) 217 ​​and the upper barrier layer (InGaAs) 216 into 16 (4×4) laminated bodies 230. Therefore, the upper barrier layers (InGaAs) 216 in the separated regions remain continuous with each other as shown in FIG.

[0070] 22(A) to 22(C) are diagrams showing the state in which the laminated wafer 200 of Fig. 21(A) to 21(C) has been further patterned, Fig. 22(A) is a plan view, Fig. 22(B) is a side view, and Fig. 22(C) is a partially enlarged view of multiple blocks (area P5 enclosed by dotted lines) shown in Fig. 22(B).

[0071] Each of the laminates 230 shown in Figures 21A to 21C is further divided into four. That is, as shown in Figure 22A, along the cross-shaped separation regions of each of the laminates 230 (Figures 21A to 21C), cross-shaped grooves 232a are formed by etching up to the interface between the cladding layer (n-InP) 217 ​​and the upper barrier layer (InGaAs) 216, i.e., the four layers of the cladding layer (n-InP) 217, the light absorption layer (i-InGaAs) 218, the cladding layer (p-InP) 219, and the contact layer (p-InGaAs) 220. As a result, one laminate 230 (Figure 21) is further divided into four divided laminates 232, and the upper barrier layers (InGaAs) 216 in the further divided regions remain continuous with each other, as shown in Figure 22B.

[0072] 23A to 23C are diagrams showing the state in which the protective film 221 has been formed on each divided laminate 232, with Fig. 23A being a plan view and Fig. 23B being a side view, and Fig. 23C being a partially enlarged view of a plurality of blocks (area P5 enclosed by dotted lines) shown in Fig. 23B.

[0073] 23A to 23C, the protective film 221 is formed so as to cover the upper surfaces of the functional layer 233 and the upper barrier layer (InGaAs) 216, which are four layers from the cladding layer (n-InP) 217 ​​to the contact layer (p-InGaAs) 220 of each etched divided laminate 232. The protective film 221 is made of Al. ２ O ３ , SiN, SiO ２ As a result, when the sacrificial layer (InP) 215 is removed, it is possible to prevent the top and side surfaces of the functional layer 233, which is the four layers from the cladding layer (n-InP) 217 ​​to the contact layer (p-InGaAs) 220 of each laminate 232, from being etched.

[0074] 24(A) to 24(C) are diagrams showing a state in which slots 234 are provided in parts of the protective film 221 and upper barrier layer (InGaAs) 216 of the grooves 230a (portions indicated by two-dot chain lines) and the grooves 232a (portions indicated by one-dot chain lines) shown in FIGS. 23(A) to 23(C), where FIG. 24(A) is a plan view and FIG. 24(B) is a side view. FIG. 24(C) is a partial enlarged view of a plurality of blocks (portions P5 enclosed by dotted lines) shown in FIG. 24(B).

[0075] As shown in FIGS. 24A to 24C, in the grooves 230a and 232a between the divided laminates 232, elongated holes 234 are formed by etching along the grooves 230a and 232a, reaching the sacrificial layer (InP) 215.

[0076] 25(A) to 25(D) are diagrams for explaining the progress of etching of the sacrificial layer (InP) 215 and the retention layer (InGaAsP) 214, and show, for example, the region P5 enclosed by the dotted line in FIG. 24(B). FIG. 25(A) shows the state before etching begins, FIGS. 25(B) and 25(C) show the process of etching, and FIG. 25(D) shows the state after etching has finished. Note that, for simplicity, the growth substrate 211, the buffer layer 212, and the functional layer 233 above the upper barrier layer 216 are not shown here.

[0077] The etchant used here is hydrochloric acid, a mixture of hydrochloric acid and phosphoric acid, or a mixture of hydrochloric acid and nitric acid. In this etching, the etching rate of the sacrificial layer (InP) 215 is faster than that of the upper barrier layer (InGaAs) 216, and the difference between the two is large, so the upper barrier layer (InGaAs) 216 is hardly etched.

[0078] As in the first embodiment, the etching rate of each layer is such that the etching rate of the sacrificial layer (InP) 215 is greater than the etching rate of the retention layer (InGaAsP) 214, and the etching rate of the sacrificial layer (InP) 215 is greater than the etching rate of the upper barrier layer (InGaAs) 216.

[0079] With the etchant used here, the etching rate of the sacrificial layer (InP) 215 is 1000 times or more the etching rate of the upper barrier layer (InGaAs) 216 (i.e., a selectivity ratio of 1000 or more), and the etching rate of the sacrificial layer (InP) 215 is 2 times or more but less than 1000 times the etching rate of the retention layer (InGaAsP) 214 (i.e., a selectivity ratio of 2 or more but less than 1000). Here, the etching rate of the sacrificial layer (InP) 215 is set to 2 to 4 times the etching rate of the retention layer (InGaAsP) 214 (i.e., a selectivity ratio of 2 to 4). Note that the composition of the retention layer (InGaAsP) 214 here is In(x)Ga(1-x)As(y)P(1-y), where y = 0.4.

[0080] Furthermore, since the lower barrier layer (InGaAs) 213 is formed of the same material as the upper barrier layer (InGaAs) 216, the etching rate of the sacrificial layer (InP) 215 is similarly 1000 times or more the etching rate of the lower barrier layer (InGaAs) 213. Therefore, the sacrificial layer (InP) 215 is hardly etched while the upper retention layer (InGaAsP) 214 is being etched. This also protects the buffer layer (InP) 212 and growth substrate (InP) 211 below the lower barrier layer (InGaAs) 213 from etching.

[0081] That is, when a predetermined etchant is used, the etching selectivity of the sacrificial layer (InP) 215 to the upper barrier layer (InGaAs) 216 is greater than the etching selectivity of the sacrificial layer (InP) 215 to the retention layer (InGaAsP) 214. Also, the etching selectivity of the sacrificial layer (InP) 215 to the lower barrier layer (InGaAs) 213 is greater than the etching selectivity of the sacrificial layer (InP) 215 to the retention layer (InGaAsP) 214.

[0082] Here, as described in Figures 24(A) to (C), long holes 234 are formed along the grooves 230a, 232a formed in a grid pattern, so that etching progresses from the periphery of each divided laminate 232 toward its center.

[0083] 25(B) and 25(C), as the etching of the sacrificial layer (InP) 215 progresses, the retention layer (InGaAsP) 214 is also etched, but because the etching of the sacrificial layer (InP) 215 progresses first, the retention layer (InGaAsP) 214 is also etched from its upper surface. However, because the lower barrier layer (InGaAs) 213 is not etched, the retention layer (InGaAsP) 214 is not etched from its lower surface. As a result, the retention layer (InGaAsP) 214 is etched in a tapered shape at both end portions.

[0084] When the sacrificial layer (InP) 215 is finally removed, the upper barrier layer (InGaAs) 216 of each divided stack 232 is supported at its center by the remaining retention layer (InGaAsP) 214 in the shape of a quadrangular pyramid or truncated quadrangular pyramid, as shown in FIG. 25(D).

[0085] Therefore, in the process of removing the sacrificial layer (InP) 215 by etching, the area of ​​the upper surface of the retention layer (InGaAsP) 214 that contacts the upper barrier layer (InGaAs) 216 is made smaller than the area of ​​the lower surface that contacts the lower barrier layer (InGaAs) 213.

[0086] FIG. 26 is a partially enlarged view of the vicinity of the end (area P6 enclosed by a dotted line) of the retention layer (InGaAsP) 214 shown in FIG. 25(C) where etching has progressed in a tapered shape.

[0087] 26 , the ratio of the thickness L7 of the retention layer (InGaAsP) 214 to the depth L6 of the tapered etching progressed portion of the end of the retention layer (InGaAsP) 214, i.e., tan(θ2) of the angle θ2 of the tip, becomes larger by adjusting x and y in In(x)Ga(1-x)As(y)P(1-y), which is the composition of the retention layer (InGaAsP) 214, within the ranges of 0<x<1 (4) 0<y<1 (5) to increase the concentrations (composition ratios) of In and P. Specifically, 0.7≦x is desirable (to increase the In concentration), and y≦0.5 is desirable (to increase the P concentration). Within this range (x is 0.7 or more and y is 0.5 or less), θ2 of the retention layer (InGaAsP) 214 becomes larger than 0, that is, the retention layer 214 has a triangular shape, so that the semiconductor thin film 235 (described later) can be releasably held with a smaller area (vertex portion). However, in this embodiment, the composition ratio of In to P in the retention layer (InGaAsP) 214 may be as close to 0 as possible, and the angle θ2 may be as close to 0 as possible.

[0088] In addition, the angle θ2 can be reduced by increasing the thickness of the sacrificial layer (InP) 215, but if the thickness of the retention layer (InGaAsP) 214 is less than twice the thickness of the sacrificial layer (InP) 215, there is a possibility that the retention layer (InGaAsP) 214 will not remain to the required height.

[0089] Figures 27(A) to (C) show the state of the laminated wafer 200 with the slots 234 shown in Figures 24(A) to (C) after the sacrificial layer (InP) 215 has been removed by etching, and the retention layer (InGaAsP) 214 has also been removed except for the central portion, corresponding to the stage shown in Figure 25(D). Figure 27(A) is a plan view, and Figure 27(B) is a side view. Figure 27(C) is a partially enlarged view of multiple blocks (area P5 enclosed by dotted lines) shown in Figure 27(B). Figure 28 is a top view corresponding to Figure 27(C).

[0090] 27A to 27C and 28, when the sacrificial layer (InP) 215 is completely removed by etching, multiple locations on the lower surface of the upper barrier layer (InGaAs) 216 are held by the upper surface of the retention layer (InGaAsP) 214 remaining in the shape of a quadrangular pyramid or a truncated quadrangular pyramid corresponding to each divided stack 232. Here, the stacked structure from the upper barrier layer (InGaAs) 216 to the protective film 221 may be referred to as a semiconductor thin film 235.

[0091] At this time, the lower surface of the upper barrier layer (InGaAs) 216 and the respective upper surfaces of the abutting retention layer (InGaAsP) 214 are bonded with a force weaker than that of a covalent bond and with a sufficiently small contact area. This allows for easy peeling when separating the semiconductor thin film 235, which will be described later. The lower surface of the retention layer (InGaAsP) 214 is covalently bonded to the lower barrier layer (InGaAs) 213.

[0092] Etching of the sacrificial layer (InP) 215 and the retention layer (InGaAsP) 214 progresses from all directions toward the center of each rectangularly formed divided stack 232. At this time, although the etching rate of the retention layer (InGaAsP) 214 is slower than the etching rate of the sacrificial layer (InP) 215, the retention layer (InGaAsP) 214 is etched from above as the etching of the sacrificial layer (InP) 215 progresses, forming a wedge-shaped opening (corresponding to region 150 in FIG. 19 ). This maintains the penetration of the etching solution inward, and the sacrificial layer (InP) 215 is completely removed.

[0093] In this embodiment, as described above, etching is performed at this stage in a state where the upper barrier layer (InGaAs) 216 is formed continuously (except for the slots 234) without being divided into individual divided laminated bodies 232. Therefore, there is no need to provide the holding structure 122 required in the first embodiment.

[0094] 29 is a diagram showing a state in which a stamp 240 is attached to the semiconductor thin film 235 shown in FIG. 27(C), FIG. 30 is a diagram showing a state in which the semiconductor thin film 235 has been peeled off from the retention layer (InGaAsP) 214 by the stamp 240, and FIG. 31 is a diagram showing a state in which the upper barrier layer (InGaAs) 216 has been etched.

[0095] In order to peel and move the semiconductor thin film 235 from the holding layer (InGaAsP) 214, a stamp 240 is attached to the upper surface of the protective film 221 of the semiconductor thin film 235 as shown in FIG. 29, and the semiconductor thin film 235 is peeled from the holding layer (InGaAsP) 214 using the stamp 240 as shown in FIG. 30.

[0096] At this time, the upper barrier layer (InGaAs) 216 is bonded to the upper surface of the retention layer (InGaAsP) 214 by a force weaker than a covalent bond and over a sufficiently small contact area, so that it can be easily peeled off when separating the semiconductor thin film 235. The lower surface of the retention layer (InGaAsP) 214 is covalently bonded to the lower barrier layer (InGaAs) 213.

[0097] FIG. 31 is a diagram showing the semiconductor thin film 235 held on the stamp 240 shown in FIG. 30 with the upper barrier layer (InGaAs) 216 removed.

[0098] 31, the upper barrier layer (InGaAs) 216 of the semiconductor thin film 235 is completely removed by etching, but as described in the first embodiment with reference to FIGS. 14A to 14C, as the etching progresses, etching from below in the vertical direction is completed before reaching the cladding layer (n-InP) 117 from the horizontal direction. As a result, at least the portion of the upper barrier layer (InGaAs) 216 that is in contact with the lower surface of the cladding layer (n-InP) 217 ​​is removed only by etching from below in the vertical direction, and therefore, uniform removal of this portion is possible.

[0099] FIG. 32 shows the semiconductor thin film 235 from which the upper barrier layer (InGaAs) 216 has been removed, attached to a transfer substrate 241, and FIG. 33 shows the protective film 221 has been removed and a first electrode 242 and a second electrode 243 have been formed.

[0100] As shown in Fig. 32, the semiconductor thin film 235 from which the upper barrier layer (InGaAs) 216 has been etched is attached by intermolecular forces to a transfer substrate 241, which is a Si substrate separate from the growth substrate (InP) 211. Next, as shown in Fig. 33, the stamp 240 and the protective film 221 are removed, and functional layers 233 electrically divided into divided stacks 232 (see Figs. 22A to 22C) are formed on the transfer substrate (Si) 241. Each functional layer 233 as a semiconductor layer has a cladding layer (n-InP) 217, a light absorption layer (i-InGaAs) 218, a cladding layer (p-InP) 219, and a contact layer (p-InGaAs) 220.

[0101] 33, a first electrode 242 is formed on the contact layer (p-InGaAs) 220 of the functional layer 233, and a second electrode 243 is formed so as to be in contact with the cladding layer (n-InP) 217. In this way, a semiconductor device including the transfer substrate 241, the functional layer 233, the first electrode 242, and the second electrode 243 is formed.

[0102] The semiconductor device here is, for example, a photodiode or an LED, which is used in, for example, an image sensor, an LED print head, an LED display, etc.

[0103] As described above, according to the configuration of the semiconductor laminate of this embodiment, when removing the sacrificial layer (InP) 215, the underlying retention layer (InGaAsP) 214 can be left in a tapered shape that tapers toward the top. This makes it possible to completely remove the sacrificial layer (InP) 215 down to the center of each divided laminate 232, making it easy to peel off the semiconductor thin film 235.

[0104] Furthermore, while the lower surface of the upper barrier layer (InGaAs) 216, which is the bottom layer of the semiconductor thin film 235, is kept flat with a roughness of, for example, 10 nm or less, the remaining tapered retention layer (InGaAsP) 214 can stably retain the semiconductor thin film 235 until peeling. Furthermore, since the upper barrier layer (InGaAs) 216 can be etched in the vertical direction after peeling, the lower surface of the cladding layer (n-InP) 217, which is attached to the transfer substrate 241 by intermolecular forces, can be kept flat.

[0105] Furthermore, in this embodiment, the upper barrier layer (InGaAs) 216, which is formed continuously without being divided (except for the long holes 234), is held by the plurality of holding layers (InGaAsP) 214, so that when removing the sacrificial layer (InP) 215, it is not necessary to form a resist (corresponding to the holding structure 122 in the first embodiment) or the like.

[0106] Furthermore, in the claims and in the description of the embodiments, terms such as "upper," "lower," "left," and "right" are used for convenience and do not limit the absolute positional relationship in the state in which the semiconductor laminate is arranged.

[0107] 100 Stacked wafer, 111 Growth substrate (substrate), 112 Buffer layer, 113 Lower barrier layer (fourth layer), 114 Support layer (first layer), 115 Sacrificial layer (second layer), 116 Upper barrier layer (third layer), 116a Step portion, 117 Cladding layer, 118 Light absorption layer, 119 Cladding layer, 120 Contact layer, 121 Protective film, 122 Support structure portion, 130 Stacked body, 131a Groove portion, 131b Groove portion, 133 Functional layer (semiconductor layer), 135 Semiconductor thin film, 140 Stamp, 141 Transfer substrate, 142 First electrode, 143 Second electrode, 150 Region, 200 Stacked wafer, 211 Growth substrate (substrate), 212 Buffer layer, 213 Lower barrier layer (fourth layer), 214 Support layer (first layer), 215 Sacrificial layer (second layer), 216 Upper barrier layer (third layer), 217 Cladding layer, 218 Light absorption layer, 219 Cladding layer, 220 Contact layer, 221 Protective film, 230 Stacked body, 230a Groove portion, 232 Divided stacked body, 232a Groove portion, 233 Functional layer (semiconductor layer), 234 Slot, 235 Semiconductor thin film, 240 Stamp, 241 Transfer substrate, 242 First electrode, 243 Second electrode.

Claims

1. A semiconductor stack comprising: a substrate; a first layer stacked above the substrate; a second layer stacked on the first layer; a third layer stacked on the second layer; and a semiconductor layer stacked on the third layer, at least a layer in contact with the third layer being made of the same material as the second layer, wherein, when a specified etchant is used, the etching selectivity of the second layer to the third layer is greater than the etching selectivity of the second layer to the first layer.

2. The semiconductor laminate according to claim 1, further comprising a fourth layer stacked above the substrate and made of the same material as the third layer, and the first layer is stacked on the fourth layer.

3. The semiconductor laminate of claim 2, wherein the substrate, the layer in contact with the third layer of the semiconductor layer, and the second layer are made of indium phosphide, the first layer is made of indium gallium arsenide phosphide, and the third layer and the fourth layer are made of indium gallium arsenide.

4. A semiconductor laminate according to any one of claims 1 to 3, characterized in that the thickness of the first layer is greater than the thickness of the second layer.

5. A semiconductor laminate as claimed in any one of claims 1 to 4, characterized in that the semiconductor layer is formed to be smaller in size in a first direction parallel to the top surface of the substrate than the third layer, and the third layer has a thickness in a second direction perpendicular to the top surface of the substrate smaller than the length in the first direction of a portion of the semiconductor layer protruding from the outer periphery.

6. A semiconductor laminate according to any one of claims 1 to 5, further comprising a protective film formed so as to cover the semiconductor layer except for the surface in contact with the third layer.

7. A method for manufacturing a semiconductor device, comprising the steps of: removing the second layer from a semiconductor laminate having a first layer stacked above a substrate, a second layer stacked on the first layer, a third layer stacked on the second layer, and a semiconductor layer stacked on the third layer, at least a layer in contact with the third layer being made of the same material as the second layer; separating the semiconductor layer and the third layer from the substrate; removing the third layer; and transferring the semiconductor layer to a transfer substrate different from the substrate.

8. A method for manufacturing a semiconductor device as described in claim 7, characterized in that when removing the second layer, a second surface of the first layer on the third layer side is made smaller than a first surface of the first layer on the substrate side, which is parallel to the top surface of the substrate, and the third layer and the second surface are bonded together.

9. The method for manufacturing a semiconductor device according to claim 7 or 8, further comprising forming a protective film so as to cover all surfaces of the semiconductor layer except the surface in contact with the third layer before removing the second layer.

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