Semiconductor light-emitting device

Abstract

A semiconductor light-emitting device (10) comprises: a substrate (20); a plurality of semiconductor light-emitting elements (30) provided on the substrate (20); and a plurality of drive circuits (40A to 40H) provided on the substrate (20) and each driving one or more of the plurality of semiconductor light-emitting elements (30). Each of the plurality of semiconductor light-emitting elements (30) is positioned on a main surface (21) of the substrate (20), and is configured with a light-outputting element that outputs light in a direction intersecting the main surface (21). Each of the plurality of drive circuits (40A to 40H) includes switching elements (411 to 418) for controlling one or more of the plurality of semiconductor light-emitting elements (30), and capacitors (421 to 428) for supplying a current to the one or more of the plurality of semiconductor light-emitting elements (30).

Description

Semiconductor light-emitting device

[0001] The present disclosure relates to semiconductor light emitting devices.

[0002] One type of semiconductor light-emitting device is a semiconductor laser device that includes a semiconductor laser element as a light source. Semiconductor laser devices are widely used as light source devices mounted in various electronic devices. Patent Document 1 discloses an example of a semiconductor laser device.

[0003] JP 2016-29718 A

[0004] [Summary] In recent years, there has been a demand for further improvements in the performance of semiconductor light-emitting devices. For example, when semiconductor light-emitting devices are applied to laser systems such as LiDAR (Light Detection and Ranging, Laser Imaging Detection and Ranging) that use three-dimensional distance measurement, there is a demand for a wider viewing angle and improved resolution. To meet these demands, there is a demand for a further increase in the number of semiconductor light-emitting elements that can be installed in a semiconductor light-emitting device.

[0005] A semiconductor light emitting device according to one aspect of the present disclosure includes a substrate, a plurality of semiconductor light emitting elements provided on the substrate, and a plurality of drive circuits provided on the substrate and configured to drive one or more of the plurality of semiconductor light emitting elements, respectively. Each of the plurality of semiconductor light emitting elements is configured by a light emitting element located on a major surface of the substrate and emitting light in a direction intersecting with the major surface. Each of the plurality of drive circuits includes a switching element that controls one or more of the plurality of semiconductor light emitting elements, and a capacitor that supplies current to one or more of the plurality of semiconductor light emitting elements.

[0006] FIG. 1 is a schematic plan view of an exemplary semiconductor light emitting device according to a first embodiment. FIG. 2 is a schematic plan view showing an enlarged central region of the semiconductor light emitting device of FIG. 1. FIG. 3 is a schematic plan view showing an enlarged portion of a peripheral region of the semiconductor light emitting device of FIG. 1. FIG. 4 is a schematic plan view showing an enlarged portion of a peripheral region of the semiconductor light emitting device of FIG. 1. FIG. 5 is a schematic plan view showing an enlarged portion of a peripheral region of the semiconductor light emitting device of FIG. 1. FIG. 6 is a schematic plan view showing an enlarged portion of a peripheral region of the semiconductor light emitting device of FIG. 1. FIG. 7 is a schematic cross-sectional view of a semiconductor light emitting device taken along line F7-F7 in FIG. 3. FIG. 8 is a schematic perspective view of a semiconductor light emitting element. FIG. 9 is a schematic plan view of a back electrode layer of the semiconductor light emitting device of FIG. 1. FIG. 10 is a schematic plan view of an intermediate electrode layer of the semiconductor light emitting device of FIG. 1. FIG. 11 is a schematic cross-sectional view showing a current path in the semiconductor light emitting device of FIG. 1. FIG. 12 is a schematic circuit diagram of an exemplary light emitting system including the semiconductor light emitting device of FIG. 1. FIG. 13 is a schematic plan view of an exemplary semiconductor light emitting device according to a second embodiment. FIG. 14 is a schematic plan view showing an enlarged central portion of the semiconductor light emitting device of FIG. 13 . FIG. 15 is a schematic plan view showing an enlarged portion of the front electrode layer of the semiconductor light emitting device of FIG. 13 . FIG. 16 is a schematic plan view showing an enlarged portion of the front electrode layer of the semiconductor light emitting device of FIG. 13 . FIG. 17 is a schematic plan view showing an enlarged portion of the front electrode layer of the semiconductor light emitting device of FIG. 13 . FIG. 18 is a schematic plan view showing an enlarged portion of the front electrode layer of the semiconductor light emitting device of FIG. 13 . FIG. 19 is a schematic plan view of a back electrode layer of the semiconductor light emitting device of FIG. 13 . FIG. 20 is a schematic plan view of a front-side intermediate electrode layer of the semiconductor light emitting device of FIG. 13 . FIG. 21 is a schematic plan view of a back-side intermediate electrode layer of the semiconductor light emitting device of FIG. 13 . FIG. 22 is a schematic plan view of an exemplary semiconductor light emitting device according to a third embodiment. FIG. 23 is a schematic plan view showing an enlarged central portion of the semiconductor light emitting device of FIG. 22 . FIG. 24 is a schematic plan view showing an enlarged portion of the front electrode layer of the semiconductor light emitting device of FIG. 22 . Fig. 25 is a schematic plan view showing an enlarged view of a portion of the front electrode layer of the semiconductor light emitting device of Fig. 22. Fig. 26 is a schematic plan view showing an enlarged view of a portion of the front electrode layer of the semiconductor light emitting device of Fig. 22. Fig. 27 is a schematic plan view showing an enlarged view of a portion of the front electrode layer of the semiconductor light emitting device of Fig. 22.Fig. 28 is a schematic plan view of a back electrode layer of the semiconductor light emitting device of Fig. 22. Fig. 29 is a schematic plan view of a front surface side intermediate electrode layer of the semiconductor light emitting device of Fig. 22. Fig. 30 is a schematic plan view of a back surface side intermediate electrode layer of the semiconductor light emitting device of Fig. 22.

[0007] DETAILED DESCRIPTION Hereinafter, several embodiments of semiconductor light emitting devices according to the present disclosure will be described with reference to the accompanying drawings. Note that for simplicity and clarity of description, components shown in the drawings are not necessarily drawn to scale. Also, hatching lines may be omitted in cross-sectional views to facilitate understanding. The accompanying drawings are merely illustrative of embodiments of the present disclosure and should not be considered to limit the present disclosure.

[0008] The following detailed description includes devices, systems, and methods embodying exemplary embodiments of the present disclosure. This detailed description is merely illustrative in nature and is not intended to limit the embodiments of the present disclosure or the application and uses of such embodiments.

[0009] First Embodiment A semiconductor light emitting device 10 according to a first embodiment will be described with reference to FIGS. 1 to 12. FIG. 1 shows a schematic planar structure of the semiconductor light emitting device 10. FIG. 2 shows a schematic planar structure of the central portion of the semiconductor light emitting device 10. FIGS. 3 to 6 show schematic planar structures of four different portions of the peripheral region of the semiconductor light emitting device 10. FIG. 7 shows a schematic cross-sectional structure taken along line F7-F7 in FIG. 3, and FIG. 8 is a schematic perspective view of the semiconductor light emitting element. FIG. 9 shows a schematic back electrode structure of the semiconductor light emitting device 10, and FIG. 10 shows a schematic intermediate electrode structure of the semiconductor light emitting device 10. FIG. 11 is a diagram illustrating a current path in the semiconductor light emitting device 10, and FIG. 12 shows a schematic circuit of a light emitting system 200 including the semiconductor light emitting device 10.

[0010] In this disclosure, components may be described based on mutually orthogonal X, Y, and Z axes shown in the drawings. The term "planar view" used in this disclosure refers to viewing the semiconductor light-emitting device 10 in the Z-axis direction.

[0011] 1, the semiconductor light emitting device 10 includes a substrate 20, a plurality of (e.g., eight in FIG. 1) semiconductor light emitting elements 30, and a plurality of (e.g., eight in FIG. 1) drive circuits 40A-40H. In the following description, when the drive circuits 40A-40H are not to be distinguished from one another, the drive circuits 40A-40H will be referred to as drive circuit 40 (or each drive circuit 40).

[0012] The plurality of semiconductor light-emitting elements 30 and the plurality of drive circuits 40 are provided on a substrate 20. The semiconductor light-emitting device 10 is realized as a multi-channel (eight channels in the example of FIG. 1 ) drive type light-emitting module in which the plurality of semiconductor light-emitting elements 30 are driven by the plurality of drive circuits 40. The number of semiconductor light-emitting elements 30 and the number of drive circuits 40 can be changed as appropriate depending on the number of channels.

[0013] The substrate 20 has a rectangular shape in a plan view. In the example of FIG. 1, the substrate 20 is square, but it may have any shape in a plan view. Note that a plan view is synonymous with viewing the semiconductor light-emitting device 10 in the thickness direction of the substrate 20 (a direction perpendicular to the plane of the paper in FIG. 1). The substrate 20 includes a main surface 21, a back surface 22 (see FIG. 7) on the opposite side, and first to fourth side surfaces 23 to 26. The first and second side surfaces 23 and 24 correspond to both end surfaces of the substrate 20 in the Y-axis direction. In the example of FIG. 1, the first side surface 23 is located on the lower side of the paper, and the second side surface 24 is located on the upper side of the paper. The third and fourth side surfaces 25 and 26 correspond to both end surfaces of the substrate 20 in the X-axis direction. In the example of FIG. 1, the third side surface 25 is located on the left side of the paper, and the fourth side surface 26 is located on the right side of the paper.

[0014] 7, for example, a multilayer substrate is used as the substrate 20. In the example of FIG. 7, the substrate 20 is a four-layer substrate and includes first to fourth electrode layers 28A to 28D and first to third base materials 27A to 27C located between the first to fourth electrode layers 28A to 28D. The first to fourth electrode layers 28A to 28D are formed of one or more materials selected from the group including, for example, Ti (titanium), TiN (titanium nitride), Au (gold), Ag (silver), Cu (copper), Al (aluminum), and W (tungsten).

[0015] The first to third base materials 27A to 27C are formed of, for example, an insulating material. One example of an insulating material is a material containing epoxy resin, and for example, glass epoxy resin can be used. Another example of an insulating material is a material containing ceramic. Examples of materials containing ceramic include aluminum nitride (AlN) or alumina (Al ２ O ３ If a material containing ceramic is used, the heat dissipation performance of the first to third base members 27A to 27C is improved, and an excessive temperature rise in the semiconductor light emitting device 10 is suppressed.

[0016] The first substrate 27A includes the main surface 21 of the substrate 20. The second substrate 27B includes the back surface 22 of the substrate 20. In other words, the main surface of the first substrate 27A corresponds to the main surface 21 of the substrate 20, and the back surface of the second substrate 27A corresponds to the back surface 22 of the substrate 20. The third substrate 27C is located midway between the first substrate 27A and the second substrate 27B. The four side surfaces of each of the first to third substrates 27A to 27C correspond to the first to fourth side surfaces 23 to 26 of the substrate 20.

[0017] The main surface 21 of the substrate 20 is covered with a main surface resist layer 29A, and the back surface 22 of the substrate 20 is covered with a back surface resist layer 29B. The main surface resist layer 29A and the back surface resist layer 29B are formed of an insulating material such as an epoxy resin or a polyimide resin. The main surface resist layer 29A and the back surface resist layer 29B may contain a filler such as silica or alumina.

[0018] The ends of the first to fourth electrode layers 28A to 28D are not exposed on the first to fourth side surfaces 23 to 26 of the substrate 20 (the right end surface in FIG. 7 indicates the first side surface 23). As shown in FIG. 7, the end of the first electrode layer 28A located on the main surface 21 of the substrate 20 is covered by a main surface resist layer 29A, and the end of the second electrode layer 28B located on the back surface 22 of the substrate 20 is covered by a back surface resist layer 29B. The ends of the second and third electrode layers 28C, 28D located between the first to third base materials 27A to 27C are covered by the first to third base materials 27A to 27C. Note that in FIG. 7, for the purpose of explanation, the interfaces between the first to third base materials 27A to 27C are shown with solid lines, but in reality, these interfaces may not be clearly defined.

[0019] [1-2. Semiconductor Light-Emitting Element] Each of the semiconductor light-emitting elements 30 is positioned on the primary surface 21 of the substrate 20 and is composed of a light-emitting element that emits light in a direction intersecting the primary surface 21 (the Z-axis direction in FIG. 1 ). The light-emitting element functions as a light source for the semiconductor light-emitting device 10. While the mounting configuration of each semiconductor light-emitting element 30 is not particularly limited, in the first embodiment, the semiconductor light-emitting elements 30 are positioned on the primary surface 21 of the substrate 20 via a first electrode layer 28A. For example, each semiconductor light-emitting element 30 is composed of a photonic-crystal surface-emitting laser (PCSEL) element that outputs laser light in a predetermined wavelength band. PCSEL elements are capable of high-power operation (high-brightness operation) by emitting a beam with high beam quality and a narrow divergence angle, and are characterized by low temperature dependence of the operating wavelength. Each semiconductor light-emitting element 30 has the same configuration. As an example, the PCSEL element employed in each semiconductor light-emitting element 30 has a beam divergence angle expressed as a full width at half maximum (FWHM) of 1° or less, more preferably 0.10° to 0.15°, and a spectral width of 0.2 nm or less. The element size of the PCSEL element is, for example, approximately 1.0 mm × 1.0 mm in plan view and a thickness of 0.2 mm or less. The laser light may be visible light or laser light with a wavelength longer than visible light, such as infrared light.

[0020] As shown in FIGS. 1 and 2 , each semiconductor light-emitting element 30 has a rectangular shape, e.g., a square shape, in a planar view. The plurality of semiconductor light-emitting elements 30 are collectively arranged in a central region AC of the substrate 20. The central region AC refers to a region including the center of the substrate 20 in a planar view. In one example, a first set including some of the plurality of semiconductor light-emitting elements 30 (four of eight in the example of FIG. 1 ) is arranged in a row in the X-axis direction within the central region AC, and a second set including the remaining semiconductor light-emitting elements 30 (the remaining four in the example of FIG. 1 ) is arranged in a row in the X-axis direction within the central region AC, adjacent to the first set in the Y-axis direction. Therefore, the plurality of semiconductor light-emitting elements 30 are arranged in a matrix adjacent to each other in the central region AC of the substrate 20. The arrangement of the semiconductor light-emitting elements 30 is not limited to the two rows and four columns shown in FIG. 1 .

[0021] 7 and 8 , each semiconductor light emitting element 30 includes an element front surface 31 and an element back surface 32 on the opposite side. The semiconductor light emitting element 30 has a light emitting region 33 in the center of the element front surface 31. A front surface electrode 34 is provided on the element front surface 31. The front surface electrode 34 is formed in, for example, a rectangular ring shape with an opening (through hole) that exposes the light emitting region 33 of the element front surface 31. A back surface electrode 35 is provided on the element back surface 32. The back surface electrode 35 is formed, for example, over the entire surface of the element back surface 32. The front surface electrode 34 corresponds to a cathode electrode, and the back surface electrode 35 corresponds to an anode electrode.

[0022] [1-3. Drive Circuits for Semiconductor Light-Emitting Device] As shown in FIG. 1, drive circuits 40A-40H are provided to drive multiple (eight in FIG. 1) semiconductor light-emitting elements 30 mounted on the semiconductor light-emitting device 10. Each of these drive circuits 40A-40H is configured to drive one or more of the multiple semiconductor light-emitting elements 30. In the example of FIG. 1, one semiconductor light-emitting element 30 is provided per channel (each drive circuit 40), and each of drive circuits 40A-40H drives one of the eight semiconductor light-emitting elements 30. Note that, because each drive circuit 40 has the same configuration, the following description will focus on drive circuit 40A, and detailed descriptions of drive circuits 40B-40H will be omitted.

[0023] The drive circuit 40A includes a switching element 411 and one or more capacitors 421. The switching element 411 is configured to control one or more of the plurality of semiconductor light emitting elements 30. In the example of FIG. 1, the switching element 411 drives one of the eight semiconductor light emitting elements 30. The switching element 411 is provided near the semiconductor light emitting element 30 to be controlled. In the example of FIG. 1, the switching element 411 is provided at a position adjacent to or close to the semiconductor light emitting element 30 in the Y-axis direction.

[0024] The switching element 411 has a rectangular shape in a plan view. In the example of FIG. 1 , the switching element 411 has a square shape, but the switching element 411 may have any shape in a plan view. For example, a vertical transistor is used as the switching element 411. Examples of such vertical transistors include a metal-oxide-semiconductor field-effect transistor (MOSFET), an insulated gate bipolar transistor (IGBT), and a bipolar transistor. In the first embodiment, for example, an n-type MOSFET is used as the switching element 411.

[0025] As shown in Fig. 7, the switching element 411 includes a front surface 41A and a rear surface 41B on the opposite side. A source electrode 41S and a gate electrode 41G (see Fig. 3) are provided on the front surface 41A. The source electrode 41S is disposed, for example, over most of the front surface 41A. The gate electrode 41G is disposed, for example, near one corner of the front surface 41A. As shown in Fig. 7, a drain electrode 41D is provided on the rear surface 41B. The drain electrode 41D is disposed, for example, over the entire surface of the rear surface 41B.

[0026] Returning to Fig. 1 , the capacitor 421 is configured to supply current to one or more of the plurality of semiconductor light-emitting elements 30. In the example of Fig. 1 , the drive circuit 40A includes four capacitors 421 connected in parallel, and these four capacitors 421 are configured to supply current to one semiconductor light-emitting element 30 that is the target of control by the switching element 411. The four capacitors 421 are provided near the switching element 411. In the example of Fig. 1 , the four capacitors 421 are provided at positions adjacent to or close to the switching element 411 in the Y-axis direction. The four capacitors 421 are provided closer to the first side surface 23 of the substrate 20 than the switching element 411 in the Y-axis direction.

[0027] The capacitors 421 are, for example, ceramic capacitors. Each capacitor 421 is rectangular in plan view, with two long sides along the Y-axis direction and two short sides along the X-axis direction. The four capacitors 421 are spaced apart from each other and lined up in a row in the X-axis direction with their long sides adjacent to each other. As shown in FIG. 7 , each capacitor 421 includes a first electrode 42A and a second electrode 42B. The first electrode 42A is located at one end of the capacitor 421 in the Y-axis direction, and the second electrode 42B is located at the other end of the capacitor 421 in the Y-axis direction.

[0028] Like drive circuit 40A, drive circuits 40B to 40H also include switching elements 412 to 418 configured similarly to switching element 411, and capacitors 422 to 428 configured similarly to capacitor 421. Like drive circuit 40A, drive circuit 40B also includes, for example, four capacitors 422, and this also applies to capacitors 423 to 428 of the other drive circuits 40C to 40H.

[0029] 1, the semiconductor light emitting device 10 includes, in addition to the plurality of semiconductor light emitting elements 30 and the plurality of drive circuits 40 described above, a plurality of (e.g., eight in FIG. 1) protection diodes 70A-70H that protect the semiconductor light emitting elements 30 mounted on the semiconductor light emitting device 10. The protection diodes 70A-70H are provided, for example, for each channel (drive circuit 40). Note that, because the configurations of the protection diodes 70A-70H are the same, the following description will focus on the protection diode 70A, and detailed description of the protection diodes 70B-70H will be omitted.

[0030] As shown in FIG. 12 , the protection diode 70A is connected in anti-parallel to one semiconductor light emitting element 30 that is the target of control by the switching element 411 (drive circuit 40A). However, the number of semiconductor light emitting elements 30 connected to the protection diode 70A is not limited to one. The protection diode 70A may be connected in anti-parallel to one or more semiconductor light emitting elements 30 provided per channel (each drive circuit 40). Note that, for clarity, FIG. 12 shows only the drive circuits 40A, 40B, 40G, and 40H and their associated circuit elements, and omits the drive circuits 40C, 40D, 40E, and 40F and their associated circuit elements.

[0031] [1-5. Electrode Layers of the Substrate] Next, the configuration of the multiple electrode layers of the substrate 20, i.e., the first to fourth electrode layers 28A to 28D, will be described. As shown in FIG. 7 , the first electrode layer 28A is provided as a front electrode layer located on the main surface 21 of the substrate 20. The second electrode layer 28B is provided as a back electrode layer located on the back surface 22 of the substrate 20. The third and fourth electrode layers 28C and 28D are each provided as intermediate electrode layers located between the first and second electrode layers 28A and 28B in the thickness direction of the substrate 20. Of these, the third electrode layer 28C is provided as a front-side intermediate electrode layer located closer to the first electrode layer 28A (front electrode layer), and the fourth electrode layer 28D is provided as a back-side intermediate electrode layer located closer to the second electrode layer 28B (back electrode layer). In the first embodiment, the third and fourth electrode layers 28C and 28D have, for example, the same structure.

[0032] 1 to 6 , the first electrode layer 28A (surface electrode layer) located on the main surface 21 of the substrate 20 includes a plurality of surface electrodes (pattern electrodes) spaced apart from one another. In the first embodiment, the first electrode layer 28A includes first surface electrodes 61A to 61H, second surface electrodes 62A to 62H, third surface electrodes 63A to 63H, fourth surface electrode 64, fifth surface electrodes 65A to 65H, and sixth surface electrodes 66A to 66H.

[0033] The first surface electrodes 61A to 61H are used to mount a plurality of semiconductor light emitting elements 30. In the first embodiment, one semiconductor light emitting element 30 is mounted on each of the first surface electrodes 61A to 61H. The second surface electrodes 62A to 62H, the third surface electrodes 63A to 63H, the fourth surface electrode 64, the fifth surface electrodes 65A to 65H, and the sixth surface electrodes 66A to 66H are used to mount the drive circuits 40A to 40H.

[0034] As shown in Fig. 2, the first surface electrodes 61A to 61H are located in a central region AC of the substrate 20. As shown in Figs. 3 to 6, the surface electrodes other than the first surface electrodes 61A to 61H, i.e., the second surface electrodes 62A to 62H, the third surface electrodes 63A to 63H, the fourth surface electrode 64, the fifth surface electrodes 65A to 65H, and the sixth surface electrodes 66A to 66H, are located in a peripheral region AP of the substrate 20, which is outside the first surface electrodes 61A to 61H in a planar view. Note that the fourth surface electrode 64 is formed in a ring shape surrounding the first surface electrodes 61A to 61H, the second surface electrodes 62A to 62H, and the third surface electrodes 63A to 63H in a planar view, as shown in Fig. 1.

[0035] The first surface electrodes 61A to 61H are collectively arranged in a central region AC of the substrate 20. In the first embodiment, the first surface electrodes 61A to 61D are arranged in a row in the X-axis direction, and the remaining first surface electrodes 61E to 61H are arranged in a row in the X-axis direction while being adjacent to each other in the Y-axis direction. Therefore, the first surface electrodes 61A to 61H are arranged in a matrix adjacent to each other in the central region AC of the substrate 20. Therefore, eight semiconductor light emitting elements 30 are mounted in the central region AC. As shown in FIG. 7 , the semiconductor light emitting elements 30 are mounted on the first surface electrode 61A with a conductive bonding material SD. Note that semiconductor light emitting elements 30 are similarly mounted on the other first surface electrodes 61B to 61H.

[0036] The first surface electrodes 61A to 61H, the second surface electrodes 62A to 62H, the third surface electrodes 63A to 63H, the fourth surface electrode 64, the fifth surface electrodes 65A to 65H, and the sixth surface electrodes 66A to 66H are arranged symmetrically within the substrate 20. In the first embodiment, these surface electrodes are arranged in a line-symmetric relationship with respect to an imaginary center line VC extending in the Y-axis direction at the center of the substrate 20 in the X-axis direction. These surface electrodes are also arranged in a line-symmetric relationship with respect to an imaginary center line HC extending in the X-axis direction at the center of the substrate 20 in the Y-axis direction.

[0037] Here, the peripheral area AP of the substrate 20 is divided into four wiring (electrode) arrangement areas based on the two virtual center lines VC and HC described above, and includes a first peripheral area AP1, a second peripheral area AP2, a third peripheral area AP3, and a fourth peripheral area AP4, which correspond to the lower right area, lower left area, upper right area, and upper left area of ​​the substrate 20, respectively, in Fig. 1. The surface electrode layouts within the first to fourth peripheral areas AP1 to AP4 will be described below.

[0038] 3, the first peripheral region AP1 (the lower right region in FIG. 1) is used for arranging the second surface electrodes 62A, 62B, the third surface electrodes 63A, 63B, a part of the fourth surface electrode 64 (the lower right region in FIG. 1), the fifth surface electrodes 65A, 65B, and the sixth surface electrodes 66A, 66B. As described above, the first surface electrodes 61A, 61B are arranged in the central region AC of the substrate 20.

[0039] As described above, each of the first surface electrodes 61A, 61B is used to mount one semiconductor light emitting element 30. The second to fifth surface electrodes 62A, 63A, 64, and 65A are used to mount the drive circuit 40A. The fifth and sixth surface electrodes 65A and 66A are used to mount the protection diode 70A. The second to fifth surface electrodes 62B, 63B, 64, and 65B are used to mount the drive circuit 40B. The fifth and sixth surface electrodes 65B and 66B are used to mount the protection diode 70B.

[0040] Therefore, the fourth surface electrode 64 in the first peripheral area AP1 (the lower right area in FIG. 1 ) is shared by the mounting of the drive circuits 40A and 40B. In this manner, the first peripheral area AP1 of the substrate 20 is allocated to the mounting of the two semiconductor light emitting elements 30, the two drive circuits 40A and 40B, and the two protection diodes 70A and 70B.

[0041] The switching element 411 of the drive circuit 40A is mounted on the second surface electrode 62A. The second surface electrode 62A is located adjacent to or close to the first surface electrode 61A in the Y-axis direction. The drain electrode 41D (see FIG. 7) of the switching element 411 is bonded to the second surface electrode 62A with a conductive bonding material SD (see FIG. 7). The second surface electrode 62A is connected by a wire W1 to the surface electrode 34 (cathode electrode) of the semiconductor light-emitting element 30 mounted on the first surface electrode 61A. Therefore, the drain electrode 41D (see FIG. 7) of the switching element 411 is connected to the surface electrode 34 of the semiconductor light-emitting element 30 on the first surface electrode 61A via the second surface electrode 62A and the wire W1.

[0042] The source electrode 41S of the switching element 411 is connected to the fourth surface electrode 64 by a wire W2. The gate electrode 41G of the switching element 411 is connected to the third surface electrode 63A by a wire W3. The third surface electrode 63A is provided in a position adjacent to or close to the second surface electrode 62A (gate electrode 41G of the switching element 411) in the X-axis direction. The fourth surface electrode 64 includes a portion adjacent to or close to the second surface electrode 62A (mounting area of ​​the switching element 411) in the Y-axis direction.

[0043] The wires W1 to W3 are bonding wires formed by a wire bonding device, and are made of a conductor such as Au, Al, or Cu. The number of each of the wires W1 to W3 is not particularly limited, as long as it is one or more. In the first embodiment, from the perspective of reducing the wiring inductance of the entire circuit, for example, the number of wires W1 and W2 located on the current path CP (see FIG. 11 ) between the switching element 411 and the semiconductor light emitting element 30 is set to a plurality (for example, four or more).

[0044] The four capacitors 421 of the drive circuit 40A are mounted across both the fourth and fifth surface electrodes 64, 65A. The first electrode 42A of each capacitor 421 is joined to the fourth surface electrode 64 by a conductive bonding material SD (see FIG. 7), and the second electrode 42B of each capacitor 421 is joined to the fifth surface electrode 65A by a conductive bonding material SD (see FIG. 7).

[0045] Although not shown in a cross-sectional view, the protection diode 70A is mounted across both the fifth and sixth surface electrodes 65A, 66A. The protection diode 70A includes an anode electrode 71 and a cathode electrode 72. The anode electrode 71 is joined to the sixth surface electrode 66A by a conductive bonding material, and the cathode electrode 72 is joined to the fifth surface electrode 65A by a conductive bonding material.

[0046] The switching element 412 of the drive circuit 40B is mounted on the second surface electrode 62B. The second surface electrode 62B is provided adjacent to or close to the first surface electrode 61B in the X-axis direction. Although a cross-sectional view is omitted, similar to the switching element 411, the drain electrode 41D of the switching element 412 is bonded to the second surface electrode 62B with a conductive bonding material. The second surface electrode 62B is connected by a wire W1 to the surface electrode 34 (cathode electrode) of the semiconductor light-emitting element 30 mounted on the first surface electrode 61B. Therefore, the drain electrode 41D of the switching element 412 is connected to the surface electrode 34 of the semiconductor light-emitting element 30 on the first surface electrode 61B via the second surface electrode 62B and the wire W1.

[0047] The source electrode 41S of the switching element 412 is connected to the fourth surface electrode 64 by a wire W2. The gate electrode 41G of the switching element 412 is connected to the third surface electrode 63B by a wire W3. The third surface electrode 63B is provided in a position adjacent to or close to the second surface electrode 62B (gate electrode 41G of the switching element 412) in the Y-axis direction. The fourth surface electrode 64 includes a portion adjacent to or close to the second surface electrode 62B (mounting area of ​​the switching element 412) in the X-axis direction.

[0048] Here, similarly to the switching element 411, from the viewpoint of reducing the wiring inductance of the entire circuit, the number of wires W1 and W2 located on the current path CP (see FIG. 11) between the switching element 412 and the semiconductor light-emitting element 30 is set to multiple (for example, four or more).

[0049] The four capacitors 422 of the drive circuit 40B are mounted across both the fourth and fifth surface electrodes 64, 65B. Although a cross-sectional view is omitted, similar to the capacitor 421, the first electrode 42A of each capacitor 422 is joined to the fourth surface electrode 64 by a conductive bonding material, and the second electrode 42B of each capacitor 422 is joined to the fifth surface electrode 65B by a conductive bonding material.

[0050] Although not shown in a cross-sectional view, the protection diode 70B is mounted across both the fifth and sixth surface electrodes 65B, 66B. The anode electrode 71 of the protection diode 70B is joined to the sixth surface electrode 66B with a conductive bonding material, and the cathode electrode 72 of the protection diode 70B is joined to the fifth surface electrode 65B with a conductive bonding material.

[0051] 4, the second peripheral region AP2 (the lower left region in FIG. 1) is used for arranging the second surface electrodes 62C, 62D, the third surface electrodes 63C, 63D, the fourth surface electrode 64, the fifth surface electrodes 65C, 65D, and the sixth surface electrodes 66C, 66D. As described above, the first surface electrodes 61C, 61D are arranged in the central region AC of the substrate 20.

[0052] As described above, each of the first surface electrodes 61C, 61D is used to mount one semiconductor light emitting element 30. The second to fifth surface electrodes 62C, 63C, 64, 65C are used to mount the drive circuit 40C. The fifth and sixth surface electrodes 65C, 66C are used to mount the protection diode 70C. The second to fifth surface electrodes 62D, 63D, 64, 65D are used to mount the drive circuit 40D. The fifth and sixth surface electrodes 65D, 66D are used to mount the protection diode 70D.

[0053] Therefore, the area of ​​the fourth surface electrode 64 located within the second peripheral area AP2 is shared by the mounting of the drive circuits 40C and 40D. In this manner, the second peripheral area AP2 of the substrate 20 is allocated to the mounting of the two semiconductor light emitting elements 30, the two drive circuits 40C and 40D, and the two protection diodes 70C and 70D.

[0054] The surface electrodes (and the elements mounted thereon) arranged in the second peripheral region AP2 and the surface electrodes (and the elements mounted thereon) arranged in the first peripheral region AP1 are arranged in a line-symmetric relationship with respect to the imaginary center line VC. Therefore, detailed descriptions of the arrangement of the first surface electrodes 61C, 61D, second surface electrodes 62C, 62D, third surface electrodes 63C, 63D, fourth surface electrode 64, fifth surface electrodes 65C, 65D, and sixth surface electrodes 66C, 66D, as well as the two semiconductor light-emitting elements 30, drive circuits 40C, 40D (switching elements 413, 414 and capacitors 423, 424), and protection diodes 70C, 70D mounted on these surface electrodes will be omitted.

[0055] 5, the third peripheral region AP3 (the upper right region in FIG. 1) is used for arranging the second surface electrodes 62E, 62F, the third surface electrodes 63E, 63F, the fourth surface electrode 64, the fifth surface electrodes 65E, 65F, and the sixth surface electrodes 66E, 66F. As described above, the first surface electrodes 61E, 61F are arranged in the central region AC of the substrate 20.

[0056] As described above, each of the first surface electrodes 61E, 61F is used to mount one semiconductor light emitting element 30. The second to fifth surface electrodes 62E, 63E, 64, 65E are used to mount the drive circuit 40E. The fifth and sixth surface electrodes 65E, 66E are used to mount the protection diode 70E. The second to fifth surface electrodes 62F, 63F, 64, 65F are used to mount the drive circuit 40F. The fifth and sixth surface electrodes 65F, 66F are used to mount the protection diode 70F.

[0057] Therefore, the area of ​​the fourth surface electrode 64 located within the third peripheral area AP3 is shared by the mounting of the drive circuits 40E and 40F. In this manner, the third peripheral area AP3 of the substrate 20 is allocated to the mounting of the two semiconductor light emitting elements 30, the two drive circuits 40E and 40F, and the two protection diodes 70E and 70F.

[0058] The surface electrodes (and the elements mounted thereon) arranged in the third peripheral region AP3 and the surface electrodes (and the elements mounted thereon) arranged in the first peripheral region AP1 are arranged in a line-symmetric relationship with respect to the imaginary center line HC. Therefore, detailed descriptions of the arrangement of the first surface electrodes 61E, 61F, second surface electrodes 62E, 62F, third surface electrodes 63E, 63F, fourth surface electrode 64, fifth surface electrodes 65E, 65F, and sixth surface electrodes 66E, 66F, as well as the two semiconductor light-emitting elements 30, drive circuits 40E, 40F (switching elements 415, 416 and capacitors 425, 426), and protection diodes 70E, 70F mounted on these surface electrodes will be omitted.

[0059] 6, the fourth peripheral region AP4 (the upper left region in FIG. 1) is used for arranging the second surface electrodes 62G, 62H, the third surface electrodes 63G, 63H, the fourth surface electrode 64, the fifth surface electrodes 65G, 65H, and the sixth surface electrodes 66G, 66H. As described above, the first surface electrodes 61G, 61H are arranged in the central region AC of the substrate 20.

[0060] As described above, each of the first surface electrodes 61G, 61H is used to mount one semiconductor light emitting element 30. The second to fifth surface electrodes 62G, 63G, 64, 65G are used to mount the drive circuit 40G. The fifth and sixth surface electrodes 65G, 66G are used to mount the protection diode 70G. The second to fifth surface electrodes 62H, 63H, 64, 65H are used to mount the drive circuit 40H. The fifth and sixth surface electrodes 65H, 66H are used to mount the protection diode 70H.

[0061] Therefore, the area of ​​the fourth surface electrode 64 located within the fourth peripheral area AP4 is shared by the mounting of the drive circuits 40G and 40H. In this manner, the fourth peripheral area AP4 of the substrate 20 is allocated to the mounting of the two semiconductor light emitting elements 30, the two drive circuits 40G and 40H, and the two protection diodes 70G and 70H.

[0062] The surface electrodes (and the elements mounted thereon) arranged in the fourth peripheral region AP4 and the surface electrodes (and the elements mounted thereon) arranged in the second peripheral region AP2 are arranged in a line-symmetric relationship with respect to the imaginary center line HC. The surface electrodes (and the elements mounted thereon) arranged in the fourth peripheral region AP4 and the surface electrodes (and the elements mounted thereon) arranged in the third peripheral region AP3 are arranged in a line-symmetric relationship with respect to the imaginary center line VC. Therefore, detailed descriptions of the arrangements of the first surface electrodes 61G, 61H, second surface electrodes 62G, 62H, third surface electrodes 63G, 63H, fourth surface electrode 64, fifth surface electrodes 65G, 65H, and sixth surface electrodes 66G, 66H, as well as the two semiconductor light-emitting elements 30, drive circuits 40G, 40H (switching elements 417, 418 and capacitors 427, 428), and protection diodes 70G, 70H mounted on these surface electrodes will be omitted.

[0063] 7, the main surface resist layer 29A includes a plurality of openings that expose portions of the first electrode layer 28A. The plurality of semiconductor light emitting elements 30, the components of the drive circuits 40A-40H, and the protection diodes 70A-70H are mounted on the portions of the first electrode layer 28A exposed by the openings in the main surface resist layer 29A. Note that in FIGS. 1 to 6, the openings in the main surface resist layer 29A are indicated by two-dot chain lines.

[0064] 9 , the second electrode layer 28B (rear electrode layer) located on the rear surface 22 of the substrate 20 includes a plurality of rear electrodes (pattern electrodes) spaced apart from one another. These rear electrodes function as external electrode terminals electrically connected to a circuit board (not shown) when the semiconductor light emitting device 10 is mounted on the circuit board. In the first embodiment, the second electrode layer 28B includes first rear electrodes 81A-81H, second rear electrodes 82A-82H, third rear electrodes 83A-83H, fourth rear electrodes 84A-84D, and fifth rear electrodes 85A-85H.

[0065] The first back-surface electrodes 81A-81H, the second back-surface electrodes 82A-82H, the third back-surface electrodes 83A-83H, the fourth back-surface electrodes 84A-84D, and the fifth back-surface electrodes 85A-85H are arranged in a line-symmetric relationship with respect to each of the two imaginary center lines VC and HC. As described above, the peripheral region AP includes first to fourth peripheral regions AP1-AP4 as four wiring arrangement regions divided based on the imaginary center lines VC and HC. When the substrate 20 is viewed from the rear surface 22, the first peripheral region AP1, the second peripheral region AP2, the third peripheral region AP3, and the fourth peripheral region AP4 correspond to the lower left region, lower right region, upper left region, and upper right region of the substrate 20, respectively, in FIG. 9 . The rear surface electrode layouts within the first to fourth peripheral regions AP1-AP4 will be described below.

[0066] The first peripheral region AP1 (the lower left region in Figure 9) is used for arranging the first back surface electrodes 81A, 81B, the second back surface electrodes 82A, 82B, the third back surface electrodes 83A, 83B, the fourth back surface electrode 84A, and the fifth back surface electrodes 85A, 85B.

[0067] The first to fifth back electrodes 81A, 82A, 83A, 84A, and 85A are provided for electrical connection between the drive circuit 40A (switching element 411 and capacitor 421), one semiconductor light-emitting element 30 to be driven by the drive circuit 40A, and the protection diode 70A.

[0068] The first back surface electrode 81A is disposed at a position overlapping the first and fifth surface electrodes 61A, 65A (see FIG. 3) in a plan view. The first back surface electrode 81A is formed, for example, in a strip shape extending in the Y-axis direction. The second back surface electrode 82A is disposed at a position overlapping the second surface electrode 62A (see FIG. 3) in a plan view. The second back surface electrode 82A is formed, for example, in an oval shape, and is disposed adjacent to or close to the first back surface electrode 81A in the X-axis direction.

[0069] The third back surface electrode 83A is arranged in a position overlapping the third surface electrode 63A (see FIG. 3) in a plan view. The third back surface electrode 83A is formed, for example, in a curved strip shape shorter than the first back surface electrode 81A in the Y-axis direction, and is provided adjacent to or close to the first back surface electrode 81A in the X-axis direction. The fourth back surface electrode 84A is arranged in a position overlapping a portion of the fourth surface electrode 64 (see FIG. 3) in the first peripheral region AP1 in a plan view. The fifth back surface electrode 85A is arranged in a position overlapping the sixth surface electrode 66A (see FIG. 3) in a plan view. The fifth back surface electrode 85A is formed, for example, in an oval shape, and is located between the first back surface electrode 81A and the third back surface electrode 83A in the X-axis direction.

[0070] The first to fifth rear surface electrodes 81B, 82B, 83B, 84A, and 85B are provided for electrical connection between the drive circuit 40B (switching element 412 and capacitor 422), one semiconductor light-emitting element 30 to be driven by the drive circuit 40B, and the protection diode 70B.

[0071] The first back surface electrode 81B is disposed at a position overlapping the first and fifth surface electrodes 61B, 65B (see FIG. 3) in a plan view. The first back surface electrode 81B is formed, for example, in a strip shape extending in the X-axis direction. The second back surface electrode 82B is disposed at a position overlapping the second surface electrode 62B (see FIG. 3) in a plan view. The second back surface electrode 82B is formed, for example, in an oval shape, and is disposed adjacent to or close to the first back surface electrode 81B in the Y-axis direction.

[0072] The third back surface electrode 83B is disposed at a position overlapping with the third surface electrode 63B (see FIG. 3) in a plan view. The third back surface electrode 83B is formed, for example, in a curved strip shape with a dimension shorter than that of the first back surface electrode 81B in the X-axis direction, and is disposed adjacent to or close to the first back surface electrode 81B in the Y-axis direction. The fifth back surface electrode 85B is disposed at a position overlapping with the sixth surface electrode 66B (see FIG. 3) in a plan view. The sixth back surface electrode 85B is formed, for example, in an oval shape, and is located between the first back surface electrode 81B and the third back surface electrode 83B in the Y-axis direction.

[0073] The second peripheral region AP2 (the lower right region in Figure 9) is used for arranging the first back surface electrodes 81C, 81D, the second back surface electrodes 82C, 82D, the third back surface electrodes 83C, 83D, the fourth back surface electrode 84B, and the fifth back surface electrodes 85C, 85D.

[0074] The first to fifth back surface electrodes 81C, 82C, 83C, 84B, and 85C are provided for electrical connection between the drive circuit 40C (switching element 413 and capacitor 423), one semiconductor light emitting element 30 to be driven by the drive circuit 40C, and the protection diode 70C. The first to fifth back surface electrodes 81D, 82D, 83D, 84B, and 85D are provided for electrical connection between the drive circuit 40D (switching element 414 and capacitor 424), one semiconductor light emitting element 30 to be driven by the drive circuit 40D, and the protection diode 70D.

[0075] The back-surface electrodes arranged in the second peripheral region AP2 and the back-surface electrodes arranged in the first peripheral region AP1 are arranged in a line-symmetric relationship with respect to the imaginary center line VC. Therefore, detailed description of the arrangement of the first back-surface electrodes 81C, 81D, second back-surface electrodes 82C, 82D, third back-surface electrodes 83C, 83D, fourth back-surface electrode 84B, and fifth back-surface electrodes 85C, 85D will be omitted.

[0076] The third peripheral region AP3 (upper left region in Figure 9) is used for arranging the first back surface electrodes 81E, 81F, the second back surface electrodes 82E, 82F, the third back surface electrodes 83E, 83F, the fourth back surface electrode 84C, and the fifth back surface electrodes 85E, 85F.

[0077] The first to fifth rear surface electrodes 81E, 82E, 83E, 84C, and 85E are provided for electrical connection between the drive circuit 40E (switching element 415 and capacitor 425), one semiconductor light emitting element 30 to be driven by the drive circuit 40E, and the protection diode 70E. The first to fifth rear surface electrodes 81F, 82F, 83F, 84C, and 85F are provided for electrical connection between the drive circuit 40F (switching element 416 and capacitor 426), one semiconductor light emitting element 30 to be driven by the drive circuit 40F, and the protection diode 70F.

[0078] The back-surface electrodes arranged in the third peripheral region AP3 and the back-surface electrodes arranged in the first peripheral region AP1 are arranged in a line-symmetric relationship with respect to the imaginary center line HC. Therefore, detailed description of the arrangement of the first back-surface electrodes 81E, 81F, second back-surface electrodes 82E, 82F, third back-surface electrodes 83E, 83F, fourth back-surface electrode 84C, and fifth back-surface electrodes 85E, 85F will be omitted.

[0079] The fourth peripheral region AP4 (the upper right region in Figure 9) is used for arranging the first back surface electrodes 81G, 81H, the second back surface electrodes 82G, 82H, the third back surface electrodes 83G, 83H, the fourth back surface electrode 84D, and the fifth back surface electrodes 85G, 85H.

[0080] The first to fifth back surface electrodes 81G, 82G, 83G, 84D, and 85G are provided for electrical connection between the drive circuit 40G (switching element 417 and capacitor 427), one semiconductor light emitting element 30 to be driven by the drive circuit 40G, and the protection diode 70G. The first to fifth back surface electrodes 81H, 82H, 83H, 84D, and 85H are provided for electrical connection between the drive circuit 40H (switching element 418 and capacitor 428), one semiconductor light emitting element 30 to be driven by the drive circuit 40H, and the protection diode 70H.

[0081] The back-surface electrodes arranged in the fourth peripheral region AP4 and the second peripheral region AP2 are arranged in a line-symmetric relationship with respect to the imaginary center line HC. The back-surface electrodes arranged in the fourth peripheral region AP4 and the third peripheral region AP3 are arranged in a line-symmetric relationship with respect to the imaginary center line VC. Therefore, detailed descriptions of the arrangements of the first back-surface electrodes 81G, 81H, second back-surface electrodes 82G, 82H, third back-surface electrodes 83G, 83H, fourth back-surface electrode 84D, and fifth back-surface electrodes 85G, 85H will be omitted.

[0082] As shown in Fig. 7, the back surface resist layer 29B includes a plurality of openings that expose portions of the second electrode layer 28B. The semiconductor light emitting device 10 is mounted on a circuit board (not shown) using the portions of the second electrode layer 28B exposed by the openings in the back surface resist layer 29B. Therefore, the semiconductor light emitting device 10 can be said to be a surface-mounted device mounted on a circuit board. In Fig. 9, the openings in the back surface resist layer 29B are indicated by two-dot chain lines.

[0083] [1-5C. Third and Fourth Electrode Layers (Intermediate Electrode Layers)] As shown in FIG. 7 , the third and fourth electrode layers 28C, 28D, which are intermediate electrode layers, are embedded in the substrate 20. The third electrode layer 28C, which serves as the front-side intermediate electrode layer, is located between the first substrate 27A, which includes the main surface 21 of the substrate 20, and the third substrate 27C, which is located midway in the thickness direction of the substrate 20. Meanwhile, the fourth electrode layer 28D, which serves as the back-side intermediate electrode layer, is located between the second substrate 27B, which includes the back surface 22 of the substrate 20, and the third substrate 27C. In the first embodiment, the third electrode layer 28C (front-side intermediate electrode layer) and the fourth electrode layer 28D (back-side intermediate electrode layer) have the same structure. Therefore, the following description will focus on the third electrode layer 28C, and a detailed description of the fourth electrode layer 28D will be omitted.

[0084] 10, the third electrode layer 28C includes a plurality of intermediate electrodes (pattern electrodes) spaced apart from one another. In the first embodiment, the third electrode layer 28C includes first intermediate electrodes 91A to 91H, second intermediate electrodes 92A to 92H, third intermediate electrodes 93A to 93H, and fourth intermediate electrodes 94A to 94D.

[0085] The first intermediate electrodes 91A-91H, the second intermediate electrodes 92A-92H, the third intermediate electrodes 93A-93H, and the fourth intermediate electrodes 94A-94D are arranged in a line-symmetric relationship with respect to each of the two imaginary center lines VC and HC. As described above, the peripheral region AP includes first to fourth peripheral regions AP1-AP4 as four wiring arrangement regions divided based on the imaginary center lines VC and HC. The first peripheral region AP1, the second peripheral region AP2, the third peripheral region AP3, and the fourth peripheral region AP4 correspond to the lower right region, the lower left region, the upper right region, and the upper left region of the substrate 20, respectively, in FIG. 10. The layout of the intermediate electrodes within the first to fourth peripheral regions AP1-AP4 will be described below.

[0086] The first peripheral area AP1 (the lower right area in FIG. 10) is used for arranging first intermediate electrodes 91A and 91B, second intermediate electrodes 92A and 92B, third intermediate electrodes 93A and 93B, and a fourth intermediate electrode 94A.

[0087] The first to fourth intermediate electrodes 91A, 92A, 93A, and 94A are provided for electrical connection between the drive circuit 40A (switching element 411 and capacitor 421), one semiconductor light-emitting element 30 to be driven by the drive circuit 40A, and the protection diode 70A.

[0088] The first intermediate electrode 91A is formed in an elongated shape in the Y-axis direction, and is positioned so that it overlaps with the first and fifth surface electrodes 61A, 65A (see Figure 3) in a planar view, as well as with the first back surface electrode 81A (see Figure 9).

[0089] The second intermediate electrode 92A is disposed at a position overlapping the second and sixth front surface electrodes 62A, 66A (see FIG. 3) and the second and fifth rear surface electrodes 82A, 85A (see FIG. 9) in a plan view. The second intermediate electrode 92A is formed, for example, in a curved strip shape with a dimension shorter in the Y-axis direction than the first intermediate electrode 91A, and is disposed adjacent to or close to the first intermediate electrode 91A in the X-axis direction.

[0090] The third intermediate electrode 93A is disposed at a position overlapping the third surface electrode 63A (see FIG. 3) and the third back surface electrode 83A (see FIG. 9) in a plan view. The third intermediate electrode 93A is formed, for example, in a circular shape. The fourth intermediate electrode 94A is disposed at a position overlapping a portion of the fourth surface electrode 64 (see FIG. 3) in the first peripheral region AP1 and also overlapping the fourth back surface electrode 84A (see FIG. 9) in a plan view. The fourth intermediate electrode 94A is formed, for example, in a rectangular shape.

[0091] The first to fourth intermediate electrodes 91B, 92B, 93B, and 94A are provided for electrical connection between the drive circuit 40B (switching element 412 and capacitor 422), one semiconductor light-emitting element 30 to be driven by the drive circuit 40B, and the protection diode 70B.

[0092] The first intermediate electrode 91B is formed in an elongated shape in the X-axis direction, and is positioned so that it overlaps with the first and fifth surface electrodes 61B, 65B (see Figure 3) in a planar view, as well as with the first back surface electrode 81B (see Figure 9).

[0093] The second intermediate electrode 92B is disposed at a position overlapping the second and sixth front surface electrodes 62B, 66B (see FIG. 3) and the second and fifth rear surface electrodes 82B, 85B (see FIG. 9) in a plan view. The second intermediate electrode 92B is formed, for example, in a curved strip shape with a dimension shorter in the X-axis direction than the first intermediate electrode 91B, and is disposed adjacent to or close to the second intermediate electrode 91B in the Y-axis direction.

[0094] The third intermediate electrode 93B is disposed at a position overlapping the third front surface electrode 63B (see FIG. 3) and the third back surface electrode 83B (see FIG. 9) in a plan view. The third intermediate electrode 93B is formed in, for example, a circular shape.

[0095] The second peripheral area AP2 (the lower left area in FIG. 10) is used for arranging the first intermediate electrodes 91C and 91D, the second intermediate electrodes 92C and 92D, the third intermediate electrodes 93C and 93D, and the fourth intermediate electrode 94B.

[0096] The first to fourth intermediate electrodes 91C, 92C, 93C, and 94B are provided for electrically connecting the drive circuit 40C (switching element 413 and capacitor 423), one semiconductor light-emitting element 30 to be driven by the drive circuit 40C, and the protection diode 70C. The first intermediate electrodes 91D, 92D, 93D, and 94B are provided for electrically connecting the drive circuit 40D (switching element 414 and capacitor 424), one semiconductor light-emitting element 30 to be driven by the drive circuit 40D, and the protection diode 70D.

[0097] The intermediate electrodes arranged in the second peripheral region AP2 and the intermediate electrodes arranged in the first peripheral region AP1 are arranged in a line-symmetric relationship with respect to the imaginary center line VC. Therefore, detailed description of the arrangement of the first intermediate electrodes 91C, 91D, second intermediate electrodes 92C, 92D, third intermediate electrodes 93C, 93D, and fourth intermediate electrode 94B will be omitted.

[0098] The third peripheral region AP3 (the upper right region in FIG. 10) is used for arranging the first intermediate electrodes 91E and 91F, the second intermediate electrodes 92E and 92F, the third intermediate electrodes 93E and 93F, and the fourth intermediate electrode 94C.

[0099] The first to fourth intermediate electrodes 91E, 92E, 93E, and 94C are provided for electrical connection between the drive circuit 40E (switching element 415 and capacitor 425), one semiconductor light-emitting element 30 to be driven by the drive circuit 40E, and the protection diode 70E. The first to fourth intermediate electrodes 91F, 92F, 93F, and 94C are provided for electrical connection between the drive circuit 40F (switching element 416 and capacitor 426), one semiconductor light-emitting element 30 to be driven by the drive circuit 40F, and the protection diode 70F.

[0100] The intermediate electrodes arranged in the third peripheral region AP3 and the intermediate electrodes arranged in the first peripheral region AP1 are arranged in a line-symmetric relationship with respect to the imaginary center line HC. Therefore, detailed description of the arrangement of the first intermediate electrodes 91E, 91F, the second intermediate electrodes 92E, 92F, the third intermediate electrodes 93E, 93F, and the fourth intermediate electrode 94C will be omitted.

[0101] The fourth peripheral region AP4 (upper left region in FIG. 10) is used for arranging the first intermediate electrodes 91G and 91H, the second intermediate electrodes 92G and 92H, the third intermediate electrodes 93G and 93H, and the fourth intermediate electrode 94D.

[0102] The first to fourth intermediate electrodes 91G, 92G, 93G, and 94D are provided for electrically connecting the drive circuit 40G (switching element 417 and capacitor 427), one semiconductor light-emitting element 30 to be driven by the drive circuit 40G, and the protection diode 70G. The first to fourth intermediate electrodes 91H, 92H, 93H, and 94D are provided for electrically connecting the drive circuit 40H (switching element 418 and capacitor 428), one semiconductor light-emitting element 30 to be driven by the drive circuit 40H, and the protection diode 70H.

[0103] The intermediate electrodes arranged in the fourth peripheral region AP4 and the intermediate electrodes arranged in the second peripheral region AP2 are arranged in a line-symmetric relationship with respect to the imaginary center line HC. Also, the intermediate electrodes arranged in the fourth peripheral region AP4 and the intermediate electrodes arranged in the third peripheral region AP3 are arranged in a line-symmetric relationship with respect to the imaginary center line VC. Therefore, detailed description of the arrangement of the first intermediate electrodes 91G, 91H, second intermediate electrodes 92G, 92H, third intermediate electrodes 93G, 93H, and fourth intermediate electrode 94D will be omitted.

[0104] [1-6. Connection Structure Between Electrode Layers] The substrate 20 includes a plurality of vias (connection conductors) that electrically connect the first electrode layer 28A (front electrode layer), the second electrode layer 28B (rear electrode layer), and the third and fourth electrode layers 28C, 28D (intermediate electrode layers). For example, as shown in FIGS. 3 to 10 , the substrate 20 includes first vias 101A-101H, second vias 102A-102H, third vias 103A-103H, fourth vias 104A-104D, fifth vias 105A-105H, and sixth vias 106A-106H that penetrate the first to third base materials 27A-27C and the third and fourth electrode layers 28C, 28D, respectively, in the thickness direction of the substrate 20. Note that these multiple vias may also penetrate the first and second electrode layers 28A, 28B. The vias are formed of one or more materials selected from the group including Ti, TiN, Au, Ag, Cu, Al, and W, for example.

[0105] As shown in Figures 3 to 6, 9, and 10, the first vias 101A to 101H are located in a central region AC of the substrate 20. The second vias 102A to 102H, the third vias 103A to 103H, the fourth vias 104A to 104D, the fifth vias 105A to 105H, and the sixth vias 106A to 106H are located in a peripheral region AP of the substrate 20 and are arranged in a line-symmetric relationship with respect to each of two imaginary center lines VC and HC. As described above, the peripheral region AP includes first to fourth peripheral regions AP1 to AP4 that are divided based on the imaginary center lines VC and HC. The layout of the multiple vias in the first to fourth peripheral regions AP1 to AP4 will be described below.

[0106] The first peripheral area AP1 includes first vias 101A and 101B, second vias 102A and 102B, third vias 103A and 103B, fourth via 104A, fifth vias 105A and 105B, and sixth vias 106A and 106B.

[0107] The first vias 101A electrically connect the first surface electrode 61A of the first electrode layer 28A, the first back surface electrode 81A of the second electrode layer 28B, and the first intermediate electrodes 91A of the third and fourth electrode layers 28C and 28D. The number of first vias 101A is not particularly limited and may be, for example, one or more per semiconductor light emitting element 30. In the first embodiment, for example, a large number of first vias 101A are arranged in a matrix (e.g., 3 × 3) using almost the entire area of ​​the electrode overlap portion available for arranging the first vias 101A.

[0108] The second vias 102A electrically connect the second surface electrode 62A of the first electrode layer 28A, the second back surface electrode 82A of the second electrode layer 28B, and the second intermediate electrodes 92A of the third and fourth electrode layers 28C and 28D. The number of second vias 102A is not particularly limited, and may be one or more at positions where the second surface electrode 62A, the second back surface electrode 82A, and the two second intermediate electrodes 92A overlap, for example.

[0109] The third via 103A electrically connects the third surface electrode 63A of the first electrode layer 28A, the third back surface electrode 83A of the second electrode layer 28B, and the third intermediate electrodes 93A of the third and fourth electrode layers 28C and 28D. The number of third vias 103A is not particularly limited, and may be one or more at positions where the third surface electrode 63A, the third back surface electrode 83A, and the two third intermediate electrodes 93A overlap, for example.

[0110] The fourth via 104A electrically connects the fourth surface electrode 64 of the first electrode layer 28A, the fourth back surface electrode 84A of the second electrode layer 28B, and the fourth intermediate electrodes 94A of the third and fourth electrode layers 28C and 28D. The number of fourth vias 104A is not particularly limited, and may be, for example, one or more at positions where the fourth surface electrode 64, the fourth back surface electrode 84A, and the two fourth intermediate electrodes 94A overlap. In the first embodiment, for example, a large number of fourth vias 104A are arranged in a matrix (e.g., 4 × 8) using almost the entire area of ​​the electrode overlapping portion available for arranging the fourth vias 104A.

[0111] The fifth vias 105A electrically connect the fifth surface electrode 65A of the first electrode layer 28A, the first back surface electrode 81A of the second electrode layer 28B, and the first intermediate electrodes 91A of the third and fourth electrode layers 28C and 28D. The number of fifth vias 105A is not particularly limited, and may be, for example, one or more at positions where the fifth surface electrode 65A, the first back surface electrode 81A, and the two first intermediate electrodes 91A overlap. In the first embodiment, for example, a large number of fifth vias 105A are arranged in a matrix (e.g., 2 × 5) using the electrode overlap area available for arranging the fifth vias 105A.

[0112] The sixth via 106A electrically connects the sixth surface electrode 66A of the first electrode layer 28A, the fifth back surface electrode 85A of the second electrode layer 28B, and the second intermediate electrodes 92A of the third and fourth electrode layers 28C and 28D. The number of sixth vias 106A is not particularly limited, and may be one or more at a position where the sixth surface electrode 66A, the fifth back surface electrode 85A, and the two second intermediate electrodes 92A overlap.

[0113] In the first peripheral area AP1, the first, second, third, fifth, and sixth vias 101B, 102B, 103B, 105B, and 106B are arranged in the same manner as the above-described first, second, third, fifth, and sixth vias 101A, 102A, 103A, 105A, and 106A, and therefore detailed description of the first, second, third, fifth, and sixth vias 101B, 102B, 103B, 105B, and 106B will be omitted.

[0114] The second peripheral area AP2 includes the first vias 101C and 101D, the second vias 102C and 102D, the third vias 103C and 103D, the fourth via 104B, the fifth vias 105C and 105D, and the sixth vias 106C and 106D. The third peripheral area AP3 includes the first vias 101E and 101F, the second vias 102E and 102F, the third vias 103E and 103F, the fourth via 104C, the fifth vias 105E and 105F, and the sixth vias 106E and 106F. The fourth peripheral area AP4 includes first vias 101G and 101H, second vias 102G and 102H, third vias 103G and 103H, fourth via 104D, fifth vias 105G and 105H, and sixth vias 106G and 106H. The arrangement of these vias in the second to fourth peripheral areas AP2 to AP4 is similar to the arrangement of the vias in the first peripheral area AP1 described above, and therefore detailed description thereof will be omitted.

[0115] [1-7. Current Path of Semiconductor Light-Emitting Device] The semiconductor light-emitting device 10 is embodied as a multi-channel drive type light-emitting module in which a plurality of drive circuits 40 each drive one or more (one in the first embodiment) semiconductor light-emitting elements 30. As described above, in the semiconductor light-emitting device 10, the drive circuits 40 are mounted on the substrate 20 together with the semiconductor light-emitting elements 30. Therefore, a current path between each drive circuit 40 and the semiconductor light-emitting element 30 that it drives is formed within the substrate 20.

[0116] FIG. 11 shows a current path CP (path indicated by an arrow) of a current flowing through the drive circuit 40A (switching element 411 and capacitor 421) and the semiconductor light emitting element 30 to be driven by the drive circuit 40A.

[0117] The current path CP is configured in the form of a loop in which current flows in the following order: the second electrode 42B of the capacitor 421, the fifth surface electrode 65A of the first electrode layer 28A (surface electrode layer), the fifth via 105A, the first intermediate electrode 91A of the third electrode layer 28C (surface-side intermediate electrode layer), the first via 101A, the first surface electrode 61A of the first electrode layer 28A, the back electrode 35 (anode electrode) of the semiconductor light-emitting element 30, the surface electrode 34 (cathode electrode) of the semiconductor light-emitting element 30, the wire W1, the second surface electrode 62A of the first electrode layer 28A, the drain electrode 41D of the switching element 411, the source electrode 41S of the switching element 411, the wire W2, the fourth surface electrode 64 of the first electrode layer 28A, and the first electrode 42A of the capacitor 421. As described above, a protection diode 70A is connected in anti-parallel to the semiconductor light-emitting element 30 to be driven by the drive circuit 40A.

[0118] Although detailed description is omitted here, the other drive circuits 40B to 40H are also electrically connected in the same manner as the drive circuit 40A, and each of them has a loop-shaped current path similar to the above-described current path CP. The other protection diodes 70B to 70H are also electrically connected in the same manner as the protection diode 70A.

[0119] 12, a light-emitting system 200 including a semiconductor light-emitting device 10 includes a DC power supply 201, a capacitor 202 connected in parallel to the DC power supply 201, a current-limiting resistor 203, backflow prevention diodes 204A-204H, gate drivers 205A-205H, pulse generators 206A-206H, and control power supplies 207A-207H. For clarity, drive circuits 40C-40F, semiconductor light-emitting elements 30 to be driven by drive circuits 40C-40F, protection diodes 70C-70F, backflow prevention diodes 204C-204F, gate drivers 205C-205F, pulse generators 206C-206F, and control power supplies 207C-207F are not shown in FIG. The backflow prevention diodes 204A to 204H, the gate drivers 205A to 205H, the pulse generators 206A to 206H, and the control power supplies 207A to 207H are provided corresponding to the drive circuits 40A to 40H, respectively.

[0120] The DC power supply 201, the capacitor 202, and the current-limiting resistor 203 are configured to supply current to the semiconductor light-emitting elements 30 and the drive circuits 40A to 40H. The DC power supply 201, the capacitor 202, and the current-limiting resistor 203 are an example of a power supply input unit. A first terminal of the current-limiting resistor 203 is electrically connected to the positive electrode of the DC power supply 201.

[0121] The anodes of the backflow prevention diodes 204A to 204H are electrically connected to the second terminal of the current limiting resistor 203. The cathodes of the backflow prevention diodes 204A to 204H are electrically connected to the back surface electrodes 35 (anode electrodes) of the respective semiconductor light emitting elements 30 and the second electrodes 42B of the capacitors 421 to 428 via the second back surface electrodes 82A to 82H.

[0122] The gate drivers 205A to 205H are electrically connected to the gate electrodes 41G of the switching elements 411 to 418 of the drive circuits 40A to 40H, respectively. In the first embodiment, the gate drivers 205A to 205H are electrically connected to the third rear surface electrodes 83A to 83H, which are electrically connected to the gate electrodes 41G of the switching elements 411 to 418, respectively. The gate drivers 205A to 205H are configured to apply gate voltage signals to the gate electrodes 41G of the switching elements 411 to 418, respectively, to individually drive the switching elements 411 to 418.

[0123] The pulse generators 206A to 206H and the control power supplies 207A to 207H are electrically connected to the gate drivers 205A to 205H, respectively. The pulse generators 206A to 206H are configured to output pulse signals to the gate drivers 205A to 205H, respectively, for controlling the switching elements 411 to 418. The control power supplies 207A to 207H are configured to apply operating voltages to the gate drivers 205A to 205H, respectively.

[0124] The negative electrode of the DC power supply 201, the capacitor 202, the pulse generators 206A to 206H, the first electrodes 42A of the capacitors 421 to 428, the negative electrodes of the control power supplies 207A to 207H, and the source electrodes 41S of the switching elements 411 to 418 are electrically connected to a ground terminal (the fourth back surface electrodes 84A to 84D of the second electrode layer 28B) via ground wiring (the fourth surface electrode 64 of the first electrode layer 28A and the fourth intermediate electrodes 94A to 94D of the third and fourth electrode layers 28C, 28D).

[0125] The drain electrodes 41D of the switching elements 411 to 418 are electrically connected to the front surface electrodes 34 (cathode electrodes) of the corresponding semiconductor light emitting elements 30 and the anode electrodes 71 of the protection diodes 70A to 70H. The cathode electrodes 72 of the protection diodes 70A to 70H are electrically connected to the rear surface electrodes 35 (anode electrodes) of the corresponding semiconductor light emitting elements 30.

[0126] In the semiconductor light-emitting device 10 configured as described above, when the switching elements 411 to 418 of the drive circuits 40A to 40H are in the OFF state, the capacitors 421 to 428 are charged by the DC power supply 201. When the switching elements 411 to 418 are switched from the OFF state to the ON state, a current flows from the capacitors 421 to 428 to each semiconductor light-emitting element 30 to be controlled via the switching elements 411 to 418. This causes the semiconductor light-emitting element 30 to emit pulsed laser light. In this way, each drive circuit 40A to 40H is configured to individually drive the semiconductor light-emitting element 30.

[0127] As an example, the drive circuits 40A-40H sequentially drive the semiconductor light-emitting elements 30 to be driven. In this case, the pulsed light emission of each semiconductor light-emitting element 30 can be adjusted so that the pulse interval of the laser light emitted from the semiconductor light-emitting device 10 is shorter, compared to a semiconductor light-emitting device having, for example, only one semiconductor light-emitting element. This allows for an increase in the number of pulses per unit time. Furthermore, by having the semiconductor light-emitting elements 30 to be driven by the drive circuits 40A-40H emit light in sequence, heat generation from each semiconductor light-emitting element 30 can be suppressed, compared to a semiconductor light-emitting device having only one semiconductor light-emitting element.

[0128] [1-9. Operation of Semiconductor Light-Emitting Device] In recent years, there has been an increasing demand for higher output power semiconductor light-emitting devices. For example, when semiconductor light-emitting devices are applied to laser systems such as LiDAR, a wider viewing angle and improved resolution are required. To meet these demands, the semiconductor light-emitting device 10 of the first embodiment is embodied as a multi-channel (eight channels in the first embodiment) drive-type light-emitting module that drives multiple semiconductor light-emitting elements 30 using multiple (eight in the first embodiment) drive circuits 40A to 40H.

[0129] In the first embodiment, a plurality of (e.g., eight) semiconductor light-emitting elements 30 configured as light-emitting elements (e.g., PCSEL elements) that emit light in a direction intersecting the main surface 21 of the substrate 20 are collectively arranged in a central region AC of the substrate 20. In this configuration, compared to when a plurality of semiconductor light-emitting elements configured as edge-emitting elements are arranged at the edge of the substrate 20, a greater number of semiconductor light-emitting elements 30 can be mounted in the semiconductor light-emitting device 10 with a high degree of layout freedom without being subject to design constraints such as wiring layout. This allows the number of channels to be increased, thereby achieving a wider viewing angle and improved resolution, as required, for example, in LiDAR.

[0130] [1-10. Advantages of the Semiconductor Light-Emitting Device] The semiconductor light-emitting device 10 of the first embodiment has the following advantages. (1-1) The semiconductor light-emitting device 10 includes a plurality of semiconductor light-emitting elements 30 and a plurality of drive circuits 40A-40H that each drive one or more of the semiconductor light-emitting elements 30 (one in the first embodiment). That is, the semiconductor light-emitting device 10 is embodied as a multi-channel (eight-channel in the example of FIG. 1 ) drive-type light-emitting module. Furthermore, each semiconductor light-emitting element 30 employs a light-emitting element that emits light in a direction intersecting with the main surface 21 of the substrate 20. With this configuration, compared to when the semiconductor light-emitting elements 30 are arranged at the edge of the substrate 20, a greater number of semiconductor light-emitting elements 30 can be mounted on the semiconductor light-emitting device 10 with a high degree of layout freedom without being subject to design constraints such as wiring layout.

[0131] (1-2) A PCSEL element is used for each semiconductor light-emitting element 30. The PCSEL element is capable of high-power operation (high-brightness operation) by emitting a beam with high beam quality and a narrow divergence angle. In particular, the beam divergence angle can be made extremely small (e.g., 1° or less) compared to edge-emitting elements, so that a collimating lens, for example, that is required when using edge-emitting elements, can be omitted. This reduces the number of parts, thereby enabling the size of each semiconductor light-emitting element 30 and, therefore, the miniaturization and cost reduction of the semiconductor light-emitting device 10 (light-emitting module).

[0132] (1-3) The PCSEL element has the characteristics of a narrow wavelength spectrum width and little temperature dependency of the operating wavelength, which can, for example, reduce optical noise and improve the optical characteristics of the semiconductor light-emitting device 10 (light-emitting module). This is advantageous when the semiconductor light-emitting device 10 is applied to a laser system such as LiDAR.

[0133] (1-4) Since the semiconductor light emitting elements 30 are concentrated in the central region AC of the substrate 20, it is possible to improve the degree of freedom in the wiring design of the drive circuits 40A to 40H that drive the semiconductor light emitting elements 30 and the associated circuit elements. As a result, it is possible to further increase the number of channels.

[0134] (1-5) A plurality of semiconductor light emitting elements 30 are arranged adjacent to one another in a matrix in the central region AC of the substrate 20. This allows even more semiconductor light emitting elements 30 to be mounted on the semiconductor light emitting device 10.

[0135] (1-6) The multiple drive circuits 40A to 40H are arranged in a peripheral area AP surrounding the central area AC of the substrate 20. This allows, for example, multiple semiconductor light emitting elements 30 to be collectively arranged in the central area AC of the substrate 20, while the multiple drive circuits 40A to 40H can be mounted in the peripheral area AP of the substrate 20 with a high degree of design freedom. This further promotes multi-channelization.

[0136] (1-7) The peripheral area AP of the substrate 20 includes first to fourth peripheral areas AP1 to AP4, which are divided based on two imaginary center lines VC and HC, and the multiple drive circuits 40A to 40H are each disposed in one of the first to fourth peripheral areas AP1 to AP4. In this configuration, the multiple drive circuits 40A to 40H can be disposed in line symmetry within the first to fourth peripheral areas AP1 to AP4, which are divided by the two imaginary center lines VC and HC, i.e., around the multiple semiconductor light emitting elements 30 mounted in the central area AC. This simplifies the wiring layout design while achieving multi-channelization.

[0137] (1-8) Two or more of the plurality of drive circuits 40A to 40H are arranged in each of the first to fourth peripheral regions AP1 to AP4. This allows the drive circuits 40A to 40H to be arranged efficiently when eight or more semiconductor light emitting elements 30 are mounted on the semiconductor light emitting device 10.

[0138] (1-9) The semiconductor light-emitting device 10 includes multiple semiconductor light-emitting elements 30 and drive circuits 40A-40H that drive the multiple semiconductor light-emitting elements 30. In this configuration, the current paths CP of the currents flowing through each drive circuit 40 and the semiconductor light-emitting elements 30 they drive are formed on the substrate 20, thereby shortening the current paths CP compared to when the drive circuits 40A-40H are provided external to the semiconductor light-emitting device 10. This reduces the inductance due to the length of the current paths CP and the inductance variation of each current path CP. As a result, the pulse width of the laser light emitted by each semiconductor light-emitting element 30 can be shortened, thereby reducing the variation in pulse width. In one example, the pulse width of the laser light emitted by each semiconductor light-emitting element 30 is 4 ns or less. In another example, the absolute value of the variation in the pulse width of the laser light emitted by each semiconductor light-emitting element 30 is 10% or less.

[0139] (1-10) Each drive circuit 40 includes multiple capacitors connected in parallel. For example, drive circuit 40A includes four capacitors 421 connected in parallel, and the other drive circuits 40B to 40H also include the same number of capacitors. This configuration can reduce inductance compared to when each drive circuit 40 includes a single capacitor.

[0140] (1-11) The semiconductor light emitting device 10 includes protection diodes 70A to 70H connected in anti-parallel to one or more (two in the first embodiment) semiconductor light emitting elements 30 provided in each channel. This configuration prevents excessive reverse bias from being applied to the semiconductor light emitting elements 30, thereby increasing the peak optical output of each semiconductor light emitting element 30.

[0141] (1-12) The number of wires W1, W2 located on the current path CP between the switching element of each drive circuit 40 (for example, the switching element 411 of the drive circuit 40A) and the semiconductor light emitting element 30 to be controlled is set to a plurality (for example, four or more in the first embodiment). This configuration can reduce the inductance in the entire semiconductor light emitting device 10.

[0142] Second Embodiment Next, a semiconductor light emitting device 10 according to a second embodiment will be described with reference to Figures 13 to 21. The semiconductor light emitting device 10 according to the second embodiment differs from the semiconductor light emitting device 10 according to the first embodiment mainly in that silicon capacitors are used for the capacitors 421 to 428 of the drive circuits 40A to 40H. Below, the second embodiment will be described, focusing on the differences from the semiconductor light emitting device 10 according to the first embodiment, and components common to the first embodiment will be designated by the same reference numerals and will not be described in detail.

[0143] FIG. 13 shows a schematic planar structure of a semiconductor light-emitting device 10 of the second embodiment. FIG. 14 shows a schematic planar structure of the central portion of the semiconductor light-emitting device 10 of FIG. 13. FIGS. 15 to 18 show schematic planar structures of four different portions of the peripheral region of the semiconductor light-emitting device 10 of FIG. 13. FIG. 19 shows a schematic back electrode structure of the semiconductor light-emitting device 10 of FIG. 13. FIG. 20 shows a schematic front-side intermediate electrode structure of the semiconductor light-emitting device 10 of FIG. 13, and FIG. 21 shows a schematic back-side intermediate electrode structure of the semiconductor light-emitting device 10 of FIG. 13. Note that in FIGS. 13 to 18, openings in the main surface resist layer 29A are indicated by two-dot chain lines, and in FIG. 19, openings in the back surface resist layer 29B are indicated by two-dot chain lines.

[0144] 13, the semiconductor light emitting device 10 includes a plurality of (eight in FIG. 13, for example) semiconductor light emitting elements 30 and a plurality of (eight in FIG. 13, for example) drive circuits 40A-40D. In the following description, when the drive circuits 40A-40H are not to be distinguished from one another, the drive circuits 40A-40H will be referred to as drive circuit 40 (or each drive circuit 40).

[0145] The plurality of semiconductor light-emitting elements 30 and the plurality of drive circuits 40 are provided on a substrate 20. The semiconductor light-emitting device 10 is realized as a multi-channel (eight channels in the example of FIG. 13 ) drive type light-emitting module in which the plurality of semiconductor light-emitting elements 30 are driven by the plurality of drive circuits 40. The number of semiconductor light-emitting elements 30 and the number of drive circuits 40 can be changed as appropriate depending on the number of channels.

[0146] Unlike the first embodiment, the second embodiment employs silicon capacitors for the capacitors 421-428 of the drive circuits 40A-40H. Silicon capacitors are smaller than ceramic capacitors, making it easier to increase the capacitance per unit area of ​​the substrate. This reduces the mounting area of ​​the capacitors 421-428 relative to the area of ​​the substrate 20, thereby enabling the miniaturization of the substrate 20 and the module size of the semiconductor light-emitting device 10. In the second embodiment, each of the drive circuits 40A-40H includes multiple silicon capacitors (e.g., two in FIG. 13 ) connected in parallel. However, each of the drive circuits 40A-40H may also include a single silicon capacitor. The silicon capacitor has a vertical structure including two electrodes facing each other in the Z-axis direction relative to the main surface 21 of the substrate 20. In accordance with this change in the type of capacitor, the configuration of the substrate 20 has also been changed from that of the first embodiment.

[0147] 2-2. Electrode Layers of the Substrate Next, a description will be given of the first to fourth electrode layers 28A to 28D of the substrate 20 according to the second embodiment. In the second embodiment, the first to fourth electrode layers 28A to 28D have different configurations.

[0148] 13 to 18 , the first electrode layer 28A (surface electrode layer) of the second embodiment includes first surface electrodes 61A to 61H, second surface electrodes 62A to 62H, third surface electrodes 63A to 63H, fourth surface electrodes 64A to 64D, fifth surface electrodes 65A to 65H, and sixth surface electrodes 66A to 66H. As in the first embodiment, these surface electrodes are arranged in line symmetry with respect to the respective imaginary center lines VC and HC.

[0149] Here, the first electrode layer 28A of the second embodiment differs from the first embodiment mainly in that the fourth surface electrode 64 (see FIGS. 3 to 6) of the first embodiment is divided into fourth surface electrodes 64A to 64D (see FIGS. 15 to 18), and only fifth surface electrodes 65A to 65H are used to mount capacitors 421 to 428. The shapes and arrangements of the other surface electrodes are the same as or substantially similar to those of the first embodiment. Therefore, the following description will focus on the configuration of the surface electrodes that differ from the first embodiment, and the configuration of the surface electrodes corresponding to those of the first embodiment will be assigned the same reference numerals and their detailed description will be omitted.

[0150] 15 , in the first peripheral region AP1, the fourth surface electrode 64A includes a first branch portion 64AA and a second branch portion 64AB. The first branch portion 64AA includes a tip portion located adjacent to or close to the switching element 411 of the drive circuit 40A, and the source electrode 41S of the switching element 411 is connected to the tip portion of the first branch portion 64AA by a wire W2. Similarly, the second branch portion 64AB includes a tip portion located adjacent to or close to the switching element 412 of the drive circuit 40B, and the source electrode 41S of the switching element 412 is connected to the tip portion of the first branch portion 64AB by a wire W2.

[0151] The fifth surface electrode 65A includes a mounting area for one or more (two in the second embodiment) capacitors 421 in the drive circuit 40A. As described above, each capacitor 421 in the second embodiment is a silicon capacitor having a vertical structure and includes a surface electrode 42S and a back electrode (not shown) that face each other in the Z-axis direction. This also applies to capacitors 422 to 428. The back electrode of each capacitor 421 is bonded to the fifth surface electrode 65A with a conductive bonding material (not shown), and the surface electrode 42S of each capacitor 421 is connected to the source electrode 41S of the switching element 411 by a wire W4. Similarly, in the drive circuit 40B, the back electrode of each capacitor 422 is bonded to the fifth surface electrode 65B, and the surface electrode 42S of each capacitor 422 is connected to the source electrode 41S of the switching element 412 by a wire W4.

[0152] The wire W4 can be made of the same material as the wires W1 to W3. The number of wires W4 is not particularly limited, as long as it is one or more. In the second embodiment, from the viewpoint of reducing the wiring inductance of the entire circuit, the number of wires W1 and W4 located on the current path between the switching element 411 and the semiconductor light emitting element 30 is set to a plurality (for example, four or more).

[0153] 16 , in the second peripheral region AP2, the fourth surface electrode 64B includes a first branch portion 64BC and a second branch portion 64BD. The source electrode 41S of the switching element 413 is connected to the tip of the first branch portion 64BC via a wire W2, and the source electrode 41S of the switching element 414 is connected to the tip of the second branch portion 64BD via a wire W2. Capacitors 423 are mounted on the fifth surface electrode 65C, and the surface electrode 42S of each capacitor 423 is connected to the source electrode 41S of the switching element 413 via a wire W4. Similarly, two capacitors 424 are mounted on the fifth surface electrode 65D, and the surface electrode 42S of each capacitor 424 is connected to the source electrode 41S of the switching element 414 via a wire W4.

[0154] 17 , in the third peripheral region AP3, the fourth surface electrode 64C includes a first branch portion 64CE and a second branch portion 64CF. The source electrode 41S of the switching element 415 is connected to the tip of the first branch portion 64CE via a wire W2, and the source electrode 41S of the switching element 416 is connected to the tip of the second branch portion 64CF via a wire W2. Capacitors 425 are mounted on the fifth surface electrode 65E, and the surface electrode 42S of each capacitor 425 is connected to the source electrode 41S of the switching element 415 via a wire W4. Similarly, two capacitors 426 are mounted on the fifth surface electrode 65F, and the surface electrode 42S of each capacitor 426 is connected to the source electrode 41S of the switching element 416 via a wire W4.

[0155] 18 , in the fourth peripheral region AP4, the fourth surface electrode 64D includes a first branch portion 64DG and a second branch portion 64DH. The source electrode 41S of the switching element 417 is connected to the tip of the first branch portion 64DG via a wire W2, and the source electrode 41S of the switching element 418 is connected to the tip of the second branch portion 64DH via a wire W2. Capacitors 427 are mounted on the fifth surface electrode 65G, and the surface electrode 42S of each capacitor 427 is connected to the source electrode 41S of the switching element 417 via a wire W4. Similarly, two capacitors 428 are mounted on the fifth surface electrode 65H, and the surface electrode 42S of each capacitor 428 is connected to the source electrode 41S of the switching element 418 via a wire W4.

[0156] 19 , the second electrode layer 28B (rear electrode layer) of the second embodiment includes first rear surface electrodes 81A to 81H, second rear surface electrodes 82A to 82H, third rear surface electrodes 83A to 83H, fourth rear surface electrodes 84A to 84D, fifth rear surface electrodes 85A to 85H, and sixth rear surface electrodes 86A to 86H. As in the first embodiment, these rear surface electrodes are arranged in a line-symmetric relationship with respect to the respective imaginary center lines VC and HC.

[0157] Here, the second electrode layer 28B of the second embodiment differs from the first embodiment mainly in that sixth back surface electrodes 86A to 86H are further added to the second electrode layer 28B of the first embodiment (see FIG. 9: first back surface electrodes 81A to 81H, second back surface electrodes 82A to 82H, third back surface electrodes 83A to 83H, fourth back surface electrodes 84A to 84D, and fifth back surface electrodes 85A to 85H). The shapes and arrangements of the other back surface electrodes are the same as or substantially similar to those of the first embodiment. Therefore, the following description will mainly focus on the configuration of the back surface electrodes that differ from the first embodiment, and the configuration of the back surface electrodes corresponding to those of the first embodiment will be denoted by the same reference numerals and detailed description thereof will be omitted.

[0158] 19 , in a first peripheral region AP1 (the lower left region in FIG. 19 ), the sixth back-surface electrodes 86A and 86B are provided as electrodes for connection with the fourth surface electrode 64A (see FIG. 15 ). For example, the sixth back-surface electrode 86A is disposed at a position overlapping with the tip of the first branch portion 64AA of the fourth surface electrode 64A in a plan view, and the sixth back-surface electrode 86B is disposed at a position overlapping with the tip of the second branch portion 64AB of the fourth surface electrode 64A in a plan view.

[0159] Similarly, in the second peripheral region AP2 (the lower right region in FIG. 19 ), the sixth back-surface electrodes 86C and 86D are provided as electrodes for connection to the fourth surface electrode 64B (see FIG. 16 ). For example, the sixth back-surface electrode 86C is disposed at a position overlapping with the tip of the first branch portion 64BC of the fourth surface electrode 64B in a plan view, and the sixth back-surface electrode 86D is disposed at a position overlapping with the tip of the second branch portion 64BD of the fourth surface electrode 64B in a plan view.

[0160] Similarly, in the third peripheral region AP3 (the upper left region in FIG. 19 ), the sixth back-surface electrodes 86E, 86F are provided as electrodes for connection with the fourth surface electrode 64C (see FIG. 17 ). For example, the sixth back-surface electrode 86E is disposed at a position overlapping with the tip of the first branch portion 64CE of the fourth surface electrode 64C in a plan view, and the sixth back-surface electrode 86F is disposed at a position overlapping with the tip of the second branch portion 64CF of the fourth surface electrode 64C in a plan view.

[0161] Similarly, in the fourth peripheral region AP4 (the upper right region in FIG. 19 ), the sixth back-surface electrodes 86G, 86H are provided as electrodes for connection with the fourth surface electrode 64D (see FIG. 18 ). For example, the sixth back-surface electrode 86G is disposed at a position overlapping with the tip of the first branch portion 64DG of the fourth surface electrode 64D in a plan view, and the sixth back-surface electrode 86H is disposed at a position overlapping with the tip of the second branch portion 64DH of the fourth surface electrode 64D in a plan view.

[0162] 19, the sixth back surface electrodes 86A to 86H are formed in a circular shape, but may be formed in other shapes. Furthermore, the sixth back surface electrodes 86A to 86H may be arranged in other positions as long as they overlap with the fourth front surface electrodes 64A to 64D.

[0163] 20 , the third electrode layer 28C (surface-side intermediate electrode layer) of the second embodiment includes first intermediate electrodes 91A to 91H, second intermediate electrodes 92A to 92H, third intermediate electrodes 93A to 93H, fourth intermediate electrodes 94A to 94D, and fifth intermediate electrodes 95A to 95H. As in the first embodiment, these intermediate electrodes are arranged in line symmetry with respect to the respective imaginary center lines VC and HC.

[0164] Here, the third electrode layer 28C of the second embodiment differs from the first embodiment mainly in that fifth intermediate electrodes 95A-95H are added to the third electrode layer 28C of the first embodiment (see FIG. 10 : first intermediate electrodes 91A-91H, second intermediate electrodes 92A-92H, third intermediate electrodes 93A-93H, and fourth intermediate electrodes 94A-94D). The shapes and arrangements of the other surface-side intermediate electrodes are the same as or substantially similar to those of the third electrode layer 28C of the first embodiment (see FIG. 10 ). Therefore, the following description will focus on the configuration of the surface-side intermediate electrodes that differ from the first embodiment, and the configuration of the surface-side intermediate electrodes corresponding to those of the first embodiment will be denoted by the same reference numerals and will not be described in detail.

[0165] 20 , in the first peripheral region AP1 (the lower right region in FIG. 20 ), the fifth intermediate electrodes 95A and 95B are provided as connection electrodes with the fourth surface electrode 64A (see FIG. 15 ) and the sixth back surface electrodes 86A and 86B (see FIG. 19 ). For example, the fifth intermediate electrode 95A is arranged in a position overlapping the tip of the first branch portion 64AA of the fourth surface electrode 64A and the sixth back surface electrode 86A in a plan view. The fifth intermediate electrode 95B is arranged in a position overlapping the tip of the second branch portion 64AB of the fourth surface electrode 64A and the sixth back surface electrode 86B in a plan view.

[0166] Similarly, in the second peripheral region AP2 (the lower left region in FIG. 20 ), fifth intermediate electrodes 95C and 95D are provided as connection electrodes with the fourth surface electrode 64B (see FIG. 16 ) and the sixth back surface electrodes 86C and 86D (see FIG. 19 ). For example, the fifth intermediate electrode 95C is arranged in a position overlapping the tip of the first branch portion 64BC of the fourth surface electrode 64B and the sixth back surface electrode 86C in a plan view. The fifth intermediate electrode 95D is arranged in a position overlapping the tip of the second branch portion 64BD of the fourth surface electrode 64B and the sixth back surface electrode 86D in a plan view.

[0167] Similarly, in the third peripheral region AP3 (the upper right region in FIG. 20 ), fifth intermediate electrodes 95E and 95F are provided as connection electrodes with the fourth surface electrode 64C (see FIG. 17 ) and the sixth back surface electrodes 86E and 86F (see FIG. 19 ). For example, the fifth intermediate electrode 95E is arranged at a position overlapping the tip of the first branch portion 64CE of the fourth surface electrode 64C and the sixth back surface electrode 86E in a plan view. The fifth intermediate electrode 95F is arranged at a position overlapping the tip of the second branch portion 64CF of the fourth surface electrode 64C and the sixth back surface electrode 86F in a plan view.

[0168] Similarly, in the fourth peripheral region AP4 (upper left region in FIG. 20 ), fifth intermediate electrodes 95G and 95H are provided as connection electrodes with the fourth surface electrode 64D (see FIG. 18 ) and the sixth back surface electrodes 86G and 86H (see FIG. 19 ). For example, the fifth intermediate electrode 95G is arranged in a position overlapping the tip of the first branch portion 64DG of the fourth surface electrode 64D and the sixth back surface electrode 86G in a plan view. The fifth intermediate electrode 95H is arranged in a position overlapping the tip of the second branch portion 64DH of the fourth surface electrode 64D and the sixth back surface electrode 86H in a plan view.

[0169] 20, the fifth intermediate electrodes 95A-95H are formed in a circular shape, but other shapes are also possible. Furthermore, the fifth intermediate electrodes 95A-95H may be arranged in other positions as long as they overlap with the fourth front electrodes 64A-64D and the sixth back electrodes 86A-86H.

[0170] 21 , the fourth electrode layer 28D (back-side intermediate electrode layer) of the second embodiment includes first intermediate electrodes 91A to 91H, second intermediate electrodes 92A to 92H, third intermediate electrodes 93A to 93H, fourth intermediate electrodes 94A to 94D, and fifth intermediate electrodes 95A to 95H. As in the first embodiment, these intermediate electrodes are arranged in line symmetry with respect to the respective imaginary center lines VC and HC.

[0171] The fourth electrode layer 28D of the second embodiment differs from the first embodiment mainly in that the shapes of the second intermediate electrodes 92A-92H and the fourth intermediate electrodes 94A-94D of the fourth electrode layer 28D of the first embodiment (see FIG. 10 ) are modified, and fifth intermediate electrodes 95A-95H are further added. The shapes and arrangements of the other back-side intermediate electrodes are the same as or substantially similar to those of the fourth electrode layer 28D of the first embodiment (see FIG. 10 ). Therefore, the following description will focus on the configuration of the back-side intermediate electrodes that differ from the first embodiment, and the configuration of the back-side intermediate electrodes corresponding to the first embodiment will be denoted by the same reference numerals and will not be described in detail.

[0172] 21 , in the first peripheral region AP1 (the lower right region in FIG. 21 ), the second intermediate electrode 92A (rear-side intermediate electrode) of the second embodiment may correspond to one of two individual electrodes obtained by dividing the second intermediate electrode 92A (see FIG. 10 ) of the first embodiment into two, and the fifth intermediate electrode 95A may correspond to the other of the two individual electrodes. Similarly, the second intermediate electrode 92B (rear-side intermediate electrode) may correspond to one of two individual electrodes obtained by dividing the second intermediate electrode 92B (see FIG. 10 ) of the first embodiment into two, and the fifth intermediate electrode 95B may correspond to the other of the two individual electrodes.

[0173] The second intermediate electrode 92A (rear-side intermediate electrode) is arranged at a position overlapping the second surface electrode 62A (see FIG. 15 ), the second rear surface electrode 82A (see FIG. 19 ), and the second intermediate electrode 92A (see FIG. 20 ), which is a surface-side intermediate electrode, in a plan view. The fifth intermediate electrode 95A (rear-side intermediate electrode) is arranged at a position overlapping the sixth surface electrode 66A (see FIG. 15 ), the fifth rear surface electrode 85A (see FIG. 19 ), and the second intermediate electrode 92A (see FIG. 20 ), which is a surface-side intermediate electrode, in a plan view. The second and fifth intermediate electrodes 92B, 95B (rear-side intermediate electrodes) are configured similarly to the second and fifth intermediate electrodes 92A, 95A (rear-side intermediate electrodes), and therefore detailed description thereof will be omitted.

[0174] In the first peripheral region AP1, the fourth intermediate electrode 94A (rear-side intermediate electrode) includes a first branch portion 94AA and a second branch portion 94AB. The first branch portion 94AA is arranged at a position overlapping the first branch portion 64AA of the second surface electrode 64A (see FIG. 15), the sixth rear surface electrode 86A (see FIG. 19), and the fifth intermediate electrode 95A (see FIG. 20), which is a front-side intermediate electrode, in a plan view. The second branch portion 94AB is arranged at a position overlapping the second branch portion 64AB of the second surface electrode 64A (see FIG. 15), the sixth rear surface electrode 86B (see FIG. 19), and the fifth intermediate electrode 95B (see FIG. 20), which is a front-side intermediate electrode, in a plan view. In addition, the fourth intermediate electrode 94A (rear surface side intermediate electrode) is arranged in a position that overlaps with the second surface electrode 64A (see Figure 15), the fourth rear surface electrode 84A (Figure 19), and the fourth intermediate electrode 94A (see Figure 20), which is a surface side intermediate electrode, in a planar view.

[0175] The second intermediate electrodes 92C, 92D and fifth intermediate electrodes 95C, 95D in the second peripheral region AP2 (lower left region in Figure 21), the second intermediate electrodes 92E, 92F and fifth intermediate electrodes 95E, 95F in the third peripheral region AP3 (upper right region in Figure 21), and the second intermediate electrodes 92G, 92H and fifth intermediate electrodes 95G, 95H in the fourth peripheral region AP4 (upper left region in Figure 21) are configured in the same manner as the second intermediate electrodes 92A, 92B and fifth intermediate electrodes 95A, 95B in the first peripheral region AP1 described above. The fourth intermediate electrodes 94B, 94C, and 94D are configured similarly to the fourth intermediate electrode 94A, with the fourth intermediate electrode 94B including first and second branch portions 94BC and 94BD, the fourth intermediate electrode 94C including first and second branch portions 94CE and 94CF, and the fourth intermediate electrode 94D including first and second branch portions 94DG and 94DH. Therefore, detailed description of the back-side intermediate electrodes in the second to fourth peripheral regions AP2 and AP3 will be omitted.

[0176] 21, the second intermediate electrodes 92A-92H are formed in an oval shape and the fifth intermediate electrodes 95A-95H are formed in a rectangular shape, but other shapes are also possible. Furthermore, the second intermediate electrodes 92A-92H and the fifth intermediate electrodes 95A-95H in the fourth electrode layer 28D may be arranged in other positions as long as they overlap with the fourth front electrodes 64A-64D, the sixth back electrodes 86A-86H, and the second intermediate electrodes 82A-82H in the third electrode layer 28C.

[0177] [2-3. Connection Structure Between Electrode Layers] The substrate 20 includes a plurality of vias (connection conductors) that electrically connect the first electrode layer 28A (front surface electrode layer), the second electrode layer 28B (rear surface electrode layer), the third electrode layer 28C (front surface-side intermediate electrode layer), and the fourth electrode layer 28D (rear surface-side intermediate electrode layer) to one another. For example, as shown in Figures 15 to 21 , the substrate 20 includes first vias 101A to 101H, second vias 102A to 102H, third vias 103A to 103H, fourth vias 104A to 104D, fifth vias 105A to 105H, sixth vias 106A to 106H, and seventh vias 107A to 107H that penetrate the first to third base materials 27A to 27C and the third and fourth electrode layers 28C and 28D, respectively, in the thickness direction of the substrate 20. The plurality of vias may penetrate the first and second electrode layers 28A, 28B. The plurality of vias are formed of one or more materials selected from the group including, for example, Ti, TiN, Au, Ag, Cu, Al, and W. The following description will focus on differences from the via configuration in the first embodiment, and similar via configurations will be denoted by similar reference numerals and will not be described in detail.

[0178] As shown in FIGS. 15 to 21 , in the first peripheral region AP1, the sixth via 106A electrically connects the sixth surface electrode 66A (see FIG. 15 ) of the first electrode layer 28A, the fifth back surface electrode 85A (see FIG. 19 ) of the second electrode layer 28B, the second intermediate electrode 92A (see FIG. 20 ) of the third electrode layer 28C, and the fifth intermediate electrode 95A (see FIG. 21 ) of the fourth electrode layer 28D. Here, the second intermediate electrode 92A (see FIG. 20 ) of the third electrode layer 28C is connected to the second via 102A (i.e., the second surface electrode 62A). Therefore, the sixth surface electrode 66A is electrically connected to the second surface electrode 62A. The same applies to the sixth via 106B.

[0179] In the first peripheral region AP1, the seventh via 107A electrically connects the first branch portion 64AA of the fourth surface electrode 64A (see FIG. 15 ) of the first electrode layer 28A, the sixth back surface electrode 86A (see FIG. 19 ) of the second electrode layer 28B, the fifth intermediate electrode 95A (see FIG. 20 ) of the third electrode layer 28C, and the first branch portion 94AA of the fourth intermediate electrode 94A (see FIG. 21 ) of the fourth electrode layer 28D. Here, the first branch portion 94AA of the fourth intermediate electrode 94A (see FIG. 21 ) of the fourth electrode layer 28D is connected to the fourth via 104A (i.e., the fourth surface electrode 64A). Therefore, similar to the fourth via 104A, the seventh via 107A serves to connect the fourth surface electrode 64A to the ground terminal (the fourth back surface electrode 84A).

[0180] The vias in the second peripheral region AP2 (see, for example, FIG. 16), the vias in the third peripheral region AP3 (see, for example, FIG. 17), and the vias in the fourth peripheral region AP4 (see, for example, FIG. 18) are configured and arranged similarly to the vias in the first peripheral region AP1 (see, for example, FIG. 15). Therefore, detailed description of the configuration and arrangement of these vias in the second to fourth peripheral regions AP2 to AP4 will be omitted.

[0181] [2-4. Current Path of Semiconductor Light-Emitting Device] In the second embodiment, the current path of a current flowing through the drive circuit 40A and the semiconductor light-emitting element 30 to be driven by the drive circuit 40A is configured in the shape of a loop in which current flows in the following order: the back electrode (not shown) of the capacitor 421, the fifth surface electrode 65A of the first electrode layer 28A (surface electrode layer), the fifth via 105A, the first intermediate electrode 91A of the third electrode layer 28C (surface-side intermediate electrode layer), the first via 101A, the first surface electrode 61A of the first electrode layer 28A, the back electrode 35 (anode electrode) of the semiconductor light-emitting element 30, the surface electrode 34 (cathode electrode) of the semiconductor light-emitting element 30, the wire W1, the second surface electrode 62A of the first electrode layer 28A, the drain electrode 41D of the switching element 411, the source electrode 41S of the switching element 411, the wire W4, and the surface electrode 42S of the capacitor 421. As in the first embodiment, a protection diode 70A is connected in antiparallel to the semiconductor light emitting element 30 to be driven by the drive circuit 40A.

[0182] Although detailed description is omitted here, each of the other drive circuits 40B to 40H has the same electrical connection as drive circuit 40A, and a loop-shaped current path similar to the above-described current path is individually configured. Also, each of the other protection diodes 70B to 70H has the same electrical connection as protection diode 70A.

[0183] [2-5. Circuit Configuration of Semiconductor Light-Emitting Device] A light-emitting system 200 including the semiconductor light-emitting device 10 of the second embodiment may be configured similarly to the circuit configuration described in the first embodiment with reference to Fig. 12. Therefore, unnecessary explanations will be omitted here.

[0184] 2-6. Advantages of Semiconductor Light-Emitting Device The semiconductor light-emitting device 10 of the second embodiment described above has the following advantages in addition to the advantages similar to those of the semiconductor light-emitting device 10 of the first embodiment.

[0185] (2-1) Silicon capacitors are used for the capacitors 421 to 428 of the drive circuits 40A to 40H. Silicon capacitors are smaller than ceramic capacitors, which has the advantage of making it easier to increase the capacitance per unit area of ​​the substrate. This reduces the mounting area of ​​the capacitors 421 to 428 relative to the area of ​​the substrate 20, allowing for a smaller substrate 20 and therefore a more compact semiconductor light-emitting device 10 (light-emitting module) than would be possible if ceramic capacitors were used, for example.

[0186] 22 to 30, a semiconductor light-emitting device 10 according to a third embodiment will be described. The semiconductor light-emitting device 10 according to the third embodiment differs from the semiconductor light-emitting device 10 according to the first embodiment mainly in that nitride semiconductor transistors, which are an example of lateral transistors, are used for the switching elements 411 to 418 of the drive circuits 40A to 40H. The following description of the third embodiment will focus on the differences from the semiconductor light-emitting device 10 according to the first embodiment, and components common to the first and second embodiments will be denoted by the same reference numerals and will not be described in detail.

[0187] Fig. 22 shows a schematic planar structure of the semiconductor light-emitting device 10 of the second embodiment. Fig. 23 shows a schematic planar structure of the central portion of the semiconductor light-emitting device 10 of Fig. 23. Figs. 24 to 27 show schematic planar structures of four different portions of the peripheral region of the semiconductor light-emitting device 10 of Fig. 23. Fig. 28 shows a schematic back electrode structure of the semiconductor light-emitting device 10 of Fig. 23. Fig. 29 shows a schematic front-side intermediate electrode structure of the semiconductor light-emitting device 10 of Fig. 23, and Fig. 30 shows a schematic back-side intermediate electrode structure of the semiconductor light-emitting device 10 of Fig. 23. Note that in Figs. 22 to 27, openings in the main surface resist layer 29A are indicated by two-dot chain lines, and in Fig. 28, openings in the back surface resist layer 29B are indicated by two-dot chain lines.

[0188] 22, the semiconductor light emitting device 10 includes a plurality of (eight in FIG. 22, for example) semiconductor light emitting elements 30 and a plurality of (eight in FIG. 22, for example) drive circuits 40A to 40D. In the following description, when the drive circuits 40A to 40H are not to be distinguished from one another, the drive circuits 40A to 40H will be referred to as drive circuit 40 (or each drive circuit 40).

[0189] The plurality of semiconductor light-emitting elements 30 and the plurality of drive circuits 40 are provided on a substrate 20. The semiconductor light-emitting device 10 is realized as a multi-channel (eight channels in the example of FIG. 22 ) drive type light-emitting module in which the plurality of semiconductor light-emitting elements 30 are driven by the plurality of drive circuits 40. The number of semiconductor light-emitting elements 30 and the number of drive circuits 40 can be changed as appropriate depending on the number of channels.

[0190] Unlike the first embodiment, the third embodiment employs horizontal transistors for the switching elements 411 to 418 of the drive circuits 40A to 40H. An example of such a horizontal transistor is a nitride semiconductor transistor using a nitride semiconductor (e.g., gallium nitride (GaN)). In the third embodiment, for example, a high electron mobility transistor (HEMT) using a nitride semiconductor is used. Note that MOSFETs may also be used for the switching elements 411 to 418, as long as they are horizontal transistors. In accordance with this change in the type of switching elements, the configuration of the substrate 20 has also been changed from that of the first embodiment.

[0191] Electrode Layers of Substrate] Next, a description will be given of the first to fourth electrode layers 28A to 28D of the substrate 20 according to the third embodiment. In the third embodiment, the first to fourth electrode layers 28A to 28D have different configurations.

[0192] 22 to 27, the first electrode layer 28A (surface electrode layer) of the third embodiment includes first surface electrodes 61A to 61H, second surface electrodes 62A to 62H, third surface electrodes 63A to 63H, fourth surface electrode 64, fifth surface electrodes 65A to 65H, and sixth surface electrodes 66A to 66H. Note that in the third embodiment, the layout of some of the surface electrodes (and the elements mounted thereon) located in the second to fourth peripheral regions AP2 to AP4 corresponds to the layout of some of the corresponding surface electrodes (and the elements mounted thereon) located in the first peripheral region AP1 rotated 90° clockwise in plan view.

[0193] Here, the first electrode layer 28A of the third embodiment differs from the first embodiment mainly in that the shapes of the second surface electrodes 62A-62H and the fourth surface electrode 64 of the first electrode layer 28A (see FIGS. 3 to 6) of the first embodiment are changed. The shapes and arrangements of the other surface electrodes are the same as or substantially similar to those of the first embodiment. Therefore, the following description will focus on the configuration of the surface electrodes that differ from the first embodiment, and the configuration of the surface electrodes corresponding to those of the first embodiment will be assigned the same reference numerals and will not be described in detail.

[0194] As shown in Fig. 24 , in the first peripheral region AP1, the second surface electrode 62A is provided adjacent to or close to the first surface electrode 61A in the Y-axis direction. In the example of Fig. 15 , the second surface electrode 62A is formed in a T-shape in a plan view, but this is not necessarily limited to a T-shape. The second surface electrode 62A is connected by a wire W1 to the surface electrode 34 (cathode electrode) of the semiconductor light emitting element 30 mounted on the first surface electrode 61A. The drain electrode 41D of the switching element 411 is joined to the second surface electrode 62A by a conductive bonding material (not shown).

[0195] Similarly, the second surface electrode 62B is provided at a position adjacent to or close to the first surface electrode 61B in the X-axis direction. In the example of Fig. 15, the second surface electrode 62B is formed in a T-shape in a plan view, but this is not necessarily limited to a T-shape. The second surface electrode 62B is connected by a wire W1 to the surface electrode 34 (cathode electrode) of the semiconductor light emitting element 30 mounted on the first surface electrode 61B. The drain electrode 41D of the switching element 412 is joined to the second surface electrode 62B by a conductive bonding material (not shown).

[0196] The fourth surface electrode 64 includes a notched recess for arranging a part of the second surface electrodes 62A, 62B (a part to which the drain electrode 41D of the switching elements 411, 412 is joined) and the third surface regions 63A, 63B. As in the first embodiment, the fourth surface electrode 64 is formed in an annular shape (see FIG. 22 ) surrounding the first surface electrodes 61A to 61H, the second surface electrodes 62A to 62H, and the third surface electrodes 63A to 63H in a plan view.

[0197] The source electrode 41S of the switching element 411 is joined to the fourth surface electrode 64 by a conductive bonding material (not shown) at a position facing the second surface electrode 62A (drain electrode 41D) in the cutout recess in the X-axis direction. The gate electrode 41G of the switching element 411 is joined to the third surface electrode 63A by a conductive bonding material (not shown) at a position facing the second surface electrode 62A (drain electrode 41D) in the cutout recess in the X-axis direction.

[0198] The first surface electrodes 61C to 61H, the second surface electrodes 62C to 62H, the third surface electrodes 63C to 63H, the fourth surface electrode 64, the fifth surface electrodes 65C to 65H, and the sixth surface electrodes 66C to 66H located in the second to fourth peripheral regions AP2 to AP4 (see FIGS. 25 to 27) are configured similarly to the first surface electrodes 61A, 61B, the second surface electrodes 62A, 62B, the third surface electrodes 63A, 63B, the fourth surface electrode 64, the fifth surface electrodes 65A, 65B, and the sixth surface electrodes 66A, 66B located in the first peripheral region AP1. As described above, the layout of the surface electrodes in the second to fourth peripheral regions AP2 to AP4 corresponds to the layout of the surface electrodes in the first peripheral region AP1 rotated by 90 degrees clockwise in a plan view. Therefore, detailed description of the surface electrodes in the second to fourth peripheral areas AP2 to AP4 will be omitted.

[0199] 28 , the second electrode layer 28B (back surface electrode layer) of the third embodiment includes first back surface electrodes 81A to 81H, second back surface electrodes 82A to 82H, third back surface electrodes 83A to 83H, fourth back surface electrodes 84A to 84D, fifth back surface electrodes 85A to 85H, and sixth back surface electrodes 86A to 86H. Note that in the third embodiment, the layout of the back surface electrodes located in the second to fourth peripheral regions AP2 to AP4 corresponds to the layout of the back surface electrodes located in the first peripheral region AP1 rotated by 90° clockwise in a plan view.

[0200] Here, the second electrode layer 28B of the third embodiment differs from the first embodiment mainly in that the shapes of the third back surface electrodes 83A-83H of the second electrode layer 28B (see FIG. 9) of the first embodiment are changed and sixth back surface electrodes 86A-86H are further added to the second electrode layer 28B (see FIG. 9) of the first embodiment. The shapes and arrangements of the other back surface electrodes are the same as or substantially similar to those of the first embodiment. Therefore, the following description will focus on the configuration of the back surface electrodes that differ from the first embodiment, and the configuration of the back surface electrodes corresponding to the first embodiment will be assigned the same reference numerals and their detailed description will be omitted.

[0201] 28 , in the first peripheral region AP1 (the lower left region in FIG. 28 ), the third back surface electrode 83A is disposed at a position overlapping with the third front surface electrode 63A (see FIG. 24 ) in a plan view. Similarly, the third back surface electrode 83B is disposed at a position overlapping with the third front surface electrode 63B (see FIG. 24 ) in a plan view. In the example of FIG. 28 , the third back surface electrodes 83A and 83B are circular, but are not necessarily limited to a circular shape.

[0202] In the first peripheral region AP1, the sixth back-surface electrodes 86A and 86B are each arranged at a position overlapping the fourth front-surface electrode 64 (see FIG. 24 ) in a plan view. The sixth back-surface electrode 86A is formed, for example, in a curved strip shape that is shorter in the Y-axis direction than the first back-surface electrode 81A, and its tip is provided adjacent to or close to the first back-surface electrode 81A. Similarly, the sixth back-surface electrode 86B is formed, for example, in a curved strip shape that is shorter in the X-axis direction than the first back-surface electrode 81B, and its tip is provided adjacent to or close to the first back-surface electrode 81B. However, the shapes of the sixth back-surface electrodes 86A and 86B are not limited to the shapes shown in FIG. 28 .

[0203] The first back-surface electrodes 81C-81H, the second back-surface electrodes 82C-82H, the third back-surface electrodes 83C-83H, the fourth back-surface electrodes 84B-84D, the fifth back-surface electrodes 85C-85H, and the sixth back-surface electrodes 86C-86H located in the second to fourth peripheral regions AP2-AP4 (the lower right region, the upper left region, and the upper right region, respectively, in FIG. 28 ) are configured similarly to the first back-surface electrodes 81A, 81B, the second back-surface electrodes 82A, 82B, the third back-surface electrodes 83A, 83B, the fourth back-surface electrode 84A, the fifth back-surface electrodes 85A, 85B, and the sixth back-surface electrodes 86A, 86B located in the first peripheral region AP1. As described above, the layout of the back-surface electrodes in the second to fourth peripheral regions AP2-AP4 corresponds to the layout of the back-surface electrodes in the first peripheral region AP1 rotated by 90° clockwise in a plan view. Therefore, detailed description of the back surface electrodes in the second to fourth peripheral regions AP2 to AP4 will be omitted.

[0204] 29 , the third electrode layer 28C (surface-side intermediate electrode layer) of the third embodiment includes first intermediate electrodes 91A to 91H, second intermediate electrodes 92A to 92H, third intermediate electrodes 93A to 93H, fourth intermediate electrodes 94A to 94D, and fifth intermediate electrodes 95A to 95H. Note that in the third embodiment, the layout of the surface-side intermediate electrodes located in the second to fourth peripheral regions AP2 to AP4 corresponds to the layout of the surface-side intermediate electrodes located in the first peripheral region AP1 rotated by 90° clockwise in plan view.

[0205] Here, the third electrode layer 28C of the third embodiment differs from the first embodiment mainly in that fifth intermediate electrodes 95A-95H are added to the third electrode layer 28C of the first embodiment (see FIG. 10 : first intermediate electrodes 91A-91H, second intermediate electrodes 92A-92H, third intermediate electrodes 93A-93H, and fourth intermediate electrodes 94A-94D). The shapes and arrangements of the other surface-side intermediate electrodes are the same as or substantially similar to those of the third electrode layer 28C of the first embodiment (see FIG. 10 ). Therefore, the following description will focus on the configuration of the surface-side intermediate electrodes that differ from the first embodiment, and the configuration of the surface-side intermediate electrodes corresponding to those of the first embodiment will be denoted by the same reference numerals and will not be described in detail.

[0206] 29 , in the first peripheral region AP1 (the lower right region in FIG. 29 ), the fifth intermediate electrode 95A is disposed at a position overlapping both the fourth surface electrode 64 (see FIG. 24 ) and the sixth back surface electrode 86A (see FIG. 28 ). Similarly, the fifth intermediate electrode 95B is disposed at a position overlapping both the fourth surface electrode 64 (see FIG. 24 ) and the sixth back surface electrode 86B (see FIG. 28 ) in plan view.

[0207] With respect to the third electrode layer 28C, the first intermediate electrodes 91C-91H, the second intermediate electrodes 92C-92H, the third intermediate electrodes 93C-93H, the fourth intermediate electrodes 94B-94D, and the fifth intermediate electrodes 95C-95H located in the second to fourth peripheral regions AP2-AP4 (the lower left region, the upper right region, and the upper left region, respectively, in FIG. 29 ) are configured similarly to the first intermediate electrodes 91A and 91B, the second intermediate electrodes 92A and 92B, the third intermediate electrodes 93A and 93B, the fourth intermediate electrode 94A, and the fifth intermediate electrodes 95A and 95B located in the first peripheral region AP1. As described above, the layout of the front-side intermediate electrodes in the second to fourth peripheral regions AP2-AP4 corresponds to the layout of the front-side intermediate electrodes in the first peripheral region AP1 rotated by 90° clockwise in a plan view. Therefore, detailed description of the front-side intermediate electrodes in the second to fourth peripheral regions AP2 to AP4 will be omitted.

[0208] 30 , the fourth electrode layer 28D (back-side intermediate electrode layer) of the third embodiment includes first intermediate electrodes 91A to 91H, second intermediate electrodes 92A to 92H, third intermediate electrodes 93A to 93H, fourth intermediate electrodes 94A to 94D, and fifth intermediate electrodes 95A to 95H. Note that in the third embodiment, the layout of the back-side intermediate electrodes located in the second to fourth peripheral regions AP2 to AP4 corresponds to the layout of the back-side intermediate electrodes located in the first peripheral region AP1 rotated by 90° clockwise in plan view.

[0209] Here, the fourth electrode layer 28D of the third embodiment differs from the first embodiment mainly in that the shapes of the second intermediate electrodes 92A-92H and the fourth intermediate electrodes 94A-94D of the fourth electrode layer 28D of the first embodiment (see FIG. 10 ) are modified, and fifth intermediate electrodes 95A-95H are further added. The shapes and arrangements of the other back-side intermediate electrodes are the same as or substantially similar to those of the fourth electrode layer 28D of the first embodiment (see FIG. 10 ). Therefore, the following description will focus on the configuration of the back-side intermediate electrodes that differ from the first embodiment, and the configuration of the back-side intermediate electrodes corresponding to the first embodiment will be denoted by the same reference numerals and will not be described in detail.

[0210] 30 , in the first peripheral region AP1 (the lower right region in FIG. 30 ), the second intermediate electrode 92A (rear-side intermediate electrode) of the third embodiment may correspond to one of two individual electrodes obtained by dividing the second intermediate electrode 92A (see FIG. 10 ) of the first embodiment into two, and the fifth intermediate electrode 95A may correspond to the other of the two individual electrodes. Similarly, the second intermediate electrode 92B (rear-side intermediate electrode) may correspond to one of two individual electrodes obtained by dividing the second intermediate electrode 92B (see FIG. 10 ) of the first embodiment into two, and the fifth intermediate electrode 95B may correspond to the other of the two individual electrodes.

[0211] The second intermediate electrode 92A (rear-side intermediate electrode) is arranged at a position overlapping the second surface electrode 62A (see FIG. 24), the second rear surface electrode 82A (see FIG. 28), and the second intermediate electrode 92A (see FIG. 29), which is a surface-side intermediate electrode, in a plan view. The fifth intermediate electrode 95A (rear-side intermediate electrode) is arranged at a position overlapping the sixth surface electrode 66A (see FIG. 24), the fifth rear surface electrode 85A (see FIG. 28), and the second intermediate electrode 92A (see FIG. 29), which is a surface-side intermediate electrode, in a plan view. The second and fifth intermediate electrodes 92B, 95B (rear-side intermediate electrodes) are configured similarly to the second and fifth intermediate electrodes 92A, 95A (rear-side intermediate electrodes), and therefore detailed description thereof will be omitted.

[0212] In the first peripheral region AP1, the fourth intermediate electrode 94A (rear-side intermediate electrode) includes a circular hole for disposing the third intermediate electrode 93A (rear-side intermediate electrode) and a notched recess for disposing the third intermediate electrode 93B (rear-side intermediate electrode). The fourth intermediate electrode 94A (rear-side intermediate electrode) is disposed at a position overlapping with the fourth front surface electrode 64 (see FIG. 24 ), the fourth rear surface electrode 84A (see FIG. 28 ), and the fourth and fifth front surface intermediate electrodes 94A, 95A, and 95B (see FIG. 29 ) in a plan view.

[0213] With respect to the fourth electrode layer 28D, the first intermediate electrodes 91C-91H, the second intermediate electrodes 92C-92H, the third intermediate electrodes 93C-93H, the fourth intermediate electrodes 94B-94D, and the fifth intermediate electrodes 95C-95H located in the second to fourth peripheral regions AP2-AP4 (the lower left region, the upper right region, and the upper left region, respectively, in FIG. 30 ) are configured similarly to the first intermediate electrodes 91A and 91B, the second intermediate electrodes 92A and 92B, the third intermediate electrodes 93A and 93B, the fourth intermediate electrode 94A, and the fifth intermediate electrodes 95A and 95B located in the first peripheral region AP1. As described above, the layout of the back-side intermediate electrodes in the second to fourth peripheral regions AP2-AP4 corresponds to the layout of the back-side intermediate electrodes in the first peripheral region AP1 rotated by 90° clockwise in a plan view. Therefore, detailed description of the back surface-side intermediate electrodes in the second to fourth peripheral regions AP2 to AP4 will be omitted.

[0214] [3-3. Connection Structure Between Electrode Layers] The substrate 20 includes a plurality of vias (connection conductors) that electrically connect the first electrode layer 28A (front surface electrode layer), the second electrode layer 28B (rear surface electrode layer), the third electrode layer 28C (front surface-side intermediate electrode layer), and the fourth electrode layer 28D (rear surface-side intermediate electrode layer) to one another. For example, as shown in Figures 24 to 30, the substrate 20 includes first vias 101A to 101H, second vias 102A to 102H, third vias 103A to 103H, fourth vias 104A to 104D, fifth vias 105A to 105H, sixth vias 106A to 106H, and seventh vias 107A to 107H that penetrate the first to third base materials 27A to 27C and the third and fourth electrode layers 28C and 28D, respectively, in the thickness direction of the substrate 20. The plurality of vias may penetrate the first and second electrode layers 28A, 28B. The plurality of vias are formed of one or more materials selected from the group including, for example, Ti, TiN, Au, Ag, Cu, Al, and W. The following description will focus on differences from the via configuration in the first embodiment, and similar via configurations will be denoted by similar reference numerals and will not be described in detail.

[0215] As shown in FIGS. 24 to 30 , in the first peripheral region AP1, the sixth via 106A electrically connects the sixth surface electrode 66A (see FIG. 24 ) of the first electrode layer 28A, the fifth back surface electrode 85A (see FIG. 28 ) of the second electrode layer 28B, the second intermediate electrode 92A (see FIG. 29 ) of the third electrode layer 28C, and the fifth intermediate electrode 95A (see FIG. 30 ) of the fourth electrode layer 28D. Here, the second intermediate electrode 92A (see FIG. 29 ) of the third electrode layer 28C is connected to the second via 102A (i.e., the second surface electrode 62A). Therefore, the sixth surface electrode 66A is electrically connected to the second surface electrode 62A. The same applies to the sixth via 106B.

[0216] In the first peripheral region AP1, the seventh via 107A electrically connects the fourth surface electrode 64 (see FIG. 24 ) of the first electrode layer 28A, the sixth back surface electrode 86A (see FIG. 28 ) of the second electrode layer 28B, the fifth intermediate electrode 95A (see FIG. 29 ) of the third electrode layer 28C, and the fourth intermediate electrode 94A (see FIG. 30 ) of the fourth electrode layer 28D. Here, the fourth intermediate electrode 94A (see FIG. 30 ) of the fourth electrode layer 28D is connected to the fourth via 104A (i.e., the fourth surface electrode 64). Therefore, similar to the fourth via 104A, the seventh via 107A serves to connect the fourth surface electrode 64 to the ground terminal (the fourth back surface electrode 84A).

[0217] The vias in the second peripheral region AP2 (see, for example, FIG. 25), the vias in the third peripheral region AP3 (see, for example, FIG. 26), and the vias in the fourth peripheral region AP4 (see, for example, FIG. 27) are configured and arranged similarly to the vias in the first peripheral region AP1 (see, for example, FIG. 24). Therefore, detailed description of the configuration and arrangement of these vias in the second to fourth peripheral regions AP2 to AP4 will be omitted.

[0218] [3-4. Current Path of Semiconductor Light-Emitting Device] In the third embodiment, the current path of a current flowing through the drive circuit 40A and the semiconductor light-emitting element 30 to be driven by the drive circuit 40A is configured in the shape of a loop, with the current flowing in the following order: the second electrode 42B of the capacitor 421, the fifth surface electrode 65A of the first electrode layer 28A (surface electrode layer), the fifth via 105A, the first intermediate electrode 91A of the third electrode layer 28C (surface-side intermediate electrode layer), the first via 101A, the first surface electrode 61A of the first electrode layer 28A, the back electrode 35 (anode electrode) of the semiconductor light-emitting element 30, the surface electrode 34 (cathode electrode) of the semiconductor light-emitting element 30, the wire W1, the second surface electrode 62A of the first electrode layer 28A, the drain electrode 41D of the switching element 411, the source electrode 41S of the switching element 411, the fourth surface electrode 64 of the first electrode layer 28A, and the first electrode 42A of the capacitor 421. As in the first embodiment, a protection diode 70A is connected in antiparallel to the semiconductor light emitting element 30 to be driven by the drive circuit 40A.

[0219] Although detailed description is omitted here, each of the other drive circuits 40B to 40H has the same electrical connection as drive circuit 40A, and a loop-shaped current path similar to the above-described current path is individually configured. Also, each of the other protection diodes 70B to 70H has the same electrical connection as protection diode 70A.

[0220] [3-5. Circuit Configuration of Semiconductor Light-Emitting Device] A light-emitting system 200 including the semiconductor light-emitting device 10 of the third embodiment has the same circuit configuration as that described in the first embodiment with reference to Fig. 12. Therefore, unnecessary explanations will be omitted here.

[0221] 3-6. Advantages of Semiconductor Light-Emitting Device The semiconductor light-emitting device 10 of the third embodiment described above has the following advantages in addition to the advantages similar to those of the semiconductor light-emitting device 10 of the first embodiment.

[0222] (3-1) Nitride semiconductor transistors, an example of lateral transistors, are employed for the switching elements 411 to 418 of the drive circuits 40A to 40H. For example, in the first embodiment, GaN-HEMTs are used as the nitride semiconductor transistors. This configuration can reduce the number of wires required for the light-emitting module. For example, while wires W1 to W3 are used in the first embodiment and wires W1 to W4 are used in the second embodiment, only wire W1 is used in the third embodiment. This can reduce the effects of an increase in the number of wires, such as an increase in mutual inductance between the wires.

[0223] [Modifications] The above embodiment can be modified as follows: Furthermore, the above embodiment and the following modifications can be combined with each other within the scope of technical compatibility.

[0224] In the above embodiments, a PCSEL element is used as the semiconductor light emitting element 30, but the invention is not limited to a PCSEL element. For example, a vertical cavity surface emitting laser (VCSEL) element may be used as the light emitting element that emits light in a direction intersecting with the main surface 21 of the substrate 20.

[0225] In each of the above embodiments, the multiple drive circuits 40A to 40H are arranged in a linearly symmetric or rotationally symmetric manner in the peripheral area AP, but this layout is not necessarily limited to this, and the multiple drive circuits 40A to 40H may be arranged in any layout in the peripheral area AP.

[0226] In each of the above embodiments, the number of capacitors provided in each drive circuit 40 may be one. In each of the above embodiments, the number of intermediate electrode layers provided inside the substrate 20 is not limited to two, but may be one layer or three or more layers. Furthermore, the material of the substrate 20 is not limited to glass epoxy resin or ceramic, but may be silicon.

[0227] The gate drivers 205A to 205H may be mounted on the substrate 20 of the first embodiment. That is, the semiconductor light emitting device 10 may include the gate drivers 205A to 205H.

[0228] The protection diodes 70A to 70H do not have to be mounted on the substrate 20 of the second embodiment. That is, the semiconductor light emitting device 10 does not have to include the protection diodes 70A to 70H.

[0229] The term "on" as used in this disclosure includes the meanings of "on" and "above," unless the context clearly indicates otherwise. Thus, for example, the phrase "a first element is mounted on a second element" is intended to mean that in some embodiments, the first element may be placed directly on the second element in contact with the second element, while in other embodiments, the first element may be placed above the second element without contacting the second element. In other words, the term "on" does not exclude a structure in which another element is formed between the first element and the second element.

[0230] The Z-axis direction used in this disclosure does not necessarily have to be the vertical direction, nor does it have to completely coincide with the vertical direction. Therefore, various structures according to this disclosure (e.g., the structure shown in FIG. 1 ) are not limited to the "up" and "down" in the Z-axis direction described herein being "up" and "down" in the vertical direction. For example, the X-axis direction may be the vertical direction, or the Y-axis direction may be the vertical direction.

[0231] [Notes] The technical ideas that can be understood from the above-described embodiments and modifications are described below. Note that the reference numerals of the components of the embodiments corresponding to the components described in each note are shown in parentheses. The reference numerals are shown as examples to aid understanding, and the components described in each note should not be limited to the components indicated by the reference numerals.

[0232] (Supplementary Note 1) A semiconductor light emitting device (10) comprising: a substrate (20); a plurality of semiconductor light emitting elements (30) provided on the substrate (20); and a plurality of drive circuits (40A-40H) provided on the substrate (20) and each driving one or more of the plurality of semiconductor light emitting elements (30), wherein the plurality of semiconductor light emitting elements (30) are each located on a main surface (21) of the substrate (20) and are configured by a light emitting element (30) that emits light in a direction intersecting with the main surface (21), and each of the plurality of drive circuits (40A-40H) includes: a switching element (411-418) that controls one or more of the plurality of semiconductor light emitting elements (30); and a capacitor (421-428) that supplies current to the one or more of the plurality of semiconductor light emitting elements (30).

[0233] (Supplementary Note 2) The semiconductor light emitting device (10) according to Supplementary Note 1, wherein the plurality of semiconductor light emitting elements (30) are collectively arranged in a central region (AC) of the substrate (20).

[0234] (Supplementary Note 3) The semiconductor light emitting device (10) according to Supplementary Note 2, wherein the plurality of semiconductor light emitting elements (30) are arranged adjacent to each other in a matrix in the central region (AC) of the substrate (20).

[0235] (Appendix 4) The semiconductor light-emitting device (10) according to Appendix 2 or 3, wherein the plurality of drive circuits (40A to 40H) are arranged in a peripheral region (AP) of the substrate (20) surrounding the central region (AC) of the substrate (20) in a planar view.

[0236] (Appendix 5) The semiconductor light-emitting device of claim 4, wherein the peripheral region (AP) includes first to fourth peripheral regions (AP1 to AP4) divided based on two mutually perpendicular imaginary center lines (VC, HC) passing through the center of the substrate (20) in a planar view, and the plurality of drive circuits (40A to 40H) are each arranged in one of the first to fourth peripheral regions (AP1 to AP4).

[0237] (Appendix 6) The semiconductor light emitting device (10) according to Appendix 5, wherein the number of the semiconductor light emitting elements (30) is eight or more, and two or more of the plurality of drive circuits (40A to 40H) are arranged in each of the first to fourth peripheral regions (AP1 to AP4).

[0238] (Supplementary Note 7) The semiconductor light emitting device (10) according to any one of Supplementary Notes 1 to 6, wherein the light emitting element (30) is a photonic crystal surface emitting laser element or a vertical cavity surface emitting laser element.

[0239] (Appendix 8) The semiconductor light-emitting device (10) according to any one of Appendices 1 to 7, wherein the capacitor is one of a plurality of capacitors (421 to 428) provided in each of the plurality of drive circuits (40A to 40H).

[0240] (Supplementary Note 9) The semiconductor light emitting device (10) according to any one of Supplementary Notes 1 to 8, wherein the capacitors (421 to 428) are ceramic capacitors or silicon capacitors.

[0241] (Supplementary Note 10) The semiconductor light emitting device (10) according to any one of Supplementary Notes 1 to 9, wherein the switching elements (411 to 418) are MOSFETs or nitride semiconductor transistors.

[0242] (Appendix 11) The semiconductor light-emitting device (10) according to any one of Appendices 1 to 10, wherein the switching elements (411 to 418) are connected to each of the one or more of the plurality of semiconductor light-emitting elements (30) by a plurality of wires (W1).

[0243] (Appendix 12) The semiconductor light emitting device (10) according to any one of Appendices 1 to 11, further comprising a plurality of gate drivers (205A to 205H) that respectively drive the switching elements (411 to 418) in one of the plurality of drive circuits (40A to 40H).

[0244] (Appendix 13) The semiconductor light emitting device (10) according to any one of Appendices 1 to 12, further comprising a plurality of protection diodes (70A to 70H) each connected in anti-parallel to one or more of the plurality of semiconductor light emitting elements (30).

[0245] (Appendix 14) The semiconductor light emitting device (10) according to any one of Appendices 1 to 13, further comprising a plurality of backflow prevention diodes (204A to 204H) each provided between a power supply input section (201, 202, 203) that supplies current to the plurality of semiconductor light emitting elements (30) and the plurality of drive circuits (40A to 40H) and one of the plurality of drive circuits (40A to 40H).

[0246] (Appendix 15) The semiconductor light emitting device (10) according to any one of appendices 1 to 14, wherein the substrate (20) is formed from any one of glass epoxy resin, ceramic, and silicon.

[0247] (Supplementary Note 16) A semiconductor device comprising: a surface electrode layer (28A) located on a main surface (21) of the substrate (20); a back electrode layer (28B) located on a back surface (22) of the substrate (20); intermediate electrode layers (28C; 28D) located between the surface electrode layer (28A) and the back electrode layer (28B) in the thickness direction of the substrate (20); and a plurality of vias provided in the substrate (20) and electrically connecting the surface electrode layer (28A), the back electrode layer (28B), and the intermediate electrode layer (28C; 28D), wherein the plurality of semiconductor light-emitting elements (30) and the plurality of drive circuits (40A to 40H) are mounted on the surface electrode layer (28A), A semiconductor light-emitting device (10) described in any one of Appendices 1 to 15, wherein a current path (CP) of a current flowing through each of the plurality of drive circuits (40A to 40H) and one or more of the plurality of semiconductor light-emitting elements (30) to be driven by each of the drive circuits (40A to 40H) is composed of the surface electrode layer (28A), the intermediate electrode layer (28C; 28D), and some of the plurality of vias (101A to 101H, 105A to 105H).

[0248] 10: Semiconductor light-emitting device 20: Substrate 21: Main surface 22: Rear surface 23-26: First to fourth side surfaces 27A-27C: First to third base materials 28A: First electrode layer (front electrode layer) 28B: Second electrode layer (rear electrode layer) 28C: Third electrode layer (intermediate electrode layer; front-side intermediate electrode layer) 28D: Fourth electrode layer (intermediate electrode layer; rear-side intermediate electrode layer) 29A: Main surface resist layer 29B: Rear resist layer 30: Semiconductor light-emitting element 31: Element front surface 32: Element rear surface 33: Light-emitting region 34: Front electrode 35: Rear electrode 40, 40A-40H: Drive circuit 411-418: Switching element 41A: Element front surface 41B: Element rear surface 41S: Source electrode 41G: Gate electrode 41D: Drain electrode 421-428: Capacitor 42A: First electrode 42B: Second electrode 42S: Surface electrode 70A to 70H: Protection diode 71: Anode electrode 72: Cathode electrode 200: Light-emitting system 201: DC power supply 202: Capacitor 203: DC limiting resistor 204A to 204H: Reverse current prevention diode 205A to 205H: Gate driver 206A to 206H: Pulse generator 207A to 207H: Control power supply 101A to 101H: First via 102A to 102H: Second via 103A to 103H: Third via 104A to 104D: Fourth via 105A to 105H: Fifth via 106A to 106H: Sixth via 107A to 107H: Seventh via AC: Central region AP: Peripheral region AP1: First peripheral region AP2: Second peripheral region AP3: Third peripheral region AP4: Fourth peripheral region CP: Current path VC, HC: Virtual center lines W1 to W4: Wires

Claims

1. A semiconductor light emitting device comprising: a substrate; a plurality of semiconductor light emitting elements provided on the substrate; and a plurality of drive circuits provided on the substrate for respectively driving one or more of the plurality of semiconductor light emitting elements, wherein each of the plurality of semiconductor light emitting elements is located on a main surface of the substrate and is composed of a light emitting element that emits light in a direction intersecting with the main surface, and each of the plurality of drive circuits includes a switching element that controls one or more of the plurality of semiconductor light emitting elements, and a capacitor that supplies current to the one or more of the plurality of semiconductor light emitting elements.

2. The semiconductor light emitting device according to claim 1, wherein the plurality of semiconductor light emitting elements are concentrated and arranged in a central region of the substrate.

3. The semiconductor light emitting device according to claim 2, wherein the plurality of semiconductor light emitting elements are arranged adjacent to one another in a matrix in the central region of the substrate.

4. The semiconductor light emitting device according to claim 2 or 3, wherein the plurality of drive circuits are arranged in a peripheral region of the substrate surrounding the central region of the substrate in a plan view.

5. The semiconductor light-emitting device described in claim 4, wherein the peripheral region includes first to fourth peripheral regions divided based on two mutually perpendicular imaginary center lines passing through the center of the substrate in a planar view, and each of the plurality of driving circuits is disposed in one of the first to fourth peripheral regions.

6. The semiconductor light emitting device according to claim 5, wherein the number of said semiconductor light emitting elements is eight or more, and two or more of said plurality of driving circuits are arranged in each of said first to fourth peripheral regions.

7. The semiconductor light emitting device according to any one of claims 1 to 6, wherein the light emitting element is a photonic crystal surface emitting laser element or a vertical cavity surface emitting laser element.

8. The semiconductor light emitting device according to claim 1, wherein the capacitor is one of a plurality of capacitors provided in each of the plurality of drive circuits.

9. The semiconductor light emitting device according to claim 1, wherein the capacitor is a ceramic capacitor or a silicon capacitor.

10. The semiconductor light emitting device according to any one of claims 1 to 9, wherein the switching element is a MOSFET or a nitride semiconductor transistor.

11. The semiconductor light emitting device according to any one of claims 1 to 10, wherein the switching element is connected to each of the one or more of the plurality of semiconductor light emitting elements by a plurality of wires.

12. The semiconductor light emitting device according to claim 1, further comprising a plurality of gate drivers each driving the switching element in one of the plurality of drive circuits.

13. The semiconductor light emitting device according to any one of claims 1 to 12, further comprising a plurality of protection diodes respectively connected in anti-parallel to said one or more of said plurality of semiconductor light emitting elements.

14. A semiconductor light emitting device according to any one of claims 1 to 13, further comprising a plurality of backflow prevention diodes each provided between a power supply input section which supplies current to the plurality of semiconductor light emitting elements and the plurality of drive circuits, and one of the plurality of drive circuits.

15. The semiconductor light emitting device according to any one of claims 1 to 14, wherein the substrate is made of any one of glass epoxy resin, ceramic, and silicon.

16. A semiconductor light-emitting device as described in any one of claims 1 to 15, comprising: a surface electrode layer located on a main surface of the substrate; a back electrode layer located on a back surface of the substrate; an intermediate electrode layer located between the surface electrode layer and the back electrode layer in the thickness direction of the substrate; and a plurality of vias provided in the substrate and electrically connecting the surface electrode layer, the back electrode layer, and the intermediate electrode layer, wherein the plurality of semiconductor light-emitting elements and the plurality of drive circuits are mounted on the surface electrode layer, and a current path of a current flowing through each of the plurality of drive circuits and the one or more of the plurality of semiconductor light-emitting elements to be driven by each of the drive circuits is constituted by the surface electrode layer, the intermediate electrode layer, and some of the plurality of vias.

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