Semiconductor substrate for power semiconductor manufacturing, method of manufacturing same, and method of manufacturing power semiconductor device using same

Abstract

An embodiment relates to a semiconductor substrate for power semiconductor manufacturing, a method of manufacturing same, and a method of manufacturing a power semiconductor device using same. The method of manufacturing a semiconductor substrate for power semiconductor manufacturing according to an embodiment may comprise the steps of: preparing an off-cut base substrate; forming a graphene layer and a carbon non-single crystal layer on the base substrate; and separating the graphene layer from the carbon non-single crystal layer. In addition, the semiconductor substrate for power semiconductor manufacturing according to an embodiment may comprise: an off-cut base substrate; and a carbon non-single crystal layer formed on the base substrate.

Description

Semiconductor substrate for manufacturing power semiconductors, manufacturing method thereof, and manufacturing method of power semiconductor devices using the same

[0001] The present invention relates to a semiconductor substrate for manufacturing power semiconductors, a method for manufacturing the same, and a method for manufacturing a power semiconductor device using the same.

[0002] Power semiconductors are one of the key elements that determine the efficiency, speed, durability, and reliability of power electronics systems.

[0003] With the recent development of the power electronics industry, research is actively being conducted on WBG (Wide Bandgap) power semiconductors such as silicon carbide (SiC) and gallium nitride (GaN) to replace the existing silicon (Si) power semiconductors that have reached their physical limits.

[0004] WBG power semiconductor devices have a bandgap energy approximately three times that of Si power semiconductor devices, resulting in lower intrinsic carrier concentration, higher breakdown field (approximately 4 to 20 times), higher thermal conductivity (approximately 3 to 13 times), and larger electron saturation velocity (approximately 2 to 2.5 times).

[0005] These characteristics enable operation in high-temperature, high-voltage environments, high switching speeds, and low switching losses. Among these, gallium nitride (GaN) power semiconductor devices can be used in low-voltage systems, while silicon carbide (SiC) power semiconductor devices are suitable for high-voltage systems.

[0006] Conventional SiC MOSFET power semiconductors are generally denoted as VDMOSFETs due to their vertically diffused structure, but can also be simply referred to as double-diffused structure DMOSFETs. Furthermore, SiC MOSFETs can be classified into planar MOSFETs and trench MOSFETs depending on the channel orientation.

[0007] Among these, Trench MOSFET is a structure in which a channel is formed on the sidewall of a trench, and for this purpose, a gate insulating film is formed on the sidewall of the trench and a gate electrode is formed in the trench.

[0008] Meanwhile, conventional techniques for manufacturing SiC MOSFET power semiconductor devices involve forming a graphene layer on a base substrate, forming a buffer layer and a SiC epilayer while the base substrate is in a horizontal (on-axis) state, and then separating the SiC epilayer on top of the graphene layer to manufacture a SiC MOSFET power semiconductor device.

[0009] However, in the conventional technology, when the epitaxy process is performed with the parent substrate in a horizontal (on-axis) state, there is a problem that a polycrystalline SiC epilayer is grown instead of a single crystal, and the defect density also increases, which lowers the crystal quality and lowers the yield of the SiC MOSFET power semiconductor device.

[0010] One of the technical tasks of the present invention is to provide a semiconductor substrate for manufacturing high-quality power semiconductor devices, a method for manufacturing the same, and a method for manufacturing power semiconductor devices using the same.

[0011] The technical tasks of the embodiment are not limited to those described in this article, but include those that can be understood through the description of the invention.

[0012] A method for manufacturing a semiconductor substrate for manufacturing a power semiconductor according to an embodiment may include a step of preparing an off-cut base substrate (210), a step of forming a graphene layer (220) and a carbon non-single-crystal layer (230) on the base substrate (210), and a step of separating the graphene layer (220) from the carbon non-single-crystal layer (230).

[0013] The step of forming the graphene layer (220) and the carbon non-single-crystal layer (230) may include a step of forming the graphene layer (220) on the upper side of the base substrate (210) by heating the base substrate (210) to a first temperature and a step of forming the carbon non-single-crystal layer (230) between the surface of the base substrate (210) and the graphene layer (220) by heating the base substrate (210) to a second temperature lower than the first temperature.

[0014] The above carbon non-single crystal layer (230) may include a polycrystalline carbon layer, an amorphous carbon layer, or a combination thereof.

[0015] The above carbon non-single crystal layer (230) maintains a covalent bond with the above substrate (210) and can maintain a bond weaker than the covalent bond with the graphene layer (220).

[0016] The above carbon non-single crystal layer (230) may maintain a covalent bond with the above base material substrate (210) and may not maintain a covalent bond with the above graphene layer (220).

[0017] In addition, a semiconductor substrate for manufacturing a power semiconductor according to an embodiment may include an off-cut base substrate (210) and a carbon non-single crystal layer (230) formed on the base substrate (210).

[0018] The above carbon non-single crystal layer (230) may include a polycrystalline carbon layer, an amorphous carbon layer, or a combination thereof.

[0019] The above carbon non-single crystal layer (230) can maintain a covalent bond with the above base material substrate (210).

[0020] In addition, a method for manufacturing a power semiconductor device according to an embodiment may include a step of preparing a semiconductor substrate for manufacturing a power semiconductor, a step of forming a first SiC semiconductor structure on the semiconductor substrate for manufacturing a power semiconductor, and a step of separating the first SiC semiconductor structure from the semiconductor substrate for manufacturing a power semiconductor.

[0021] The carbon non-single crystal layer (230) of the semiconductor substrate for manufacturing the above power semiconductor can maintain a bond weaker than a covalent bond with the first SiC semiconductor structure (100A).

[0022] The carbon non-single crystal layer (230) of the semiconductor substrate for manufacturing the power semiconductor can provide a nucleation site for the SiC semiconductor structure (100A).

[0023] Additionally, the embodiment may include a step of forming a second SiC semiconductor structure on the semiconductor substrate for manufacturing a power semiconductor from which the first SiC semiconductor structure is separated.

[0024] According to an embodiment, a semiconductor substrate for manufacturing a high-quality power semiconductor device, a method for manufacturing the same, and a method for manufacturing a power semiconductor device using the same can be provided. For example, according to an embodiment, a single-crystal SiC epilayer can be grown by growing a SiC epilayer on an off-cut SiC base substrate, and a defect density is also significantly reduced, thereby providing a technical effect of providing a high-quality SiC MOSFET power semiconductor device.

[0025] In addition, the carbon non-single crystal layer (230) of the embodiment can improve the crystal quality of the SiC semiconductor structure (100A) grown thereafter by providing a nucleation site.

[0026] Accordingly, according to an embodiment, a semiconductor substrate (200) for manufacturing a power semiconductor having a carbon non-single crystal layer (230) has a technical effect of improving the crystal quality of a SiC semiconductor structure (100A) that is subsequently grown, and at the same time, allowing the SiC semiconductor structure (100A) to be easily separated from the semiconductor substrate (200) for manufacturing a power semiconductor due to a difference in bonding strength with the SiC semiconductor structure (100A) after growth.

[0027] In addition, the semiconductor substrate (200) for manufacturing power semiconductors having a carbon non-single crystal layer (230) remaining after separation of the SiC semiconductor structure (100A) has a special technical effect in that it can be reused as a substrate for growing a SiC epitaxial structure in a separate process.

[0028] The technical effects of the embodiments are not limited to those described in this article, but include those that can be understood through the description of the invention.

[0029] Figure 1 is an example diagram of the configuration of a power conversion device (1000) according to an embodiment.

[0030] Figures 2 to 5 are cross-sectional views of a process for manufacturing a semiconductor substrate for manufacturing a power semiconductor according to an embodiment.

[0031] Figures 6 to 9 are cross-sectional views of a process for manufacturing a power semiconductor device (100) using a semiconductor substrate for manufacturing a power semiconductor device according to an embodiment.

[0032] Hereinafter, an invention according to an embodiment for solving the above problem will be described in more detail with reference to the drawings.

[0033] The suffixes "module" and "part" used in the following description are given solely for the convenience of writing this specification and do not impart any particularly significant meaning or role to the components themselves. Therefore, the terms "module" and "part" may be used interchangeably.

[0034] Terms that include ordinal numbers, such as first, second, etc., may be used to describe various components, but the components are not limited by these terms. These terms are used solely to distinguish one component from another.

[0035] In the specification, the meaning of “composition A includes at least one of a, b, and / or c” may include ① cases where composition A includes a, ② cases where composition A includes b, ③ cases where composition A includes c, ④ cases where composition A includes a and b, ⑤ cases where composition A includes b and c, ⑥ cases where composition A includes a and c, and ⑦ cases where composition A includes all of a, b, and c.

[0036] Singular expressions include both singular and plural expressions, unless the context clearly indicates otherwise. For example, the meaning of "composition A includes a structure" can include the meaning of "composition A includes one or more structures."

[0037] In this application, it should be understood that terms such as “include,” “have,” or “comprising” are intended to specify the presence of a feature, number, step, operation, component, part, or combination thereof described in the specification, but do not preclude the possibility of the presence or addition of one or more other features, numbers, steps, operations, components, parts, or combinations thereof.

[0038] (Example)

[0039] Figure 1 is an example diagram of the configuration of a power conversion device (1000) according to an embodiment.

[0040] A power conversion device (1000) according to an embodiment can receive DC power from a battery or a fuel cell, convert it into AC power, and supply AC power to a predetermined load. For example, the power conversion device (1000) according to an embodiment can include an inverter, and can receive DC power from a battery, convert it into three-phase AC power, and supply it to a motor (M), and the motor (M) can provide power to an electric vehicle, a fuel cell vehicle, etc.

[0041] A power conversion device (1000) according to an embodiment may include a power semiconductor device (100). The power semiconductor device (100) may be a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), but is not limited thereto, and may include an IGBT (Insulated Gate Bipolar Transistor).

[0042] For example, the power conversion device (1000) may include a plurality of power semiconductor elements (100a, 100b, 100c, 100d, 100e, 100f) and may include a plurality of diodes (not shown). Each of the plurality of diodes may be embedded in the power semiconductor elements (100a, 100b, 100c, 100d, 100e, 100f) in the form of an internal diode, but is not limited thereto, and may be arranged separately.

[0043] The embodiment can convert DC power into AC power through on-off control for a plurality of power semiconductor elements (100a to 100f). For example, the power conversion device (1000) according to the embodiment can supply positive power to the motor (M) by turning on the first power semiconductor element (100a) and turning off the second power semiconductor element (100b) in a first time section of one cycle, and can supply negative power to the motor (M) by turning off the first power semiconductor element (100a) and turning on the second power semiconductor element (100b) in a second time section of one cycle.

[0044] In an embodiment, a group of power semiconductor devices arranged in series on the high-voltage line and the low-voltage line of the input side may be referred to as an arm. For example, a first power semiconductor device (100a) and a second power semiconductor device (100b) may constitute a first arm, a third power semiconductor device (100c) and a fourth power semiconductor device (100d) may constitute a second arm, and a fifth power semiconductor device (100e) and a sixth power semiconductor device (100f) may constitute a third arm.

[0045] In the above arm, the upper power semiconductor element and the lower power semiconductor element can be controlled so as not to be turned on simultaneously. For example, in the first arm, the first power semiconductor element (100a) and the second power semiconductor element (100b) can be turned on and off alternately without being turned on simultaneously.

[0046] Each power semiconductor element (100a to 100f) can receive a high voltage while in an off state. For example, when the second power semiconductor element (100b) is turned off while the first power semiconductor element (100a) is turned on, the input voltage can be applied as is to the second power semiconductor element (100b). The voltage input to the second power semiconductor element (100b) can be a relatively high voltage, and the withstand voltage of each power semiconductor element (100a to 100f) can be designed to be at a high level so as to withstand such a high voltage.

[0047] Each power semiconductor element (100a to 100f) can conduct a high current when turned on. The motor (M) is driven by a relatively high current, and this high current can be supplied to the motor (M) through the turned-on power semiconductor element.

[0048] A high voltage applied to each power semiconductor element (100a to 100f) may cause high switching loss. A high current flowing through the power semiconductor element (100a to 100f) may cause high conduction loss. To dissipate the heat generated by such loss, the power semiconductor elements (100a to 100f) may be packaged into a power semiconductor module including a heat dissipation means.

[0049] The power semiconductor device (100) of the embodiment may be a silicon carbide (SiC) power semiconductor device, and may be capable of operating in a high temperature, high voltage environment and may have a high switching speed and low switching loss.

[0050] Figures 2 to 5 are cross-sectional views of a process for manufacturing a semiconductor substrate for manufacturing a power semiconductor according to an embodiment.

[0051] First, as shown in Fig. 2, a base substrate (210) is prepared. The base substrate (210) may be a SiC (Silicon Carbide) substrate. For example, the base substrate (210) may include a 4H-SiC material, but is not limited thereto, and may include 3C-SiC or 6H-SiC.

[0052] The parent substrate (210) of the embodiment may include an off-cut (OC) SiC parent substrate, thereby providing high-quality power semiconductor devices and improving yield. For example, the parent substrate (210) of the embodiment may include, but is not limited to, an approximately 4° off-cut SiC parent substrate.

[0053] In the embodiment, 'off-cut' may also be referred to as 'off-axis cut', and is not limited thereto.

[0054] According to an embodiment, a single-crystal SiC epilayer can be grown by growing a SiC epilayer on an off-cut SiC base substrate, and there is a technical effect of providing a high-quality SiC MOSFET power semiconductor device by significantly reducing the defect density.

[0055] Next, as shown in Fig. 3, a carbon non-single crystal layer (230) and a graphene layer (220) are formed on the above-mentioned base material substrate (210).

[0056] Meanwhile, a comparative technology was studied to form a graphene layer on a SiC substrate by internally heating the SiC substrate.

[0057] However, there was a problem that the crystal quality of the SiC epilayer grown on the SiC base substrate on which the graphene layer was formed in the comparative technology was not high, and the problem that the SiC base substrate was difficult to recycle in subsequent processes was studied.

[0058] In this embodiment, in order to solve the problems of the above comparative technology, a graphene layer (220) and a carbon non-single crystal layer (230) were formed on a base substrate (210) through an annealing process at high temperature in a vacuum state.

[0059] For example, the embodiment may form a graphene layer (220) by heating the parent substrate (210) to a first temperature to evaporate Si on the upper surface. The graphene layer (220) may include a plurality of graphene layers. For example, the graphene layer (220) may include 3 to 6 graphene layers, but is not limited thereto.

[0060] Thereafter, by heating the parent substrate (210) to a second temperature lower than the temperature at which the graphene layer is formed, a carbon non-single crystal layer (230) can be formed between the upper surface of the parent substrate (210) and the graphene layer (220).

[0061] The above carbon non-single-crystal layer (230) may be a carbon layer, but may not be a single-crystal layer. For example, the above carbon non-single-crystal layer (230) may be a polycrystalline carbon layer, an amorphous carbon layer, or a combination thereof.

[0062] The second temperature may be lower than the first temperature, but is not limited thereto.

[0063] For example, the first temperature may be a temperature of about 1300°C or higher, and the second temperature may be a temperature of less than 1300°C, but is not limited thereto.

[0064] According to an embodiment, by heating the parent substrate (210) to a second temperature lower than the first temperature for forming a graphene layer, a 'carbon non-single-crystal layer (230)', which may be a polycrystalline carbon layer, an amorphous carbon layer, or a combination thereof, can be formed between the upper surface of the parent substrate (210) and the graphene layer (220).

[0065] In an embodiment, the carbon non-single crystal layer (230) may maintain a covalent bond with the parent substrate (210), while not forming a covalent bond with the graphene layer (220).

[0066] For example, according to an embodiment, even if Si is evaporated from the surface of the parent substrate (210), the covalent bond between the remaining carbon and the SiC parent substrate can be maintained.

[0067] For example, according to an embodiment, by heating the parent substrate (210) to a second temperature lower than the first temperature for forming a graphene layer while evaporating Si from the surface of the parent substrate (210), a carbon non-single-crystal layer (230) capable of maintaining a covalent bond with the parent substrate (210) can be formed.

[0068] On the other hand, the carbon non-single-crystal layer (230) can maintain a weak bond of van der Waals force with the graphene layer (220). For example, the carbon of the carbon non-single-crystal layer (230) and the graphene layer (220) can maintain a weak bond of van der Waals force rather than a covalent bond.

[0069] Next, as shown in FIG. 4, the graphene layer (220) can be separated using hydrogen plasma or the like, and through this, a semiconductor substrate (200) for manufacturing a power semiconductor having a carbon non-single crystal layer (230) according to an embodiment as shown in FIG. 5 can be manufactured.

[0070] A semiconductor substrate (200) for manufacturing a power semiconductor having a carbon non-single crystal layer (230) according to an embodiment has the effect of improving the crystal quality of a SiC epitaxial layer structure (100A) (see FIG. 6) grown thereafter.

[0071] In addition, the semiconductor substrate (200) for manufacturing a power semiconductor having a carbon non-single crystal layer (230) according to the embodiment has a special technical effect in that the grown SiC epitaxial layer structure (100A) can be recycled in a subsequent process after separation.

[0072] In the internal comparison technology, a technology was studied to form a graphene layer on a SiC base substrate by heating the SiC base substrate, but there was a problem that the crystal quality of the SiC epilayer grown on the SiC base substrate on which the graphene layer was formed was not high, and there was a problem that the SiC base substrate was difficult to recycle in subsequent processes.

[0073] To solve these problems, a semiconductor substrate (200) for manufacturing power semiconductors having a carbon non-single crystal layer (230) was studied in an embodiment.

[0074] Table 1 below shows data on the characteristics of the 'carbon non-single crystal layer (230)' of the example and the 'graphene layer' of the comparative example.

[0075] Gap between target substrate and bonding energy of substrate and carbon single crystal layer 2.1 ~ 2.4 Å 2 ~ 5 eV / atom Comparative example graphene layer 3.35 Å 106 meV / atom

[0076] The binding energy between the graphene layer and the SiC base substrate of the comparative example is about 106 meV / atom, which is a weak binding force, and the gap between the graphene layer and the SiC base substrate is also about 3.35 Å, which corresponds to the bond length of the van der Waals force. On the other hand, the binding energy between the carbon non-single crystal layer and the SiC base substrate of the example is about 2 to 5 eV / atom, which is a very strong binding force, and the gap between the carbon non-single crystal layer and the SiC base substrate is about 2.1 to 2.4 Å, which corresponds to the covalent bond length.

[0077] Additionally, the root mean square (RMS) of the surface roughness of the carbon non-single-crystal layer of the embodiment is approximately 1.4 times larger than that of the graphene layer of the comparative example. The carbon non-single-crystal layer of the embodiment may exhibit increased roughness as nearby constituent atoms are strained to relieve strain caused by covalent bonding.

[0078] Additionally, the band gap energy (Eg) of the carbon non-single crystal layer of the embodiment is approximately 0.6 eV, and unlike the graphene layer, it may have semiconductor properties.

[0079] Additionally, the bonding structure of the carbon non-single-crystal layer of the embodiment may exhibit distortion due to partial covalent bonds. For example, the bonding structure of the carbon non-single-crystal layer of the embodiment may be an undistorted σ state, but may also exhibit a partially distorted π state. On the other hand, the graphene layer does not exhibit such a bonding structure.

[0080] Next, FIGS. 6 to 9 are cross-sectional views of a process for manufacturing a power semiconductor device (100) using a semiconductor substrate for manufacturing a power semiconductor according to an embodiment.

[0081] First, as shown in Fig. 6, a SiC semiconductor structure (100A) can be formed on a semiconductor substrate (200) for manufacturing a power semiconductor having a carbon non-single crystal layer (230).

[0082] The carbon non-single crystal layer (230) of the embodiment can form a bond weaker than a covalent bond, for example, a van der Waals bond, with the SiC semiconductor structure (100A) grown thereafter.

[0083] In addition, the carbon non-single crystal layer (230) of the embodiment can improve the crystal quality of the SiC semiconductor structure (100A) grown thereafter by providing a nucleation site.

[0084] Accordingly, according to an embodiment, a semiconductor substrate (200) for manufacturing a power semiconductor having a carbon non-single crystal layer (230) has a technical effect of improving the crystal quality of a SiC semiconductor structure (100A) that is subsequently grown, and at the same time, allowing the SiC semiconductor structure (100A) to be easily separated from the semiconductor substrate (200) for manufacturing a power semiconductor due to a difference in bonding strength with the SiC semiconductor structure (100A) after growth.

[0085] For example, the carbon non-single-crystal layer (230) of the embodiment can maintain a strong covalent bond with the parent substrate (210), while maintaining a weak bond with the SiC semiconductor structure (100A) through van der Waals forces. Accordingly, there is a technical effect in that the SiC semiconductor structure (100A) having a relatively weak bond can be easily separated from the semiconductor substrate (200) for manufacturing a power semiconductor having the carbon non-single-crystal layer (230).

[0086] In addition, the semiconductor substrate (200) for manufacturing power semiconductors having a carbon non-single crystal layer (230) remaining after separation of the SiC semiconductor structure (100A) has a special technical effect in that it can be reused as a substrate for growing a SiC epitaxial structure in a separate process.

[0087] Next, Fig. 7 is a cross-sectional view of a SiC semiconductor structure (100A) grown on a semiconductor substrate (200) for manufacturing a power semiconductor having a carbon non-monocrystalline layer (230) according to an embodiment. The SiC semiconductor structure (100A) according to the embodiment is an example of a trench MOSFET structure, but is not limited to the embodiment.

[0088] A SiC semiconductor structure (100A) according to an embodiment may include at least one of a substrate (110), an epi layer (110E), a first well (121) of a second conductivity type, a first conductivity type source region (141), a source contact region (142), a source electrode (140), a gate insulating layer (131), a trench gate (132), and an interlayer insulating layer (150).

[0089] The above epi layer (110E) may include a first epi layer (111) of a first conductivity type and a second epi layer (112) of the first conductivity type. The first conductivity type may be N type, and the second conductivity type may be P type, but is not limited thereto. For example, the N type dopant may be injected with N or P, but is not limited thereto. In addition, the P type dopant may be injected with Al or boron, but is not limited thereto.

[0090] The substrate (110), the first conductive type first epi layer (111), and the first conductive type second epi layer (112) may include SiC (Silicon Carbide) and may be doped with N type, but are not limited thereto. For example, the substrate (110) and the first and second conductive type epi layers (111, 112) may include a 4H-SiC material, but are not limited thereto. For example, the substrate (110) and the first and second conductive type epi layers (111, 112) may include 3C-SiC or 6H-SiC.

[0091] The first epi layer (111) of the first conductive type may include a first conductive buffer layer (not shown) and a first conductive drift layer (not shown). The first epi layer (111) of the first conductive type may have a breakdown voltage (V) as it is doped at a lower concentration than the substrate (110). B ) can prevent drop. In addition, the second epi layer (112) of the first conductive type can lower the on-resistance by functioning as a current spreading layer (CSL) as it is doped at a higher concentration than the first epi layer (111) of the first conductive type.

[0092] The first well (121) of the second conductive type may be formed by ion implantation of a second conductive type dopant into the second epi layer (112) of the first conductive type or growth of the second conductive type epi layer. The first well (121) of the second conductive type may be referred to as a second conductive type base layer, but is not limited thereto.

[0093] The first conductive source region (141) may be formed by ion implantation into the second conductive first well (121). The doping concentration of the first conductive source region (141) may be higher than that of the second conductive first well (121). A predetermined second conductive contact region (not shown) may be partially formed, and the second conductive contact region may function to maintain the zero potential of the second conductive first well (121).

[0094] Next, a gate insulating layer (131) may be formed on the bottom and side walls of the trench region from which a portion of the first conductive source region (141), the second conductive first well (121), and the second epi layer (112) of the first conductive type are removed, by a thermal oxidation or deposition process. Next, a trench gate (132) may be formed in a trench on the gate insulating layer (131) by a polysilicon deposition process and an etch-back process.

[0095] Next, the source contact region (142) may be formed as a first conductive source region (141) and / or the second conductive contact region. For example, the source contact region (142) may be formed using Ti or Ni, but is not limited thereto. Next, the interlayer insulating layer (150) may be formed on the trench gate (132) by a deposition process such as an oxide film. Next, a source electrode (140) and a gate electrode (not shown) may be formed. The source electrode (140) or the gate electrode may include an Al-based metal, and may include a Ni layer, a Ti layer, a Ni / Ti layer, or a TiN / Ti silicide layer.

[0096] Next, as shown in Fig. 8, the SiC semiconductor structure (100A) can be separated from the semiconductor substrate (200) for manufacturing power semiconductors having a carbon non-single crystal layer (230).

[0097] The carbon non-single crystal layer (230) of the embodiment can form a bond weaker than a covalent bond, for example, a van der Waals bond, with the SiC semiconductor structure (100A) grown thereafter.

[0098] In addition, the carbon non-single crystal layer (230) of the embodiment can improve the crystal quality of the SiC semiconductor structure (100A) grown thereafter by providing a nucleation site.

[0099] Accordingly, according to an embodiment, a semiconductor substrate (200) for manufacturing a power semiconductor having a carbon non-single crystal layer (230) has a technical effect of improving the crystal quality of a SiC semiconductor structure (100A) that is subsequently grown, and at the same time, allowing the SiC semiconductor structure (100A) to be easily separated from the semiconductor substrate (200) for manufacturing a power semiconductor due to a difference in bonding strength with the SiC semiconductor structure (100A) after growth.

[0100] For example, the carbon non-single-crystal layer (230) of the embodiment can maintain a strong covalent bond with the parent substrate (210), while maintaining a weak bond with the SiC semiconductor structure (100A) through van der Waals forces. Accordingly, there is a technical effect in that the SiC semiconductor structure (100A) having a relatively weak bond can be easily separated from the semiconductor substrate (200) for manufacturing a power semiconductor having the carbon non-single-crystal layer (230).

[0101] In addition, the semiconductor substrate (200) for manufacturing power semiconductors having a carbon non-single crystal layer (230) remaining after separation of the SiC semiconductor structure (100A) has a special technical effect in that it can be reused as a substrate for growing a SiC epitaxial structure in a separate process.

[0102] Next, a power semiconductor device (100) according to the embodiment can be manufactured by forming a drain electrode (160) under a substrate (110) of a separated SiC semiconductor structure (100A) as shown in FIG. 9. The drain electrode (160) may include a Ni-based metal, and may include a Ti layer, a Ni layer, or a Ag layer. For example, the drain electrode (160) may include, but is not limited to, Ti / Ag, Ti / Ni / Ag, NiV / Ag, V(vanadium) / Ni / Ag, etc.

[0103] According to an embodiment, a semiconductor substrate for manufacturing a high-quality power semiconductor device, a method for manufacturing the same, and a method for manufacturing a power semiconductor device using the same can be provided. For example, according to an embodiment, a single-crystal SiC epilayer can be grown by growing a SiC epilayer on an off-cut SiC base substrate, and a defect density is also significantly reduced, thereby providing a technical effect of providing a high-quality SiC MOSFET power semiconductor device.

[0104] In addition, the carbon non-single crystal layer (230) of the embodiment can improve the crystal quality of the SiC semiconductor structure (100A) grown thereafter by providing a nucleation site.

[0105] Accordingly, according to an embodiment, a semiconductor substrate (200) for manufacturing a power semiconductor having a carbon non-single crystal layer (230) has a technical effect of improving the crystal quality of a SiC semiconductor structure (100A) that is subsequently grown, and at the same time, allowing the SiC semiconductor structure (100A) to be easily separated from the semiconductor substrate (200) for manufacturing a power semiconductor due to a difference in bonding strength with the SiC semiconductor structure (100A) after growth.

[0106] In addition, the semiconductor substrate (200) for manufacturing power semiconductors having a carbon non-single crystal layer (230) remaining after separation of the SiC semiconductor structure (100A) has a special technical effect in that it can be reused as a substrate for growing a SiC epitaxial structure in a separate process.

[0107] Although the present invention has been described above with reference to embodiments thereof, it will be readily understood by those skilled in the art that various modifications and changes to the present invention can be made without departing from the spirit and scope of the present invention as set forth in the claims below.

[0108] A semiconductor substrate for manufacturing a power semiconductor according to an embodiment can be applied to a power conversion device. The power conversion device can receive DC power from a battery or a fuel cell, convert it into AC power, and supply AC power to a predetermined load. For example, the power conversion device can include an inverter, receive DC power from a battery, convert it into three-phase AC power, and supply it to a motor, which can then provide power to an electric vehicle, a fuel cell vehicle, or the like.

Claims

1. Step of preparing an off-cut parent material substrate; A step of forming a graphene layer and a carbon non-single crystal layer on the above-mentioned parent substrate; and A method for manufacturing a semiconductor substrate for manufacturing a power semiconductor, comprising: a step of separating the graphene layer from the carbon non-single crystal layer.

2. In paragraph 1, The step of forming the above graphene layer and the above carbon non-single crystal layer is: A step of forming a graphene layer on the upper side of the base substrate by heating the base substrate to a first temperature; and A method for manufacturing a semiconductor substrate for manufacturing a power semiconductor, comprising: a step of heating the base substrate to a second temperature lower than the first temperature to form the carbon non-single-crystal layer between the surface of the base substrate and the graphene layer.

3. In paragraph 1, The above carbon non-single crystal layer is, A method for manufacturing a semiconductor substrate for manufacturing a power semiconductor, the semiconductor substrate comprising a polycrystalline carbon layer, an amorphous carbon layer, or a combination thereof.

4. In paragraph 1, A method for manufacturing a semiconductor substrate for manufacturing a power semiconductor, wherein the carbon non-single crystal layer maintains a covalent bond with the parent substrate and a bond weaker than a covalent bond with the graphene layer.

5. In paragraph 1, A method for manufacturing a semiconductor substrate for manufacturing a power semiconductor, wherein the carbon non-single crystal layer maintains a covalent bond with the parent substrate and does not maintain a covalent bond with the graphene layer.

6. Off-cut parent material substrate; and Comprising a carbon non-single crystal layer formed on the above-mentioned parent substrate; Semiconductor substrate for manufacturing power semiconductors.

7. In paragraph 6, The above carbon non-single crystal layer is, A semiconductor substrate for manufacturing power semiconductors, comprising a polycrystalline carbon layer, an amorphous carbon layer, or a combination thereof.

8. In paragraph 6, A semiconductor substrate for manufacturing power semiconductors, wherein the above carbon non-single crystal layer maintains a covalent bond with the above mother substrate.

9. A step of preparing a semiconductor substrate for manufacturing a power semiconductor according to any one of claims 6 to 8; A step of forming a first SiC semiconductor structure on a semiconductor substrate for manufacturing the power semiconductor; and A method for manufacturing a power semiconductor device, comprising: a step of separating the first SiC semiconductor structure from the semiconductor substrate for manufacturing the power semiconductor.

10. In paragraph 9, A method for manufacturing a power semiconductor device, wherein the carbon non-monocrystalline layer of the semiconductor substrate for manufacturing the power semiconductor maintains a bond weaker than a covalent bond with the first SiC semiconductor structure.

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