A resistive random-access memory device

Abstract

This document describes a resistive random-access memory (RRAM) device and a method for manufacturing the same. This application also relates to a one-transistor and one-resistor array circuit that includes a plurality of RRAM device and transistor pairs, and a method for manufacturing the array circuit.

Description

A RESISTIVE RANDOM-ACCESS MEMORY DEVICECROSS-REFERENCE TO RELATED APPLICATION

[0001] This application claims the benefit of priority to Singapore patent application no. 10202303610R which was filed on 22 December 2023, the contents of which are hereby incorporated by reference in its entirety for all purposes.TECHNICAL FIELD

[0002] This application relates to a resistive random-access memory (RRAM) device and a method for manufacturing the same. This application also relates to a one-transistor and one- resistor array circuit that includes a plurality of RRAM device and transistor pairs, and a method for manufacturing the array circuit.BACKGROUND

[0003] With the advent of the "post-Moorc era," silicon-based flash memory technologies are facing significant challenges in meeting the demands for massive information storage and processing. Resistive random-access memory (RRAM) devices have emerged as promising candidates for next-generation non-volatile memory due to their low power consumption and high-density capacity. However, RRAM devices often suffer from reliability issues, primarily caused by uncontrollable filamentary conduction within the resistive switching layer. This is due to the random motion and relaxation of defects, such as vacancies or metal ions, in amorphous resistive materials. These challenges necessitate a shift in resistive switching mechanisms to improve device reliability and enable industrial integration.

[0004] In conventional RRAM devices that utilize amorphous-based resistive switching layers, conductive filaments (CFs) form and grow along stochastic diffusion pathways driven by the random motion or relaxation of metastable defects. This results in uncontrollable CF morphology and unexpected filament overgrowth, leading to large variations in switching voltages and poor endurance over multiple cycles. The inherent randomness in the filamentary conduction mechanism is a major factor limiting the performance and scalability of defect-type amorphous RRAM devices.

[0005] As such, those skilled in the art arc constantly striving to find ways to eliminate the random motion of metastable defects to improve reliability, to reduce variability in switching voltages, and to enhance the endurance of RRAM devices to enable these devices to be widely adopted in more systems. Additionally, it is desirable to develop a method to guide the growth of conductive filaments in the resistive switching layer, thereby moving away from the conventional defect-driven filamentary conduction mechanism.SUMMARY

[0006] In one aspect, the present disclosure describes a resistive random-access memory (RRAM) device comprising a pair of electrodes, and a resistive switching layer being formed between the pair of electrodes where the resistive switching layer comprises a transition metal- doped material with a wurtzite (002) structure. In embodiments of the disclosure, a part of the resistive switching layer undergoes a phase transition from a wurtzite (002) phase to a rocksalt (111) phase when an electric field is applied across the pair of electrodes, the part of the resistive switching layer that underwent the phase transition conductively linking the pair of electrodes together, and the part of the resistive switching layer undergoes another phase transition from the rocksalt (111) phase to the wurtzite (002) phase when the electric field switches polarity across the pair of electrodes.

[0007] In a further embodiment of this aspect, the transition metal-doped material comprises an Aluminum Nitride (AIN) layer having the wurtzite (002) crystal structure whereby the AIN layer is doped with at least one element selected from Group IIIB elements including Scandium (Sc), Yttrium (Y), Lanthanum (La), Lutetium (Lu), or Actinium (Ac).

[0008] In a further embodiment of this aspect, the transition metal-doped material comprises an Aluminum Nitride (AIN) layer having the wurtzite (002) crystal structure whereby the AIN layer is co-doped with at least one element selected from Group IA elements including Lithium (Li), Sodium (Na), Potassium (K), Rubidium (Rb), Cesium (Cs) or Francium (Fr) and at least one element selected from Group VB elements including Vanadium (V), Niobium (Nb) or Tantalum (Ta).

[0009] In a further embodiment of this aspect, the transition metal-doped material comprises an Aluminum Nitride (AIN) layer having the wurtzite (002) crystal structurewhereby the AIN layer is co-dopcd with at least one element selected from Group IIA elements including Magnesium (Mg), Beryllium (Be), Calcium (Ca), Strontium (Sr), Barium (Ba) or Radium (Ra) and at least one element selected from Group IVB elements including Zirconium (Zr), Hafnium (Hf) or Titanium (Ti).

[0010] In a further embodiment of this aspect, the part of the resistive switching layer that underwent the phase transition is formed in a region of the transition metal-doped material where the applied electric field is the strongest or is formed in a region of the transition metal- doped material with a high concentration of dopants.

[0011] In yet a further embodiment of this aspect, the present disclosure describes a one- transistor and one-resistor array circuit comprising a first and a second transistor, and a first and a second RRAM device according to the RRAM device described in the embodiments above, whereby source electrodes of the first and second transistors are electrically connected to a source line terminal, gate electrodes of the first and second transistors are electrically connected to a word line terminal, a drain electrode of the first transistor is electrically connected to an electrode of the pair of electrodes of the first RRAM device, another electrode of the pair of electrodes of the first RRAM device is electrically connected to a first bit line terminal, a drain electrode of the second transistor is electrically connected to an electrode of the pair of electrodes of the second RRAM device, and another electrode of the pair of electrodes of the second RRAM device is electrically connected to a second bit line terminal.

[0012] In another aspect, the present disclosure describes a method for forming a resistive random-access memory (RRAM) device comprising the steps of forming a resistive switching layer comprising a transition metal -doped material with a wurtzite (002) structure on a bottom electrode and forming a top electrode on the resistive switching layer such that the resistive switching layer is disposed between the top and bottom electrodes. In this embodiment, a part of the resistive switching layer undergoes a phase transition from a wurtzite (002) phase to a rocksalt (111) phase when an electric field is applied across the pair of electrodes, the part of the resistive switching layer that underwent the phase transition conductively linking the pair of electrodes together, and the resistive switching layer undergoes another phase transition from the rocksalt (111) phase to the wurtzite (002) phase when the electric field switches polarity across the pair of electrodes.

[0013] In a further embodiment of this another aspect, the transition metal-doped material comprises an Aluminum Nitride (AIN) layer having the wurtzite (002) crystal structure whereby the AIN layer is doped with at least one element selected from Group IIIB elements including Scandium (Sc), Yttrium (Y), Lanthanum (La), Lutetium (Lu), or Actinium (Ac)

[0014] In a further embodiment of this another aspect, the transition metal-doped material comprises an Aluminum Nitride (AIN) layer having the wurtzite (002) crystal structure whereby the AIN layer is co-doped with at least one element selected from Group IA elements including Lithium (Li), Sodium (Na), Potassium (K), Rubidium (Rb), Cesium (Cs) or Francium (Fr) and at least one element selected from Group VB elements including Vanadium (V), Niobium (Nb) or Tantalum (Ta).

[0015] In a further embodiment of this another aspect, the transition metal-doped material comprises an Aluminum Nitride (AIN) layer having the wurtzite (002) crystal structure whereby the AIN layer is co-doped with at least one element selected from Group 11A elements including Magnesium (Mg), Beryllium (Be), Calcium (Ca), Strontium (Sr), Barium (Ba) or Radium (Ra) and at least one element selected from Group IVB elements including Zirconium (Zr), Hafnium (Hf) or Titanium (Ti).

[0016] In yet a further embodiment of this another aspect, the present disclosure describes a one-transistor and one-resistor array circuit comprising a first and a second transistor, and a first and a second RRAM device formed according to the methods described in the embodiments whereby source electrodes of the first and second transistors are electrically connected to a source line terminal, gate electrodes of the first and second transistors are electrically connected to a word line terminal, a drain electrode of the first transistor is electrically connected to the bottom electrode of the first RRAM device, the top electrode of the first RRAM device is electrically connected to a first bit line terminal, a drain electrode of the second transistor is electrically connected to the bottom electrode of the second RRAM device, and the top electrode of the second RRAM device is electrically connected to a second bit line terminal.BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Various embodiments of the present disclosure arc described below with reference to the following drawings:Figure 1 illustrates a structural diagram of a resistive random-access memory (RRAM) device in accordance with embodiments of the present disclosure when a negative and a positive biasing voltage is applied to a pair of electrodes of the RRAM device;Figure 2 illustrates the transition of a wurtzite (002) structure from a wurtzite (002) phase to a rocksalt (111) phase when a positive biasing voltage is applied to the structure and the transition back to the wurtzite (002) phase when a negative biasing voltage is applied;Figure 3 illustrates a current-voltage plot of an RRAM device when the resistive switching layer of the RRAM device comprises an Aluminum Nitride layer doped with Scandium (AlScN) and the electrodes comprise Platinum;Figure 4 illustrates a cycling endurance of the RRAM device described in Figure 3 when the RRAM device is subject to a pulse test;Figure 5 illustrates a plot showing the Reset-Set transition speed measurement of the RRAM device described in Figure 3;Figure 6 illustrates a plot showing the switching curves of the RRAM device described in Figure 3 at different temperatures;Figure 7 illustrates a schematic diagram of a one-transistor one -resistor array circuit in accordance with embodiments of the present disclosure;Figure 8 illustrates a diagram of a one -transistor one-resistor pair where the one-resistor comprises an RRAM device in accordance with embodiments of the present disclosure; and Figure 9 illustrates a flowchart showing a process for forming an RRAM device in accordance with embodiments of the present disclosure.DETAILED DESCRIPTION

[0018] The following detailed description is made with reference to the accompanying drawings, showing details and embodiments of the present disclosure for the purposes of illustration. Features that are described in the context of an embodiment may correspondingly be applicable to the same or similar features in the other embodiments, even if not explicitly described in these other embodiments. Additions and / or combinations and / or alternatives as described for a feature in the context of an embodiment may correspondingly be applicable to the same or similar feature in the other embodiments.

[0019] Tn the context of various embodiments, the articles “a”, “an” and “the” as used with regard to a feature or element include a reference to one or more of the features or elements.

[0020] In the context of various embodiments, the term “about” or “approximately” as applied to a numeric value encompasses the exact value and a reasonable variance as generally understood in the relevant technical field, c.g., within 10% of the specified value.

[0021] As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0022] As used herein, “comprising” means including, but not limited to, whatever follows the word “comprising”. Thus, use of the term “comprising” indicates that the listed elements are required or mandatory, but that other elements are optional and may or may not be present.

[0023] As used herein, “consisting of’ means including, and limited to, whatever follows the phrase “consisting of’. Thus, use of the phrase “consisting of’ indicates that the listed elements are required or mandatory, and that no other elements may be present.

[0024] In the context of various embodiments, the directional terms mentioned herein, such as “top” and “bottom” or “upper” and “lower” refer to directions as described with reference to the drawings. Therefore, the directional terms are only used for illustration and are not meant to limit the present disclosure.

[0025] In the context of various embodiments, it should be noted that when a material compound is described, such as AlxSc(i-x)N, the description refers to combinations of the listed elements. For example, AlxSc(i-x)N encompasses various ratios of Aluminum and Scandium within the compound where x can be equal to or less than 1, among other possibilities.

[0026] It should be noted that although the terms first, second and third are used herein to describe various elements, these elements should not be limited by these terms as these terms are meant to only distinguish one element from another element. Thus, the first element described herein could be termed as a second element without departing from this disclosure.

[0027] As used herein, a “layer” refers to a material portion including a region having a particular thickness. The layer may extend over the entirety of the structure or may cover only part of the structure as defined in the description. For example, a layer may be located betweentwo horizontal planes; may be located between, or at, a top surface and a bottom surface of the structure. The layer may also extend horizontally, vertically, and / or along the surface of the structure.

[0028] Additionally, for the sake of brevity, extensive explanations of conventional techniques of fabricating semiconductor devices and integrated circuits are not described in detail herein. The tasks and processes described herein may also be integrated into a more comprehensive procedure with extra steps of features that are not elaborated upon in this document. Specifically, certain processes of fabricating semiconductor devices are well known to one skilled in the art hence, such processes will be omitted entirely.

[0029] Transition metals comprise a class of elements that arc located in the d-block of the periodic table, encompassing groups 3 through 12. These elements are defined by their ability to form ions with partially filled d orbitals, which impart unique chemical and physical properties. When transition metals are doped to form a wurtzite (002) structure, this causes the transition metal’s electronic, structural, and resistive switching properties to significantly alter through the introduction of strain or modification of the lattice constants of the transition metal due to their ionic radii and electronic configurations.

[0030] The wurtzite (002) structure is a specific orientation of the hexagonal wurtzite crystal lattice. In such a structure, the atoms arc usually arranged in a hexagonal close-packed geometry with a distinctive layering along a c-axis (i.e., perpendicular to the (002) plane). It is useful to note that the (002) plane denotes a crystallographic plane in the hexagonal lattice that is aligned along the c-axis, representing the direction of the unit cell's vertical stacking. In most embodiments, the wurtzite structure comprises a tetrahedral coordination, whereby each atom in this structure is surrounded by four nearest neighbors.

[0031] A rocksalt (111) structure or phase refers to a specific orientation of a cubic rocksalt crystal lattice, commonly seen in doped Aluminum Nitride (AIN) under certain conditions. In the rocksalt crystal lattice, atoms are arranged in a face-centered cubic structure, where each cation is surrounded by six anions, and vice versa, forming an octahedral coordination. The (111) plane is one of the crystallographic planes in this structure, cutting through the crystal lattice in a direction that exposes a dense packing of atoms.

[0032] In the context of transition metal-doped materials, the rocksalt (111) phase often arises as a result of a phase transition from other crystalline phases, such as the wurtzite (002) structure, under the influence of external stimuli such as electrical bias or electric field. This transition involves a rearrangement of atoms from a hexagonal arrangement to a cubic configuration, accompanied by changes in physical properties such as conductivity and defect behavior.

[0033] A structural diagram of resistive random-access memory (RRAM) device 100 in accordance with embodiments of the present disclosure is illustrated in Figure 1. RRAM device 100 comprises substrate 102, bottom electrode 104 that is disposed on substrate 102, resistive switching layer 106 that is formed on bottom electrode 104, and top electrode 108 that is disposed on resistive switching layer 106 such that the resistive switching layer 106 is formed between the pair of electrodes, i.e., bottom electrode 104 and top electrode 108.

[0034] In embodiments of the disclosure, substrate 102 may comprise silicon or silicon dioxide, and bottom electrode 104 and top electrode 108 may each comprise Platinum, whereby the bottom electrode 104 may be disposed on substrate 102 through a magnetron sputtering process, and the top electrode 108 may be disposed on resistive switching layer 106 through the magnetron sputtering process.

[0035] In embodiments of the disclosure, resistive switching layer 106 may comprise a type of high-performance transition metal-doped material having a wurtzite type structure such as, but not limited to, a wurtzite-type Aluminum Nitride poly crystalline film that is doped with at least one element selected from Group IIIB elements including Scandium (Sc), Yttrium (Y), Lanthanum (La), Lutetium (Lu), or Actinium (Ac). In other embodiments of the disclosure, the wurtzite-type Aluminum Nitride poly crystalline film may be co-doped with at least one element selected from Group IA elements including Lithium (Li), Sodium (Na), Potassium (K), Rubidium (Rb), Cesium (Cs) or Francium (Fr) and at least one element selected from Group VB elements including Vanadium (V), Niobium (Nb) or Tantalum (Ta). In yet other embodiments of the disclosure, the wurtzite-type Aluminum Nitride polycrystalline film may be co-doped with at least one element selected from Group IIA elements including Magnesium (Mg), Beryllium (Be), Calcium (Ca), Strontium (Sr), Barium (Ba) or Radium (Ra) and at leastone element selected from Group IVB elements including Zirconium (Zr), Hafnium (Hf) or Titanium (Ti).

[0036] When a positive biasing voltage 110 is applied between bottom electrode 104 and top electrode 108, i.e., the pair of electrodes, this causes an electric field to be formed between the pair of electrodes. As a result, a part of the resistive switching layer undergoes a phase transition from a wurtzite (002) phase to a rocksalt (111) phase. This part of the resistive switching layer that underwent the phase transition is identified in Figure 1 as phase-changed region 112. As can be seen from this Figure, phase-changed region 112 is formed between the pair of electrodes, conductively linking bottom electrode 104 and top electrode 108. This conductive link that is formed by phase-change region 1 12 transitions RRAM device 100 from a high resistance state to a low resistance state.

[0037] In embodiments of the disclosure, dopants may be strategically introduced and distributed within resistive switching layer 106 in order to control the location and size of phase-changed region 112. This occurs because the distribution of dopants within resistive switching layer 106 determines the electric field strength and current density within this layer. Areas with higher dopant concentrations typically exhibit lower resistivity, leading to greater local electric field intensities and higher current densities when a positive bias is applied between the pair of electrodes. This localized field concentration within the resistive switching layer 106, and this localized field may in turn bigger the formation of a conductive filament or a phase transition in this specific region when an electric field is applied. Additionally, the formation or the distribution of the electric field between the pair of electrodes may be selectively tailored to control the location and size of phase-changed region 112.

[0038] Figure 2 illustrates a wurtzite (002) crystal structure 202 that has transitioned from a wurtzite (002) phase to a rocksalt (1 1 1) phase 210. This diagram illustrates a reversible phase transition between the wurtzite phase and the rocksalt phase 210 when an external voltage is applied to the structure, i.e., when an electric field is formed across the structure. Wurtzite structure 202, with its hexagonal crystal structure, represents the high-resistance state of the material when a negative voltage is applied. It is characterized by a tetrahedral arrangement of atoms and a layered atomic arrangement along the c-axis. In embodiments of the disclosure, wurtzite structure 202 may be formed by a combination of aluminum 204, nitride 208, anddopants from Group IIIB, VB, or IVB elements 206. When a positive voltage is applied to wurtzite structure 202, the voltage and the subsequent electric field induces a phase transition from the wurtzite phase to the rocksalt phase 210, while a negative voltage reverses the process.

[0039] For completeness, it should be noted that rocksalt phase 210 exhibits a cubic structure with octahedral coordination of atoms, which is associated with the low-resistance state of the material. This structure is denser and more conductive due to its higher atomic packing efficiency and alignment of ions. The dopants incorporated into the material (from Group IIIB, VB, or IVB) facilitate the controlled growth and rupture of conductive filaments during the phase transitions, ensuring reliable and repeatable resistive switching. These phase transitions are used for the operation of the RRAM device, where the two phases represent binary states ("1 " for low resistance and "0" for high resistance) in non-volatile memory storage applications.

[0040] Based on Figures 1 and 2, it can be seen that resistive switching layer 106 exhibits a reversible wurtzitc-to-rocksalt phase transition when appropriate biasing voltages or electric fields are applied to RRAM device 100, enabling phase-changeable resistive switching during the operation of the device. This unique property allows the controlled growth and rupture of phase transition-type conductive filaments within phase-changed region 1 12 of resistive switching layer 106. The precise control over these phase transitions results in stable resistive switching (RS) behaviors.

[0041] Additionally, such RRAM devices are able to achieve remarkably fast switching speeds, on the order of nanoseconds, with potential switching times as low as the picosecond (ps) level due to the rapid wurtzite-to-rocksalt phase transition process. This fast phase change enables ultra-fast write and erase operations, making such RRAMs an ideal candidate for highspeed, energy-efficient non-volatile memory applications.

[0042] Experimental Results

[0043] In embodiments of the disclosure, a RRAM device having a transition metal-doped layer comprising an Aluminum Nitride (AIN) layer that was doped with Scandium (Sc), i.e., a group IIIB clement, was formed. The top and bottom electrodes of this RRAM device wereformed from Platinum (111) as Platinum (111) was a good lattice match with the AlScN resistive switching layer. The resulting RRAM device comprised a 50nm thick resistive switching layer of poly cry stallinc Alo7Sco 3N that was found to be stable, possesses low leakage current and good compatibility with existing complementary metal oxide semiconductor (CMOS) technology. In the absence of an applied electric field between the pair of electrodes, the AlScN resistive switching layer possessed a wurtzite (002) structure. When an electric field is applied across the pair of electrodes, a part of the AlScN resistive switching layer undergoes a phase transition from a wurtzite (002) phase to a rocksalt (111) phase.

[0044] The current-voltage (I-V) characteristics of the RRAM device described above device over approximately 50 switching cycles are illustrated in Figure 3. The I-V plots in Figure 3 illustrate bipolar RS behavior of the RRAM device. It can be seen that the RRAM device operates with a positive SET voltage of about +0.3 V, where the resistive switching layer transitions to a low-resistance state (LRS), and a negative RESET voltage of about -0.25 V, where the layer returns to a high-resistance state (HRS). In other words, it can be said that the RRAM device described above has a resistive switching voltage of about 0.3 Volts. These transitions indicate the formation and rupture of conductive filaments (CFs) within the resistive switching layer, driven by the applied electric field across the pair of electrodes.

[0045] It should be noted from these plots that the RRAM device operates at lower voltages compared to traditional oxide -based RRAM, which typically requires higher SET / RESET voltages. This characteristic makes the RRAM device particularly suitable for low-power applications and high-density integration in modem memory technologies. The plots in Figure 3 also highlight the stable and repeatable resistive switching performance over multiple cycles, further emphasizing the RRAM device's potential for reliable non-volatile memory applications.

[0046] Figure 4 illustrates the endurance characteristics of the RRAM device, demonstrating its ability to sustain reliable switching over an exceptionally high number of cycles, exceeding 1 x 108cycles. The graph tracks the resistance values of the device's low- resistance state 402 plots and high-resistance state 404 plots during repeated switching cycles, showing low coefficient of relative fluctuations in resistance values of approximately 7.77% for the LRS, and 9.78% for the HRS. These minimal fluctuations underscore the device'sstability and reliability, even under prolonged operation. The excellent endurance may be attributed to the controlled growth and rupture of phase-changeable conductive filaments facilitated by the reversible wurtzitc-to-rocksalt phase transition. This phase-transition mechanism eliminates the randomness typically associated with defect-based conduction paths, leading to highly consistent switching behavior.

[0047] Figure 5 illustrates the resistive switching response of the RRAM device when it is triggered by write and erase pulses of approximately +1.5 V (write) and -1.5 V (erase), each with a pulse width of 20 ns. The graph shows the device's input voltage 504 and corresponding output current 502 over time, with consistent read pulses verifying the device’ s resistance state. The fast transition between the high-resistance state and low-resistance state demonstrates reliable resistive switching behavior. Notably, the SET / RESET process was found to occur within a switching time of <3 ns, which is significantly faster than most oxide-based RRAM technologies. This ultrafast switching speed may be attributed to the rapid wurtzite-to-rocksalt phase change mechanism in the transition metal-doped layer.

[0048] Figure 6 illustrates the switching curves of the RRAM device at various ambient temperatures, ranging from 323 K to 523 K. As can be seen from this Figure, the currentvoltage characteristics demonstrate consistent resistive switching behavior across this wide temperature range. The RRAM device was able to maintain its functionality and exhibits no degradation at the highest tested temperature of 523 K with both the SET and RESET processes occurring reliably, and with the switching voltages remaining stable across the temperature spectrum. This remarkable thermal robustness is attributed to the temperature-independent phase transition mechanism in the transition metal-doped Aluminum Nitride layer. Unlike defect-based mechanisms that are often sensitive to thermal fluctuations, the wurtzite-to- rocksalt phase transition in this RRAM device remains unaffected by changes in ambient temperature.

[0049] A one-transistor and one-resistor array circuit

[0050] In embodiments of the disclosure, the RRAM device described in the previous sections may be used in high-density and highly integrated storage applications such as inmemory computing.

[0051] Such a one-transistor and one -resistor (1T1R) array circuit 700 is illustrated in Figure 7. Specifically, a memory cell in array circuit 700 comprises RRAM device 702 (that acts as a memory cell) and transistor 704 that acts as a selector for the corresponding RRAM device and this enables precise control of read and write operations of the RRAM device. Although the array circuit in Figure 7 illustrates eight 1T1R circuits, one skilled in the art will recognize that the array circuit may comprise of any number of IT 1R circuits without departing from this disclosure.

[0052] The shared interconnects between the 1T1R circuits include the source line (SL), which is laid out in a vertical direction in Figure 7 and is common to all cells in a column; the bit line (BL), which is also laid out vertically and is used for reading or writing data to the RRAM devices; and the word line (WL), which is laid out horizontally and enables the selection of specific rows for operation. It is useful to note that the source line (SL) is electrically coupled to the source electrodes of transistors 704 and 706 (and other corresponding transistors as shown in Figure 7), the word line (WL) is electrically coupled to the gate electrodes of transistor 704 and 706, the bit line (BL1) is electrically coupled to an electrode of RRAM device 708 with the other electrode of RRAM device 708 being electrically coupled to the drain electrode of transistor 706, and the bit line (BL2) is electrically coupled to an electrode of RRAM device 702 with the other electrode of RRAM device 702 being electrically coupled to the drain electrode of transistor 704.

[0053] The operation of the anay circuit 700 relies on the voltages provided to the word line (WL) and the source line (SL). During a write operation, a specific voltage is provided to the word line (WL) to activate the transistor, allowing a current to flow between the bit lines (BL1), (BL2) and the source line (SL). Depending on the bias applied across the corresponding RRAM device, this bias then triggers the wurtzite-to-rocksalt phase transition in the RRAM device, resulting in the formation or rupture of conductive filaments in a part of the resistive switching layer of the RRAM device. During a read operation, a lower voltage is applied to the word line (WL) to activate the transistor without disturbing the RRAM device’s state, enabling current sensing through the corresponding bit line (BL) to determine whether the cell is in the high-resistance or low-resistance state. During a write operation, the state of the RRAM device is altered by applying the appropriate voltage to induce the desired resistive switching behavior.The process involves selectively addressing the target cell by activating the corresponding word line (WL) and applying the required bias across the bit line (BL) and source line (SL) to either form a SET - Low-Resistance State or RESET - High-Resistance State. Such a configuration of the array circuit ensures high selectivity, avoids sneak path currents, and enhances the scalability of the array circuit.

[0054] Figure 8 illustrates a cross-sectional view of a 1T1R memory cell structure 800, which integrates a RRAM device with a transistor for precise control of its operation. The structure is formed on substrate 802, typically comprising silicon or a silicon-on-insulator (SOI) material. Oxide layer 804 is deposited as an insulating material on substrate 802. The transistor illustrated in Figure 8 comprises source electrode 808 which is electrically coupled to the source line (SL), gate electrode 810 which is electrically coupled to the word line (WL), and gate electrode 806 which is electrically coupled to the bottom electrode 818 of RRAM device 812. RRAM device 812 comprises a resistive switching layer 816 that is disposed between bottom electrode 818 and top electrode 814. Top electrode 814 is in turn electrically coupled to the bit line (BL).

[0055] A process for forming a resistive random-access memory (RRAM) device in accordance with an embodiment of this disclosure is illustrated in Figure 9. It should be noted that process 900 may be performed using standard semiconductor fabrication or manufacturing steps.

[0056] Process 900 begins at step 902 by forming a resistive switching layer comprising a transition metal-doped material with a wurtzite (002) structure on a bottom electrode. In embodiments of the disclosure, the bottom electrode may be formed on a substrate layer. Process 900 then proceeds to step 904 where process 900 proceeds to form a top electrode on the resistive switching layer such that the resistive switching layer is disposed between the top and bottom electrodes. A part of the resistive switching layer then undergoes a phase transition from a wurtzite (002) phase to a rocksalt (111) phase when an electric field is applied across the pair of electrodes with the part of the resistive switching layer that underwent the phase transition, i.c., the phase-changed region, conductivcly linking the pair of electrodes together. When the electric field switches polarity across the pair of electrodes, the phase-changed regionthen undergoes another phase transition from the rocksait (111) phase to the wurtzite (002) phase.

[0057] In embodiments of the disclosure, the transition metal-doped material of the RRAM device may comprise an Aluminum Nitride (AIN) layer having the wurtzite (002) crystal structure, the AIN layer being doped with at least one element selected from Group IIIB elements including Scandium (Sc), Yttrium ( Y), Lanthanum (La), Lutetium (Lu), or Actinium (Ac); or the AIN layer being co-doped with at least one element selected from Group IA elements including Lithium (Li), Sodium (Na), Potassium (K), Rubidium (Rb), Cesium (Cs) or Francium (Fr) and at least one element selected from Group VB elements including Vanadium (V), Niobium (Nb) or Tantalum (Ta); or the AIN layer being co-doped with at least one element selected from Group IIA elements including Magnesium (Mg), Beryllium (Be), Calcium (Ca), Strontium (Sr), Barium (Ba) or Radium (Ra) and at least one element selected from Group 1VB elements including Zirconium (Zr), Hafnium (Hf) or Titanium (Ti).

[0058] In embodiments of the disclosure, process 900 may form a one-transistor and one- resistor array circuit comprising a first and a second transistor, and a first and a second RRAM device formed according to steps 902 and 904 whereby source electrodes of the first and second transistors are electrically connected to a source line terminal; gate electrodes of the first and second transistors are electrically connected to a word line terminal; a drain electrode of the first transistor is electrically connected to the bottom electrode of the first RRAM device; the top electrode of the first RRAM device is electrically connected to a first bit line terminal; a drain electrode of the second transistor is electrically connected to the bottom electrode of the second RRAM device; and the top electrode of the second RRAM device is electrically connected to a second bit line terminal.

[0059] In embodiments of the disclosure, process 900 may form a third and a fourth transistor, and a third and a fourth RRAM device in the previously formed one-transistor and one-resistor array circuit according to steps 902 and 904 whereby source electrodes of the third and fourth transistors arc electrically connected to the source line terminal; gate electrodes of the third and fourth transistors are electrically connected to the word line terminal; a drain electrode of the third transistor is electrically connected to the bottom electrode of the third RRAM device; the top electrode of the third RRAM device is electrically connected to the firstbit line terminal; a drain electrode of the fourth transistor is electrically connected to the bottom electrode of the fourth RRAM device; and the top electrode of the fourth RRAM device is electrically connected to the second bit line terminal.

[0060] Numerous other changes, substitutions, variations, and modifications may be ascertained by the skilled in the art and it is intended that the present application encompass all such changes, substitutions, variations and modifications as falling within the scope of the appended claims.

Claims

CLAIMS1. A resistive random-access memory (RRAM) device comprising: a pair of electrodes; a resistive switching layer being formed between the pair of electrodes, the resistive switching layer comprising a transition metal -doped material with a wurtzite (002) structure, wherein a part of the resistive switching layer undergoes a phase transition from a wurtzite (002) phase to a rocksalt (111) phase when an electric field is applied across the pair of electrodes, the part of the resistive switching layer conductively linking the pair of electrodes together, and wherein the part of the resistive switching layer undergoes another phase transition from the rocksalt (111) phase to the wurtzite (002) phase when the electric field switches polarity across the pair of electrodes.

2. The device according to claim 1, wherein the transition metal-doped material comprises an Aluminum Nitride (AIN) layer having the wurtzite (002) crystal structure, the AIN layer being doped with at least one element selected from Group IIIB elements including Scandium (Sc), Yttrium (Y), Lanthanum (La), Lutetium (Lu), or Actinium (Ac).

3. The device according to claim 1, wherein the transition metal-doped material comprises an Aluminum Nitride (AIN) layer having the wurtzite (002) crystal structure, the AIN layer being co-doped with at least one element selected from Group IA elements including Lithium (Li), Sodium (Na), Potassium (K), Rubidium (Rb), Cesium (Cs) or Francium (Fr) and at least one element selected from Group VB elements including Vanadium (V), Niobium (Nb) or Tantalum (Ta).

4. The device according to claim 1, wherein the transition metal-doped material comprises an Aluminum Nitride (AIN) layer having the wurtzite (002) crystal structure, the AIN layer being co-doped with at least one element selected from Group IIA elements including Magnesium (Mg), Beryllium (Be), Calcium (Ca), Strontium (Sr), Barium (Ba) or Radium (Ra) and at least one element selected from Group IVB elements including Zirconium (Zr), Hafnium (Hf) or Titanium (Ti).

5. The device according to claim 1 wherein the transition metal-doped material comprises an Alo.7Sco.3N layer, and wherein the pair of electrodes each comprise a Platinum (Pt) (111) structure that is lattice matched with the Alo 7Sco 3N layer.

6. The device according to claim 5 wherein the lattice matching of the Platinum (Pt) (111) structure with the Alo.7Sco.3N layer enables a resistive switching voltage of 0.3 Volts.

7. The device according to claim 1 wherein the part of the resistive switching layer that underwent the phase transition is formed in a region of the transition metal-doped material where the applied electric field is the strongest.

8. The device according to any one of claims 2 to 4 wherein the part of the resistive switching layer that underwent the phase transition is formed in a region of the transition metal-doped material with a high concentration of dopants.

9. A one-transistor and one-resistor array circuit comprising a first and a second transistor, and a first and a second RRAM device according to the RRAM device of any one of claims 1 to 8 whereby: source electrodes of the first and second transistors are electrically connected to a source line terminal; gate electrodes of the first and second transistors are electrically connected to a word line terminal; a drain electrode of the first transistor is electrically connected to an electrode of the pair of electrodes of the first RRAM device; another electrode of the pair of electrodes of the first RRAM device is electrically connected to a first bit line terminal; a drain electrode of the second transistor is electrically connected to an electrode of the pair of electrodes of the second RRAM device; and another electrode of the pair of electrodes of the second RRAM device is electrically connected to a second bit line terminal.

10. The one-transistor and one-resistor array circuit according to claim 9, further comprising a third and a fourth transistor, and a third and a fourth RRAM device according to the RRAM device of any one of claims 1 to 8 whereby:source electrodes of the third and fourth transistors are electrically connected to the source line terminal; gate electrodes of the third and fourth transistors are electrically connected to the word line terminal; a drain electrode of the third transistor is electrically connected to an electrode of the pair of electrodes of the third RRAM device; another electrode of the pair of electrodes of the third RRAM device is electrically connected to the first bit line terminal; a drain electrode of the fourth transistor is electrically connected to an electrode of the pair of electrodes of the fourth RRAM device; and another electrode of the pair of electrodes of the fourth RRAM device is electrically connected to the second bit line terminal.

11. A method for forming a resistive random-access memory (RRAM) device comprising: forming a resistive switching layer comprising a transition metal-doped material with a wurtzite (002) structure on a bottom electrode; forming a top electrode on the resistive switching layer such that the resistive switching layer is disposed between the top and bottom electrodes, wherein a part of the resistive switching layer undergoes a phase transition from a wurtzite (002) phase to a rocksalt (111) phase when an electric field is applied across the pair of electrodes, the part of the resistive switching layer conductively linking the pair of electrodes together, and wherein the part of the resistive switching layer undergoes another phase transition from the rocksalt (111) phase to the wurtzite (002) phase when the electric field switches polarity across the pair of electrodes.

12. The method according to claim 11, wherein the transition metal -doped material comprises an Aluminum Nitride (AIN) layer having the wurtzite (002) crystal structure, the AIN layer being doped with at least one element selected from Group IIIB elements including Scandium (Sc), Yttrium (Y), Lanthanum (La), Lutetium (Lu), or Actinium (Ac).

13. The method according to claim 11, wherein the transition metal-doped material comprises an Aluminum Nitride (AIN) layer having the wurtzite (002) crystal structure, the AIN layer being co-doped with at least one element selected from Group IA elements includingLithium (Li), Sodium (Na), Potassium (K), Rubidium (Rb), Cesium (Cs) or Francium (Fr) and at least one element selected from Group VB elements including Vanadium (V), Niobium (Nb) or Tantalum (Ta).

14. The method according to claim 11, wherein the transition metal -doped material comprises an Aluminum Nitride (AIN) layer having the wurtzite (002) crystal structure, the AIN layer being co-doped with at least one element selected from Group IIA elements including Magnesium (Mg), Beryllium (Be), Calcium (Ca), Strontium (Sr), Barium (Ba) or Radium (Ra) and at least one element selected from Group IVB elements including Zirconium (Zr), Hafnium (Hf) or Titanium (Ti).

15. The method according to claim 11 wherein the transition metal-doped material comprises an Alo.7Sco.3N layer, and wherein the top and bottom electrodes each comprise a Platinum (Pt) (111) structure that is lattice matched with the Alo 7Sco 3N layer.

16. The method according to claim 15 wherein the lattice matching of the Platinum (Pt) (111) structure with the Alo.7Sco.3N layer enables a resistive switching voltage of 0.3 Volts.

17. The method according to claim 11 wherein the part of the resistive switching layer that underwent the phase transition is formed in a region of the transition metal-doped material where the applied electric field is the strongest.

18. The method according to any one of claims 12 to 14 wherein the part of the resistive switching layer that underwent the phase transition is formed in a region of the transition metal-doped material with a high concentration of dopants.

19. A one-transistor and one-resistor array circuit comprising a first and a second transistor, and a first and a second RRAM device formed according to the method of any one of claims 11 to 18 whereby: source electrodes of the first and second transistors are electrically connected to a source line terminal; gate electrodes of the first and second transistors are electrically connected to a word line terminal; a drain electrode of the first transistor is electrically connected to the bottom electrode of the first RRAM device;the top electrode of the first RRAM device is electrically connected to a first bit line terminal; a drain electrode of the second transistor is electrically connected to the bottom electrode of the second RRAM device; and the top electrode of the second RRAM device is electrically connected to a second bit line terminal.

20. The one-transistor and one-resistor array circuit according to claim 19, further comprising a third and a fourth transistor, and a third and a fourth RRAM device formed according to the method of any one of claims 11 to 18 whereby: source electrodes of the third and fourth transistors are electrically connected to the source line terminal; gate electrodes of the third and fourth transistors are electrically connected to the word line terminal; a drain electrode of the third transistor is electrically connected to the bottom electrode of the third RRAM device; the top electrode of the third RRAM device is electrically connected to the first bit line terminal; a drain electrode of the fourth transistor is electrically connected to the bottom electrode of the fourth RRAM device; and the top electrode of the fourth RRAM device is electrically connected to the second bit line terminal.

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