Sacrificial film to reduce bowing for a high aspect ratio etch

Abstract

A method of etching recessed features in a stack is provided. A sacrificial layer is formed over the stack. A patterned mask is formed over the sacrificial layer. Features are etched in the stack and sacrificial layer through the patterned mask, where a bowing of the features occurs in the sacrificial layer. The sacrificial layer is removed.

Description

SACRIFICIAL FILM TO REDUCE BOWING FOR A HIGH ASPECT RATIO ETCHCROSS-REFERENCE TO RELATED APPLICATION

[0001] This application claims the benefit of priority of U.S. Application No. 63 / 611,879, filed December 19, 2023, which is incorporated herein by reference for all purposes.BACKGROUND

[0002] One process frequently employed during the fabrication of semiconductor devices is the formation of a recessed feature in a stack below a mask. The stack may be alternating / repeating layers into which the recessed feature is formed, or a thick film of a single layer of material. One example context where such a process may occur is memory applications such as dynamic random access memory (DRAM) and “not and” devices (NAND). In the manufacturing of some semiconductor devices, metal or other materials may be etched below a mask. As the semiconductor industry advances and device dimensions become smaller, such recessed features become increasingly harder to etch in a uniform manner, especially for high aspect ratio features having narrow widths and / or deep depths.

[0003] The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent it is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.SUMMARY

[0004] To achieve the foregoing and in accordance with the purpose of the present disclosure, a method of etching recessed features in a stack is provided. A sacrificial layer is formed over the stack. A patterned mask is formed over the sacrificial layer. Features are etched in the stack and sacrificial layer through the patterned mask, where a bowing of the features occurs in the sacrificial layer. The sacrificial layer is removed.

[0005] These and other features of the present disclosure will be described in more detail below in the detailed description and in conjunction with the following figures.BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The present disclosure is illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings and in which like reference numerals refer tosimilar elements and in which:

[0007] FIG. 1 depicts a flow chart describing a method of etching recessed features into a stack below a mask according to various embodiments.

[0008] FIGS. 2A-2I illustrate a schematic cross-sectional illustration of a stack processed according to some embodiments.

[0009] FIG. 3 is a top schematic view of a processing tool that may be used in an embodiment.

[0010] FIG. 4 shows a schematic view of an etch chamber that may be used in some embodiments.

[0011] FIG. 5 illustrates a computer system for implementing a controller used in some embodiments.

[0012] In the drawings, like reference numerals are sometimes used to designate like structural elements. It should also be appreciated that the depictions in the figures are diagrammatic and not to scale.DETAILED DESCRIPTION

[0013] The present disclosure will now be described in detail with reference to a few preferred embodiments thereof as illustrated in the accompanying drawings. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present disclosure. It will be apparent, however, to one skilled in the art, that the present disclosure may be practiced without some or all of these specific details. In other instances, well known process steps and / or structures have not been described in detail in order to not unnecessarily obscure the present disclosure.

[0014] Fabrication of certain semiconductor devices involves etching features into a stack of materials. In various embodiments herein, the stack of materials includes one or more layers of one or more materials below a carbon containing mask. In some embodiments, at least one layer of the stack contains at least one of silicon, germanium, and metal. Silicon containing layers may contain silicon nitride, silicon oxide, silicon carbide, silicon oxy-nitride, silicon oxycarbide, poly silicon, or silicon germanium. In one example, the stack includes alternating layers of silicon oxide and polysilicon (OPOP). In some embodiments, the stack comprises an alternating silicon oxide film with silicon nitride films (ONON), a single silicon oxide layer, or a single silicon layer. In some embodiments, the stack may be a conductive or dielectric layer that may be a metal or silicon containing layer below a carbon containing mask. In some embodiments, the carbon containing mask is a carbon containing at least one of a photoresist, adoped carbon, and an amorphous carbon mask.

[0015] The features etched into a stack may be cylinders, trenches, or other recessed features. The aspect ratio of such a feature is defined as the ratio of the depth to the lateral critical dimension. As the aspect ratio of such features continues to increase, several issues arise including (1) insufficient mask selectivity, (2) etch resolution, (3) twisting of the features, (4) non-circularity of the features, (5) aspect-ratio dependent etch rate, (6) bowing etch profile, and (7) low etch rate.

[0016] Insufficient mask selectivity is problematic when the etch process removes an excessive amount of the carbon containing mask, so that no mask remains at the end of the process, or when the amount of mask remaining is insufficient to properly transfer the pattern from the mask to the stack. One common result of insufficient mask selectivity is the degradation of the feature profile near the top of the recessed features. In order to compensate for insufficient mask selectivity, a thicker mask may be formed. However, a thicker mask results in lower mask resolution and an overall higher aspect ratio, which causes more issues during the etching of both mask and underlayer materials.

[0017] Twisting refers to random deviations between the intended bottom locations of the features and the actual final bottom locations of the features (e.g., with the final location of a feature corresponding to the position of the bottom of the feature after the feature is etched). For instance, in some cases, it is intended that cylindrical features are etched in a regular array. When some or all features randomly deviate at the bottom away from this array, they are understood to have twisted.

[0018] Non-circularity of the features refers to deviations of the bottom hole shape away from a circular hole shape. This issue is relevant when etching circular features such as cylinders, where it is desired that the bottoms of the recessed features are circular. When the bottom hole shape deviates away from a circular shape, it often forms a shape closer to an ellipse, triangle, or irregular polygon. In many cases, these non-circular shapes are not desirable.

[0019] Aspect-ratio dependent etch rate refers to an issue where the etch rate slows down as the aspect ratio of the features increases. In other words, as the features are etched further into the stack, the etching process slows down. This issue is problematic because it can lead to low throughput and associated high processing costs.

[0020] Bowing etch profile refers to the tendency for the features to etch laterally in the stack such that the final profile bows outwards excessively somewhere along the depth of the features.In other words, the actual maximum critical dimension of the features exceeds the desired maximum critical dimension of the features, which can compromise the integrity of the structures being formed or limit the electrical performance of the final devices.

[0021] A low etch rate refers to an etch rate that is slower than desired for a particular application. A low etch rate is problematic because it leads to long etch times, reduced throughput, and high processing costs.

[0022] Unfortunately, techniques that improve some of these issues, such as insufficient mask selectivity, often make other issues worse. As such, these issues are balanced against one another when designing an etching operation. For example, conventional commercially practiced dielectric etch processes often result in substantial bowing. Previously, such tradeoffs have been difficult to avoid.

[0023] The techniques described herein may be used to etch recessed features into a stack below without some or all of the issues identified above. In other words, the disclosed techniques may be used to etch recessed features into a stack below a mask with a high stack to mask selectivity and with reduced mask twisting, reasonably circular features, an acceptable degree of aspect ratio dependent etch rate, acceptable bowing, with reduced non-uniformity, reduced asymmetric mask shadowing, and sufficient etch rate.

[0024] Current technology relies on process trade-off between mask selectivity and CD control while etching the stack. This causes either limited capacitor performance or a need to deposit films within the etched structure to reduce the CDs after etch. This adds integration complexity and manufacturing cost.

[0025] Increased mask selectivity and reduced CDs require a DRAM capacitor high aspect ratio etch and similar high aspect ratio applications, yet CD control becomes challenging with increased mask selectivity since ions scattered from the mask concentrate near the same depth on the etched stack. As a result, ion lateral etching is caused typically near the top of the stack since the mask height changes little when the mask selectivity is very high. This creates a faster lateral CD growth near the top of the right under the mask material. Some embodiments add a sacrificial film between the mask and the stack so that the CDs are smaller for the etched features once this sacrificial film is removed.

[0026] Some embodiments provide a planar deposition of a sacrificial film that can be removed post etch by well-established industrial processes. Taking advantage of localized CD growth underneath the mask helps provide smaller CDs underneath the sacrificial film.Masking Process

[0027] To facilitate understanding, FIG. 1 is a high level flow chart of a method that may be used in some embodiments. A sacrificial layer is deposited over a stack (step 104). FIG. 2A is a schematic cross-sectional view of a stack 204 that may be processed according to some embodiments. In some embodiments, the stack 204 may be formed over a substrate 208. In some embodiments, the stack 204 may comprise a silicon containing layer, such as silicon oxide, silicon nitride, or silicon. In some embodiments, the stack 204 may be a metal containing layer such as a pure or alloy conductive metal layer or a metal nitride or metal oxide. In some embodiments, the stack 204 may comprise a germanium containing layer. In some embodiments, the stack is a single bulk layer. In some embodiments, the stack is a plurality of layers. In some embodiments, the stack is a plurality of bilayers, trilayers, or more multiple layers. In some embodiments, the stack 204 comprises a plurality of bilayers, where each bilayer includes a layer of silicon oxide and a layer of silicon nitride. A sacrificial layer 212 is formed over the stack. In some embodiments, the sacrificial layer is of a material that provides a minimum of processing contaminants, such as non-volatile etch by-products. In some embodiments, the sacrificial layer 212 may comprise an inorganic film such as low-k silicon oxide based material, a polysilicon based material, or a SiC-based film; or an organic film such as amorphous carbon or photoresist. In the specification and claims, a low-k material is defined as a material with a dielectric constant (k) of less than 4.0. In some embodiments, the sacrificial layer 212 is made of a material that is resistant to etching by ion bombardment. In some embodiments, one or more layers may be between the stack 204 and the substrate 208. In some embodiments, one or more layers may be between the stack 204 and the sacrificial layer 212.

[0028] After the sacrificial layer 212 has been formed, a patterned mask is provided over the sacrificial layer 212 (step 106). In some embodiments, the forming of a patterned mask comprises depositing a mask layer and then forming features in the mask layer. In some embodiments, lithographic processes may be used to pattern the mask layer. In some embodiments, another mask may be formed over the mask layer and an etch process may be used to transfer a pattern from the other mask into the mask layer. In some embodiments, the mask is formed from at least one of a photoresist material, a carbon-based material, a silicon containing material, or a metal film.

[0029] FIG. 2B is a schematic cross-sectional view of a stack 204 after a patterned mask 216has been formed over the sacrificial layer 212. The patterned mask 216 has at least one mask feature 220.Etching

[0030] After the patterned mask 216 has been formed over the sacrificial layer 212, features are etched through the sacrificial layer 212 and stack 204 using the patterned mask 216 (step 108). In some embodiments, the etch uses ion bombardment in order to etch high aspect ratio features into the stack 204.

[0031] In some embodiments, an etch gas is transformed into a plasma in order to provide bombardment ions. In some embodiments, radio frequency (RF) power is used to transform the etch gas into a plasma. In some embodiments, the plasma is formed in a process chamber. In some embodiments, the plasma is formed remotely outside of the process chamber and then provided into the process chamber. In some embodiments, the etch gas is provided at a pressure of 1 millitorr to 10 torr.

[0032] In some embodiments, the plasma may be generated at a radio frequency (RF) power between about 1 kilowatt (kW) to 100 kW. In some cases, a dual-frequency RF may be used to generate the plasma. Thus, the RF power may be provided at two or more frequency components, for example, a first frequency component at about 400 kilohertz (kHz) and a second frequency component at about 60 megahertz (MHz). Different powers may be provided at each frequency component. For instance, the first frequency component (e.g., about 400 kHz) may be provided at a power between about 1-100 kW, and the second frequency component (e.g., about 60 MHz) may be provided at a different power, for example between about 1 to 50 kW. These power levels assume that the RF power is delivered to a single 300 millimeter (mm) wafer. The power levels can be scaled linearly based on substrate area for additional substrates and / or substrates of other sizes (thereby maintaining a uniform power density delivered to the substrate). In other cases, three-frequency RF power may be used to generate the plasma.

[0033] In some embodiments, the applied RF power is a continuous RF power. In some embodiments, the applied RF power may be pulsed. In some embodiments, the pulsed RF may have two or three states, providing multistate pulsed RF power. A three state pulsing pulses between three different (high, medium, low) power levels. In some embodiments, the high power level has a 1% to 30% duty cycle, the medium power level has a 10% to 90% duty cycle,and the low power level has a 20% to 90% duty cycle. In some embodiments, the low power level is 0 Watts. In some embodiments, the high power level is 2 to 20 times the low power level, and the medium power level is between the high power level and the low power level. In some embodiments, the RF power is pulsed at repetition rates of 1-50,000 Hz. The RF power may be pulsed between two non- zero values (e.g., between higher power and lower power states) or between zero and a non-zero value (e.g., between off and on states). Where the RF power is pulsed between two non-zero values, the powers may be a higher power state and a lower power state. The lower power state may correspond to an RF power of about 4 kW or lower. A pulsing duty cycle may be in the range of 1-50%. The pulsing may be at a repetition rate in the range of 100 Hz to 20 kHz. The maximum ion energy at the substrate may be relatively low, for example between about 0-10 kilo electron volts (keV). The maximum ion energy is determined by the applied RF power in combination with the details of RF excitation frequencies, electrode sizes, electrode placement, chamber geometry, and plasma interactions.

[0034] In some embodiments, a bias in the range of 1 to 100 kilowatts (kW) is provided to accelerate ions toward the top surfaces of stack 204. The stack 204 is exposed to the accelerated bombardment ions. The bombardment ions etch features in the stack.

[0035] The stack 204 is exposed to the plasma and bombarding ions formed from the etch gas etching at least one feature 224 into the sacrificial layer 212 and the stack 204. FIG. 2C is a schematic cross-sectional view of a stack 204 after the at least one feature 224 is etched into the stack (step 108). The at least one feature 224 has a bow, as shown, located in the sacrificial layer 212, where the bow has a maximum CD / diameter 228 of the at least one feature 224. In some embodiments, the maximum CD / diameter 228 is greater than 110% times the CD / diameter of the mask feature.

[0036] After the features have been etched, the sacrificial layer 212 is removed (step 112). In some embodiments, a chemical etch is provided to selectively remove / etch the sacrificial layer 212 with respect to the stack 204. In some embodiments, the sacrificial layer 212 may be removed by at least one of chemical mechanical polishing (CMP), plasma strip / etch, and ashing) In some embodiments, the removal of the sacrificial layer 212 also removes the remaining patterned mask 216. In some embodiments, another step is used to separately remove the patterned mask 216 before removing the sacrificial layer 212. In some embodiments, the etch process (step 108) removes the patterned mask 216. FIG. 2D is a schematic cross-sectional view of a stack 204 after the sacrificial layer 212, shown in FIG. 2C, has been removed. After thesacrificial layer 212 has been removed, the at least one feature 224 has a widest CD / diameter 232 that is less than the widest CD / diameter 228 of the bowed part of the sacrificial layer 212, shown in FIG. 2C. The use and removal of the sacrificial layer 212 reduces or eliminates bowing. In some embodiments, the maximum CD / diameter 228 is greater than 110% times the widest CD / diameter 232 of the remaining at least one feature 224.

[0037] In some embodiments, the material forming the sacrificial layer 212 is more etch resistant to ion bombardment etching than the stack so that the sacrificial layer 212 is more resistant to bowing. In some embodiments, although the sacrificial layer is resistant to etching by ion bombardment so that there is less bowing, the sacrificial layer can be etched using a chemical etch allowing for a selective removal of the sacrificial layer with respect to the stack.

[0038] The thickness of the sacrificial layer 212 may be dictated by various factors such as the etch process and the aspect ratio. In some embodiments, the sacrificial layer 212 has a thickness so that all or almost all of the bowing occurs in the sacrificial layer 212. In some embodiments, the sacrificial layer 212 has a thickness so that the widest CD / diameter of the etched features is in the sacrificial layer 212. In some embodiments, the sacrificial layer has a thickness in the range of 30 nm to 180 nm. In some embodiments, the sacrificial layer has a thickness in the range of 50 nm to 150 nm. In some embodiments, the sacrificial layer has a thickness in the range of 70 nm to 90 nm. If the sacrificial layer 212 is too thin, then more bowing occurs in the stack. If the sacrificial layer 212 is too thick, high aspect ratio etch and aspect ratio dependent problems may be increased.Overhang Embodiments

[0039] FIG. 2E is a schematic cross-sectional view of a stack 204 that may be processed according to some embodiments. In some embodiments, the stack 204 may be formed over a substrate 208. In some embodiments, the stack 204 may comprise a silicon containing layer, such as silicon oxide, silicon nitride, or silicon. In some embodiments, the stack 204 may be a metal containing layer such as a pure or alloy conductive metal layer or a metal nitride or metal oxide. A sacrificial layer 212 is formed over the stack. In some embodiments, the sacrificial layer is of a material that provides a minimum of processing contaminants, such as non-volatile etch by-products. In some embodiments, the sacrificial layer 212 may comprise an inorganic film such as low-k silicon oxide based material, a polysilicon based material, or a SiC-based film; or an organic film such as amorphous carbon or photoresist.

[0040] After the sacrificial layer 212 has been formed, a patterned mask is provided over the sacrificial layer 212 (step 106). FIG. 2F is a schematic cross-sectional view of a stack 204 after a patterned mask 216 has been formed over the sacrificial layer 212. The patterned mask 216 has at least one mask feature 220.

[0041] After the patterned mask 216 has been formed over the sacrificial layer 212, features are etched through the sacrificial layer 212 using the patterned mask 216 (step 108). FIG. 2G is a schematic cross-sectional view of a stack 204 after the at least one feature 236 is etched into the sacrificial layer 212 (step 108). The etch of the sacrificial layer 212 creates an overhang 240 of the mask 216 over the sacrificial layer 212. The overhang 240 may be created during the opening of the sacrificial layer 212 or may be formed by a subsequent wet etch after the sacrificial layer 212 is opened.

[0042] After the sacrificial layer 212 has been opened to form at least one feature 236 and an overhang 240 is formed, at least one feature is etched into the stack 204. FIG. 2H is a schematic cross-sectional view of a stack 204 after the at least one feature 244 is etched into the stack 204 (step 108).

[0043] After the features have been etched, the sacrificial layer 212 is removed (step 112). FIG. 21 is a schematic cross-sectional view of a stack 204 after the sacrificial layer 212, shown in FIG. 2H, has been removed.

[0044] The overhang in the sacrificial layer minimizes the bombardment of deflected ions on the surfaces of the material etched underneath. Therefore, lateral etch is minimized and CDs are reduced underneath. The CD protection benefit can be doubled with the optimization of the overhang versus no overhang. The optimal overhang would change based on material choices, sacrificial layer thickness, CDs, distance of the layer from the top of the mask, and plasma conditions.

[0045] In some embodiments, the method may be used for providing an increased mask selectivity and reduced CDs for etching DRAM capacitors with high aspect ratios. In some embodiments, the etching of DRAM capacitors may be performed at cryogenic temperatures. In some embodiments, the cryogenic temperature is provided by cooling a wafer support surface to temperatures of less than or equal to 0° C. In some embodiments, the cooling causes a wafer support surface to be cooled to a temperature of less than or equal to -20° C. In other embodiments, the cryogenic temperatures is provided by cooling the wafer support surface to temperatures of less than or equal to -60° C.

[0046] One application for the disclosed methods is in the context of forming a vertical NAND. In this case, the material into which the feature is etched may have a repeating layered structure. For instance, the material may include alternating layers of silicon oxide and silicon nitride. In other embodiments, the stack may comprise alternating layers of silicon oxide and polysilicon. The alternating layers form pairs or repeating groups of materials. In various cases, the number of pairs or repeating groups may be between about 10-500 (e.g., between about 20- 1000 individual layers). The feature etched into the stack of layers may have a depth between about 2-15 pm, for example between about 5-9 pm. The feature may have a CD width between about 3-500 nm, for example between about 50-100 nm or between about 40-85 nm. In some embodiments, the features have a width of less than 100 nm. In some embodiments, the features have a width of less than 85 nm. In some embodiments, the stack comprises at least one of a layer of SiO, SiN, and SiON.

[0047] As used herein, “high aspect ratio” as applied to features in a stack refers to a depth to width aspect ratio on the order of approximately 60:1 or higher. More preferably, this range may include ratios greater than 100:1 , 120: 1, 140:1, etc., or higher. However, the processes described herein may be beneficial for lower aspect ratios, such as 30:1, or 10:1. In some embodiments the features may have a depth from 3 nm to 10 pm. The mask aspect ratio refers to the ratio of the thickness of the mask to the width of the feature in the mask. In some embodiments, the mask aspect ratio is greater than 15:1. In some embodiments, the mask aspect ratio is greater than 30:1. For example, a mask may have a thickness of about 300 nm and the CD of the feature may be less than 20 nm.

[0048] The dimensional / parametric details provided herein, such as high aspect ratio, thickness, width, depth, etc., are for example and illustration only. Based on the disclosure described herein, it should be understood that varying dimensions / parameters may also be applicable or used.APPARATUS

[0049] Typically, though not necessarily, such processes may be used or conducted together in a common fabrication facility. FIG. 3 is a top schematic view of a processing tool 300, that may be used in an embodiment. A cassette 302 houses the unprocessed substrates / wafers with stacks before they are processed and then holds the treated wafers once all processing is complete in the processing tool 300. The cassette 302 can hold many wafers, often as many as 25. An atmosphere transport module (ATM) 314 is used to transport wafers to and from the cassette302. A load lock station 305 represents at least one device that operates to transfer the wafer back and forth between the atmosphere of the ATM 314 and the vacuum of a vacuum transport module (VTM) 312. The VTM 312 is part of the processing tool and connects to a plurality of processing chambers. There may be different types of processing chambers. In some embodiments, the plurality of processing chambers comprises a sacrificial layer deposition chamber 308, a mask deposition chamber 316, a lithography chamber 320, an etch chamber 324, and a sacrificial mask removal chamber 328. In some embodiments, additional chambers may be provided. A robotic system within the vacuum transport module 312 uses an end effector to move a wafer between the load lock station 305 and the processing chambers. The ATM 314 uses a robotic system to transfer wafers between the cassette 302 and the load lock station 305.

[0050] The sacrificial layer deposition chamber 308 is able to deposit the sacrificial layer 212 (step 104). The mask deposition chamber 316 is able to deposit a mask layer. The lithography chamber 320 may be used to pattern the mask layer to form a patterned mask 216 (step 106). The etch chamber 324 may be used to etch features in the stack 204 (step 108). The sacrificial mask removal chamber 328 may be used to remove the sacrificial layer 212 (step 112).

[0051] In some embodiments, the lithography chamber 320 may comprise a plurality of chambers for performing various lithography steps. Lithographic patterning of a film typically comprises some or all of the following steps, each step enabled with a number of possible tools: (1) application of photoresist on a workpiece, e.g., a substrate having a silicon containing film formed thereon, using a spin-on or spray-on tool; (2) curing of photoresist using a hot plate or furnace or other suitable curing tool; (3) exposing the photoresist to visible or ultraviolet (UV) or x-ray light with a tool such as a wafer stepper; (4) developing the resist so as to selectively remove the resist and thereby pattern it using a tool such as a wet bench or a spray developer; (5) transferring the resist pattern into an underlying film or workpiece by using a dry or plasma- assisted etching tool; and (6) removing the resist using a tool such as an RF or microwave plasma resist stripper. In some embodiments, an ashable hard mask layer (such as an amorphous carbon layer) and another suitable hard mask (such as an antireflective layer) may be deposited prior to applying the photoresist.

[0052] In this application, the terms “semiconductor wafer,” “wafer,” “substrate,” “wafer substrate,” and “partially fabricated integrated circuit” are used interchangeably. One of ordinary skill in the art would understand that the term “partially fabricated integrated circuit” can refer to a silicon wafer during any of many stages of integrated circuit fabrication thereon. A wafer orsubstrate used in the semiconductor device industry typically has a diameter of 200 mm, 300 mm, or 450 mm. The above detailed description assumes the embodiments are implemented on a wafer. However, the embodiments are not so limited. The workpiece may be of various shapes, sizes, and materials. In addition to semiconductor wafers, other work pieces that may take advantage of the disclosed embodiments include various articles such as printed circuit boards, magnetic recording media, magnetic recording sensors, mirrors, optical elements, micromechanical devices, and the like.

[0053] Unless otherwise defined for a particular parameter, the terms “about” and “approximately” as used herein are intended to mean ±10% with respect to a relevant value.

[0054] FIG. 4 is a schematic view of an etch reactor system 400 that may be used in some embodiments. In some embodiments, an etch reactor system 400 comprises a gas distribution plate 406 providing a gas inlet and an electrostatic chuck (ESC) 408, within an etch (or process) chamber 324, enclosed by a chamber wall 452. Within the etch chamber 324, a stack 204 is positioned over the ESC 408 that is used as a substrate support. A bias may be provided to the ESC 408 from an ESC source 448. A gas source 410 is connected to the etch chamber 324 through the gas distribution plate 406. An ESC temperature controller 450 is connected to the ESC 408. A radio frequency (RF) source 430 provides RF power to a lower electrode and / or an upper electrode, which in this embodiment are the ESC 408 and the gas distribution plate 406, respectively. In some embodiments, 400 kilohertz (kHz), 60 megahertz (MHz), and optionally, 2 MHz, and 27 MHz power sources make up the RF source 430 and the ESC source 448. In some embodiments, the upper electrode is grounded. In some embodiments, one generator is provided for each frequency. In some embodiments, the generators may be in separate RF sources or separate RF generators may be connected to different electrodes. For example, the upper electrode may have inner and outer electrodes connected to different RF sources. Other arrangements of RF sources and electrodes may be used in other embodiments. A controller 435 is controllably connected to the RF source 430, the ESC source 448, an exhaust pump 420, and the gas source 410. An example of such an etch chamber is the Vantex® etch system manufactured by Lam Research Corporation of Fremont, CA. The process chamber can be a CCP (capacitively coupled plasma) reactor or an ICP (inductively coupled plasma) reactor.

[0055] FIG. 5 is a high level block diagram showing a computer system 500, which is suitable for implementing the controller 435 used in embodiments. The computer system 500 may have many physical forms ranging from an integrated circuit, a printed circuit board, and a smallhandheld device up to a huge supercomputer. The computer system 500 includes one or more processors 502 and further can include an electronic display device 504 (for displaying graphics, text, and other data), a main memory 506 (e.g., random access memory (RAM)), storage device 508 (e.g., hard disk drive), removable storage device 510 (e.g., optical disk drive), user interface devices 512 (e.g., keyboards, touch screens, keypads, mice or other pointing devices, etc.), and a communications interface 514 (e.g., wireless network interface). The communications interface 514 allows software and data to be transferred between the computer system 500 and external devices via a link. The system may also include a communications infrastructure 516 (e.g., a communications bus, cross-over bar, or network) to which the aforementioned devices / modules are connected.

[0056] Information transferred via communications interface 514 may be in the form of signals such as electronic, electromagnetic, optical, or other signals capable of being received by communications interface 514, via a communications link that carries signals and may be implemented using wire or cable, fiber optics, a phone line, a cellular phone link, a radio frequency link, and / or other communications channels. With such a communications interface 514, it is contemplated that the one or more processors 502 might receive information from a network or might output information to the network in the course of performing the abovedescribed method steps. Furthermore, method embodiments may execute solely upon the processors or may execute over a network such as the Internet, in conjunction with remote processors that share a portion of the processing.

[0057] The term “non-transient computer readable medium” is used generally to refer to media such as main memory, secondary memory, removable storage, and storage devices, such as hard disks, flash memory, disk drive memory, CD-ROM, and other forms of persistent memory and shall not be construed to cover transitory subject matter, such as carrier waves or signals. Examples of computer code include machine code, such as produced by a compiler, and files containing higher level code that is executed by a computer using an interpreter. Computer readable media may also be computer code transmitted by a computer data signal embodied in a carrier wave and representing a sequence of instructions that are executable by a processor.

[0058] In some embodiments, the controller 435 is configured to a) form a sacrificial layer over the stack, b) form a patterned mask over the stack, c) etch features into the sacrificial mask and stack through the patterned mask; and remove the sacrificial mask.

[0059] It is to be understood that the configurations and / or approaches described herein areexemplary in nature and that these specific embodiments or examples are not to be considered in a limiting sense, because numerous variations are possible. The specific routines or methods described herein may represent one or more of any number of processing strategies. As such, various acts illustrated may be performed in the sequence illustrated, in other sequences, in parallel, or in some cases omitted. Likewise, the order of the above described processes may be changed. Certain references have been incorporated by reference herein. It is understood that any disclaimers or disavowals made in such references do not necessarily apply to the embodiments described herein. Similarly, any features described as necessary in such references may be omitted in the embodiments herein. The subject matter of the present disclosure includes all novel and nonob vious combinations and sub-combinations of the various processes, systems and configurations, and other features, functions, acts, and / or properties disclosed herein, as well as any and all equivalents thereof.CONCLUSION

[0060] While this disclosure has been described in terms of several preferred embodiments, there are alterations, modifications, permutations, and various substitute equivalents, that fall within the scope of this disclosure. It should also be noted that there are many alternative ways of implementing the methods and apparatuses of the present disclosure. It is therefore intended that the following appended claims be interpreted as including all such alterations, modifications, permutations, and various substitute equivalents as fall within the true spirit and scope of the present disclosure. As used herein, the phrase “A, B, or C” should be construed to mean a logical (“A OR B OR C”), using a non-exclusive logical “OR,” and should not be construed to mean ‘only one of A or B or C. Each step within a process may be an optional step and is not required. Different embodiments may have one or more steps removed or may provide steps in a different order. In addition, various embodiments may provide different steps simultaneously instead of sequentially.

Claims

CLAIMSWhat is claimed is:

1. A method of etching recessed features in a stack, comprising: a. forming a sacrificial layer over the stack; b. forming a patterned mask over the sacrificial layer; c. etching features in the stack and sacrificial layer through the patterned mask, where a bowing of the features occurs in the sacrificial layer; and d. removing the sacrificial layer.

2. The method of claim 1, wherein the sacrificial layer is more resistant to bowing than the stack.

3. The method of claim 1, wherein the features have a widest diameter in the sacrificial layer.

4. The method of claim 1, wherein the sacrificial layer has a thickness in a range of 30 nm to 180 nm.

5. The method of claim 1, wherein the patterned mask has a thickness, and the features have a width so that a mask aspect ratio is provided with a depth to width of at least 30:1.

6. The method of claim 1, wherein the etched features in the stack have a depth to width aspect ratio of at least 100:1.

7. The method of claim 1 , wherein the etching the stack uses ion bombardment.

8. The method of claim 7, wherein the removing the sacrificial layer comprises using a chemical etch to selectively etch the sacrificial layer with respect to the stack.

9. The method, as recited in claim 1, wherein the removing the sacrificial layer comprises a chemical etch that selectively etches the sacrificial layer with respect to the stack.

10. The method, as recited in claim 1 , wherein the bowing occurs in the sacrificial layer and not in the stack.

11. The method, as recited in claim 1, wherein the etching comprises: providing an etch gas; forming the etch gas into a plasma; and bombarding the stack with ions from the plasma.

12. The method, as recited in claim 1, further comprising laterally etching the sacrificial layer so that the patterned mask overhangs the sacrificial layer.

13. The method, as recited in claim 1, further comprising cooling a substrate support to a temperature of less than or equal to 0° C.

14. The method, as recited in claim 1, wherein the etching features in the stack comprises etching DRAM capacitors in the stack.

15. The method, as recited in claim 14, further comprising cooling a substrate support to a temperature of less than or equal to 0” C.

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