Substrate and manufacturing method therefor, and sensor module

Abstract

A substrate and a manufacturing method therefor, and a sensor module. The substrate comprises a base (21); the base (21) is configured to be connected to a chip (10); a plurality of through holes (100) are formed in the base; the through holes (100) run through the base (21) in a direction perpendicular the chip (10); stack structures are sequentially provided in the through holes (100) in a direction perpendicular to and moving away from the base (21); a coefficient of thermal expansion of each layer in the stack structures is different; and the stack structures comprise first conductive portions (241), wherein the first conductive portions (241) are electrically connected to the chip (10).

Description

Substrate and preparation method thereof, sensor module Technical Field

[0001] The present application relates to, but is not limited to, the field of integrated technology, and specifically to a substrate and a preparation method thereof, and a sensor module. Background Art

[0002] In recent years, with the booming development of emerging fields such as 5G, wearable devices, smartphones, automotive electronics, and artificial intelligence, integrated circuit applications are developing towards diversified applications. Advanced three-dimensional packaging technology has gradually become an important means to achieve the miniaturization, lightweighting, and multifunctionality of electronic products. Through-hole interconnect technology has application advantages such as excellent high-frequency electrical characteristics, low cost, simple process flow, and strong mechanical stability. It has broad application prospects in RF devices, microelectromechanical system (MEMS) packaging, optoelectronic system integration, and other fields. Compared with traditional planar integration technology, through-hole interconnect technology can achieve vertical interconnection, thereby expanding the integration space into the third dimension and significantly improving space utilization.

[0003] Summary of the Invention

[0004] The following is an overview of the subject matter described in detail in this application. This overview is not intended to limit the scope of protection of the claims.

[0005] In one aspect, the present application provides a substrate, comprising a substrate configured to be connected to a chip, the substrate being provided with a plurality of through holes, the through holes penetrating the substrate in a direction perpendicular to the chip, the through holes being provided with a stacked structure in sequence in a direction perpendicular to and away from the substrate, and the thermal expansion coefficient of each layer in the stacked structure being different;

[0006] The stacked structure includes a first conductive portion electrically connected to the chip.

[0007] On the other hand, the present application also provides a sensor module, comprising:

[0008] A substrate as described above; and

[0009] The chip, the surface of the substrate close to the chip is electrically connected to the chip.

[0010] In another aspect, the present application further provides a method for preparing a substrate, comprising:

[0011] providing a substrate connected to the chip;

[0012] forming a plurality of through holes on the substrate, wherein the through holes penetrate the substrate in a direction perpendicular to the chip;

[0013] A stacked structure is sequentially formed in the through hole along a direction perpendicular to and away from the substrate, and each layer in the stacked structure has a different thermal expansion coefficient. The stacked structure includes a first conductive portion electrically connected to the chip.

[0014] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description.

[0015] Summary of the Figures

[0016] The accompanying drawings are used to provide an understanding of the technical solution of the present application and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the technical solution of the present application and do not constitute a limitation on the technical solution of the present application.

[0017] 1A and 1B are schematic diagrams of a sensor module after a substrate pattern is formed in one embodiment of the present application;

[0018] 2A and 2B are schematic diagrams of a sensor module after forming a first conductive layer in one embodiment of the present application;

[0019] 3A and 3B are schematic diagrams of a sensor module after forming a second conductive layer in one embodiment of the present application;

[0020] 4A and 4B are schematic diagrams of a sensor module after forming a conductive structure pattern in one embodiment of the present application;

[0021] 5A and 5B are schematic diagrams of a sensor module after forming an insulating layer pattern in one embodiment of the present application;

[0022] 6A and 6B are schematic diagrams of a sensor module after forming a connection electrode pattern in one embodiment of the present application;

[0023] 7A and 7B are schematic diagrams of a sensor module after a substrate pattern is formed in another embodiment of the present application;

[0024] 8A and 8B are schematic diagrams of a sensor module after forming a buffer layer in another embodiment of the present application;

[0025] 9A and 9B are schematic diagrams of a sensor module after forming a first conductive layer pattern in another embodiment of the present application;

[0026] 10A and 10B are schematic diagrams of a sensor module after forming a second conductive layer in another embodiment of the present application;

[0027] 11A and 11B are schematic diagrams of a sensor module after forming a conductive structure pattern in another embodiment of the present application;

[0028] 12A and 12B are schematic diagrams of a sensor module after forming an insulating layer pattern in another embodiment of the present application;

[0029] 13A and 13B are schematic diagrams of a sensor module after forming a connection electrode pattern in another embodiment of the present application;

[0030] 14A and 14B are schematic diagrams of a sensor module after a substrate pattern is formed in another embodiment of the present application;

[0031] 15A and 15B are schematic diagrams of a sensor module after forming a first conductive layer pattern in another embodiment of the present application, wherein the groove is located within the through hole;

[0032] 16A and 16B are schematic diagrams of a sensor module after forming a second conductive layer pattern in another embodiment of the present application;

[0033] 17A and 17B are schematic diagrams of a sensor module after forming a conductive structure pattern in another embodiment of the present application;

[0034] 18A and 18B are schematic diagrams of a sensor module after forming an insulating layer pattern in another embodiment of the present application;

[0035] 19A and 19B are schematic diagrams of a sensor module after forming a connection electrode pattern in another embodiment of the present application;

[0036] 20A, 20B and 20C are partial schematic diagrams of a sensor module after forming a first conductive layer pattern in another embodiment of the present application;

[0037] 20D and 20E are schematic diagrams of a sensor module after forming a first conductive layer pattern in another embodiment of the present application, wherein the groove is located around the through hole;

[0038] FIG20F is a schematic cross-sectional view of a sensor module after forming a first conductive layer pattern in another embodiment of the present application, wherein some through holes are sequentially arranged in a direction perpendicular to the chip;

[0039] 21A and 21B are schematic diagrams of a sensor module after a substrate pattern is formed in yet another embodiment of the present application;

[0040] 22A and 22B are schematic diagrams of a sensor module after forming a first conductive layer in yet another embodiment of the present application;

[0041] 23A and 23B are schematic diagrams of a sensor module after forming a filling structure layer in yet another embodiment of the present application;

[0042] 24A and 24B are schematic diagrams of a sensor module after forming a conductive structure pattern in yet another embodiment of the present application;

[0043] 25A and 25B are schematic diagrams of a sensor module after forming an insulating layer pattern in another embodiment of the present application;

[0044] 26A and 26B are schematic diagrams of a sensor module after forming a connection electrode pattern in yet another embodiment of the present application;

[0045] Explanation of the accompanying drawings: 10. Chip; 11. Electrode part; 12. Piezoresistor; 20. Substrate; 21. Substrate; 22. First conductive layer; 23. Second conductive layer; 24. Conductive structure; 241. First conductive part; 242. Second conductive part; 243. Buffer part; 25. Insulating layer; 26. Connecting electrode; 27. Buffer layer; 28. Filler; 100. Through hole; 200. Groove structure; 300. Cavity; 400. Via hole; 500. Connecting hole; 600. Recess; 700. Cavity.

[0046] Details

[0047] In order to make the purpose, technical solutions and advantages of the present application clearer, the embodiments of the present application will be described in detail below with reference to the accompanying drawings. Note that the embodiments can be implemented in a plurality of different forms. A person of ordinary skill in the art can easily understand the fact that the method and content can be transformed into various forms without departing from the purpose and scope of the present application. Therefore, the present application should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments in the present application and the features in the embodiments can be combined with each other in any way.

[0048] The scales of the figures in this application can be used as a reference for actual processes, but are not limited to such. For example, the width-to-length ratio of the channel, the thickness and spacing of the various film layers, and the width and spacing of the various signal lines can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the numbers shown in the figures. The figures described in this application are merely schematic diagrams of the structures, and one embodiment of this application is not limited to the shapes or values ​​shown in the figures.

[0049] In this specification, ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements, and are not intended to limit the number.

[0050] In this specification, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the convenience of describing this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation. Therefore, it should not be understood as a limitation on this application. The positional relationships of the constituent elements may be appropriately changed according to the direction in which each constituent element is described. Therefore, the words and phrases are not limited to those described in the specification and may be appropriately replaced according to the circumstances.

[0051] In this specification, unless otherwise specified or limited, the terms "mounted," "connected," and "connected" should be interpreted broadly. For example, they can refer to fixed, removable, or integral connections; mechanical or electrical connections; direct connections, indirect connections through intermediaries, or internal communication between two components. Those skilled in the art will understand the specific meanings of these terms in this application.

[0052] In this specification, a transistor refers to a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0053] In this specification, the first electrode can be a drain electrode and the second electrode can be a source electrode, or vice versa. The functions of "source electrode" and "drain electrode" may be interchanged when using transistors with opposite polarity or when the direction of current changes during circuit operation. Therefore, in this specification, "source electrode" and "drain electrode" can be interchanged, and "source terminal" and "drain terminal" can be interchanged.

[0054] In this specification, "electrically connected" includes components connected together via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables the transfer of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0055] In this specification, "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°, and thus also includes a state where the angle is greater than -5° and less than 5°. Furthermore, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°, and thus also includes a state where the angle is greater than 85° and less than 95°.

[0056] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced with "conductive film." Similarly, "insulating film" may be replaced with "insulating layer."

[0057] The triangles, rectangles, trapezoids, pentagons or hexagons in this specification are not in the strict sense, but may be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances, and there may be chamfers, arc edges and deformations.

[0058] The term "about" in this application refers to a numerical value that is not strictly limited to a certain limit and allows for process and measurement errors.

[0059] Currently, one of the technical difficulties limiting the application of through-hole interconnect technology is high-quality metal filling. Unlike through-silicon vias (TSVs), larger-diameter vias require long electroplating times and high costs. Furthermore, unlike silicon materials, smooth substrates (for example, glass substrates) have poor adhesion to common metals (such as Cu), which can easily cause delamination between the substrate and the metal layer, leading to curling or even shedding of the metal layer.

[0060] During the actual electroplating hole filling process, it was found that when electroplating to fill through-holes with a diameter of 50-300μm and a depth of about 300μm, if the electroplating operating current is set too high, the metal at the top of the through-hole will grow too quickly, causing the through-hole to be quickly sealed, while the metal at the bottom of the through-hole will not be fully filled, and the purpose of hole electrical interconnection cannot be achieved. At the same time, if the through-hole is not filled, it will also affect the subsequent film coating effect and cause more defects. In the subsequent exposure process of the through-hole structure, due to the large diameter and lack of filling, photoresist will accumulate in the through-hole, resulting in thin or missing photoresist at the edge, causing the hole electrical connection to fail.

[0061] To achieve hole filling, the thermal expansion coefficient of commonly used metals (such as Cu) and the substrate is quite different. In subsequent high-temperature processes (such as annealing and reflow soldering), large stress is easily concentrated at the through-hole position, causing cracks or direct breakage at the through-hole position.

[0062] Figure 2A is a schematic plan view of a sensor module after forming a first conductive layer in one embodiment of the present application. Figure 2B is a schematic cross-sectional view of a sensor module after forming a first conductive layer in one embodiment of the present application. Figure 6A is a schematic plan view of a sensor module after forming a connection electrode pattern in one embodiment of the present application. Figure 6B is a schematic cross-sectional view of a sensor module after forming a connection electrode pattern in one embodiment of the present application, wherein the cross section is perpendicular to chip 10.

[0063] On a plane perpendicular to the chip 10, the base plate 20 includes a substrate 21. The substrate 21 is configured to connect to the chip 10 and is provided with a plurality of through-holes 100 extending perpendicularly through the substrate 21. A stacked structure is sequentially arranged within the through-holes 100 in a direction perpendicular to and away from the substrate 21. The stacked structure includes a first conductive portion 241, which is electrically connected to the chip 10 to ensure electrical conductivity within the through-holes 100. Objects expand and contract due to temperature changes. This expansion capacity is expressed as the change in length per unit temperature change under constant pressure (constant pressure), i.e., the coefficient of thermal expansion. Each layer in the stacked structure has a different coefficient of thermal expansion. This allows stress in each layer to be released to adjacent layers with relatively smaller coefficients of thermal expansion, preventing significant stress from concentrating in the through-holes 100 during subsequent high-temperature processes (such as annealing and reflow soldering), potentially causing cracks or even breakage.

[0064] In an exemplary embodiment, the stacked structure further includes a cavity 700, which is disposed on a side of the first conductive portion 241 away from the chip 10. The cavity 700 is a cavity filled with gas and has a low thermal expansion coefficient.

[0065] This leaves the through hole 100 in an unfilled state, ensuring electrical conductivity and connection of the first conductive portion 241 within the through hole 100. Furthermore, the unfilled state of the through hole 100 allows for spatial stress relief in the first conductive portion 241, thereby preventing cracks or even breakage in the through hole 100 due to excessive stress in the first conductive portion 241. The stacked structure may include the first conductive portion 241 and the cavity 700.

[0066] In an exemplary embodiment, the substrate 20 further includes a second conductive portion 242 , which is disposed on the side of the first conductive portion 241 away from the chip 10 and seals the side of the through hole away from the chip 10, making the side of the through hole 100 away from the chip 10 flat. The photoresist can be applied normally by spin coating, spray coating, or the like, ensuring a normal photoresist thickness at the through hole 100. This prevents photoresist from accumulating within the through hole 100, which could result in missing or thinner photoresist on the side of the through hole 100 away from the chip 10. This could cause etching to partially etch the first conductive portion 241 on the side of the through hole 100 away from the chip 10, leading to abnormal electrical conduction at the location of the through hole 100. The first conductive portion 241 and the second conductive portion 242 together form a cavity 300 .

[0067] In an exemplary embodiment, the second conductive portion 242 is provided with a via 400 , which penetrates the second conductive portion 242 in a direction perpendicular to the chip 10 and communicates with the cavity 300 to prevent the plating solution from remaining in the cavity 300 after the through hole 100 is sealed, resulting in poor reliability.

[0068] In an exemplary embodiment, the diameter of the via hole 400 may be approximately 10 μm to 20 μm. Setting the diameter of the via hole 400 to a smaller size can prevent the second conductive portion 242 from collapsing under force, thereby affecting electrical conduction.

[0069] In an exemplary embodiment, FIG13A is a schematic diagram of a planar structure of a sensor module after forming a connection electrode pattern in another embodiment of the present application. FIG13B is a schematic diagram of a cross-sectional structure of a sensor module after forming a connection electrode pattern in another embodiment of the present application, wherein the cross section is perpendicular to the chip 10.

[0070] The stacked structure further includes a buffer layer 243, which is disposed on a side of the substrate 21 away from the chip 10, and the first conductive portion 241 is disposed on a side of the buffer layer 243 away from the chip 10. In this case, the stacked structure may include the first conductive portion 241, the cavity 700, and / or the buffer layer 243.

[0071] The thermal expansion coefficient of the material of the buffer layer 243 is between the thermal expansion coefficients of the material of the substrate and the thermal expansion coefficients of the material of the first conductive portion. The provision of the buffer layer 243 can reduce the stress gradient between the substrate 21 and the first conductive portion 241, thereby lowering the risk of delamination between the substrate 21 and the first conductive portion 241. In the embodiment of the present application, the substrate 21 is a glass substrate, and the thermal expansion coefficient of the material of the buffer layer 243 is between the thermal expansion coefficients of glass and the thermal expansion coefficients of the material of the first conductive portion 241.

[0072] In an exemplary embodiment, FIG19A is a schematic diagram of a planar structure of a sensor module after forming a connection electrode pattern in another embodiment of the present application. FIG19B is a schematic diagram of a cross-sectional structure of a sensor module after forming a connection electrode pattern in another embodiment of the present application, wherein the cross section is perpendicular to the chip 10.

[0073] The first conductive portion 241 is provided with a groove 600. The provision of the groove 600 does not affect the electrical conductivity characteristics of the first conductive portion 241. Due to the provision of the groove 600, when stress in the first conductive portion 241 increases during the subsequent manufacturing process, the stress of the first conductive portion 241 can be first released at the groove 600, causing partial delamination and warping around the groove 600, thereby reducing the impact on the overall film adhesion and electrical conductivity of the first conductive portion 241.

[0074] In an exemplary embodiment, at least one groove 600 is disposed in the through hole 100 .

[0075] In an exemplary embodiment, as shown in FIG. 15A , FIG. 15B , FIG. 20A , FIG. 20B and FIG. 20C , a plurality of grooves 600 are provided in the through hole 100 , and the plurality of grooves 600 are evenly distributed around the axis of the through hole 100 to ensure that stress can be evenly released.

[0076] In an exemplary embodiment, as shown in FIG. 20F , a plurality of grooves 600 are provided in the through-hole 100 , and orthographic projections of portions of the plurality of through-holes 100 on the chip 10 overlap.

[0077] In an exemplary embodiment, as shown in FIG. 20D and FIG. 20E , at least one groove 600 is provided around the periphery of the through hole 100 .

[0078] In an exemplary embodiment, a plurality of grooves 600 are disposed around the through hole 100 , and the plurality of grooves 600 are evenly distributed around the axis of the through hole 100 to ensure that stress can be evenly released.

[0079] In an exemplary embodiment, referring to FIG. 20A , FIG. 20B , and FIG. 20C , the orthographic projection of the groove 600 on the chip 10 is circular, straight, or arc-shaped.

[0080] In an exemplary embodiment, FIG26A is a schematic diagram of a planar structure of a sensor module after forming a connection electrode pattern in another embodiment of the present application. FIG26B is a schematic diagram of a cross-sectional structure of a sensor module after forming a connection electrode pattern in another embodiment of the present application, wherein the cross section is perpendicular to the chip 10.

[0081] The stacked structure further includes a filler 28 . The filler 28 is disposed on a side of the first conductive portion 241 away from the chip 10 , and seals the side of the through hole 100 away from the chip 10 .

[0082] The cavity 700 is filled with a filling material, and the side of the through hole 100 away from the chip 10 is sealed. The thermal expansion coefficient of the material of the filler 28 is negative. By filling the cavity 700 with a material with a negative thermal expansion coefficient, the stress of the first conductive portion 241 can be neutralized, and the through hole 100 can be filled and leveled, making the side of the through hole 100 away from the chip 10 flat. The photoresist can be properly spread through spin coating, spray coating, etc., and the photoresist thickness at the through hole 100 is normal. This can prevent the accumulation of photoresist in the through hole 100, resulting in missing or thin photoresist on the side of the through hole 100 away from the chip 10. As a result, during etching, the first conductive portion 241 on the side of the through hole 100 away from the chip 10 is partially etched, resulting in abnormal electrical conductivity at the through hole 100.

[0083] The following is an illustrative description of the preparation process of the sensor module. The "patterning process" mentioned in this application, for metal materials, inorganic materials or transparent conductive materials, includes depositing a film layer, coating a photoresist on the film layer, mask exposure, development, etching, stripping the photoresist and other processes; for organic materials, it includes coating an organic material, mask exposure and development and other processes. Deposition can be achieved by any one or more of sputtering, evaporation, chemical vapor deposition, and electroplating; coating can be achieved by any one or more of spraying, spin coating and inkjet printing; etching can be achieved by any one or more of dry etching and wet etching, and this application does not limit this. "Thin film" refers to a thin film made by deposition, coating or other processes on a substrate of a certain material. If the "thin film" does not require a patterning process during the entire production process, the "thin film" can also be called a "layer". If the "thin film" requires a patterning process during the entire production process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern". As used herein, "A and B are disposed in the same layer" means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer refers to the dimension of the film layer in the direction perpendicular to the substrate. In exemplary embodiments of the present application, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A includes the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or that the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0084] The preparation process of the sensor module in an exemplary embodiment of the present application may include the following operations.

[0085] 1. Prepare a chip 10. In an exemplary embodiment, the chip 10 may be a piezoresistive chip. The chip 10 may include at least one electrode portion 11 and at least one piezoresistor 12. The piezoresistor 12 is connected to the electrode portion 11 in a one-to-one correspondence.

[0086] In the exemplary embodiment, the electrode portion 11 is provided on the surface of the chip 10 .

[0087] In an exemplary embodiment, the material of the electrode portion 11 includes, but is not limited to, gold (Au), copper (Cu), molybdenum (Mo), aluminum (Al), or the like.

[0088] The chip 10 can be manufactured using conventional processes, which will not be described in detail here.

[0089] 2. Forming a substrate pattern. The substrate 21 may be a glass substrate. In an exemplary embodiment, forming the substrate 21 pattern may include forming the substrate 21 pattern on the substrate 21 by sandblasting, photosensitive glass etching, focused discharge etching, plasma etching, laser ablation, electrochemical etching, and laser-induced etching. The substrate 21 pattern may include a plurality of through-holes 100 and at least one groove structure 200. The through-holes 100 penetrate the substrate 21 in a direction perpendicular to the chip 10 and correspond to the position of the electrode portion 11, so that the electrode portion 11 is exposed to the through-holes 100. The groove structure 200 is provided on the side of the substrate 21 close to the chip 10.

[0090] The surface of the substrate 21 near the chip 10 is connected to the surface of the chip 10 so that the orthographic projection of the through hole 100 on the chip 10 at least partially overlaps with the electrode portion 11, thereby exposing the electrode portion 11 and allowing the chip 10 to enclose the groove structure 200, forming a sealed cavity, as shown in Figures 1A and 1B. Figure 1A is a schematic diagram of the planar structure of the sensor module after the substrate 21 pattern is formed in one embodiment of the present application. Figure 1B is a schematic diagram of the cross-sectional structure of the sensor module after the substrate 21 pattern is formed in one embodiment of the present application, wherein the cross section is perpendicular to the chip 10.

[0091] In an exemplary embodiment, a surface of the substrate 21 close to the chip 10 is anodically bonded to a surface of the chip 10 .

[0092] In an exemplary embodiment, on a plane parallel to the chip 10 , the cross-sectional shape of the through hole 100 may be, but is not limited to, a circle, a triangle, a square, a rectangle, or the like.

[0093] In an exemplary embodiment, taking the cross-sectional shape of the through hole 100 parallel to the plane of the chip 10 as a circle, the diameter of the through hole 100 may be approximately 50 μm to 300 μm, for example, the diameter of the through hole 100 may be approximately 175 μm.

[0094] In an exemplary embodiment, the depth of the through hole 100 may be approximately 200 μm to 400 μm, where the depth may be a dimension in a direction perpendicular to the plane of the chip 10. For example, the depth of the through hole 100 may be approximately 200 μm.

[0095] In an exemplary embodiment, the wall of the through hole 100 is tapered, so that the through hole 100 has a large end and a small end along a cross section perpendicular to the chip 10, wherein the large end is located on the side of the through hole 100 away from the chip 10, and the small end is located on the side of the through hole 100 close to the chip 10. By arranging the wall of the through hole 100 in this structure, it is possible to facilitate the deposition of material on the wall of the through hole 100. The diameter of the through hole 100 can be the diameter of the large end, the diameter of the small end, or the average diameter, and this application is not limited thereto.

[0096] In an exemplary embodiment, the depth of the groove structure 200 may be approximately 40 μm to 240 μm, where the depth may be measured in a direction perpendicular to the plane of the chip 10. For example, the groove depth of the groove structure 200 may be approximately 140 μm. It is understood that in other embodiments, the groove depth of the groove structure 200 may be within other ranges and may be designed based on the deformation distance of the sensor module.

[0097] In an exemplary embodiment, the cross-sectional shape of the trench structure 200 parallel to the chip 10 may be, but is not limited to, a circle, a triangle, a square, or a rectangle.

[0098] In an exemplary embodiment, taking the cross-section of the groove structure 200 parallel to the chip 10 as a square, the side length of the groove structure 200 may be approximately 100 μm to 600 μm, for example, the side length of the groove structure 200 may be approximately 350 μm.

[0099] In an exemplary embodiment, the orthographic projection of the through-hole 100 on the chip 10 does not overlap with the orthographic projection of the groove structure 200 on the chip 10 .

[0100] In an exemplary embodiment, there are multiple electrode portions 11, and the number of through-holes 100 matches the number of electrode portions 11, with each through-hole 100 corresponding one-to-one to the multiple electrode portions 11. The multiple through-holes 100 are arranged around the slot structure 200, and the distance between the slot structure 200 and the through-hole 100 in the circumferential direction is greater than or equal to the side length of the slot structure 200, thereby reducing the impact of deformation of the sensor module on the through-hole 100 and the structures disposed on the wall of the through-hole 100.

[0101] 3. Forming a first conductive layer 22. In an exemplary embodiment, forming the first conductive layer 22 may include: electroplating a first conductive film with a first electroplating current on the substrate 21 on which the aforementioned pattern is formed, so as to form the first conductive layer 22 on the side of the substrate 21 away from the chip 10 and on the hole wall of the through hole 100, wherein the first conductive layer 22 is electrically connected to the electrode portion 11, and the first conductive layer 22 in the through hole 100 is in an unfilled state, and a cavity 700 is formed, and the cavity 700 corresponds to the through hole 100 one-to-one and is located in the corresponding through hole 100, as shown in Figures 2A and 2B. Figure 2A is a planar schematic diagram of the sensor module after the first conductive layer is formed in one embodiment of the present application. Figure 2B is a cross-sectional schematic diagram of the sensor module after the first conductive layer is formed in one embodiment of the present application, wherein the cross section is perpendicular to the chip 10.

[0102] In an exemplary embodiment, the material of the first conductive film may include, but is not limited to, electrically conductive and electroplatable metals such as copper (Cu), nickel (Ni), chromium (Cr), or zinc (Zn).

[0103] In an exemplary embodiment, the thickness of the first conductive layer 22 can be about 3 μm to 7 μm, and the time for electroplating the first conductive film can be about 3 hours to 7 hours. For example, the thickness of the first conductive layer 22 can be about 5 μm, and the time for electroplating the first conductive film can be about 5 hours. In this way, the first conductive film can be slowly formed on the side of the substrate 21 away from the chip 10 and on the hole wall of the through hole 100, so that the first conductive film grows on the substrate 21 toward the side away from the chip 10 and grows on the hole wall of the through hole 100 toward the axis of the through hole 100. The cavity 700 can keep the through hole 100 in an unfilled state, ensuring the electrical conductivity of the first conductive layer 22 in the through hole 100 and achieving electrical connection with the chip 10. At the same time, the slow growth of the first conductive film and the unfilled state of the through hole 100 make the first conductive layer 22 conducive to stress release in both time and space, avoiding cracks or even breakage at the position of the through hole 100 due to excessive stress in the first conductive layer 22.

[0104] 4. Forming a second conductive layer 23. In an exemplary embodiment, forming the second conductive layer 23 may include: electroplating a second conductive film with a second electroplating current on the substrate 21 formed with the aforementioned pattern to form the second conductive layer 23 on the side of the first conductive layer 22 away from the chip 10. The second conductive layer 23 seals the side of the through hole 100 away from the chip 10, as shown in Figures 3A and 3B. Figure 3A is a plan view schematic diagram of the sensor module after the second conductive layer is formed in one embodiment of the present application. Figure 3B is a cross-sectional schematic diagram of the sensor module after the second conductive layer is formed in one embodiment of the present application, wherein the cross section is perpendicular to the chip 10.

[0105] In an exemplary embodiment, the material of the second conductive film may include, but is not limited to, a metal that is conductive and can be deposited by electroplating, such as copper (Cu), nickel (Ni), chromium (Cr), or zinc (Zn).

[0106] In exemplary embodiments, the material of the first conductive film and the material of the second conductive film may be the same or different.

[0107] In an exemplary embodiment, the thickness of the second conductive layer 23 can be approximately 2 μm to 4 μm, and the time for electroplating the second conductive film can be approximately 20 minutes to 40 minutes. For example, the thickness of the second conductive layer 23 can be approximately 3 μm, and the time for electroplating the second conductive film can be approximately 30 minutes. In this way, by electroplating the second conductive film, the side of the through hole away from the chip 10 can be sealed, making the side of the through hole 100 away from the chip 10 flat. The photoresist can be normally spread through spin coating, spray coating, etc., and the photoresist thickness at the through hole 100 is normal. This can prevent the accumulation of photoresist in the through hole 100, resulting in missing or thin photoresist on the side of the through hole 100 away from the chip 10, causing the first conductive layer 22 at the mouth of the cavity 700 to be partially etched during etching, resulting in abnormal electrical conductivity at the position of the through hole 100.

[0108] In an exemplary embodiment, the first current used for electroplating the first conductive film is less than the second current used for electroplating the second conductive film. The ratio of the first current to the second current may be approximately 1:10 to 1:40. For example, the ratio of the first current to the second current may be approximately 1:25.

[0109] Different plating currents are used for electroplating the first conductive film and the second conductive film, which is beneficial to stress release of the first conductive layer 22 and can quickly form the second conductive layer 23, saving plating time and improving production efficiency.

[0110] 5. Forming a conductive structure pattern. In an exemplary embodiment, forming the conductive structure pattern may include: patterning the first conductive layer 22 and the second conductive layer 23 through a patterning process to form a conductive structure pattern disposed on the side of the substrate 21 away from the chip 10 and the wall of the through hole 100. The conductive structure pattern may include at least one conductive structure 24. The conductive structure 24 may include a first conductive portion 241 and a second conductive portion 242. The first conductive portion 241 is disposed on the side of the substrate 21 away from the chip 10 and the wall of the through hole 100. The first conductive portion 241 is connected to the electrode portion 11. The second conductive portion 242 is disposed on the side of the first conductive portion 241 away from the chip 10 and closes the through hole 100 to form a closed cavity 300, as shown in Figures 4A and 4B. Figure 4A is a planar schematic diagram of the sensor module after the conductive structure pattern is formed in one embodiment of the present application. Figure 4B is a cross-sectional schematic diagram of the sensor module after the conductive structure pattern is formed in one embodiment of the present application, wherein the cross section is perpendicular to the chip 10.

[0111] In an exemplary embodiment, a via 400 is provided on the second conductive portion 242, and the via 400 passes through the second conductive portion 242 in a direction perpendicular to the chip 10 to connect the cavity 300 with the outside world, so as to avoid the plating solution remaining in the cavity 300 after the through hole 100 is closed, resulting in poor reliability.

[0112] In an exemplary embodiment, the diameter of the via hole 400 may be approximately 10 μm to 20 μm, for example, approximately 15 μm. Setting the diameter of the via hole 400 to a smaller size can prevent the second conductive portion 242 from collapsing under stress and affecting electrical conduction.

[0113] The first conductive portion 241 includes a conductive structure pattern located on the hole wall of the through hole 100 after the first conductive layer 22 and the second conductive layer 23 are patterned.

[0114] The second conductive portion 242 includes a conductive structure pattern that is arranged on a side of the substrate 21 away from the chip 10 after the first conductive layer 22 and the second conductive layer 23 are patterned.

[0115] 6. Forming an insulating layer pattern. In an exemplary embodiment, forming the insulating layer pattern may include: coating an insulating film on the substrate 21 on which the aforementioned pattern is formed, patterning the insulating film through a patterning process to form an insulating layer 25 disposed on the side of the conductive structure pattern away from the chip 10, wherein a connection hole 500 is provided on the insulating layer 25, and the insulating film within the connection hole 500 is etched away to expose the second conductive portion 242. As shown in Figures 5A and 5B. Figure 5A is a planar schematic diagram of the sensor module after the insulating layer pattern is formed in one embodiment of the present application. Figure 5B is a cross-sectional schematic diagram of the sensor module after the insulating layer pattern is formed in one embodiment of the present application, wherein the cross section is perpendicular to the chip 10.

[0116] In an exemplary embodiment, the insulating film may be made of materials including, but not limited to, polyimide (PI), epoxy resin (EP), or green oil, and may be a single-layer or multi-layer structure. The insulating layer 25 improves the water and oxygen resistance of the conductive layer pattern, preventing water and oxygen from penetrating downward from the conductive layer into the substrate 21 and chip 10, thereby affecting their electrical properties. Furthermore, the insulating layer 25 made of the aforementioned materials is ductile and does not restrict the normal deformation of the sensor module, allowing the sensor module to deform normally.

[0117] In an exemplary embodiment, the thickness of the insulating layer 25 may be approximately 9 μm to 21 μm. For example, the thickness of the insulating layer 25 may be approximately 7 μm.

[0118] In an exemplary embodiment, the number of the connection holes 500 is consistent with the number of the second conductive parts 242 and corresponds one to one.

[0119] In an exemplary embodiment, the diameter of the connection hole 500 may be approximately 30 μm to 180 μm. For example, the diameter of the connection hole 500 may be approximately 100 μm.

[0120] In an exemplary embodiment, the depth of the connection hole 500 may be approximately 9 μm to 21 μm, and, for example, the depth of the through hole 100 may be approximately 10 μm.

[0121] In an exemplary embodiment, the orthographic projection of the connecting hole 500 on the chip 10 does not overlap with the orthographic projection of the through hole 100 on the chip 10 .

[0122] 7. Forming a connection electrode pattern. In an exemplary embodiment, forming the connection electrode pattern may include: on the substrate 21 having the aforementioned pattern formed thereon, disposing the connection electrode 26 in the connection hole 500 and connecting it to the second conductive portion 242 by welding, diffusion welding, or sintering, so as to form the connection electrode pattern on the side of the insulating layer 25 away from the chip 10.

[0123] It can be understood that in other embodiments, forming the connection electrode pattern may further include: depositing a connection electrode film on the chip 10 having the aforementioned pattern formed thereon, and patterning the connection electrode film through a patterning process to form a connection electrode pattern disposed on a side of the insulating layer 25 away from the chip 10. The connection electrode pattern includes at least one connection electrode 26 disposed within the connection hole 500 and electrically connected to the second conductive portion 242.

[0124] The second conductive portion 242 can be electrically connected to the printed circuit board via the connecting electrode 26, enabling the sensor module to transmit signals to external components via the printed circuit board. This is shown in Figures 6A and 6B. Figure 6A is a plan view of the sensor module after forming the connecting electrode pattern in one embodiment of the present application. Figure 6B is a cross-sectional view of the sensor module after forming the connecting electrode pattern in one embodiment of the present application, wherein the cross section is perpendicular to the chip 10.

[0125] In an exemplary embodiment, the material of the connection electrode 26 may include, but is not limited to, copper (Cu), nickel (Ni), chromium (Cr), tin (Sn), zinc (Zn), or the like.

[0126] In an exemplary embodiment, the number of the connection electrodes 26 matches the number of the connection holes 500 and corresponds one to one.

[0127] In an exemplary embodiment, the connection electrode 26 fills the connection hole 500 and partially protrudes from the side of the insulating layer 25 away from the chip 10. The thickness of the connection electrode 26 protruding from the side of the insulating layer 25 away from the chip 10 can be approximately 9 μm to 21 μm. For example, the thickness of the connection electrode 26 protruding from the side of the insulating layer 25 away from the chip 10 can be approximately 10 μm.

[0128] The preparation process of the sensor module in another exemplary embodiment of the present application may include the following operations.

[0129] 1. Preparation of the chip 10. In the exemplary embodiment, the process of preparing the chip 10 and the electrode portion 11 and the piezoresistor 12 of the chip 10 are substantially the same as those of the aforementioned embodiment.

[0130] 2. Forming a Substrate Pattern. In this exemplary embodiment, the process for forming a substrate pattern and the resulting substrate pattern are substantially the same as those in the aforementioned embodiment, as shown in Figures 7A and 7B. Figure 7A is a schematic diagram of the planar structure of a sensor module after forming a substrate pattern in another embodiment of the present application. Figure 7B is a schematic diagram of the cross-sectional structure of a sensor module after forming a substrate pattern in another embodiment of the present application, wherein the cross section is perpendicular to chip 10.

[0131] 3. Forming a buffer layer 27. In an exemplary embodiment, forming the buffer layer 27 may include depositing a buffer film on the substrate 21 having the aforementioned pattern formed thereon, and patterning the buffer film through a patterning process to form the buffer layer 27 on the side of the substrate 21 away from the chip 10, as shown in Figures 8A and 8B. Figure 8A is a schematic diagram of the planar structure of a sensor module after forming the buffer layer 27 in another embodiment of the present application. Figure 7B is a schematic diagram of the cross-sectional structure of a sensor module after forming the buffer layer 27 in another embodiment of the present application, wherein the cross section is perpendicular to the chip 10.

[0132] 4. Forming a first conductive layer 22. In an exemplary embodiment, forming the first conductive layer 22 may include: electroplating a first conductive film with a first electroplating current on the substrate 21 formed with the aforementioned pattern to form the first conductive layer 22 on the side of the buffer layer 27 away from the substrate 21, the first conductive layer 22 being electrically connected to the electrode portion 11, the first conductive layer 22 in the through hole 100 being unfilled, and forming a cavity 700, the cavity 700 corresponding to the through hole 100 one-to-one and located in the corresponding through hole 100, as shown in Figures 9A and 9B. Figure 9A is a planar schematic diagram of a sensor module after forming the first conductive layer in another embodiment of the present application. Figure 9B is a cross-sectional schematic diagram of a sensor module after forming the first conductive layer in another embodiment of the present application, wherein the cross section is perpendicular to the chip 10.

[0133] The thermal expansion coefficient of the material of buffer layer 27 is between that of glass (3.3 ppm / °C) and that of the material of the first conductive film (e.g., copper: 17.5 ppm / °C). The provision of buffer layer 27 reduces the stress gradient between substrate 21 and first conductive layer 22, thereby lowering the risk of delamination between substrate 21 and first conductive layer 22.

[0134] In an exemplary embodiment, the material of the buffer layer 27 may include, but is not limited to, titanium (Ti) (8.6 ppm / °C), tungsten (W) (4.5 ppm / °C), platinum (Pt) (9 ppm / °C), or biphenyl polyimide (4-8 ppm / °C).

[0135] In an exemplary embodiment, the buffer layer 27 may have a thickness of approximately 0.5 μm to 2 μm. For example, the buffer layer 27 may have a thickness of approximately 1 μm.

[0136] 5. Forming the second conductive layer 23. In this exemplary embodiment, the process for forming the second conductive layer 23 and the resulting second conductive layer 23 are substantially the same as those in the previous embodiment, as shown in Figures 10A and 10B. Figure 10A is a schematic plan view of the sensor module after forming the second conductive layer in another embodiment of the present application. Figure 10B is a schematic cross-sectional view of the sensor module after forming the second conductive layer in another embodiment of the present application, wherein the cross section is perpendicular to the chip 10.

[0137] 6. Forming a Conductive Structure Pattern. In an exemplary embodiment, forming the conductive structure pattern may include patterning the buffer layer 27, the first conductive layer 22, and the second conductive layer 23 through a patterning process to form a conductive structure pattern disposed on the side of the substrate 21 facing away from the chip 10 and on the wall of the through-hole 100. The conductive structure pattern may include at least one conductive structure 24, which may include a first conductive portion 241, a second conductive portion 242, and a buffer portion 243. The buffer portion 243 is disposed on the side of the substrate 21 facing away from the chip 10 and on the wall of the through-hole 100. The first conductive portion 241 is disposed on the side of the buffer portion 243 facing away from the chip 10. The second conductive portion 242 is disposed on the side of the first conductive portion 241 facing away from the chip 10, enclosing the through-hole 100 to form a closed cavity 300, as shown in Figures 11A and 11B. Figure 11A is a plan view schematically illustrating a sensor module according to another embodiment of the present application after the conductive structure pattern is formed. Figure 11B is a cross-sectional view schematically illustrating a sensor module according to another embodiment of the present application after the conductive structure pattern is formed, wherein the cross section is perpendicular to the chip 10.

[0138] 7. Forming an Insulating Layer Pattern. In this exemplary embodiment, the process for forming the insulating layer pattern and the resulting insulating layer pattern are substantially the same as those in the previous embodiment, as shown in Figures 12A and 12B. Figure 12A is a schematic diagram of the planar structure of a sensor module after forming the insulating layer pattern in another embodiment of the present application. Figure 12B is a schematic diagram of the cross-sectional structure of a sensor module after forming the insulating layer pattern in another embodiment of the present application, wherein the cross section is perpendicular to chip 10.

[0139] 8. Forming a connection electrode pattern. In an exemplary embodiment, the process for forming a connection electrode pattern and the resulting connection electrode pattern are substantially the same as those in the aforementioned embodiment, as shown in Figures 13A and 13B. Figure 13A is a schematic diagram of the planar structure of a sensor module after forming the connection electrode pattern in another embodiment of the present application. Figure 13B is a schematic diagram of the cross-sectional structure of a sensor module after forming the connection electrode pattern in another embodiment of the present application, wherein the cross section is perpendicular to chip 10.

[0140] The preparation process of the sensor module in another exemplary embodiment of the present application may include the following operations.

[0141] 1. Preparation of the chip 10. In the exemplary embodiment, the process of preparing the chip 10 and the electrode portion 11 and the piezoresistor 12 of the chip are substantially the same as those of the previous embodiment.

[0142] 2. Forming a Substrate Pattern. In this exemplary embodiment, the process for forming a substrate pattern and the resulting substrate pattern are substantially the same as those in the previous embodiment, as shown in Figures 14A and 14B. Figure 14A is a schematic diagram of the planar structure of a sensor module after forming a substrate pattern in another embodiment of the present application. Figure 14B is a schematic diagram of the cross-sectional structure of a sensor module after forming a substrate pattern in another embodiment of the present application, wherein the cross section is perpendicular to chip 10.

[0143] 3. Forming a first conductive layer pattern. In an exemplary embodiment, forming a conductive layer pattern may include: electroplating a first conductive film with a first electroplating current on the substrate 21 on which the aforementioned pattern is formed, patterning the first conductive film through a patterning process to form a first conductive layer 22 disposed on the side of the substrate 21 away from the chip 10 and on the hole wall of the through hole 100, the first conductive layer 22 being electrically connected to the electrode portion 11, the first conductive layer 22 in the through hole 100 being in an unfilled state, and forming a cavity 700, the cavity 700 corresponding to the through hole 100 one-to-one and being accommodated in the corresponding through hole 100, as shown in Figures 15A and 15B. Figure 15A is a planar schematic diagram of a sensor module in another embodiment of the present application after the first conductive layer pattern is formed. Figure 15B is a cross-sectional schematic diagram of a sensor module in another embodiment of the present application after the first conductive layer pattern is formed, wherein the cross section is perpendicular to the chip 10.

[0144] The first conductive layer pattern has a groove 600, and at least one groove 600 is provided within and / or around the through-hole 100. The provision of the groove 600 does not affect the electrical conductivity characteristics of the first conductive layer 22. Through the provision of the groove 600, when stress in the first conductive layer 22 increases during subsequent manufacturing processes, the stress of the first conductive layer 22 can be first released at the groove 600, causing partial delamination and warping around the groove 600, thereby reducing the impact on the overall film adhesion and electrical conductivity of the first conductive layer 22.

[0145] In an exemplary embodiment, the first conductive film within the groove 600 is at least partially etched away, thereby forming a hole structure or a groove structure.

[0146] In an exemplary embodiment, the edges of the groove 600 are rounded to avoid right angles, sharp corners, and other structures that are prone to cracking under stress.

[0147] In an exemplary embodiment, as shown in FIG. 15A , FIG. 15B , FIG. 20A , FIG. 20B and FIG. 20C , a plurality of grooves 600 are provided in the through hole 100 , and the plurality of grooves 600 are evenly distributed around the axis of the through hole 100 to ensure that stress can be evenly released.

[0148] 20F , a plurality of grooves 600 are provided in the through hole 100, and orthographic projections of portions of the plurality of through holes 100 overlap on the chip 10. Part of the through holes 100 are sequentially arranged in a direction perpendicular to the chip.

[0149] In an exemplary embodiment, as shown in FIG. 20D and FIG. 20E , a plurality of grooves 600 are provided around the through hole 100 . The plurality of grooves 600 are evenly distributed around the axis of the through hole 100 to ensure that stress can be evenly released.

[0150] In an exemplary embodiment, the orthographic projection of the groove 600 on the chip 10 may be, but is not limited to, a circle, a straight line, or an arc.

[0151] 20A , four grooves 600 are provided in the through hole 100, and the four grooves 600 are evenly distributed around the axis of the through hole 100. The orthographic projection of the grooves 600 on the chip 10 is a circle.

[0152] In an exemplary embodiment, as shown in FIG20B , four grooves 600 are provided in the through hole 100, and are evenly distributed around the axis of the through hole 100. The orthographic projection of the grooves 600 on the chip 10 is a straight line, and the orthographic projection of the straight line is arranged along the radial direction of the through hole 100, which can facilitate stress release along the direction perpendicular to the radius.

[0153] In an exemplary embodiment, as shown in FIG20C , four grooves 600 are provided in the through hole 100, and the four grooves 600 are evenly distributed around the axis of the through hole 100. The orthographic projection of the grooves 600 on the chip 10 is an arc, and the orthographic projection of the arc is arranged along a radial direction perpendicular to the through hole 100, which can facilitate stress release along the radial direction.

[0154] It can be understood that in other embodiments, the position of the groove 600 on the first conductive layer 22, the number of the grooves 600, the distribution and density of the grooves 600, the radial setting direction of the grooves 600 relative to the through hole 100, and the shape of the positive projection of the groove 600 on the chip 10 can be adjusted and designed according to the direction in which the stress release of the first conductive layer 22 is severe.

[0155] 4. Forming a second conductive layer 23. In an exemplary embodiment, forming the second conductive layer 23 may include: electroplating a second conductive film with a second electroplating current on the substrate 21 on which the aforementioned pattern is formed, so as to form the second conductive layer 23 on the side of the first conductive layer 22 away from the chip 10, wherein the second conductive layer 23 seals the side of the through hole 100 away from the chip 10, and the formed second conductive layer 23 can also partially fill the groove 600 and / or seal the mouth of the groove 600. As shown in Figures 16A and 16B. Figure 16A is a planar schematic diagram of the sensor module after forming the second conductive layer in another embodiment of the present application. Figure 16B is a cross-sectional schematic diagram of the sensor module after forming the second conductive layer in another embodiment of the present application, wherein the cross section is perpendicular to the chip 10.

[0156] 5. Forming a Conductive Structure Pattern. In this exemplary embodiment, the process for forming a conductive structure pattern and the resulting conductive structure pattern are substantially the same as those in the previous embodiment, as shown in Figures 17A and 17B. Figure 17A is a schematic plan view of the sensor module after forming the conductive structure pattern in another embodiment of the present application. Figure 17B is a schematic cross-sectional view of the sensor module after forming the conductive structure pattern in another embodiment of the present application, wherein the cross section is perpendicular to chip 10.

[0157] 6. Forming an Insulating Layer Pattern. In an exemplary embodiment, the process for forming the insulating layer pattern and the resulting insulating layer pattern are substantially the same as those in the aforementioned embodiment, as shown in Figures 18A and 18B. Figure 18A is a schematic diagram of the planar structure of a sensor module after forming the insulating layer pattern in another embodiment of the present application. Figure 18B is a schematic diagram of the cross-sectional structure of a sensor module after forming the insulating layer pattern in one embodiment of the present application, wherein the cross section is perpendicular to chip 10.

[0158] 7. Forming a connection electrode pattern. In an exemplary embodiment, the process for forming a connection electrode pattern and the resulting connection electrode pattern are substantially the same as those in the previous embodiment, as shown in Figures 19A and 19B. Figure 19A is a schematic diagram of the planar structure of a sensor module after forming the connection electrode pattern in another embodiment of the present application. Figure 19B is a schematic diagram of the cross-sectional structure of the sensor module after forming the connection electrode pattern in another embodiment of the present application, wherein the cross section is perpendicular to chip 10.

[0159] The preparation process of the sensor module in another exemplary embodiment of the present application may include the following operations.

[0160] 1. Preparation of the chip 10. In the exemplary embodiment, the process of preparing the chip 10 and the electrode portion 11 and the piezoresistor 12 of the chip 10 are substantially the same as those of the aforementioned embodiment.

[0161] 2. Forming a Substrate Pattern. In this exemplary embodiment, the process for forming a substrate pattern and the resulting substrate pattern are substantially the same as those in the previous embodiment, as shown in Figures 21A and 21B. Figure 21A is a schematic diagram of the planar structure of a sensor module after forming a substrate pattern in another embodiment of the present application. Figure 21B is a schematic diagram of the cross-sectional structure of a sensor module after forming a substrate pattern in another embodiment of the present application, wherein the cross section is perpendicular to chip 10.

[0162] 3. Forming a first conductive layer 22. In this exemplary embodiment, the process for forming the first conductive layer 22 and the resulting first conductive layer 22 are substantially the same as those in the previous embodiment, as shown in Figures 22A and 22B. Figure 22A is a schematic diagram of the planar structure of a sensor module after forming the first conductive layer in another embodiment of the present application. Figure 22B is a schematic diagram of the cross-sectional structure of the sensor module after forming the first conductive layer in another embodiment of the present application, wherein the cross section is perpendicular to the chip 10.

[0163] 4. Forming a filling structure layer. In an exemplary embodiment, forming the filling structure layer may include: filling the substrate 21 with the aforementioned pattern to fill the cavity 700 and closing the side of the through hole 100 away from the chip 10, thereby forming a filling structure layer on the side of the first conductive layer 22 away from the chip 10, as shown in Figures 23A and 23B. Figure 23A is a schematic diagram of the planar structure of the sensor module after the filling structure layer is formed in another embodiment of the present application. Figure 23B is a schematic diagram of the cross-sectional structure of the sensor module after the filling structure layer is formed in another embodiment of the present application, wherein the cross section is perpendicular to the chip 10.

[0164] The material of filler 28 has a negative thermal expansion coefficient. Filling cavity 700 with a material having a negative thermal expansion coefficient can neutralize the stress of first conductive layer 22 and simultaneously fill through-hole 100, making the side of through-hole 100 away from chip 10 flat. Photoresist can be applied normally through spin coating, spray coating, etc., maintaining a normal photoresist thickness at through-hole 100. This prevents photoresist accumulation within through-hole 100, which could result in missing or thinner photoresist on the side of through-hole 100 away from chip 10. This could cause etching during etching to partially etch the first conductive layer 22 on the side of through-hole 100 away from chip 10, leading to abnormal electrical conductivity at the location of through-hole 100.

[0165] In an exemplary embodiment, the material of the filler 28 may include, but is not limited to, an inverse perovskite structure material, a lead titanate-based compound material, or a silicone resin material.

[0166] 5. Forming a conductive structure pattern. In an exemplary embodiment, forming a conductive structure pattern may include: patterning the first conductive layer through a patterning process to form a conductive structure pattern arranged on the side of the substrate 21 away from the chip 10 and the hole wall of the through hole 100, the conductive structure pattern may include at least one conductive structure 24, and the conductive structure 24 may include a first conductive portion 241. The first conductive portion 241 is arranged on the side of the substrate 21 away from the chip 10 and the hole wall of the through hole 100. The first conductive portion 241 is connected to the electrode portion 11. As shown in Figures 24A and 24B. Figure 24A is a planar schematic diagram of the sensor module after forming the conductive structure pattern in another embodiment of the present application. Figure 24B is a cross-sectional schematic diagram of the sensor module after forming the conductive structure pattern in another embodiment of the present application, wherein the cross section is perpendicular to the chip 10.

[0167] 6. Forming an Insulating Layer Pattern. In this exemplary embodiment, the process for forming the insulating layer pattern and the resulting insulating layer pattern are substantially the same as those in the previous embodiment, as shown in Figures 25A and 25B. Figure 25A is a schematic diagram of the planar structure of a sensor module after forming the insulating layer pattern in another embodiment of the present application. Figure 25B is a schematic diagram of the cross-sectional structure of the sensor module after forming the insulating layer pattern in another embodiment of the present application, wherein the cross section is perpendicular to chip 10.

[0168] 7. Forming a connection electrode pattern. In an exemplary embodiment, the process for forming a connection electrode pattern and the resulting connection electrode pattern are substantially the same as those in the previous embodiment, as shown in Figures 26A and 26B. Figure 26A is a schematic diagram of the planar structure of a sensor module after forming the connection electrode pattern in another embodiment of the present application. Figure 26B is a schematic diagram of the cross-sectional structure of a sensor module after forming the connection electrode pattern in another embodiment of the present application, wherein the cross section is perpendicular to chip 10.

[0169] The structure and preparation process of the ultrasonic transducer in the exemplary embodiment of the present application are merely exemplary. In the exemplary embodiment, the corresponding structure can be changed and the patterning process can be increased or decreased according to actual needs.

[0170] The exemplary embodiment of the present application further provides a method for preparing a substrate. In an exemplary embodiment, the method for preparing a substrate may include:

[0171] Providing a substrate 21 connected to the chip 10;

[0172] A plurality of through holes 100 are formed on the substrate 21 , and the through holes 100 penetrate the substrate 21 in a direction perpendicular to the chip 10 ;

[0173] A stacked structure is sequentially formed in the through hole 100 along a direction perpendicular to and away from the substrate 21 , and each layer in the stacked structure has a different thermal expansion coefficient. The stacked structure includes a first conductive portion 241 , which is electrically connected to the chip 10 .

[0174] In an exemplary embodiment, the method for preparing a substrate may further include forming a cavity 700 on a side of the first conductive portion 241 away from the chip 10 .

[0175] In an exemplary embodiment, the method for preparing the substrate may further include forming a second conductive portion 242 on a side of the first conductive portion 241 away from the chip 10 , and closing a side of the through hole away from the chip 10 , wherein the first conductive portion 241 and the second conductive portion 242 together form a cavity 300 .

[0176] In an exemplary embodiment, the method for preparing the substrate may further include forming a via hole 400 on the second conductive portion 242 , wherein the via hole 400 penetrates the second conductive portion 242 in a direction perpendicular to the chip 10 and communicates with the cavity 300 .

[0177] In an exemplary embodiment, the first conductive portion 241 is electroplated at least on the hole wall of the through hole 100 and on the chip 10 exposed to the through hole 100 by a first electroplating current;

[0178] The second conductive portion 242 is electroplated on a side of the first conductive portion 241 away from the chip 10 using a second electroplating current;

[0179] The first electroplating current is smaller than the second electroplating current.

[0180] In an exemplary embodiment, the stacked structure is sequentially formed in the through hole 100 in a direction perpendicular to and away from the substrate 21 , and may include:

[0181] forming a buffer layer 27 on a side of the substrate away from the chip 10;

[0182] The first conductive portion 241 is formed on a side of the buffer layer 27 away from the chip 10 .

[0183] In an exemplary embodiment, the method for preparing a substrate may further include forming a groove on the first conductive portion 241 .

[0184] In an exemplary embodiment, the method for preparing a substrate may further include:

[0185] A filler 28 is formed on a side of the first conductive portion 241 away from the chip 10 .

[0186] The embodiment of the present application also provides a sensor module, including the substrate and chip 10 of the aforementioned embodiment. The surface of the substrate close to the chip 10 is bonded to the surface of the chip 10. In the embodiment of the present application, the sensor module can be, but is not limited to, a pressure sensing module, an acceleration sensing module, an inertial measurement module, an angular motion detection module, or a transducer module. The chip 10 can be electrically connected to a prefabricated circuit board (for example, a printed circuit board) through the substrate, and the packaging of the sensor module is completed by making a plastic packaging structure covering the side of the sensor module to obtain a sensor.

[0187] Although the embodiments disclosed in this application are as described above, it should be noted that the above embodiments are merely illustrative and not restrictive. Therefore, this application is not limited to what is specifically shown and described herein. Various modifications, substitutions, or omissions may be made to the forms and details of the embodiments without departing from the scope of this application.

Claims

1. A substrate, comprising a substrate configured to be connected to a chip, the substrate being provided with a plurality of through-holes, the through-holes penetrating the substrate in a direction perpendicular to the chip, the through-holes being provided with a stacked structure in a direction perpendicular to and away from the substrate, wherein each layer in the stacked structure has a different thermal expansion coefficient; The stacked structure includes a first conductive portion electrically connected to the chip.

2. The substrate according to claim 1, wherein The stacked structure further includes a cavity, which is arranged on a side of the first conductive portion away from the chip.

3. The substrate according to claim 2, wherein The substrate further includes a second conductive portion, which is arranged on a side of the first conductive portion away from the chip and closes a side of the through hole away from the chip. The first conductive portion and the second conductive portion together form a cavity.

4. The substrate according to claim 3, wherein The second conductive portion is provided with a via hole, which passes through the second conductive portion in a direction perpendicular to the chip and is connected to the cavity.

5. The substrate according to claim 4, wherein The diameter of the via hole is 10 μm to 20 μm.

6. The substrate according to claim 1 or 2, wherein The stacked structure further includes a buffer layer, which is arranged on a side of the substrate away from the chip, and the first conductive portion is arranged on a side of the buffer layer away from the chip.

7. The substrate according to claim 6, wherein The thermal expansion coefficient of the material of the buffer layer is between the thermal expansion coefficient of the material of the substrate and the thermal expansion coefficient of the material of the first conductive portion.

8. The substrate according to claim 1, wherein A groove is provided on the first conductive part.

9. The substrate according to claim 8, wherein At least one groove is provided in the through hole.

10. The substrate according to claim 9, wherein A plurality of grooves are provided in the through hole, and the plurality of grooves are evenly distributed around the axis of the through hole.

11. The substrate according to claim 8, wherein At least one groove is provided around the periphery of the through hole.

12. The substrate according to claim 11, wherein A plurality of grooves are arranged around the through hole, and the plurality of grooves are evenly distributed around the axis of the through hole.

13. The substrate according to any one of claims 8 to 12, wherein The orthographic projection of the groove on the chip is circular, straight or arc-shaped.

14. The substrate according to claim 1, wherein The stacked structure further includes a filler, which is arranged on a side of the first conductive portion away from the chip and seals the side of the through hole away from the chip.

15. The substrate according to claim 14, wherein The thermal expansion coefficient of the material of the filler is negative.

16. A sensor module, comprising: The substrate according to any one of claims 1 to 15; and The chip, the surface of the substrate close to the chip is electrically connected to the chip.

17. A method for preparing a substrate, comprising: providing a substrate connected to the chip; forming a plurality of through holes on the substrate, wherein the through holes penetrate the substrate in a direction perpendicular to the chip; A stacked structure is sequentially formed in the through hole along a direction vertical to and away from the substrate, and the stacked structure The thermal expansion coefficient of each layer is different, and the stacked structure includes a first conductive part, which is electrically connected to the chip. 18 . The method for preparing a substrate according to claim 17 , further comprising forming a cavity on a side of the first conductive portion away from the chip.

19. The method for preparing a substrate according to claim 17, further comprising: A second conductive portion is formed on a side of the first conductive portion away from the chip, and the side of the through hole away from the chip is closed, so that the first conductive portion and the second conductive portion together form a cavity. 20 . The method for preparing a substrate according to claim 19 , further comprising forming a via hole on the second conductive portion, wherein the via hole penetrates the second conductive portion in a direction perpendicular to the chip and communicates with the cavity.

21. The method for preparing a substrate according to claim 19, wherein: The first conductive portion is electroplated at least on the hole wall of the through hole and on the chip exposed to the through hole by a first electroplating current; The second conductive portion is electroplated on a side of the first conductive portion away from the chip by a second electroplating current; The first electroplating current is smaller than the second electroplating current.

22. The method for preparing a substrate according to claim 17, wherein: A stacked structure is sequentially formed in the through hole along a direction vertical to and away from the substrate, comprising: forming a buffer layer on a side of the substrate away from the chip; The first conductive portion is formed on a side of the buffer layer away from the chip. 23 . The method for preparing a substrate according to claim 17 , further comprising forming a groove on the first conductive portion.

24. The method for preparing a substrate according to claim 17, further comprising: A filler is formed on a side of the first conductive portion away from the chip.

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