Latch unit, multi-bit latch, integrated circuit and preparation method therefor

Abstract

A latch unit, a multi-bit latch, an integrated circuit and a preparation method therefor. The multi-bit latch comprises a first latch group, a second latch group, a padding row, a third latch group and a fourth latch group, which are sequentially arranged on a substrate in an X direction, wherein each latch group comprises eight latch rows sequentially arranged in the X direction; each latch row comprises one latch unit; one latch row adjacent to the padding row is further provided with one first-level clock unit; two latch rows at the middle position of each latch group are each further provided with one second-level clock unit; and the first-level clock unit and the latch unit in the same latch row, and the second-level clock unit and the latch unit in the same latch row are both sequentially arranged in a Y direction. The latch unit, the multi-bit latch and the integrated circuit in the embodiments of the present disclosure offer reliable operation, a small area and high efficiency.

Description

A latch unit, a multi-bit latch, an integrated circuit, and a method for fabricating the same. Technical Field

[0001] This disclosure relates to, but is not limited to, electronic technology, and more specifically, to a latching unit, a multi-bit latch, an integrated circuit, and a method for fabricating the same. Background Technology

[0002] A latch is a level-triggered memory cell. Data storage is determined by the level of an enable signal; the output only changes with the input when the latch is enabled. A multi-bit latch is used to store and transmit multiple bits of data. It includes a clock circuit and multiple latching circuits, each of which can store one bit. The clock signal generated by the clock circuit and its inverted clock signal serve as the enable signal for each latching circuit. Multi-bit latches are typically used to store transient data.

[0003] The layout design of multi-bit latches in integrated circuits still needs to be improved to optimize the area, operational reliability, efficiency, and energy-saving performance of multi-bit latches.

[0004] Summary of the Invention

[0005] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0006] One embodiment of this disclosure provides a latching unit, including a substrate and eight MOS transistors. The substrate includes an NMOS region and a PMOS region, with the direction from the NMOS region to the PMOS region being a first direction. Four PMOS transistors Q12, Q11, Q7, and Q13 are sequentially arranged along a second direction within the PMOS region, and four NMOS transistors Q9, Q10, Q8, and Q14 are sequentially arranged along the second direction within the NMOS region. The second direction intersects the first direction. Wherein:

[0007] Q7 and Q8 are connected to form a transmission gate, Q9, Q10, Q11, and Q12 are connected to form a clocked inverter, and Q13 and Q14 are connected to form a CMOS inverter. Q12 and Q9, Q11 and Q8, and Q13 and Q14 are respectively positioned opposite each other, and the gates of the two oppositely positioned MOS transistors are interconnected. A filling structure is formed in the PMOS region opposite to Q10 and in the NMOS region opposite to Q7. A filling structure is also formed between Q7 and Q13 and between Q8 and Q14.

[0008] The transmission gate, based on clk and clkb, either blocks the input 1-bit data d or outputs it to the input of the CMOS inverter; the CMOS inverter inverts d, resulting in an inverted signal. The output is sent to the input of a clock-controlled inverter, which uses clk and clkb to... Block or The inverted signal is output to the input of the CMOS inverter; where clk and clkb are both clock signals of the input latch unit, and clkb is the inverted signal of clk.

[0009] An embodiment of this disclosure also provides a multi-bit latch, including a first latch group, a second latch group, a fill row, a third latch group, and a fourth latch group arranged sequentially along the X direction on a substrate. Each latch group includes eight latch rows arranged sequentially along the X direction, and each latch row includes one latch unit, wherein:

[0010] A latch line adjacent to the fill line is also provided with a first-level clock unit, which is configured to receive the clock signal clkin and output the inverted signal clkout of clkin;

[0011] Each latch group has two latch rows in the middle position, each with a secondary clock unit. One secondary clock unit is configured to receive clkout and output the inverted signal clk of clkout, and the other secondary clock unit is configured to receive clk and output the inverted signal clkb of clk.

[0012] The latch unit is configured to latch and output 1-bit input data based on clk and clkb;

[0013] The primary clock unit and the latch units in the same latch row, as well as the secondary clock unit and the latch units in the same latch row, are arranged sequentially along the Y direction, with the Y direction intersecting the X direction.

[0014] One embodiment of this disclosure also provides an integrated circuit including a multi-bit latch as described in any embodiment of this disclosure.

[0015] This disclosure also provides a method for fabricating a multi-bit latch, comprising: forming one primary clock unit, eight secondary clock units, and 32 latch units on a substrate; on a plane parallel to the substrate, the multi-bit latch includes a first latch group, a second latch group, a fill row, a third latch group, and a fourth latch group sequentially arranged along the X direction on the substrate, each latch group including eight latch rows sequentially arranged along the X direction, each latch row including one latch unit; wherein, a latch row adjacent to the fill row is further provided with the primary clock unit, the primary clock unit being configured to receive a clock signal clkin and output clk. The latch unit is configured to receive clkout and output the inverted signal clkout. Each latch group has two latch rows in the middle, each with a secondary clock unit. One secondary clock unit is configured to receive clkout and output the inverted signal clkout, while the other secondary clock unit is configured to receive clk and output the inverted signal clkb. The latch unit is configured to latch and output the input 1-bit data based on clk and clkb. The primary clock unit and the latch units in the same latch row, as well as the secondary clock unit and the latch units in the same latch row, are arranged sequentially along the Y direction, with the Y direction intersecting the X direction.

[0016] After reading and understanding the accompanying drawings and detailed description, other aspects can be understood. Attached Figure Description

[0017] The accompanying drawings are provided to further illustrate the technical solutions of this disclosure and form part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of this disclosure and do not constitute a limitation on the technical solutions of this disclosure. The shape and size of one or more components in the drawings do not reflect actual proportions and are only intended to illustrate the content of this disclosure.

[0018] Figure 1 is a circuit block diagram of a multi-bit latch according to an embodiment of the present disclosure;

[0019] Figure 2 is an equivalent circuit diagram of a primary clock circuit, a secondary clock circuit, and a latch circuit according to an embodiment of this disclosure;

[0020] Figure 3 is a schematic diagram of a latch circuit according to an embodiment of the present disclosure;

[0021] Figure 4 is a schematic diagram of the structure of a multi-bit latch according to an embodiment of the present disclosure;

[0022] Figures 5A, 5B, 5C and 5D are schematic diagrams of the structure of the first latch group, the second latch group, the third latch and the fourth latch group in a multi-bit latch according to an embodiment of the present disclosure.

[0023] Figure 6 is a schematic diagram showing the distribution of the input signal terminals and output signal terminals of a multi-bit latch chip according to an embodiment of the present disclosure;

[0024] Figures 7A and 7B are schematic diagrams of the clock signal routing of a multi-bit latch according to an embodiment of the present disclosure.

[0025] Figure 8A is a top view of a latching unit after the formation of a first insulating layer and a polysilicon layer according to an embodiment of the present disclosure;

[0026] Figure 8B is a top view of a latching unit after a trench contact layer has been formed according to an embodiment of the present disclosure;

[0027] Figure 8C is a top view of a latch cell after the gate contact layer has been formed according to an embodiment of the present disclosure;

[0028] Figure 8D is a top view of a latching unit after the first contact hole pattern is formed according to an embodiment of the present disclosure;

[0029] Figure 8E is a top view of the first metal layer of a latching unit formed according to an embodiment of the present disclosure;

[0030] Figure 8F is a top view of a latching unit after the first metal layer has been formed according to an embodiment of the present disclosure;

[0031] Figure 8G is a top view of a latching unit after the second contact hole pattern is formed according to an embodiment of the present disclosure;

[0032] Figure 8H is a top view of the second metal layer of a latching unit formed according to an embodiment of the present disclosure;

[0033] Figure 8I is a top view of a latching unit after the second metal layer is formed according to an embodiment of the present disclosure;

[0034] Figure 8J is a top view of a latching unit after the third contact hole pattern is formed according to an embodiment of the present disclosure;

[0035] Figure 8K is a schematic diagram of the second metal layer, the third contact hole pattern, and the third metal layer of a latching unit formed according to an embodiment of the present disclosure.

[0036] Figure 9A is a top view of the Buffer1 cell + Latch1 cell after the formation of the first insulating layer and the polysilicon layer according to an embodiment of the present disclosure;

[0037] Figure 9B is a top view of the Buffer1 unit + Latch1 unit after the trench contact layer is formed according to an embodiment of the present disclosure;

[0038] Figure 9C is a top view of the Buffer1 cell + Latch1 cell after the gate contact layer is formed according to an embodiment of the present disclosure;

[0039] Figure 9D is a top view of the Buffer1 unit + Latch1 unit after the first contact hole pattern is formed according to an embodiment of the present disclosure;

[0040] Figure 9E is a top view of the first metal layer of the Buffer1 unit + Latch1 unit formed according to an embodiment of the present disclosure;

[0041] Figure 9F is a top view of the Buffer1 unit + Latch1 unit after the first metal layer is formed according to an embodiment of this disclosure;

[0042] Figure 10A is a top view of the B1L1 latch line (Buffer1 unit + Latch1 unit) and the B2L2 latch line (Buffer2 unit + Latch2 unit) after the second contact hole pattern is formed according to an embodiment of the present disclosure, with the B1L1 latch line above the B2L2 latch line.

[0043] Figure 10B is a top view of the second metal layer of B1L1 latch line and B2L2 latch line formed according to an embodiment of the present disclosure;

[0044] Figure 10C is a top view of the B1L1 latch line and the B2L2 latch line after the second metal layer is formed according to an embodiment of the present disclosure;

[0045] Figure 10D is a top view of the B1L1 latch line and the B2L2 latch line after the third contact hole pattern is formed according to an embodiment of the present disclosure;

[0046] Figure 10E is a top view of the second metal layer, the third contact hole pattern, and the third metal layer of B1L1 latching row and B2L2 latching row formed according to an embodiment of the present disclosure.

[0047] Figure 11A is a top view of the B2L2 latch line and the B1L1 latch line after the second contact hole pattern is formed according to an embodiment of the present disclosure, with the B2L2 latch line above the B1L1 latch line.

[0048] Figure 11B is a top view of the second metal layer of B2L2 latch line and B1L1 latch line formed according to an embodiment of the present disclosure;

[0049] Figure 11C is a top view of the B2L2 latch line and the B1L1 latch line after the second metal layer is formed according to an embodiment of the present disclosure;

[0050] Figure 11D is a top view of the B2L2 latch line and the B1L1 latch line after the third contact hole pattern is formed according to an embodiment of the present disclosure;

[0051] Figure 11E is a top view of the second metal layer, the third contact hole pattern, and the third metal layer of the B2L2 latch row and the B1L1 latch row formed according to an embodiment of the present disclosure.

[0052] Figure 12A is a top view of the IL2 latch line after the second contact hole pattern is formed according to an embodiment of the present disclosure;

[0053] Figure 12B is a top view of an IL2 latch line forming a second metal layer and a third contact hole pattern according to an embodiment of the present disclosure;

[0054] Figure 12C is a top view of the second metal layer, the third contact hole pattern, and the third metal layer of the IL2 latch line formed according to an embodiment of the present disclosure. Detailed Implementation

[0055] The embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. The implementation can be carried out in many different forms. Those skilled in the art will readily understand that the methods and content can be changed to one or more forms without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as limited to the contents described in the following embodiments. Without conflict, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other.

[0056] In the accompanying drawings, the size, thickness, or area of ​​one or more constituent elements is sometimes exaggerated for clarity. Therefore, this disclosure is not necessarily limited to these dimensions, and the shape and size of one or more components in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate ideal examples, and this disclosure is not limited to the shapes or values ​​shown in the drawings. The ordinal numbers such as "first," "second," and "third" in this disclosure are used to avoid confusion regarding constituent elements, not to limit their quantity. "A plurality" in this disclosure indicates two or more quantities. In this disclosure, for convenience, terms indicating orientation or positional relationship such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to illustrate the positional relationship of constituent elements with reference to the accompanying drawings. This is solely for the purpose of facilitating the description and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this disclosure. The positional relationship of the constituent elements may be appropriately varied depending on the direction in which the constituent elements are described. Therefore, the wording is not limited to what is stated in the instruction manual and can be appropriately replaced as needed.

[0057] In this disclosure, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linkage" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the meaning of these terms in this disclosure as appropriate. "Electrical connection" includes situations where constituent elements are connected together by a component having a certain electrical function. There are no particular limitations on the term "component having a certain electrical function," as long as it allows for the transmission and reception of electrical signals between the connected constituent elements. Examples of "component having a certain electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with one or more functions. In this document, the connection between the gate, drain, and source of a transistor such as a MOS, the connection between the gate, drain, and source of a MOS and a conductor (such as various electrodes or other conductive lines, pins, etc. formed by metals, polysilicon, etc.), and the connection between conductors refers to electrical connection.

[0058] In this disclosure, a transistor is a device that includes at least three terminals: a gate, a drain, and a source. A channel region exists between the drain (also referred to as the drain terminal, drain region, or drain electrode) and the source (also referred to as the source terminal, source region, or source electrode) of a transistor, and current can flow through the drain, the channel region, and the source. In this disclosure, the channel region refers to the region through which current primarily flows.

[0059] In this disclosure, to distinguish the two electrodes of a transistor other than the gate, one electrode may be called the first electrode, and the other electrode may be called the second electrode. The first electrode may be the source or the drain, and the second electrode may be the drain or the source. The gate of the transistor is referred to as the control electrode. In cases where transistors with opposite polarities are used or where the current direction changes during circuit operation, the functions of "source" and "drain" are sometimes interchanged. In this disclosure, "parallel" refers to a state where the angle formed by two straight lines is greater than or equal to -10° and less than 10°; therefore, it can include a state where the angle is greater than or equal to -5° and less than 5°. Similarly, "perpendicular" refers to a state where the angle formed by two straight lines is greater than or equal to 80° and less than 100°; therefore, it can include a state where the angle is greater than or equal to 85° and less than 95°. In this disclosure, "film" and "layer" may be interchanged. For example, sometimes "conductive layer" can be replaced with "conductive film." Similarly, sometimes "insulating film" can be replaced with "insulating layer." In this disclosure, "approximately" and "about" refer to situations where there are no strict limits and the process and measurement errors are allowed.

[0060] One embodiment of this disclosure provides a multibit latch, as shown in Figure 1. The multibit latch includes a primary clock circuit (also called an INV circuit), a secondary clock circuit (also called a buffer circuit), and latch circuits (also called latch circuits). Each primary clock circuit is connected to 2n secondary clock circuits, and each secondary clock circuit is connected to eight 1-bit latch circuits, where n is a positive integer. The latch shown can be a standalone latch or a latch within an integrated circuit. An integrated circuit can have multiple latches with the same or different bit widths to implement data storage functionality. Although the primary clock circuit in the figure is connected to four secondary clock circuits, i.e., n = 2, this disclosure is not limited to this; n can also be equal to 1, 3, 4, or a larger value.

[0061] In this embodiment, the multi-bit latch can be constructed using MOS, and Figure 2 shows the corresponding equivalent circuit diagram. For ease of illustration, only one primary clock circuit (also called the INV circuit), one secondary clock circuit (also called the buffer circuit), and one latch circuit (also called the Latch circuit) from Figure 1 are shown in the figure. The other secondary clock circuits and latch circuits in Figure 1 have the same structure as those shown in Figure 2.

[0062] As shown in Figures 1 and 2, the primary clock circuit includes an inverter configured to receive the input clock signal (denoted as clkin, also known as the clkin signal) from a 32-bit latch and output the inverted signal of clkin (denoted as clkout, also known as the clkout signal). One primary clock circuit is connected to four secondary clock circuits. Each secondary clock circuit includes two inverters connected in series, configured to invert the input clkout signal once and output the inverted signal of clkout (denoted as clk, also known as the clk signal), and invert the clk signal again and output the inverted signal of clk (denoted as clkb, also known as the clkb signal). Each secondary clock circuit is connected to eight latch circuits, outputting the clk and clkb signals to each latch circuit as enable signals. Each latch circuit latches and transmits 1-bit input data based on the clk and clkb signals. The inverters in both the primary and secondary clock circuits are CMOS inverters.

[0063] As shown in Figure 2, the inverter in the first-stage clock circuit includes a first transistor Q1 and a second transistor Q2, where Q1 is a PMOS and Q2 is an NMOS. The gates of Q1 and Q2 are connected as the input terminal of the first-stage clock circuit, used to receive the input clock signal clkin from the 32-bit latch; the drains of Q1 and Q2 are connected as the output terminal of the first-stage clock circuit, outputting the inverted signal clkout of clkin. The source of Q1 is connected to the power supply (denoted as VCC), and the source of Q2 is grounded (denoted as VSSX). The first inverter in the second-stage clock circuit includes a third transistor Q3 and a fourth transistor Q4, and the second inverter includes a fifth transistor Q5 and a sixth transistor Q6. Q3 and Q5 are PMOS, and Q4 and Q6 are NMOS. The sources of Q3 and Q5 are connected to the power supply, and the sources of Q4 and Q6 are grounded. The gates of Q3 and Q4 are connected, serving as the inputs of the secondary clock circuit (and also the inputs of the first inverter) to receive clkout. The drains of Q3 and Q4 are connected, serving as the output of the first inverter to output clk. The gates of Q5 and Q6 are connected, serving as the input of the second inverter to receive clk. The drains of Q5 and Q6 are connected, serving as the output of the second inverter to output clkb. In the secondary clock circuit, the outputs of the first and second inverters are also outputs of the secondary clock circuit. The output clk and clkb are transmitted to each latch circuit connected to this secondary clock circuit.

[0064] For example, the latch circuit is a transmission-gated D latch, as shown in Figure 3, including a transmission gate 31, a clocked inverter 32, and a CMOS inverter 33. The input of transmission gate 31 receives 1 bit of input data (denoted as d, also called the d signal). The output of transmission gate 31 is connected to the output of clocked inverter 32 and the input of CMOS inverter 33. The on / off state of transmission gate 31 can be controlled based on the levels of clk and clkb. The input of clocked inverter 32 is connected to the output of CMOS inverter 33. Clocked inverter 32 is state-controlled based on clk and clkb, and can operate in inverter mode or off mode. The output of CMOS inverter 33 outputs 1 bit of data (denoted as on, also called the on signal). In the latch circuit, the output of transmission gate 31, the output of clocked inverter 32, and the input of CMOS inverter 33 are connected together.

[0065] The latch circuit in this embodiment is implemented using MOS transistors. Please refer to Figures 2 and 3. Transmission gate 31 includes transistor Q7 (seventh transistor) and transistor Q8 (eighth transistor). Clocked inverter 32 includes transistor Q9 (ninth transistor), transistor Q10 (tenth transistor), transistor Q11 (eleventh transistor), and transistor Q12 (twelfth transistor). CMOS inverter 33 includes transistor Q13 (thirteenth transistor) and transistor Q14 (fourteenth transistor). Q7, Q9, Q11, and Q13 are PMOS transistors, while Q8, Q10, Q12, and Q14 are NMOS transistors. In the transmission gate 31, gate 107 of Q7 receives clkb, and gate 108 of Q8 receives clk; the drains of Q7 and Q8 are connected as the input of the transmission gate to receive the d signal, and the sources of Q7 and Q8 are connected as the output of the transmission gate, the output signal of which is marked as nk1 in Figure 2; in the clock inverter 32, the source of Q12 is connected to the power supply, and the gates of Q12 and Q9 are connected as the input of the clock inverter and connected to the output of the CMOS inverter to receive the on signal, and the drain of Q12 is connected to the source of Q11; the gate of Q11 receives clk, and the drains of Q11 and Q10 are connected as the output of the clock inverter; the gate of Q10 receives clkb, and the source of Q10 is connected to the drain of Q9; the source of Q9 is grounded. In CMOS inverter 33, the source of Q13 is connected to the power supply, and the gates of Q13 and Q14 are connected as the input of the CMOS inverter, which is connected to the output of the transmission gate and the output of the clocked inverter to receive nk1; the drains of Q13 and Q14 are connected as the output of the CMOS inverter, which is connected to the input of the clocked inverter and outputs the latched 1-bit data, i.e., the on signal.

[0066] In the aforementioned primary clock circuit, secondary clock circuit, and latch circuit, the substrate of the PMOS is connected to the power supply, and the substrate of the NMOS is grounded. The PMOS is turned off when the gate voltage is high and turned on when the gate voltage is low; the NMOS is turned on when the gate voltage is high and turned off when the gate voltage is low.

[0067] In this embodiment of the 32-bit multi-bit latch, each latch circuit latches and outputs 1 bit of data, and the 32 latch circuits can latch and output 32 bits of data. The latching and output process of 1 bit of data by one latch circuit is as follows: When the clk signal is 1 (clkb signal is 0), the transmission gate 31 is turned on, the clock-controlled inverter 32 is turned off, and the input 1 bit of data d is written to the input terminal of the CMOS inverter; when the clk signal is 0 (clkb signal is 1), the transmission gate 31 is turned off, the clock-controlled inverter 32 operates in inverter state and forms a bistable circuit with the CMOS inverter, latching the 1 bit of data d. The output of the CMOS inverter 33 is the inverted signal of d. The output of the CMOS inverter 33 can be connected to a tri-state gate to control the data output.

[0068] The transistors and interconnects in the aforementioned multi-bit latch can be constructed by forming multiple film layers on a substrate. A first-level clock circuit can be implemented using a single first-level clock cell formed on the substrate, a second-level clock cell can be implemented using two second-level clock cells formed on the substrate, and a latch circuit can be implemented using a single latch cell formed on the substrate. The physical layout, or layout diagram, of the multi-bit latch according to embodiments of this disclosure will be described below.

[0069] One embodiment of this disclosure provides a multi-bit latch, including a fill row formed on a substrate, M latch groups sequentially arranged along the X direction on one side of the fill row, and K latch groups sequentially arranged in the opposite direction along the X direction on the other side of the fill row, where M and K are positive integers. Each latch group includes 8 latch rows sequentially arranged in the X direction, and each latch row includes one latch unit, wherein:

[0070] A latch line adjacent to the filling line is also provided with a primary clock unit (also called an INV unit), which is configured to receive the clock signal clkin and output the inverted signal clkout of clkin;

[0071] Each latch group has two latch rows in the middle position, each with a secondary clock unit (also called a buffer unit). One secondary clock unit is configured to receive clkout and output the inverted signal clk of clkout, and the other secondary clock unit is configured to receive clk and output the inverted signal clkb of clk. These two secondary clock units constitute a secondary clock circuit.

[0072] The latch unit (also known as the Latch unit) is configured to latch and output 1-bit input data based on clk and clkb.

[0073] In an exemplary embodiment of this disclosure, M = K = 2, meaning this embodiment provides a multi-bit latch, as shown in Figures 4 and 5A to 5D. This multi-bit latch includes a first latch group, a second latch group, a fill row, a third latch group, and a fourth latch group sequentially arranged along the X direction on a substrate. Each latch group includes eight latch rows sequentially arranged along the X direction, and each latch row includes one latch unit.

[0074] A latch line adjacent to the fill line is also provided with a first-level clock unit, which is configured to receive the clock signal clkin and output the inverted signal clkout of clkin;

[0075] Each latch group has two latch rows in the middle position, each with a secondary clock unit. One secondary clock unit is configured to receive clkout and output the inverted signal clk of clkout, and the other secondary clock unit is configured to receive clk and output the inverted signal clkb of clk.

[0076] The latch unit is configured to latch and output 1-bit input data based on clk and clkb;

[0077] The primary clock unit and the latch units in the same latch row are arranged sequentially along the Y direction. The secondary clock unit and the latch units in the same latch row are also arranged sequentially along the Y direction. The Y direction and the X direction intersect each other as if they were perpendicular.

[0078] Although the example in the figure places the first-level clock unit (1NV unit) in the adjacent latch line above the fill line, in other embodiments it can also be placed in the adjacent latch line below the fill line.

[0079] In an exemplary embodiment of this disclosure, each latch row is divided into a first region and a second region arranged in the Y direction. In Figures 5A to 5D, the portion to the left of the dashed line extending in the X direction is the first region, and the portion to the right of the dashed line is the second region. The first and second regions of different latch rows are aligned in the X direction. The latching units are all located in the second region of their respective latch rows. The input signals b, clk, and clkb of all latching units can be set to be input from the side closer to the first region (left side in the figure), and the latched 1-bit data is output from the side farther from the first region (right side in the figure). The first-level clock unit and the second-level clock unit are both located in the first region of their respective latch rows. Except for latch rows with first-level and second-level clock units, the first region of other latch rows is provided with filler units (such as filler units). Filler units are placeholder elements used to fill blank areas of the chip. They can be composed of metal layers, polysilicon layers, etc., and have specific functions but can optimize the process, such as improving the uniformity of chemical mechanical polishing (CMP), reducing "voids" in the layout, and improving production yield.

[0080] In an exemplary embodiment of this disclosure, each latch line has a uniform width W in the X direction and a uniform length L in the Y direction, where 0.486 μm ≤ W ≤ 0.594 μm and 1.1664 μm ≤ L ≤ 1.4256 μm. In one example, a fill line located in the middle of all latch lines is a Decap cell, with a width W in the X direction and a length L in the Y direction, where W = 0.54 μm and L = 1.296 μm. The entire 32-bit latch has a length of 1.296 μm, a width of 17.82 μm, and an area of ​​23.09472 μm. 2Decap units can serve as placeholder elements to reduce chip power supply noise. They can be constructed by forming a polysilicon layer and a metal layer on the substrate to improve the chip's decoupling capacitor, reduce noise propagation and interference, and ensure normal chip operation.

[0081] In an exemplary embodiment of this disclosure, the substrates of the first and second regions in each latch row are formed with PMOS and NMOS regions, respectively. The PMOS regions have PMOS substrates, and the NMOS regions have NMOS substrates. In any two adjacent latch rows, the NMOS and PMOS regions of one latch row are arranged sequentially in the X direction, and the first direction (from the NMOS region to the PMOS region) of the latch cells in this latch row is the same as the X direction, referred to as the first latch cell. The NMOS and PMOS regions of the other latch row are arranged sequentially in the opposite direction of the X direction, and the first direction of the latch cells in this latch row is the same as the opposite direction of the X direction, referred to as the second latch cell. The first latch cell and the second latch cell each constitute a 1-bit latch circuit. The second direction (perpendicular to the first direction) of both the first latch cell and the second latch cell is the same as the Y direction. In one example, the transistor positions of the first latch cell and the second latch cell in two adjacent latch rows are mirror-symmetrical with respect to the boundary line extending along the Y direction of the two latch rows. Other structures, such as the positions of various electrodes, can also be mirror-symmetrical with respect to this boundary line, but are not limited thereto. In a reference frame based on the X and Y directions, the latch unit can be divided into a first latch unit and a second latch unit. However, in a reference frame based on the first and second directions, the structures of the first latch unit and the second latch unit both conform to the description of the relevant embodiments of the latch unit below.

[0082] In an exemplary embodiment of this disclosure, as shown in Figures 4 and 5A to 5D, both secondary clock units include a PMOS transistor disposed in the PMOS region of the first region of the latch row and an NMOS transistor disposed in the NMOS region of the first region of the latch row. The NMOS region and PMOS region of one secondary clock unit are arranged sequentially in the X direction (i.e., the direction from the NMOS region to the PMOS region is the same as the X direction), and it is called the first secondary clock unit (also referred to as Buffer1 unit in the text); the NMOS region and PMOS region of the other secondary clock unit are arranged sequentially in the opposite direction of the X direction (i.e., the direction from the NMOS region to the PMOS region is the same as the opposite direction of the X direction), and it is called the second secondary clock unit (also referred to as Buffer2 unit in the text). Referring to Figure 2, the PMOS transistor of the first secondary clock unit is the third transistor Q3, and the NMOS transistor is the fourth transistor Q4. Q3 and Q4 are connected to form a CMOS inverter to receive clkout and output clk; the PMOS transistor of the second secondary clock unit is the fifth transistor Q5, and the NMOS transistor is the sixth transistor Q6. Q5 and Q6 are connected to form a CMOS inverter to receive clk and output clkb.

[0083] Referring to Figures 4 and 5A, the first latch group in the figures includes eight latch rows. These latch rows can be categorized into several types based on the different units they combine: one type is a latch row composed of a filler unit and a first latch unit (Latch1 unit), labeled FL1; another type is a latch row composed of a filler unit and a second latch unit (Latch2 unit), labeled FL2; another type is a latch row composed of a first secondary clock unit (Buffer1 unit) and a first latch unit (Latch1 unit), labeled B1L1; and another type is a latch row composed of a second secondary clock unit (Buffer2 unit) and a second latch unit (Latch2 unit), labeled B2L2. The filler row in Figure 4 is labeled Decap. The second latch group, as shown in Figure 5B, also includes the above four types of latch rows. As shown in Figure 5C, in addition to the four types of latch lines mentioned above, the latch line adjacent to Decap in the third latch group is another type of latch line, which is composed of the first-level clock unit (INV unit) and the second latch unit (Latch2 unit), and is marked as IL2.

[0084] In this embodiment, the latch cells in the two latch rows adjacent to the fill row are the second latch cells; however, in other embodiments, the positions of different types of latch rows can change. For example, the position of the N-well (N-vell) in each latch row of Figure 4 (the position of the N-vell is the position of the PMOS region) can be moved relative to the illustrated embodiment in the X direction by the width of one latch row (the size of the latch row in the X direction). In Figure 4, the upper half of the Decap cell is the PMOS region and the lower half is the NMOS region; after the movement, the lower half of the Decap cell is the PMOS region and the upper half is the NMOS region, and at this time, the latch cells in the two latch rows adjacent to the fill row are the first latch cells. On either side of the fill row (Decap cell), in any two adjacent latch rows, the latch cells in one latch row are the first latch cells, and the latch cells in the other latch row are the second latch cells. In other embodiments, the first secondary clock unit may also include Q5 and Q6 in Figure 2, which are configured to receive clk and output clkb; the second secondary clock unit includes Q3 and Q4 in Figure 2, which are configured to receive clkout and output clk; in this case, the clock signal routing between the units can be adjusted accordingly.

[0085] In an exemplary embodiment of this disclosure, in a direction perpendicular to the substrate, the multi-bit latch includes a polysilicon layer pattern and a source and drain region of a MOS, a trench contact layer, a gate contact layer, a first contact hole, a first metal layer, a second contact hole, a second metal layer, a third contact hole, and a third metal layer sequentially formed on the substrate; clock signal lines between different latch rows are disposed on the third metal layer; clock signal lines transmitted between the first clock unit and the latch unit, and between the second clock unit and the latch unit in the same latch row are disposed on the second metal layer; and the interconnections between the transistors inside the first clock unit, the second clock unit, and the latch unit are disposed on the first metal layer and the second metal layer, or disposed on the gate contact layer, the first metal layer, and the second metal layer.

[0086] In an exemplary embodiment of this disclosure, a first insulating layer and a polysilicon layer are sequentially formed on the substrate of a secondary clock unit, the polysilicon layer comprising:

[0087] Three electrodes extend along the X direction in the PMOS region and are arranged sequentially and spaced apart in the Y direction. The third electrode serves as the PMOS gate, and the other two electrodes serve as dummy gates.

[0088] Three electrodes extend along the X direction in the NMOS region and are arranged sequentially and spaced apart in the Y direction. The third electrode serves as the NMOS gate, and the other two electrodes serve as dummy gates.

[0089] The three electrodes in the PMOS region and the three electrodes in the NMOS region are arranged opposite each other in the Y direction, and the PMOS gate and the NMOS gate are integrally formed.

[0090] The PMOS and NMOS regions of the secondary clock unit (i.e., the PMOS and NMOS regions of the first region) can be integrally formed with the PMOS and NMOS regions of the second region in the same latch row, and both can be set as rectangular regions.

[0091] Figures 9A to 9F show the structure of the first metal layer and the layers beneath it of the latch row consisting of Buffer1 and Latch1 units. The structure of Buffer1 unit will be described first; the structure of Latch1 unit will be described in the embodiments concerning the latch units below.

[0092] As shown in the figure, the PMOS gate of Buffer1 is Q3 gate 103, the NMOS gate is Q4 gate 104, and the others are virtual gates 100. In Buffer2, the PMOS gate is Q5 gate and the NMOS gate is Q6 gate. The structure of the first metal layer and the layers below the first metal layer of Buffer2 can also be seen in Figures 9A to 9F, but Q3 needs to be replaced with Q5, Q4 needs to be replaced with Q6, and the virtual gate and virtual electrode settings can be the same as those of Buffer1. The structure of the films above the first metal layer of Buffer1 and Buffer2 can be seen in Figures 10A to 10E and Figures 11A to 11E. In Figure 10E, Latch1 is labeled as 81, Latch2 as 82, Buffer1 as 83, and Buffer2 as 84.

[0093] In an exemplary embodiment of this disclosure, in a secondary clock unit, a PMOS drain and a PMOS source are formed on both sides of the PMOS gate in the Y direction, and an NMOS drain and an NMOS source are formed on both sides of the NMOS gate, and the PMOS drain and PMOS source, as well as the NMOS drain and NMOS source, are arranged sequentially in the Y direction; as shown in FIG9B, in the secondary clock unit, in the Y direction, a second virtual electrode 220 is provided between the first virtual gate 100 and the second virtual gate 100 on the side of the PMOS gate away from the latch unit, and a third virtual electrode 217 is provided between the first virtual gate 100 and the second virtual gate 100 on the side of the NMOS gate away from the latch unit.

[0094] In an exemplary embodiment of this disclosure, a gate contact layer is formed on a polysilicon layer in a secondary clock unit. The gate contact layer includes a plurality of gate contact electrodes extending along the Y direction. Referring to FIG9C, the gate contact electrodes include: a seventh gate contact electrode 307 that overlaps with the virtual gate and connects the PMOS drain 219 and the second virtual electrode 220; an eighth gate contact electrode 308 that overlaps with the virtual gate and connects the PMOS source 218 and the Q12 source 208; a ninth gate contact electrode 309 that overlaps with the virtual gate and connects the NMOS source 215 and the Q9 source 206; and a third gate contact electrode that overlaps with the virtual gate. The tenth gate contact electrode 310 connects the third virtual electrode 217 and the NMOS drain 216, and the eleventh gate contact electrode 311 connects the NMOS gate 104 and the PMOS gate 103; wherein the seventh gate contact electrode 307 and the eighth gate contact electrode 308 are located in the PMOS region, and the ninth gate contact electrode 309 and the tenth gate contact electrode 310 are located in the NMOS region; in the X direction, the eleventh gate contact electrode 311 is located between the seventh gate contact electrode 307 and the tenth gate contact electrode 310, and also between the eighth gate contact electrode 308 and the ninth gate contact electrode 309.

[0095] In an exemplary embodiment of this disclosure, in a secondary clock cell, a second insulating layer and a first metal layer are formed on a gate contact layer. The second insulating layer forms a plurality of first contact holes, as shown in Figures 9D to 9F. The first metal layer includes:

[0096] The power connection electrode VCC is located on the side of the PMOS region away from the NMOS region. The power connection electrode is connected to the power connection electrode VCC in the latch cell of the same latch row, and the two can be integrally formed.

[0097] The ground connection electrode VSSX is located on the side of the NMOS region away from the PMOS region. The ground connection electrode is connected to the ground connection electrode VSSX in the latch cell of the same latch row, and the two can be integrally formed.

[0098] The twelfth connection electrode 412 is connected to the PMOS gate through the first contact hole and the eleventh gate contact electrode 311. The twelfth connection electrode 412 is used as the input terminal of the CMOS inverter in the secondary clock unit.

[0099] The thirteenth connection electrode 413 is connected to the second virtual electrode 220 and the third virtual electrode 217 through the first contact hole. The thirteenth connection electrode 413 is used as the output terminal of the CMOS inverter in the secondary clock unit.

[0100] The first contact hole connected to the eleventh gate contact electrode 311 is located in the Y direction between the PMOS gate and the first virtual gate on the side of the PMOS gate away from the latch cell (left side in the figure);

[0101] Both VCC and VSSX can be bar patterns extending along the Y direction. The twelfth connecting electrode 412 and the thirteenth connecting electrode 413 are both bar patterns extending along the X direction. The twelfth connecting electrode 412 is located between the thirteenth connecting electrode 413 and the latch cell of the same latch line. That is, the twelfth connecting electrode 412 is closer to the latch cell of the same latch line than the thirteenth connecting electrode 413.

[0102] In this embodiment, the PMOS gate and NMOS gate are integrally formed and are the same strip pattern of the polysilicon layer. As shown in Figure 9C, the strip pattern extending along the X direction indicated by 103 and 104 is the Q3 gate and Q4 gate.

[0103] In an exemplary embodiment of this disclosure, in a secondary clock unit, a third insulating layer and a second metal layer are formed on top of the first metal layer, and the third insulating layer has a plurality of second contact holes. Figures 10A to 10C illustrate the structure of a latch row composed of a first secondary clock unit and a first latch unit, and a latch row composed of a second secondary clock unit and a second latch unit. As shown in the figures:

[0104] The second metal layer in the first and second level clock units includes: a CLKOUT lead-in line 505, configured to be connected to the twelfth connecting electrode 412 through a second contact hole; and a CLK lead-out line 506, configured to be connected to the thirteenth connecting electrode 413 through a second contact hole, and connected to the CLK transmission line 502 disposed on the second metal layer in the first latch unit of the same latch row, which may be integrally formed.

[0105] The second metal layer in the second secondary clock unit includes: a CLK lead-in line 508, configured to be connected to the twelfth connection electrode 412 through a second contact hole, and connected to the CLK transmission line 502 disposed on the second metal layer in the second latch unit of the same latch row; and a CLKB lead-out line 507, configured to be connected to the thirteenth connection electrode 413 through a second contact hole, and connected to the CLKB transmission line 503 disposed on the second metal layer in the second latch unit of the same latch row.

[0106] In embodiments of multi-bit latches, the structures in the latching unit, such as transistors, connecting electrodes, connecting lines, etc., can be found in the descriptions of related embodiments of the latching unit.

[0107] In an exemplary embodiment of this disclosure, in the second-stage clock unit, a fourth insulating layer and a third metal layer are formed on the second metal layer, and the fourth insulating layer forms a plurality of third contact holes, as shown in Figures 10D to 10E, wherein:

[0108] The third metal layer in the first secondary clock unit includes: a CLKOUT connection line 603, which extends into the primary clock unit in the X direction or the opposite direction of the X direction, and is configured to be connected to the CLKOUT lead-in line 505 through a third contact hole to transmit clkout to the Q3 gate and the Q4 gate;

[0109] When the second secondary clock unit is located on the side of the first secondary clock unit away from the fill row, the third metal layer of the second secondary clock unit is provided with the CLKOUT connection line 603.

[0110] In an exemplary embodiment of this disclosure, the primary clock unit includes a first transistor Q1 disposed in the PMOS region of the first region of the latch line and a second transistor Q2 disposed in the NMOS region of the first region of the latch line; Q1 is a PMOS and Q2 is an NMOS, and the CMOS inverter formed by connecting Q1 and Q2 is configured to receive clkin, output clkout and transmit to the CLKOUT connection line 603.

[0111] The structure of the primary clock unit in this embodiment is similar to that of the secondary clock unit. The structure of the first metal layer and the underlying film layer formed by the latch row composed of the primary clock unit and the second latch unit can be found in the relevant structure of the latch row composed of the secondary clock unit and the second latch unit. The structure of the second contact hole, the second metal layer, the third contact hole, and the third metal layer formed by the latch row composed of the primary clock unit and the second latch unit can be found in Figures 12A to 12C. The clock signal can be input from the pins of the chip containing the multi-bit latch.

[0112] In an exemplary embodiment of this disclosure, the CLKOUT connection line 603 is disposed on the third metal layer of a plurality of latch units. The CLKOUT connection line 603 includes a first segment extending from the first-level clock unit along the X direction to the first-level second-level clock unit of the fourth latch group, and a second segment extending from the first-level clock unit along the opposite direction of the X direction to the first-level second-level clock unit of the first latch group. These two segments can be disconnected at the first-level clock unit or connected as a whole.

[0113] Referring to Figures 12C, 11E, 11B, 7A, and 7B, the clk output from the first secondary clock unit is transmitted via CLK lead-out line 506 and the CLK transmission line 502 and CLK connection line 601 of the first latch unit in the same latch row to the CLK connection line 601 of other latch units in the same latch group. Then, it is transmitted via the CLK transmission line 502 of the second latch unit located in the same latch row as the second secondary clock unit in the latch group to the CLK lead-in line 508 of the second secondary clock unit in the latch group. The clk is transmitted through the CLK connection line 601 of the latch unit. The gate of the transistor that can be input into the latch unit to receive clk can be input into the gate of the second secondary clock unit to receive clk via CLK lead-in line 508. The clkb output from the second secondary clock unit is transmitted to the CLKB connection line of other latch units in the same latch group via CLKB lead-out line 507 and CLKB transmission line 503 and CLKB connection line 602 of the second latch unit in the same latch row. The clkb can be input into the gate of the transistor that can receive clkb in the latch unit via CLKB connection line 602.

[0114] In this embodiment, as shown in Figures 7A and 7B, the third metal layer of each latch unit in a latch group is provided with a CLK connection line 601 and a CLKB connection line 602 extending along the X direction; the CLK connection lines 601 of all latch units in the same latch group are connected in sequence and can be integrally formed, and the CLKB connection lines 602 of all latch units in the same latch group are connected in sequence and can be integrally formed.

[0115] The multi-bit latch of the above embodiments of this disclosure has multiple latch units arranged sequentially in the X direction. The input signal of each latch unit is input from the side closer to the first region, and the output signal is output from the side farther from the first region, which facilitates the arrangement of external input and output signal lines and reduces the overall area. The secondary clock units are basically symmetrically distributed relative to the primary clock units, and the two secondary clock units constituting the second-level clock circuit are located in the middle position in the X direction of their respective latch group, that is, in the fourth and fifth latch rows of a latch group. This makes the clock signals received by each latch unit as consistent as possible, reduces the error caused by the different arrival times of the clock signals due to the different positions of the latch units, and improves the performance of the multi-bit latch.

[0116] The multibit latch of this disclosure can be widely used in various chips that require latching circuits. It features reliable operation, small area, and high efficiency, significantly improving at least one of the physical security, flexibility, accuracy, and energy efficiency of latching circuits and multibit latches. Figure 6 is a schematic diagram of the signal distribution at the input and output terminals of the multibit latch according to this disclosure. The 32-bit latch's input signal terminals include a power supply signal terminal VCC, a ground signal terminal VSSX, an input clock signal terminal clk, and 32 input terminals d0 to d31 for 1-bit data. The 32-bit latch's output signal terminals include 32 output terminals o1n to o31n for 1-bit data. Each 1-bit data input terminal receives the 1-bit data to be latched, and each 1-bit data output terminal outputs the latched 1-bit data.

[0117] An embodiment of this disclosure also provides an integrated circuit including a multi-bit latch as described in any embodiment of this disclosure, such as one or more 32-bit latches.

[0118] This disclosure also provides a method for fabricating a multi-bit latch, comprising: forming one primary clock unit, eight secondary clock units, and 32 latch units on a substrate; wherein, on a plane parallel to the substrate, the multi-bit latch includes a first latch group, a second latch group, a fill row, a third latch group, and a fourth latch group sequentially arranged along the X direction on the substrate, each latch group including eight latch rows sequentially arranged along the X direction, each latch row including one latch unit; a latch row adjacent to the fill row is further provided with the primary clock unit, the primary clock unit being configured to receive a clock signal clkin and output clki. The inverted signal clkout of n; each of the two latch rows in the middle of each latch group is further provided with a secondary clock unit, one of which is configured to receive clkout and output the inverted signal clkout, and the other is configured to receive clk and output the inverted signal clkb of clk; the latch unit is configured to latch and output the input 1-bit data based on clk and clkb; wherein, the primary clock unit and the latch units in the same latch row, and the secondary clock unit and the latch units in the same latch row are arranged sequentially along the Y direction, and the Y direction and the X direction intersect.

[0119] One embodiment of this disclosure provides a latching unit, as shown in Figures 8A to 8I. The latching unit includes a substrate and eight MOS transistors. The substrate includes an NMOS region and a PMOS region, with the direction from the NMOS region to the PMOS region being a first direction. Four PMOS transistors Q12, Q11, Q7, and Q13 are sequentially arranged along a second direction within the PMOS region, and four NMOS transistors Q9, Q10, Q8, and Q14 are sequentially arranged along the second direction within the NMOS region. The second direction intersects the first direction. Wherein:

[0120] Q7 and Q8 are connected to form a transmission gate, Q9, Q10, Q11, and Q12 are connected to form a clocked inverter, and Q13 and Q14 are connected to form a CMOS inverter. Q12 and Q9, Q11 and Q8, and Q13 and Q14 are respectively positioned opposite each other, and the gates of the two oppositely positioned MOS transistors are interconnected. A filling structure (marked as DUMMY1) is formed in the PMOS region opposite to Q10, and a filling structure (marked as DUMMY2) is formed in the NMOS region opposite to Q7. Fill structures are also formed between Q7 and Q13 and between Q8 and Q14. The source region of Q7 and the drain region of Q11 share a P-type doped region, the drain region of Q9 and the source region of Q10 share an N-type doped region, and the source region of Q8 and the drain region of Q10 share an N-type doped region. This sharing simplifies the structure and connection, and reduces the chip size.

[0121] The transmission gate, based on clk and clkb, either blocks the input 1-bit data d or outputs it to the input of the CMOS inverter; the CMOS inverter inverts d, resulting in an inverted signal. The output is sent to the input of a clock-controlled inverter, which uses clk and clkb to... Block or The inverted signal is output to the input of the CMOS inverter; where clk and clkb are both clock signals of the input latch unit, and clkb is the inverted signal of clk.

[0122] In this embodiment, the first direction of the reference frame used by the latch unit is represented by the A-axis direction in Figures 8A to 8I, and the second direction is represented by the B-axis direction, which is perpendicular to the A-axis. As mentioned earlier, if the latch unit is the first latch unit (Latch1 unit), then the first direction is the same as the X direction, and the second direction is the same as the Y direction. If the latch unit is the second latch unit (Latch2 unit), then the first direction is the opposite direction of the X direction, and the second direction is still the same as the Y direction. The NMOS region and PMOS region in the above latch unit are the NMOS region and PMOS region of the second area in the latch row where the latch unit is located, and can be rectangular regions. In the illustrated example, the PMOS region of the latch unit is the region where the N-well (N-vell) is located on the substrate, and the NMOS region is the region other than the N-vell on the P-type doped silicon substrate.

[0123] In this embodiment, the filling structure in the latch unit can be a DUMMY cell. A DUMMY cell is a virtual element used to fill the blank area of ​​a polysilicon layer (POLY). It is usually made of polysilicon material and may have some or all of the structure of the transistor gate, source and drain but without the corresponding function. It plays the role of filling and occupying space, avoiding mutual interference and short circuits between transistors. Adding DUMMY cells to the blank area makes the polysilicon layer as flat and continuous as possible, thereby facilitating subsequent processing steps and reducing defects.

[0124] In an exemplary embodiment of this disclosure, as shown in Figures 8B and 8C, the gate of each of the eight MOS transistors extends along a first direction, and the source (denoted as S) and drain (denoted as D) of the MOS transistor are formed on both sides of the gate of each MOS transistor, and the source and drain of the MOS transistor are arranged sequentially in a second direction; wherein, the source of Q7 also serves as the drain of Q11 (if the two are integrally formed), the drain of Q9 also serves as the source of Q10, and the source of Q8 also serves as the drain of Q10.

[0125] In an exemplary embodiment of this disclosure, a first insulating layer and a polysilicon layer are sequentially formed on the substrate. The polysilicon layer includes a plurality of strip-shaped electrodes extending along a first direction, as shown in FIG8A, wherein:

[0126] In the PMOS region, nine electrodes are arranged sequentially at intervals along the second direction, wherein the second electrode is the gate 112 of Q12, the fourth electrode is the gate 111 of Q11, the fifth electrode is the gate 107 of Q7, and the eighth electrode is the gate 113 of Q13. In the NMOS region, nine electrodes are arranged sequentially at intervals along the second direction, wherein the second electrode is the gate 109 of Q9, the third electrode is the gate 110 of Q10, the fourth electrode is the gate 108 of Q8, and the eighth electrode is the gate 114 of Q14. The other electrodes in both the PMOS and NMOS regions are virtual gates 100 and do not function as transistor gates.

[0127] The nine electrodes in the PMOS region and the nine electrodes in the NMOS region are arranged opposite each other. Gate 112 of Q12 is integrally formed with gate 109 of Q9, gate 111 of Q11 is integrally formed with gate 108 of Q8, and gate 113 of Q13 is integrally formed with gate 114 of Q14. In this text, when a strip pattern in the polysilicon layer serves as the integrally formed first and second gates, this strip pattern can be referred to as either the first gate or the second gate.

[0128] In an exemplary embodiment of this disclosure, as shown in FIG8C, a gate contact layer is formed on the polysilicon layer. The gate contact layer includes a plurality of gate contact electrodes extending along a second direction. The gate contact electrodes include: a first gate contact electrode 301 that overlaps with the gate 107 of Q7; a second gate contact electrode 302 that overlaps with the gate 111 of Q11; a third gate contact electrode 303 that overlaps with the gate 112 of Q12; a fourth gate contact electrode 304 that overlaps with the gate 110 of Q10; a fifth gate contact electrode 305 that overlaps with the gate 114 of Q14; and a sixth gate contact electrode 306 that overlaps with the dummy gate and connects the drain of Q12 to the source of Q11. In one example, the second gate contact electrode 302, the third gate contact electrode 303, and the sixth gate contact electrode 306 may be located in the PMOS region, with the second gate contact electrode 302 located on the side of the drain of Q11 closer to the NMOS region, and the third gate contact electrode 303 located on the side of the source of Q12 closer to the NMOS region. Optionally, the second gate contact electrode 302 and the third gate contact electrode 303 are aligned in the second direction; the fourth gate contact electrode 304 is located on the side of the Q10 source and Q10 drain in the NMOS region closer to the PMOS region; optionally, the first gate contact electrode 301 and the fifth gate contact electrode 305 are aligned in the second direction and located between the fourth gate contact electrode 304 and the second gate contact electrode 302. In this text, "two gate contact electrodes aligned in the second direction" means that the two strip patterns constituting the two gate contact electrodes, after extending infinitely in opposite directions in the second and second directions, completely or partially overlap.

[0129] In an exemplary embodiment of this disclosure, as shown in Figures 8D to 8F, a second insulating layer and a first metal layer are formed on the gate contact layer, and the second insulating layer has a plurality of first contact holes. The first metal layer includes:

[0130] The power connection electrode VCC is located on the side of the PMOS region away from the NMOS region. The power connection electrode is connected to the source of Q12 and the source of Q13 through a first contact hole. In the illustrated example, VCC is located on the side of the PMOS region away from the NMOS region in the first direction (upper side in the figure), including a strip-shaped body extending along the second direction, a first branch 409 connected to the source of Q12 and a second branch 410 connected to the source of Q13. The first branch 409 and the second branch 410 can be strip-shaped patterns extending along the first direction.

[0131] The ground connection electrode VSSX is located on the side of the NMOS region away from the PMOS region. The ground connection electrode is connected to the source of Q9 and the source of Q14 through a first contact hole. In the illustrated example, VSSX is disposed on the side of the NMOS region away from the PMOS region in the first direction (lower side in the figure). It includes a strip-shaped body extending in the second direction, a first branch 408 connected to the source of Q9 and a second branch 411 connected to the source of Q14. The first branch 408 and the second branch 411 can be strip-shaped patterns extending in the first direction.

[0132] The first connection electrode 401 is connected to the Q9 gate 109 and the Q12 gate 112 through the first contact hole and the third gate contact electrode 303, and is used as the input terminal of the clock-controlled inverter.

[0133] The second connection electrode 402 is connected to the gate 108 of Q8 and the gate 111 of Q11 through the first contact hole and the second gate contact electrode 302, and is used to receive clk.

[0134] The third connection electrode 403 has a first end connected to the Q7 gate 107 through a first contact hole and a first gate contact electrode 301, and a second end connected to the Q10 gate 110 through a first contact hole and a fourth gate contact electrode 304, for receiving clkb.

[0135] The fourth connecting electrode 404 has a first end connected to the source of Q7 and the drain of Q11 through a first contact hole, and a second end connected to the source of Q8 and the drain of Q10 through a first contact hole, and is used as the output terminal of the transmission gate and the output terminal of the clocked inverter.

[0136] The fifth connecting electrode 405 has a first end connected to the drain of Q13 through a first contact hole and a second end connected to the drain of Q14 through a first contact hole, and is used as the output terminal of the CMOS inverter.

[0137] The sixth connection electrode 406 is connected to the gate 113 of Q13 and the gate 114 of Q14 through the first contact hole and the fifth gate contact electrode 305, and is used as the input terminal of the CMOS inverter.

[0138] The seventh connecting electrode 407 has a first end connected to the drain of Q7 through a first contact hole and a second end connected to the drain of Q8 through a first contact hole, and is used as the input terminal of the transmission gate.

[0139] In one example, as shown in Figures 8C to 8D, in the second direction, the first contact hole connected to the first gate contact electrode 301 is located between the Q7 gate 107 and the Q11 gate 111; the first contact hole connected to the second gate contact electrode 302 is located between the Q7 gate 107 and the Q11 gate 111; the first contact hole connected to the third gate contact electrode 303 is located between the Q12 gate 112 and the first dummy gate on the side of Q12 away from Q11; the first contact hole connected to the fourth gate contact electrode 304 is located between the Q10 gate 110 and the Q8 gate 108; and the first contact hole connected to the fifth gate contact electrode 305 is located between the first pair of dummy gates and the second pair of dummy gates on the side of Q13 gate closer to Q7. As shown in Figure 8E, the first connecting electrode 401, the fifth connecting electrode 405, and the sixth connecting electrode 406 are strip patterns extending along the first direction; the second connecting electrode 402 is a strip pattern extending along the second direction; the third connecting electrode 403 and the seventh connecting electrode 407 are L-shaped, and the fourth connecting electrode 404 is C-shaped.

[0140] The fourth connection electrode 404 and the seventh connection electrode 407 form a rectangular pattern with a notch, the second connection electrode 402 and the third connection electrode 403 are located within the rectangular pattern, and the third connection electrode 403 is located on the side of the second connection electrode 402 closer to the NMOS region.

[0141] In one example of this embodiment, as shown in Figures 8B to 8D, a first virtual electrode is also provided between the first pair of virtual gates and the second pair of virtual gates on the side of Q8 gate near Q14, and the middle part of the seventh connecting electrode is also connected to the first virtual electrode through a first contact hole.

[0142] In an exemplary embodiment of this disclosure, as shown in Figures 8G to 8I, a third insulating layer and a second metal layer are formed on the first metal layer. The third insulating layer forms a plurality of second contact holes, and the second metal layer includes:

[0143] The ON output line 501, which can be located in the NMOS region, is configured to be connected to the first connection electrode 401 and the fifth connection electrode 405 respectively through the second contact hole, so as to connect the input terminal of the clocked inverter and the output terminal of the CMOS inverter, and to output the signal of the CMOS inverter. Lead it out, such as leading it out to the data output terminal of the latch unit;

[0144] CLK transmission line 502 is configured to be connected to second connection electrode 402 via second contact hole;

[0145] CLKB transmission line 503 is configured to be connected to third connection electrode 403 via second contact hole;

[0146] The D transmission line 504 can be located in the PMOS region and is configured to be connected to the fourth connection electrode 404 and the sixth connection electrode 406 respectively through the second contact hole, so as to connect the output terminal of the transmission gate and the output terminal of the clocked inverter to the input terminal of the CMOS inverter.

[0147] The ON output line 501, CLKB transmission line 503, CLK transmission line 502 and D transmission line 504 can be arranged sequentially in the first direction, and can be a strip pattern extending along the second direction.

[0148] In an exemplary embodiment of this disclosure, as shown in Figures 8J to 8K, a fourth insulating layer and a third metal layer are formed on the second metal layer. The fourth insulating layer forms a plurality of third contact holes, and the third metal layer includes:

[0149] CLK connection line 601 is configured to connect to CLK transmission line 502 via a third contact hole to introduce clk into the transmission gate and clocked inverter via CLK transmission line 502;

[0150] CLKB connection line 602 is configured to connect to CLKB transmission line 503 via a third contact hole to introduce clkb to the transmission gate and clocked inverter via CLKB transmission line 503;

[0151] The CLK connecting line 601 and the CLKB connecting line 602 can be strip patterns extending along the first direction, and the CLK connecting line 601 and the CLKB connecting line 602 can be arranged sequentially in the second direction.

[0152] In some embodiments, the structures of adjacent first latch units and second latch units may be mirror symmetrical with respect to the boundary line extending along the Y-axis between them. However, this disclosure is not limited to this. The structures of the first latch unit and the second latch unit may conform to the description of the latch unit in this embodiment, but are not required to fully meet the requirement of mirror symmetry.

[0153] The latch circuit, multi-bit latch, and integrated circuit of the above embodiments disclosed herein have at least one of the following advantages: reliable operation, small area, and high efficiency.

[0154] The fabrication process of a multi-bit latch is illustrated below. The "patterning process" described in this disclosure includes, for metallic, inorganic, or transparent conductive materials, processes such as photoresist coating, mask exposure, development, etching, and photoresist stripping; for organic materials, it includes processes such as organic material coating, mask exposure, and development. Deposition can be performed using sputtering, evaporation, or chemical vapor deposition, or any one or more of these methods. Coating can be performed using spraying, spin coating, or inkjet printing, or any one or more of these methods. Etching can be performed using dry etching or wet etching, and this disclosure does not limit the methods. A "thin film" refers to a thin film made of a material on a substrate or other layer using deposition, coating, or other processes. If the "thin film" does not require a patterning process during the entire fabrication process, it can also be called a "layer." If the "thin film" requires a patterning process during the entire fabrication process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The components of a "layer" after the patterning process can be called a pattern, and a "layer" includes at least one "pattern." The phrase "A and B are arranged in the same layer" in this disclosure means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer is the dimension of the film layer in the direction perpendicular to the integrated circuit. In the exemplary embodiments of this disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A includes the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0155] In one exemplary embodiment, the fabrication method of the latch unit is described. The latch unit is used to implement a 1-bit latch circuit, including a transmission gate composed of 4 PMOS and 4 NMOS interconnected, a clocked inverter and a CMOS inverter. The connection relationship between the MOS is shown in Figures 8A to 8I and the above description.

[0156] The fabrication process of the latch unit in this embodiment may include the following steps:

[0157] (1) Forming a substrate on a substrate. In an exemplary embodiment, a P-type semiconductor can be obtained by doping a silicon substrate with trace amounts of trivalent elements (such as boron, indium, gallium, or aluminum), and then an n-vell (N-well) can be formed by doping a region where a PMOS is to be generated with trace amounts of pentavalent elements (such as phosphorus, antimony, arsenic, etc.). The n-vell can serve as the substrate for the PMOS, and other regions can serve as the substrate for the NMOS.

[0158] (2) Forming polysilicon layer patterns and source and drain regions of MOS.

[0159] In an exemplary embodiment, forming the polysilicon layer pattern and the source and drain regions of the MOS may include: sequentially depositing a first insulating film and a polysilicon film on a silicon substrate, and patterning the first insulating film and the polysilicon film using a patterning process to form a pattern of a first insulating layer covering the silicon substrate and a pattern of a polysilicon layer disposed on the first insulating layer, as shown in FIG8A. During the patterning process, exposure can use a gray-tone mask (to depict the polysilicon pattern and the source and drain regions of the MOS), and after development, a fully exposed area (no photoresist, corresponding to the source and drain regions), a half-exposed area (photoresist thickness halved, corresponding to the area outside the polysilicon layer pattern, source and drain regions), and an unexposed area (photoresist thickness unchanged, corresponding to the polysilicon layer pattern). The pattern of the first insulating layer can define the boundaries of the source and drain regions of the MOS. After development, the PMOS region can be P-type doped to form the source and drain regions of the PMOS transistor, and the NMOS region can be N-type doped to form the source and drain regions of the NMOS transistor, based on the barrier effect of the first insulating layer, the polysilicon layer on top of it, and the photoresist. In this step, the polysilicon layer can also be doped simultaneously, so that the polysilicon layer with high resistance becomes a conductive layer with low resistance, forming the gate of multiple transistors.

[0160] As shown in Figure 8A, the polysilicon layer in the latching unit includes nine strip patterns, i.e., nine electrodes, arranged sequentially along the second direction (from left to right in the figure) in the PMOS region. Each of these nine electrodes extends along the first direction. The first electrode is called the first electrode, the second electrode is called the second electrode, and so on, with the ninth electrode being called the ninth electrode. The polysilicon layer also includes nine strip patterns, i.e., nine electrodes, arranged sequentially along the second direction in the NMOS region. Each of these nine electrodes extends along the first direction. The first electrode is called the tenth electrode, the second electrode is called the eleventh electrode, and so on, with the ninth electrode being called the eighteenth electrode. The structure and function of these electrodes are described in the attached figures and the above description of the latching unit embodiments, and will not be repeated here.

[0161] In the example shown in Figure 8A, the gate of Q7 extends from the PMOS region into the NMOS region for easy interconnection. The gates of the other NMOS electrodes are located in the NMOS region, and the gates of the other PMOS electrodes are located in the PMOS region. The aforementioned 18 electrodes are arranged in nine columns in the second direction, with each column forming a gate group. For example, the first and tenth electrodes form the first gate group, the second and eleventh electrodes form the second gate group, the third and twelfth electrodes form the third gate group, and so on, with the last gate group consisting of the ninth and eighteenth electrodes. Figure 8A omits the pattern of the insulating layer (such as the field oxide or gate oxide) between the polysilicon layer and the substrate that defines the source and drain regions on both sides of the polysilicon layer.

[0162] (3) Forming a trench contact layer (TCN) pattern.

[0163] In an exemplary embodiment, forming a trench contact layer pattern may include: depositing a trench contact film on a silicon substrate on which the aforementioned pattern is formed, and patterning the trench contact film using a patterning process to form a trench contact layer pattern. Figure 8B shows a TCN pattern formed on both sides of a polysilicon layer. The trench contact layer may use polysilicon (poly-Si) as the material. The TCN includes multiple contact strips formed on the source and drain regions, which can form the source and drain of a MOS.

[0164] As shown in the figure, the trench contact layer pattern includes first contact strips 201 to fourteenth contact strips 214. In the second direction, the 14 contact strips are respectively disposed on both sides of the corresponding gate, covering the source region or drain region, and providing a current transmission path in the vertical direction. Each contact strip can be a strip pattern extending along the first direction. Wherein: the first contact strip 201 serves as the drain of Q7; the second contact strip 202 serves as the source of Q7 and the drain of Q11; the third contact strip 203 serves as the source of Q8 and the drain of Q10; the fourth contact strip 204 serves as the drain of Q8; the fifth contact strip 205 serves as the source of Q10 and the drain of Q9; and the sixth contact strip 206 serves as the source of Q9. The seventh contact 207 serves as the source of Q11; the eighth contact 208 serves as the source of Q12; the ninth contact 209 serves as the drain of Q12; the tenth contact 210 serves as the source of Q13; the eleventh contact 211 serves as the drain of Q13; the twelfth contact 212 serves as the drain of Q14; and the thirteenth contact 213 serves as the source of Q14. Furthermore, the fourteenth contact 214 is located on the side of the dummy gate 100 containing DUMMY2 closer to Q14. The fourteenth contact 214 and the fourth contact 204 are connected to the middle dummy gate 100 through the upper pattern, forming a dummy MOS that serves as a filler, labeled Dummy2 in the figure. Similarly, the ninth contact 209 and the seventh contact 207 are connected to the middle dummy gate 100 through the upper pattern, forming a dummy MOS, labeled Dummy1.

[0165] (4) Forming a gate contact layer (GCN) pattern.

[0166] In an exemplary embodiment, forming a gate contact layer pattern may include: depositing a gate contact film on a silicon substrate on which the aforementioned pattern is formed, and patterning the gate contact film using a patterning process to form a gate contact layer pattern, as shown in FIG8C. The gate contact layer may use a metallic material such as copper, and the gate contact layer establishes a stable electrical contact between the upper first metal layer and the lower polysilicon gate to achieve current transmission.

[0167] As shown in Figure 8C, the gate contact layer pattern may include six gate contact electrodes, each of which can be a strip pattern extending along the second direction.

[0168] The first end of the first gate contact electrode 301 is connected to the gate 107 of Q7, and the second end is disposed between the gate 107 of Q7 and the gate of Q11 in the second direction.

[0169] The first end of the second gate contact electrode 302 is connected to the gate of Q11, and the second end is disposed between the gate of Q11 and the gate of Q7 107 in a second direction. In the first direction, the second gate contact electrode 302 is closer to the source of Q7 than the first gate contact electrode 301.

[0170] The first end of the third gate contact electrode 303 is connected to the Q12 gate 112, and the second end is disposed in the second direction between the Q12 gate 112 and the first gate group on the side of the Q12 gate 112 away from Q11.

[0171] The fourth gate contact electrode 304 is connected to the gate 110 of Q10. The first end of the fourth gate contact electrode 304 is disposed between the gate 109 of Q9 and the gate 110 of Q10 in the second direction, and the second end is disposed between the gate 108 of Q8 and the gate 110 of Q10 in the second direction.

[0172] The fifth gate contact electrode 305 overlaps with the gate 114 of Q14. The first end of the fifth gate contact electrode 305 is disposed in the second direction between the gate 114 of Q14 and the first gate group on the side of Q14 away from Q8, and the second end is disposed in the second direction between the first gate group and the second gate group on the side of Q14 closer to Q8. The fifth gate contact electrode 305 and the first gate contact electrode 301 can be aligned in the second direction. The fifth gate contact electrode 305 can be located in the middle of the latch cell in the first direction, and can be located on the NMOS region side, or on the PMOS region side, or partially located in the PMOS region and partially located in the NMOS region.

[0173] The sixth gate contact electrode 306 is located in the second direction between the gates 112 of Q12 and Q11, and overlaps with the virtual gate 100 at the location of DUMMY1. The first end of the sixth gate contact electrode 306 overlaps with the drain 209 of Q12, and the second end overlaps with the source 207 of Q11. The sixth gate contact electrode 306 enables the connection between the drain 209 of Q12 and the source 207 of Q11.

[0174] (5) Form the first contact hole (V0) pattern.

[0175] In an exemplary embodiment, forming the first contact hole pattern may include: depositing a second insulating film on a silicon substrate on which the aforementioned pattern is formed, patterning the second insulating film by a patterning process to form a second insulating layer covering the aforementioned pattern, wherein a plurality of vias are provided on the second insulating layer, as shown in FIG8D.

[0176] The multiple vias on the second insulating layer may include vias V1 to V16 (see Figures 8C and 8D). The vias V1 and V2, V3 and V4, V5 and V6, V6 and V8, V7 and V8, V9 and V11, V11 and V14, are all positionally corresponding. The orthographic projections of the vias and contact strips on the silicon substrate at these positions at least partially overlap. The second insulating layer at the location of the via is removed, exposing the surface of the contact strip. The twelfth via V12 is positioned relative to the first gate contact electrode 301, the thirteenth via V13 is positioned relative to the second gate contact electrode 302, the fourteenth via V14 is positioned relative to the third gate contact electrode 303, the fifteenth via V15 is positioned relative to the fourth gate contact electrode 304, and the sixteenth via V16 is positioned relative to the fifth gate contact electrode 305. The corresponding vias and gate contact electrodes have the following relationship: the orthographic projection of the via on the silicon substrate at least partially overlaps with the orthographic projection of the second end of the gate contact electrode on the silicon substrate. The second insulating layer at the location of the via is removed, exposing the surface of the second end of the gate contact electrode.

[0177] (6) Form the pattern of the first metal layer (M1).

[0178] In an exemplary embodiment, forming the first metal layer pattern may include: depositing a first metal thin film on a silicon substrate on which the aforementioned pattern is formed, patterning the first metal thin film by a patterning process, and forming the first metal layer pattern on a second insulating layer, as shown in FIG8F. FIG8E is a schematic diagram of the first metal layer in FIG8F.

[0179] Referring to Figures 8E and 8F, the pattern of the first metal layer may include power lines, ground lines, and first connection electrodes 401 to eleventh connection electrodes 411, wherein,

[0180] The first connection electrode 401 is connected to the second end of the third gate contact electrode 303 through the fourteenth via V14 and is configured as the input electrode (i.e., input terminal) of the clock inverter, and needs to be connected to the ON output electrode of the latch unit.

[0181] The second connection electrode 402 is connected to the second end of the second gate contact electrode 302 through the thirteenth via V13. Configured as the clk input electrode for the transmission gate and clocked inverter, it needs to be connected to the CLK input electrode of the latch unit.

[0182] The first end of the third connection electrode 403 is connected to the second end of the first gate contact electrode 301 through the twelfth via V12, and the second end is connected to the second end of the fourth gate contact electrode 304 through the fifteenth via V15. The clkb input electrode, configured as a transmission gate and clocked inverter, needs to be connected to the CLKB input electrode of the latch unit.

[0183] The first end of the fourth connecting electrode 404 is connected to the second contact bar 202 through the second via V2, and the second end is connected to the third contact bar 203 through the third via V3. It is configured as the output electrode (i.e., the output terminal) of the transmission gate and clocked inverter, and needs to be connected to the input electrode of the CMOS inverter.

[0184] The first end of the fifth connecting electrode 405 is connected to the eleventh contact bar 211 through the eighth via V8, and the second end is connected to the twelfth contact bar 212 through the ninth via V9. Configured as the output electrode of the CMOS inverter, it leads out the ON output signal of the Latch1 circuit and can be connected to the corresponding signal output terminal of a multi-bit latch.

[0185] The sixth connection electrode 406 is connected to the fifth gate contact electrode 305 through the sixteenth via V16. Configured as the input electrode of a CMOS inverter, it needs to be connected to the output electrode of the transmission gate and the output electrode of the clocked inverter.

[0186] The first end of the seventh connecting electrode 407 is connected to the first contact strip 201 through the first via V1, and the second end is connected to the fourth contact strip 204 through the fourth via V4. The middle region between the first and second ends is connected to the fourteenth contact strip 214 through the eleventh via V11. The seventh connecting electrode 407 is configured as the input electrode of the transmission gate. By introducing the 1-bit data signal d of the input latch unit, it can be connected to the corresponding signal input terminal of the multi-bit latch.

[0187] The eighth connecting electrode 408 can be a strip pattern extending along the first direction. The first end of the eighth connecting electrode 408 is connected to the ground wire, and the second end of the eighth connecting electrode 408 is connected to the sixth contact strip 206 through the fifth via V5. Since the sixth contact strip 206 is configured as the Q9 source, the eighth connecting electrode 408 achieves the connection between the Q9 source and the ground wire. The eighth connecting electrode 408 and the ground wire can be integrally formed.

[0188] The first end of the ninth connecting electrode 409 is connected to the power line, and the second end is connected to the eighth contact strip 208 through the sixth via V6. This achieves the connection between the Q12 source and the power line. The ninth connecting electrode 409 and the power line can be integrally formed.

[0189] The first end of the tenth connecting electrode 410 is connected to the power line, and the second end is connected to the tenth contact strip 210 through the seventh via V7. This achieves the connection between the Q13 source and the power line. The tenth connecting electrode 410 and the power line can be integrally formed.

[0190] The first end of the eleventh connecting electrode 411 is connected to the ground wire, and the second end is connected to the thirteenth contact strip 213 through the tenth via V10. This achieves the connection between the Q14 source electrode and the ground wire. The eleventh connecting electrode 411 and the ground wire can be integrally formed.

[0191] The integrally formed power line VCC, the ninth connecting electrode 409 and the tenth connecting electrode 410 are collectively referred to as power connection electrodes, and the integrally formed ground line, the eighth connecting electrode 408 and the eleventh connecting electrode 411 are collectively referred to as ground connection electrodes.

[0192] (7) Form the second contact hole (V1) pattern.

[0193] In an exemplary embodiment, forming the second contact hole pattern may include: depositing a third insulating film on the silicon substrate on which the aforementioned pattern is formed, and patterning the third insulating film by a patterning process to form a third insulating layer covering the first metal layer, wherein a plurality of vias are provided on the third insulating layer, as shown in FIG8G.

[0194] The plurality of vias on the third insulating layer may include vias V21 to V26, wherein: via V21 corresponds to the first connecting electrode 401, via V22 corresponds to the second connecting electrode 402, via V23 corresponds to the third connecting electrode 403, via V24 corresponds to the fourth connecting electrode 404, via V25 corresponds to the fifth connecting electrode 405, and via V26 corresponds to the sixth connecting electrode 406. The vias corresponding to the positions and the connecting electrodes have the following relationship: the orthographic projection of the via on the silicon substrate at least partially overlaps with the orthographic projection of the connecting electrode on the silicon substrate, and the third insulating layer at the position of via V21 is removed to expose the surface of the connecting electrode.

[0195] (8) Form the pattern of the second metal layer (M2).

[0196] In an exemplary embodiment, forming the second metal layer pattern may include: depositing a second metal thin film on a silicon substrate on which the aforementioned pattern is formed, patterning the second metal thin film using a patterning process, and forming the second metal layer pattern on a third insulating layer, as shown in FIG8I. FIG8H is a schematic diagram of the second metal layer in FIG8I.

[0197] In an exemplary embodiment, the second metal layer pattern may include the ON output line 501, CLK transmission line 502, CLKB transmission line 503, and d transmission line 504 of the Latch1 circuit. The first end of the ON output line 501 is connected to the first connection electrode 401 via a twenty-first via V21, and the second end is connected to the fifth connection electrode 405 via a twenty-fifth via V25, i.e., connected to the input electrode of the clocked inverter and the output electrode of the CMOS inverter, for outputting the latched 1-bit data. The CLK transmission line 502 is connected to the second connection electrode 402 via a twenty-second via V22. The clk signal can be input to the transmission gate and the clocked inverter. The CLKB transmission line 503 is connected to the third connection electrode 403 via a twenty-third via V23. The clk signal can be input to the transmission gate and the clocked inverter. The first end of the transmission line 504 is connected to the fourth connection electrode 404 through the twenty-fourth via V24, and the second end is connected to the sixth connection electrode 406 through the twenty-sixth via V26, which can realize the connection between the output electrode of the transmission gate and the clocked inverter and the input electrode of the CMOS inverter.

[0198] (9) Form the third contact hole (V2) pattern.

[0199] In an exemplary embodiment, forming the third contact hole pattern may include: depositing a fourth insulating film on a silicon substrate on which the aforementioned pattern is formed, and patterning the fourth insulating film using a patterning process to form a fourth insulating layer covering the second metal layer. A plurality of contact holes are provided on the fourth insulating layer, as shown in FIG8J. The plurality of contact holes on the fourth insulating layer may include vias V27 to V28. The V28 and V27 are offset in a second direction by a distance equal to the width of at least one MOS active region. Herein, the channel region of a MOS covered by polysilicon, and the source and drain regions on both sides of the channel region, are collectively referred to as the active region of the MOS.

[0200] (10) Form the pattern of the third metal layer (M3).

[0201] In an exemplary embodiment, forming the third metal layer pattern may include: depositing a third metal thin film on the silicon substrate on which the aforementioned pattern is formed, patterning the third metal thin film using a patterning process, and forming the third metal layer pattern on the fourth insulating layer, as shown in FIG8K. For ease of viewing, FIG8K only shows the patterns of the second metal layer, the third contact hole, and the third metal layer of the latching unit.

[0202] The third metal layer pattern may include the CLK connection line 601 and the CLKB connection line 602 of the multiplexer.

[0203] The CLKB connection line 601 can be a strip pattern extending along the first direction and can pass through the latch unit. The CLKB connection line 601 is connected to the CLKB transmission line 503 through the twenty-seventh via V27 and is used to transmit the clkb signal output by the secondary clock unit to the Q7 gate 107 and Q10 gate 110 in the latch unit.

[0204] The CLK connection line 602 can be a strip pattern extending along the first direction and can pass through the latch unit. The CLK connection line 602 is connected to the CLK transmission line 502 through the twenty-eighth via V28, and is used to transmit the clk signal output by the secondary clock unit to the Q8 gate 108 and Q11 gate 111 in the latch unit.

[0205] The fabrication process of the latch unit has been described above. As mentioned earlier, there are two types of latch units: Latch1 and Latch2. The CLKB and CLK transmission lines on the second metal layer of both need to extend to the adjacent secondary clock unit. Their shapes may differ slightly, but both can be fabricated using the methods described above. The structure and fabrication process shown in this exemplary embodiment are merely illustrative. In some exemplary embodiments, the corresponding structure and the patterning process can be modified and increased or decreased according to actual needs.

[0206] In the following exemplary embodiments, the integrated circuit fabrication method will be described again using the latching behavior composed of Buffer1 unit and Latch1 unit as an example.

[0207] As shown in Figures 9A to 9L, in the Buffer1 cell, Q3 and Q4 are positioned opposite each other in the X direction, and their gates are integrally formed. Q3 is located on the side of Q12 closest to the Buffer1 cell, and Q4 is located on the side of Q9 closest to the Buffer1 cell. In the Y direction, a fourth fill structure DUMMY4 is disposed between Q3 and Q12, and a sixth fill structure DUMMY6 is disposed between Q4 and Q9. DUMMY4 and DUMMY6 and their right sides can be considered as the first region where the Latch1 cell is located, and the left sides of DUMMY4 and DUMMY6 can be considered as the first region where the Buffer1 cell is located. There are also connection structures such as gate contact electrodes between the two regions. A third fill structure DUMMY3 is disposed adjacent to the side of Q3 away from Q12, and a fifth fill structure DUMMY5 is disposed adjacent to the side of Q4 away from Q9. In an exemplary embodiment, in the Y direction, the source of Q3 and Q4 is located on the side of the gate of Q3 and Q4 close to the adjacent latch cell (the direction from the gate to the source is consistent with the Y direction), and the drain of Q3 and Q4 is located on the side of the gate of Q3 and Q4 away from the adjacent latch cell.

[0208] The preparation process of the latch row composed of Buffer1 unit and Latch1 unit in this embodiment may include the following steps. The preparation process of the latch unit has been described in detail above. Here, we mainly supplement the preparation process of Buffer1 unit in the latch row based on the preparation process of the latch unit, as well as the relationship between Buffer1 unit and Latch1 unit:

[0209] (1) Forming a substrate on a substrate.

[0210] In an exemplary embodiment, a P-type doped silicon substrate is used as the NMOS substrate, and an N-vell is used as the PMOS substrate. The PMOS transistor Q3 of the Buffer1 cell and the four PMOS transistors of the Latch1 cell are generated on the same N-vell N-type substrate. The NMOS transistor Q4 of the Buffer1 cell and the four NMOS transistors of the Latch1 cell are generated on a P-type substrate formed by a P-type doped silicon substrate.

[0211] (2) Forming polysilicon layer patterns and source and drain regions of MOS.

[0212] The method for forming polysilicon layer patterns is described in the latch cell fabrication method, and will not be repeated here.

[0213] As shown in Figure 9A, the polysilicon layer of the Buffer1 cell includes three strip patterns arranged sequentially along the Y direction in the PMOS region and three strip patterns arranged sequentially along the Y direction in the CMOS region. These six strip patterns themselves extend along the X direction and are referred to as the nineteenth to twenty-fourth electrodes. Among them: the nineteenth electrode serves as the virtual gate 100; the twentieth electrode serves as the virtual gate 100 (marked as DUMMY3); the twenty-first electrode serves as the Q3 gate 103; the twenty-second and twenty-third electrodes (marked as DUMMY5) both serve as virtual gates 100; the twenty-third electrode serves as the virtual gate 100; and the twenty-fourth electrode serves as the Q4 gate 104. The Q3 gate and the Q4 gate are integrally formed. In addition, DUMMY4 includes the first electrode in the Latch1 cell, and DUMMY6 includes the tenth electrode in the Latch1 cell. The first and second electrodes are also virtual gates 100.

[0214] (3) Forming a trench contact layer (TCN) pattern.

[0215] The method for forming the trench contact layer pattern is described in the preparation method of the latching unit, and will not be repeated here.

[0216] In the Buffer1 cell, the TCN pattern includes the fifteenth contact bar 215 to the twentieth contact bar 220. In the Y direction, the six contact bars are respectively disposed on both sides of the corresponding gate and cover the source or drain region at their respective locations to provide a current transport path in the vertical direction. Each contact bar can be a strip pattern extending along the X direction. As shown in Figure 9B: the fifteenth contact bar 215 serves as the source of Q4; the sixteenth contact bar 216 serves as the drain of Q4; the seventeenth contact bar 217 can be connected to the drain of Q4 through the upper pattern; the eighteenth contact bar 218 serves as the source of Q3; the nineteenth contact bar 219 serves as the drain of Q3; and the twentieth contact bar 220 can be connected to the drain of Q3 through the upper pattern.

[0217] The twentieth contact bar 220 and the seventeenth contact bar 217 mentioned above can be used as virtual electrodes. They do not have the function of the source or drain of a MOS transistor, but they can be used for connection.

[0218] (4) Forming a gate contact layer (GCN) pattern.

[0219] The method for forming the gate contact layer pattern is described in the latch cell fabrication method, and will not be repeated here.

[0220] In the Buffer1 cell, the gate contact layer pattern may include five gate contact electrodes, from the seventh gate contact electrode 307 to the eleventh gate contact electrode 311. Each gate contact electrode may be a strip pattern extending along the Y direction. Specifically: the middle of the seventh gate contact electrode 307 overlaps with the virtual gate 100 at the DUMMY3 position, and its two ends are connected to the drain of Q3 and the twentieth contact strip 220, respectively; the middle of the eighth gate contact electrode 308 overlaps with the virtual gate 100 at the DUMMY4 position, and its two ends are connected to the source of Q3 and the source of Q12, respectively; the middle of the ninth gate contact electrode 309 overlaps with the virtual gate 100 at the DUMMY6 position, and its two ends are connected to the source of Q4 and the source of Q9, respectively; the middle of the tenth gate contact electrode 310 overlaps with the virtual gate 100 at the DUMMY5 position, and its two ends are connected to the drain of Q4 and the seventeenth contact strip 217, respectively; the middle of the eleventh gate contact electrode 311 overlaps with the gate 104 of Q4. The eleventh gate contact electrode 311 and the first gate contact electrode 301 can be aligned in the X direction (their X coordinate ranges at least partially overlap) to facilitate the routing of the subsequently formed metal layer.

[0221] (5) Form the first contact hole (V0) pattern.

[0222] The method for forming the first contact hole pattern is described in the preparation method of the latching unit, and will not be repeated here, as shown in Figure 9D.

[0223] In the Buffer1 unit, the multiple vias on the second insulating layer may include vias seventeen through nineteen through holes V17 to V19. For example, please refer to Figures 9C and 9D simultaneously, where: the second insulating layer at the location of via seventeen through hole V17 is removed, exposing the surface of the eleventh gate contact electrode 311. Vias seventeen through hole V17 and twelfth through hole V12 can be aligned in the Y direction. The second insulating layer at the location of via eighteen through hole V18 is removed, exposing the surface of the seventeenth contact strip 217. The second insulating layer at the location of via nineteen through hole V19 is removed, exposing the surface of the twentieth contact strip 220.

[0224] (6) Form the pattern of the first metal layer (M1).

[0225] The method for forming the pattern of the first metal layer is described in the preparation method of the latching unit, and will not be repeated here. As shown in Figure 9F, Figure 9E is a schematic diagram of the first metal layer in Figure 9F.

[0226] In the Buffer1 cell, the pattern of the first metal layer may include a power connection electrode (also called a power line) VCC, a ground connection electrode (also called a ground line) VSSX, a twelfth connection electrode 412, and a thirteenth connection electrode 413. Specifically: the twelfth connection electrode 412 is connected to the gate contact electrode 311 through the seventeenth via V17 and is configured as the clkout input electrode (i.e., input terminal) of the CMOS inverter formed by Q3 and Q4 connections. The first end of the thirteenth connection electrode 413 is connected to the seventeenth contact layer 217 through the eighteenth via V18. The second end is connected to the twentieth contact layer 220 through the nineteenth via V19 and is configured as the clk output electrode of the CMOS inverter formed by Q3 and Q4 connections, thus serving as the output terminal of the CMOS inverter.

[0227] In the latch row composed of Buffer2 and Latch2 cells, please refer to the Buffer2 cell in the lower left corner of Figure 10A. Since the PMOS in Buffer2 cell is Q5 and the NMOS is Q6, the CMOS input terminal formed by the connection of Q5 and Q6 is used to receive clk, and the output terminal is used to output clkb. The twelfth connection electrode 412 can serve as the clk input electrode of the CMOS inverter, and the thirteenth connection electrode 413 can serve as the clkb output electrode, which is the output terminal of the CMOS inverter. In the exemplary embodiment, the structure of the first metal layer and the layers below the Buffer1 and Buffer2 cells can be mirror-symmetrical about the boundary line along the Y direction, and other layers can have some differences. The latch rows of Buffer1 cell + Latch1 cell combination and Buffer2 cell + Latch2 cell combination are described together below to describe the subsequent process of Buffer1 cell and Buffer2 cell.

[0228] (7) Form the second contact hole (V1) pattern.

[0229] The method for forming the second contact hole pattern is described in the preparation method of the latching unit, and will not be repeated here, as shown in Figure 10A.

[0230] In the Buffer1 unit, the third insulating layer includes vias 27 to 28, wherein: the third insulating layer at the location of via 27 V27 is removed, exposing the surface of the 13th connecting electrode 413. The third insulating layer at the location of via 28 V28 is removed, exposing the surface of the 12th connecting electrode 412.

[0231] In the Buffer2 unit, the third insulating layer includes vias 27 to 28. The third insulating layer at the location of via 27 V27' is removed, exposing the surface of the 13th connecting electrode 413. The third insulating layer at the location of via 28 V28' is removed, exposing the surface of the 12th connecting electrode 412.

[0232] In an exemplary embodiment, as shown in Figures 10A to 10E, the 27th via V27' in the Buffer2 cell is closer to the NMOS region and further away from the PMOS region than the 27th via V27 in the Buffer1 cell. The 13th connection electrode 413 overlapping with the 27th via V27' in the Buffer2 cell is used as the clkb output electrode and needs to be connected to the CLKB transmission line 503 in the Latch2 cell through the 27th via V27'; while the 13th connection electrode 413 overlapping with the 27th via V27 in the Buffer1 cell is used as the clk output electrode and needs to be connected to the CLK transmission line 502 in the Latch1 cell through the 27th via V27. As shown, the 27th via V27' in the Buffer2 cell and the CLKB transmission line 503 in the Latch2 cell can be aligned in the X direction (their X-axis coordinates at least partially overlap).

[0233] Similarly, the 28th via V28' in Buffer2 is closer to the PMOS region and further away from the NMOS region than the 28th via V28 in Buffer1. The 12th connection electrode 412 overlapping with the 28th via V28' in Buffer2 is used as the clk input electrode and needs to be connected to the CLK transmission line 502 in Latch2 through the 28th via V28'; while the 12th connection electrode 412 overlapping with the 28th via V28 in Buffer1 is used as the clkout input electrode and needs to be connected to the CLKOUT connection line of the third metal layer of this unit through the third contact hole (see Figure 10E). As shown, the 28th via V28' in Buffer2 and the CLK transmission line 502 in Latch2 can be aligned in the X direction.

[0234] (8) Form the pattern of the second metal layer (M2).

[0235] The method for forming the pattern of the second metal layer is described in the fabrication method of the latching unit, and will not be repeated here, as shown in Figure 10C. Figure 10B is a schematic diagram of the second metal layer in Figure 10C.

[0236] As shown in Figure 10C, the pattern of the second metal layer in Buffer1 includes the CLKOUT lead-in line 505 and the CLK lead-out line 506. Specifically: The CLKOUT lead-in line 505 can be connected to the twelfth connection electrode 412 through the twenty-eighth via V28. The CLKOUT lead-in line 505 can introduce the clkout signal output from the first-stage clock circuit to the gates of Q3 and Q4 in Buffer1 as the input clock signal for the first-stage clock circuit. The CLKOUT lead-in line 505 and the CLKB transmission line 503 in Latch1 can be aligned in the X direction. The CLK lead-out line 506 can be integrally formed with the CLK transmission line 502 of Latch1. The CLK lead-out line 506 is connected to the thirteenth connection electrode 413 through the twenty-seventh via V27, and can transmit the clk signal output from the CMOS inverter of Buffer1 to the CLK transmission line 502.

[0237] In the Buffer2 cell, in an exemplary embodiment, as shown in FIG10C, the pattern of the second metal layer of the Buffer2 cell includes the CLK lead-in line 508 and the CLKB lead-out line 507 of the Buffer2 cell. Wherein:

[0238] The CLK input line 508 can be integrally formed with the CLK transmission line 502 of the Latch2 cell. The CLK input line 508 is connected to the twelfth connection electrode 412 through the twenty-eighth via V28', which can introduce the clk signal output from the CMOS inverter of the Buffer1 cell to the input terminals of the CMOS inverter in the Buffer1 cell, namely the gates of Q3 and Q4.

[0239] The CLKB lead 507 can be integrally formed with the CLKB transmission line 503 of the Latch1 cell. The CLKB lead 507 is connected to the thirteenth connection electrode 413 through the twenty-seventh via V27', and can transmit the clkb signal output from the CMOS inverter of the Buffer2 cell to the CLKB transmission line 503.

[0240] Both the CLKOUT lead-in line and the CLK lead-out line in the Buffer1 unit and the Buffer2 unit can be bar patterns extending along the Y direction.

[0241] Figure 10C shows a schematic diagram of the B1L1 latch line and B2L2 latch line superimposed from the substrate to the second metal layer.

[0242] (9) Form the third contact hole (V2) pattern.

[0243] The method for forming the third contact hole pattern is described in the preparation method of the latching unit, and will not be repeated here, as shown in Figure 10D.

[0244] In Buffer1, the contact holes on the fourth insulating layer include the thirty-first via V31. The fourth insulating layer at the location of the thirty-first via V31 is removed, exposing the surface of the CLKOUT lead-in line 505. The third contact hole may not be provided in Buffer2.

[0245] (10) Form the pattern of the third metal layer (M3).

[0246] The method for forming the pattern of the third metal layer is described in the fabrication method of the latching unit and will not be repeated here, as shown in Figure 10E. For ease of viewing, Figure 10E only shows the pattern of the second metal layer, the third contact hole, and part of the second contact hole.

[0247] In Buffer1, the pattern of the third metal layer may include the CLKOUT connection line 603 of the multiplexer. The CLKOUT connection line 603 can be a strip pattern extending along the X direction. The CLKOUT connection line 603 is connected to the CLKOUT lead-in line 505 through the thirty-first via V31, and is used to transmit the clkout signal output from the first-level clock unit to the input terminal of the CMOS in Buffer1. If there are other Buffer1 units with other latch groups on the side of Buffer1 away from the fill row, the CLKOUT connection line 603 can pass through the Buffer1 unit. If there are no other Buffer1 units with other latch groups on the side of Buffer1 away from the latch row, the CLKOUT connection line 603 can end at the thirty-first via V31 in the Buffer1 unit. If there are other Buffer1 units on the side of Buffer2 away from the Decap unit, the Buffer2 unit has a CLKOUT connection line 603 on the third metal layer to transmit clkout. If there are no other Buffer1 units, the third metal layer pattern is not required.

[0248] Figures 10A to 10E above show the case where the latch row of Latch 1 unit of Buffer 1 is on top, and the latch row composed of Buffer 2 unit and Latch 2 unit is on the bottom. In multiplexed latches, there is also a case where the B1L1 latch row is on the bottom and the B2L2 unit is on top, as shown in Figures 11A to 11E. The basic structure of Buffer 1 unit and Buffer 2 unit can remain unchanged. However, if these two latch rows are considered as a whole, the wiring can be adjusted.

[0249] In the multiplexer, when the primary clock unit and the Latch2 unit are combined, the structures of the primary clock unit and the Buffer2 unit in the first metal layer and below can be basically the same, except that Q5 needs to be replaced with Q1 and Q6 needs to be replaced with Q2. As shown in Figures 12A and 12B, the first metal layer pattern of the primary clock unit includes a twelfth connecting electrode 412 and a thirteenth connecting electrode 413. The input clock signal clkin of the primary clock circuit can be transmitted from the clk signal input terminal of the multiplexer to the twelfth connecting electrode 412. The thirteenth connecting electrode 413 extends in the X direction and is used to transmit the clkout signal output by the primary clock unit to the CLKOUT connecting line 603.

[0250] In the first-level clock cell, when forming the third contact hole (V2) pattern, a twenty-ninth via V29 and a thirtieth via V30 overlapping with the thirteenth connection electrode 413 can be formed. These two vias are located in the PMOS region and the NMOS region, respectively, as shown in Figure 12B. When forming the second metal layer (M2) pattern, a first CLKOUT lead 510 and a second CLKOUT lead 509 can be formed. The first CLKOUT lead 510 is connected to the thirteenth connection electrode 413 through the twenty-ninth via V29, and the second CLKOUT lead 509 is connected to the thirteenth connection electrode 413 through the thirtieth via V30. As shown in Figure 12C, both the first CLKOUT lead-out line 510 and the second CLKOUT lead-out line 509 are used to bring out the clkout signal. One end of the first CLKOUT lead-out line 510 is connected to the twenty-ninth via V29, and the other end extends along the Y direction to a position where it can intersect with the CLKOUT connection line 603. One end of the second CLKOUT lead-out line 509 is connected to the thirtieth via V30, and the other end also extends along the Y direction to a position where it can intersect with the CLKOUT connection line 603.

[0251] In the primary clock unit, when forming the fourth contact hole (V2) pattern, the thirty-second via V32 and the thirty-third via V33 connected to the CLKOUT connection line 603 can be formed, as shown in Figure 12B.

[0252] In the first-level clock unit, when forming the third metal layer (M3) pattern, two CLKOUT connection lines 603 can be formed. The first CLKOUT connection line 603 is connected to the first CLKOUT lead 510 through the thirty-third via V33, transmitting the clkout signal to the Buffer1 unit on the side away from the Decap unit. The second CLKOUT connection line 603 is connected to the second CLKOUT lead 509 through the thirty-second via V32, transmitting the clkout signal to the Buffer1 unit on the side closer to the Decap unit, as shown in Figure 12C. The CLKB connection line 602 and CLB connection line 601 in the figure transmit the clk and clkb signals output from the upper Buffer1 and Buffer2 units to the Latch2 unit of this latch row, without needing to penetrate the Latch2 unit. In another embodiment, the first-level clock unit can also be combined with the Latch1 unit in one latch row. The relevant structure can be seen in Figures 12A to 12c, and will not be described again here.

[0253] In the above exemplary embodiments, each metal layer may be made of a metallic material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo), or an alloy of the above metals.

[0254] The preparation process of this exemplary embodiment can be realized using currently mature preparation equipment, is well compatible with existing preparation processes, is simple to implement, has high production efficiency, low production cost, and high yield.

[0255] The accompanying drawings in this disclosure only illustrate the structures relevant to this disclosure; other structures can be referenced to common designs. Unless otherwise specified, embodiments of this disclosure and features thereof can be combined to obtain new embodiments.

[0256] Those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions disclosed herein without departing from the spirit and scope of the technical solutions disclosed herein, and all such modifications and substitutions should be covered within the scope of the claims of this disclosure.

Claims

1. A latching unit, comprising a substrate and eight MOS transistors, wherein the substrate includes an NMOS region and a PMOS region, and the direction from the NMOS region to the PMOS region is a first direction; four PMOS transistors Q12, Q11, Q7 and Q13 are sequentially arranged along a second direction within the PMOS region, and four NMOS transistors Q9, Q10, Q8 and Q14 are sequentially arranged along the second direction within the NMOS region, the second direction intersecting the first direction; wherein: Q7 and Q8 are connected to form a transmission gate, Q9, Q10, Q11, and Q12 are connected to form a clocked inverter, and Q13 and Q14 are connected to form a CMOS inverter. Q12 and Q9, Q11 and Q8, and Q13 and Q14 are respectively positioned opposite each other, and the gates of the two oppositely positioned MOS transistors are interconnected. A filling structure is formed in the PMOS region opposite to Q10 and in the NMOS region opposite to Q7. A filling structure is also formed between Q7 and Q13 and between Q8 and Q14. The transmission gate, based on clk and clkb, either blocks the input 1-bit data d or outputs it to the input of the CMOS inverter; the CMOS inverter inverts d, resulting in an inverted signal. The output is sent to the input of a clock-controlled inverter, which uses clk and clkb to... Block or The inverted signal is output to the input of the CMOS inverter; where clk and clkb are both clock signals of the input latch unit, and clkb is the inverted signal of clk.

2. The latching unit as described in claim 1, wherein: The gate of each of the eight MOS transistors extends along a first direction. The source and drain of the MOS transistor are formed on both sides of the gate. The source to drain of the MOS transistor are arranged sequentially in a second direction. Among them, the source of Q7 also serves as the drain of Q11, the drain of Q9 also serves as the source of Q10, and the source of Q8 also serves as the drain of Q10.

3. The latching unit as described in claim 2, wherein: A first insulating layer and a polycrystalline silicon layer are sequentially formed on the substrate. The polycrystalline silicon layer includes a plurality of strip-shaped electrodes extending along a first direction, wherein: In the PMOS region, nine electrodes are arranged sequentially at intervals along the second direction, with the second electrode being the Q12 gate, the fourth electrode being the Q11 gate, the fifth electrode being the Q7 gate, and the eighth electrode being the Q13 gate. In the NMOS region, nine electrodes are arranged sequentially at intervals along the second direction, with the second electrode being the Q9 gate, the third electrode being the Q10 gate, the fourth electrode being the Q8 gate, and the eighth electrode being the Q14 gate. The other electrodes in both the PMOS and NMOS regions are dummy gates. The nine electrodes in the PMOS region and the nine electrodes in the NMOS region are arranged one-to-one. The gates of Q12 and Q9 are integrally formed, the gates of Q11 and Q8 are integrally formed, and the gates of Q13 and Q14 are integrally formed.

4. The latching unit as described in claim 3, wherein: A gate contact layer is formed on the polysilicon layer, the gate contact layer including a plurality of gate contact electrodes extending along a second direction, the gate contact electrodes including: The first gate contact electrode that overlaps with the gate of Q7; the second gate contact electrode that overlaps with the gate of Q11; the third gate contact electrode that overlaps with the gate of Q12; the fourth gate contact electrode that overlaps with the gate of Q10; the fifth gate contact electrode that overlaps with the gate of Q14; and the sixth gate contact electrode that overlaps with the dummy gate and connects the drain of Q12 to the source of Q11; The second, third, and sixth gate contacts are located in the PMOS region. The second gate contact is located on the side of the drain of Q11 near the NMOS region, and the third gate contact is located on the side of the source of Q12 near the NMOS region. The second and third gate contacts are aligned in the second direction. The fourth gate contact is located on the side of the source and drain of Q10 near the PMOS region in the NMOS region. The first and fifth gate contacts are aligned in the second direction and located between the fourth and second gate contacts.

5. The latching unit as described in claim 4, wherein: A second insulating layer and a first metal layer are formed on the gate contact layer. The second insulating layer has a plurality of first contact holes formed thereon. The first metal layer includes: A power connection electrode is located on the side of the PMOS region away from the NMOS region, and the power connection electrode is connected to the source of Q12 and the source of Q13 through a first contact hole; A ground connection electrode is located on the side of the NMOS region away from the PMOS region, and the ground connection electrode is connected to the source of Q9 and the source of Q14 through a first contact hole; The first connection electrode is connected to the gate of Q9 and the gate of Q12 through a first contact hole and a third gate contact electrode, and is used as the input terminal of the clock-controlled inverter. The second connection electrode is connected to the gate of Q8 and the gate of Q11 through the first contact hole and the second gate contact electrode, and is used to receive clk. The third connection electrode has a first end connected to the gate of Q7 through a first contact hole and a first gate contact electrode, and a second end connected to the gate of Q10 through a first contact hole and a fourth gate contact electrode, for receiving clkb; The fourth connecting electrode has its first end connected to the source of Q7 and the drain of Q11 through the first contact hole, and its second end connected to the source of Q8 and the drain of Q10 through the first contact hole. It is used as the output terminal of the transmission gate and the output terminal of the clocked inverter. The fifth connecting electrode, the first end of which is connected to the drain of Q13 through the first contact hole, the second... The terminal is connected to the drain of Q14 through the first contact hole and is used as the output terminal of the CMOS inverter. The sixth connection electrode is connected to the gate of Q13 and the gate of Q14 through the first contact hole and the fifth gate contact electrode, and is used as the input terminal of the CMOS inverter. The seventh connecting electrode has its first end connected to the drain of Q7 through the first contact hole and its second end connected to the drain of Q8 through the first contact hole, serving as the input terminal of the transmission gate.

6. The latching unit as described in claim 5, wherein: The first contact hole, which is connected to the first gate contact electrode, is located between the gates Q7 and Q11 in the second direction; The first contact hole, which is connected to the second gate contact electrode, is located between the Q7 gate and the Q11 gate in the second direction; The first contact hole connected to the third gate contact electrode is located in the second direction between the Q12 gate and the first dummy gate on the side of Q12 away from Q11; The first contact hole, which is connected to the fourth gate contact electrode, is located between the Q10 gate and the Q8 gate in the second direction; The first contact hole connected to the fifth gate contact electrode is located in the second direction between the first pair of virtual gates and the second pair of virtual gates on the side of the Q13 gate near Q7.

7. The latching unit as claimed in claim 5, wherein: The first connecting electrode, the fifth connecting electrode, and the sixth connecting electrode are strip patterns extending along a first direction; the second connecting electrode is a strip pattern extending along a second direction; the third connecting electrode and the seventh connecting electrode are L-shaped, and the fourth connecting electrode is C-shaped. The fourth and seventh connecting electrodes form a rectangular pattern with a notch, the second and third connecting electrodes are located within the rectangular pattern, and the third connecting electrode is located on the side of the second connecting electrode closer to the NMOS region.

8. The latching unit as claimed in claim 7, wherein: A first virtual electrode is also provided between the first pair of virtual gates and the second pair of virtual gates on the side of Q8 gate near Q14, and the middle part of the seventh connecting electrode is also connected to the first virtual electrode through the first contact hole.

9. The latching unit as claimed in claim 5, wherein: A third insulating layer and a second metal layer are formed on top of the first metal layer. The third insulating layer has a plurality of second contact holes. The second metal layer includes: The ON output line, located in the NMOS region, is configured to connect to the first connection electrode and the fifth connection electrode via the second contact hole. The electrodes are connected respectively to connect the input terminal of the clock-controlled inverter and the output terminal of the CMOS inverter, and to connect the output signal of the CMOS inverter. Leading out; The CLK transmission line is configured to connect to the second connection electrode via the second contact hole; The CLKB transmission line is configured to connect to the third connection electrode via a second contact hole; The D transmission line, located in the PMOS region, is configured to be connected to the fourth and sixth connection electrodes respectively through the second contact hole, so as to connect the output of the transmission gate and the output of the clocked inverter to the input of the CMOS inverter. The ON output line, CLKB transmission line, CLK transmission line and D transmission line are arranged sequentially in the first direction, and all of them are strip patterns extending along the second direction.

10. The latching unit as claimed in claim 9, wherein: A fourth insulating layer and a third metal layer are formed on top of the second metal layer. The fourth insulating layer has a plurality of third contact holes. The third metal layer includes: The CLK connection line is configured to connect to the CLK connection line via a third contact hole to introduce clk into the transmission gate and the clocked inverter via the CLK transmission line; The CLKB connection line is configured to connect to the CLKB transmission line via a third contact hole to introduce clkb to the transmission gate and the clocked inverter via the CLKB transmission line; Both the CLK connecting line and the CLKB connecting line are strip patterns extending along the first direction, and are arranged sequentially in the second direction.

11. A multi-bit latch, comprising a first latch group, a second latch group, a fill row, a third latch group, and a fourth latch group arranged sequentially along the X direction on a substrate, each latch group comprising eight latch rows arranged sequentially along the X direction, each latch row comprising one latch unit, wherein: A latch line adjacent to the filling line is also provided with a primary clock unit, which is configured to receive the clock signal clkin and output the inverted signal clkout of clkin; Each latch group has two latch rows in the middle position, each with a secondary clock unit. One secondary clock unit is configured to receive clkout and output the inverted signal clk of clkout, and the other secondary clock unit is configured to receive clk and output the inverted signal clkb of clk. The latch unit is configured to latch and output 1-bit input data based on clk and clkb; The primary clock unit and the latch units in the same latch row are arranged sequentially along the Y direction, and the secondary clock unit and the latch units in the same latch row are also arranged sequentially along the Y direction, with the Y direction intersecting the X direction.

12. The multi-bit latch as claimed in claim 11, wherein: Each latch line is divided into a first zone and a second zone arranged in the Y direction; The latching units are all located in the second zone of the latching row. The input signals b, clk, clkb of all latching units are input from the side closer to the first zone, and the latched 1-bit data is output from the side farther away from the first zone. The primary clock unit and the secondary clock unit are both located in the first area of ​​the latch line; except for the latch line with the primary clock unit and the secondary clock unit, the first area of ​​other latch lines is provided with a filling unit.

13. The multi-bit latch as claimed in claim 11, wherein: The width W of each latch line in the X direction is equal, and the length L of each latch line in the Y direction is equal, with 0.486μm≤W≤0.594μm and 1.1664μm≤L≤1.4256μm; The filling row uses a Decap cell, which has a width of W in the X direction and a length of L in the Y direction.

14. The multi-bit latch as claimed in claim 11, wherein: The latching unit is a latching unit as described in any one of claims 1 to 10; In each latch row, the substrate of the first and second regions is formed with PMOS and NMOS regions. In any two adjacent latch rows, the NMOS and PMOS regions of one latch row are arranged sequentially in the X direction, and the first direction of the latch cells in this latch row is the same as the X direction. This is called the first latch cell. The NMOS and PMOS regions of the other latch row are arranged sequentially in the opposite direction of the X direction, and the first direction of the latch cells in this latch row is the same as the opposite direction of the X direction. This is called the second latch cell. The second direction of the first latch unit and the second latch unit is the same as the Y direction. The transistor positions of the first latch unit and the second latch unit in two adjacent latch rows are mirror symmetrical with respect to the boundary line extending along the Y direction of the two latch rows.

15. The multi-bit latch as described in claim 14, wherein: Both secondary clock units include a PMOS located in the PMOS region of the first region of the latch line and an NMOS located in the NMOS region of the first region of the latch line. The NMOS region and PMOS region of one of the secondary clock units are arranged sequentially in the X direction, and it is called the first secondary clock unit. Another secondary clock unit The NMOS and PMOS regions are arranged sequentially in the opposite direction of the X direction, and are called the second-level clock unit. The first secondary clock unit has a PMOS transistor Q3 as the third transistor and an NMOS transistor Q4 as the fourth transistor. Q3 and Q4 are connected to form a CMOS inverter to receive clkout and output clk. The second secondary clock unit has a PMOS transistor Q5 as the fifth transistor and an NMOS transistor Q6 as the sixth transistor. Q5 and Q6 are connected to form a CMOS inverter to receive clk and output clkb.

16. The multi-bit latch as claimed in claim 15, wherein: In a direction perpendicular to the substrate, the multi-bit latch includes a polysilicon layer and a source and drain region of a MOS, a trench contact layer, a gate contact layer, a first contact hole, a first metal layer, a second contact hole, a second metal layer, a third contact hole, and a third metal layer, which are sequentially formed on the substrate. The clock signal lines between different latch lines are set in the third metal layer. The clock signal lines transmitted between the first clock unit and the latch unit, and between the second clock unit and the latch unit in the same latch line are set in the second metal layer. The interconnections between the transistors inside the first clock unit, the second clock unit, and the latch unit are set in the first metal layer and the second metal layer, or set in the gate contact layer, the first metal layer, and the second metal layer. The latching units in the two latching rows adjacent to the filling row are either the first latching unit or the second latching unit.

17. The multi-bit latch as claimed in claim 15, wherein: A first insulating layer and a polysilicon layer are sequentially formed on the substrate of the secondary clock unit, the polysilicon layer comprising: Three electrodes extend along the X direction in the PMOS region and are arranged sequentially and spaced apart in the Y direction. The third electrode serves as the PMOS gate, and the other two electrodes serve as dummy gates. Three electrodes extend along the X direction in the NMOS region and are arranged sequentially and spaced apart in the Y direction. The third electrode serves as the NMOS gate, and the other two electrodes serve as dummy gates. The three electrodes in the PMOS region and the three electrodes in the NMOS region are arranged opposite each other in the Y direction, and the PMOS gate and the NMOS gate are integrally formed.

18. The multi-bit latch as claimed in claim 17, wherein: In the secondary clock unit, in the Y direction, a PMOS drain and a PMOS source are formed on both sides of the PMOS gate, and an NMOS drain and an NMOS source are formed on both sides of the NMOS gate, and the PMOS drain and PMOS source, as well as the NMOS drain and NMOS source, are arranged sequentially in the Y direction. In the secondary clock unit, in the Y direction, the first virtual gate on the side of the PMOS gate furthest from the latch cell. A second virtual electrode is provided between the first virtual gate and the second virtual gate, and a third virtual electrode is provided between the first virtual gate and the second virtual gate on the side of the NMOS gate away from the latch cell.

19. The multi-bit latch as claimed in claim 18, wherein: In the secondary clock unit, a gate contact layer is formed on the polysilicon layer. The gate contact layer includes a plurality of gate contact electrodes extending along the Y direction. The gate contact electrodes include: The seventh gate contact electrode is connected to the virtual gate and connects the PMOS drain and the second virtual electrode; the eighth gate contact electrode is connected to the virtual gate and connects the PMOS source and the Q12 source; the ninth gate contact electrode is connected to the virtual gate and connects the NMOS source and the Q9 source; the tenth gate contact electrode is connected to the virtual gate and connects the third virtual electrode and the NMOS drain; and the eleventh gate contact electrode is connected to the NMOS gate and the PMOS gate. The seventh and eighth gate contacts are located in the PMOS region, while the ninth and tenth gate contacts are located in the NMOS region. In the X direction, the eleventh gate contact is located between the seventh and tenth gate contacts, and also between the eighth and ninth gate contacts.

20. The multi-bit latch as claimed in claim 19, wherein: In the secondary clock unit, a second insulating layer and a first metal layer are formed on the gate contact layer. The second insulating layer forms a plurality of first contact holes, and the first metal layer includes: A power connection electrode located on the side of the PMOS region away from the NMOS region, the power connection electrode being connected to the power connection electrode in the latch cell of the same latch row; A ground connection electrode located on the side of the NMOS region away from the PMOS region, the ground connection electrode being connected to the ground connection electrode in the latch cell of the same latch row; The twelfth connection electrode is connected to the PMOS gate and the NMOS gate through the first contact hole and the eleventh gate contact electrode. The twelfth connection electrode is used as the input terminal of the CMOS inverter in the secondary clock unit. The thirteenth connection electrode is connected to the second and third virtual electrodes through the first contact hole. The thirteenth connection electrode is used as the output terminal of the CMOS inverter in the secondary clock unit. The first contact hole connected to the eleventh gate contact electrode is located in the Y direction between the PMOS gate and the first virtual gate on the side of the PMOS gate away from the latch cell; the twelfth and thirteenth connection electrodes are strip patterns extending in the X direction, and the twelfth connection electrode is located between the thirteenth connection electrode and the latch cell in the same latch row.

21. The multi-bit latch as claimed in claim 20, wherein: In the secondary clock unit, a third insulating layer and a second metal layer are formed on top of the first metal layer, and the third insulating layer has a plurality of second contact holes; wherein: The second metal layer in the first secondary clock unit includes: a CLKOUT lead-in line configured to be connected to the twelfth connection electrode through a second contact hole; and a CLK lead-out line configured to be connected to the thirteenth connection electrode through a second contact hole and connected to the CLK transmission line disposed on the second metal layer in the first latch unit of the same latch row. The second metal layer in the second secondary clock unit includes: a CLK lead-in line configured to be connected to the twelfth connection electrode through a second contact hole and connected to the CLK transmission line disposed on the second metal layer in the second latch cell of the same latch row; and a CLKB lead-out line configured to be connected to the thirteenth connection electrode through a second contact hole and connected to the CLKB transmission line in the latch cell of the same latch row.

22. The multi-bit latch as claimed in claim 21, wherein: In the second-stage clock unit, a fourth insulating layer and a third metal layer are formed on top of the second metal layer. The fourth insulating layer has a plurality of third contact holes, wherein: The third metal layer in the first secondary clock unit includes: a CLKOUT connection line extending into the first-level clock unit along the X direction or the opposite direction of the X direction, configured to connect to the CLKOUT lead-in line through a third contact hole to transmit clkout to the Q3 gate and the Q4 gate; When the second secondary clock unit is located on the side of the first secondary clock unit away from the fill row, the third metal layer of the second secondary clock unit is provided with the CLKOUT connection line.

23. The multi-bit latch as described in claim 22, wherein: The primary clock unit includes a first transistor Q1 located in the PMOS region of the first region of the latch line and a second transistor Q2 located in the NMOS region of the first region of the latch line; Q1 is a PMOS and Q2 is an NMOS. The CMOS inverter formed by connecting Q1 and Q2 is configured to receive clkin, output clkout and transmit to the CLKOUT connection line.

24. The multi-bit latch as claimed in claim 23, wherein: The CLKOUT connection line is disposed on the third metal layer of multiple latch units, including a first segment extending from the first-level clock unit along the X direction to the first-level second-level clock unit of the fourth latch group, and a second segment extending from the first-level clock unit along the opposite direction of the X direction to the first-level second-level clock unit of the first latch group. The latching unit is the latching unit as described in claim 10; The clk output by the first secondary clock unit is transmitted to the CLK connection line of other latch units in the latch group via the CLK lead-out line and the CLK transmission line and CLK connection line of the first latch unit in the same latch row. Then, it is transmitted to the CLK lead-in line of the second secondary clock unit in the latch group via the CLK transmission line of the second latch unit located in the same latch row as the second secondary clock unit. The clkb output from the second and second level clock units is transmitted to the CLKB connection lines of other latch units in the same latch group via the CLKB lead-out line and the CLKB transmission line and CLKB connection line of the latch unit in the same latch row. The CLK connection lines of all latch cells in the same latch group are connected sequentially, and the CLKB connection lines of all latch cells in the same latch group are connected sequentially.

25. An integrated circuit comprising a multi-bit latch as described in any one of claims 11 to 24.

26. A method for fabricating a multi-bit latch, comprising: One primary clock unit, eight secondary clock units, and 32 latch units are formed on a substrate. Specifically, on a plane parallel to the substrate, the multi-bit latch includes a first latch group, a second latch group, a fill row, a third latch group, and a fourth latch group sequentially arranged along the X direction on the substrate. Each latch group includes eight latch rows sequentially arranged along the X direction, and each latch row includes one latch unit. A latch row adjacent to the fill row also has a primary clock unit configured to receive a clock signal clkin and output an inverted signal clkout from clkin. Each of the two latch rows in the middle of a latch group is further provided with a secondary clock unit. One secondary clock unit is configured to receive clkout and output the inverted signal clk of clkout, and the other secondary clock unit is configured to receive clk and output the inverted signal clkb of clk. The latch unit is configured to latch and output the input 1-bit data based on clk and clkb. The primary clock unit and the latch units in the same latch row, as well as the secondary clock unit and the latch units in the same latch row, are arranged sequentially along the Y direction, with the Y direction intersecting the X direction.

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