Circuit unit and manufacturing method therefor, light-emitting device, and display panel

Abstract

The present disclosure provides a circuit unit and a manufacturing method therefor, a light-emitting device, and a display panel. The circuit unit comprises a first planarization layer, a first pad, a first passivation layer, and a circuit layer. The first pad is located on one side of the first planarization layer. Via holes running through the first planarization layer in the thickness direction are formed in the first planarization layer. The first passivation layer is located on the side of the first planarization layer away from the first pad. First openings in one-to-one correspondence with the via holes are formed in the first passivation layer. The circuit layer is located on the side of the first passivation layer away from the first pad. A circuit in the circuit layer is electrically connected to the first pad by means of the first openings of the first passivation layer and the via holes of the first planarization layer. The first pad is connected to a signal source device. The maintenance difficulty and the maintenance cost of MLED display panels can be reduced.

Description

Circuit unit and manufacturing method thereof, light-emitting device and display panel Technical Field

[0001] The present disclosure relates to the technical field of electronic devices, and in particular to a circuit unit and a manufacturing method thereof, a light-emitting device and a display panel. Background Art

[0002] Mini LEDs (Mini Light Emitting Diodes) and Micro LEDs (Micro LEDs) are collectively referred to as MLEDs. Display panels using MLED chips as pixel units directly emit light through the MLED chips to display images. Compared to liquid crystal display (LCD) panels, they improve contrast and reduce panel thickness. Compared to organic light emitting diode (OLED) display panels, they can significantly extend the display panel's service life.

[0003] Currently, MLED display panels utilize a glass-based thin-film transistor (TFT) driver backplane for active-drive display. The pixel circuits in the TFT driver backplane include multiple thin-film transistors and capacitors. As the resolution of MLED display panels increases, the number of MLED chips in a single MLED display panel increases significantly, leading to a greater number of pixel circuits in the TFT driver backplane. This increases the risk of damage to the TFT driver backplane due to pixel circuit damage, leading to higher repair costs for MLED display panels.

[0004] Summary of the Invention

[0005] The present disclosure provides a circuit unit and a manufacturing method thereof, a light-emitting device and a display panel, so as to reduce the maintenance cost of the display panel.

[0006] In a first aspect of the present disclosure, a circuit unit is provided, comprising:

[0007] First flat layer;

[0008] A first pad is located on one side of the first flat layer; the first flat layer is provided with a via hole penetrating the first flat layer along a thickness direction; the via hole at least partially overlaps with the first pad;

[0009] The first passivation layer is located on a side of the first flat layer facing away from the first pad; the first passivation layer has first openings extending through the first passivation layer in a thickness direction and corresponding to the via holes; the orthographic projections of the first openings on the first flat layer all fall within the corresponding via holes; the first passivation layer has a protrusion that protrudes inward from the edge of the via hole, and the protrusion does not directly cover the wall surface of the via hole;

[0010] The circuit layer is located on the side of the first passivation layer away from the first pad; the circuit in the circuit layer is electrically connected to the first pad through the first opening of the first passivation layer and the via hole of the first flat layer; the first pad is used to connect the signal source device.

[0011] In the circuit unit provided by the present disclosure, the first flat layer includes a first surface close to the first pad and a second surface close to the first passivation layer; the angle between the hole wall and the first surface is greater than 80°.

[0012] In the circuit unit provided by the present disclosure, on the first surface, the aperture of the via hole is 5 μm to 30 μm; on the second surface, the aperture of the via hole is 4 μm to 30 μm.

[0013] In the circuit unit provided by the present disclosure, the thickness of the first planar layer is 2 μm to 10 μm.

[0014] In the circuit unit provided by the present disclosure, the circuit in the circuit layer includes a fan-out trace; the fan-out trace covers the protrusion and is attached to the side wall of the first opening of the first passivation layer and the hole wall of the via hole of the first flat layer, extending to be electrically connected to the first pad.

[0015] In the circuit unit provided by the present disclosure, the thickness of the fan-out trace attached to the hole wall of the via hole in the first flat layer is greater than the width of the protrusion protruding toward the inside of the via hole relative to the edge of the via hole.

[0016] In the circuit unit provided by the present disclosure, the circuit layer includes at least one thin film transistor; the orthographic projection of the active layer of the thin film transistor on the first planar layer is located in a region outside the via hole.

[0017] In the circuit unit provided by the present disclosure, the circuit layer further includes at least one capacitor; the orthographic projection of the capacitor on the first flat layer is located in an area outside the via hole.

[0018] In the circuit unit provided by the present disclosure, the circuit layer also includes connecting wires; the connecting wires are used for connecting between thin film transistors and for connecting between capacitors and thin film transistors; the orthographic projection of the connecting wires on the first flat layer is located in an area outside the via hole.

[0019] In the circuit unit provided by the present disclosure, the circuit unit includes a plurality of first pads; the first flat layer includes a plurality of vias; one first pad corresponds to one via; and the via at least partially overlaps the corresponding first pad.

[0020] In the circuit unit provided by the present disclosure, a surface of the first pad facing the first passivation layer has a plurality of recessed structures.

[0021] In the circuit unit provided by the present disclosure, a surface of the first pad facing the first passivation layer has a plurality of protruding structures.

[0022] In the circuit unit provided by the present disclosure, the circuit unit also includes multiple second pads; the second pads are located on the side of the circuit layer away from the first pads; the second pads are electrically connected to the circuit layer; and the second pads are used to connect electrical devices.

[0023] In the circuit unit provided by the present disclosure, the material of the first planar layer is an organic material; the material of the first passivation layer is an inorganic material.

[0024] In the circuit unit provided by the present disclosure, the material of the first planar layer is polyimide; the material of the first passivation layer is silicon oxide.

[0025] According to a second aspect of the present disclosure, a light-emitting device is provided, comprising a light-emitting unit and any one of the above-mentioned circuit units; the light-emitting unit is electrically connected to the circuit unit.

[0026] In the light-emitting device provided by the present disclosure, the light-emitting unit is a Mini LED chip or a Micro LED chip.

[0027] According to a third aspect of the present disclosure, a display panel is provided, comprising a driving backplane and any one of the above-mentioned light-emitting devices; the light-emitting device is electrically connected to the driving backplane.

[0028] A fourth aspect of the present disclosure provides a method for manufacturing a circuit unit, comprising:

[0029] Making the first pad;

[0030] Covering the first pad with a first material to form a first flat layer;

[0031] Depositing a second material on a side of the first planar layer away from the first pad to form a first passivation layer;

[0032] dry etching the first passivation layer using a second etching gas to form a first opening exposing the first planar layer;

[0033] Using the first passivation layer as a hard mask, a first etching gas is used to dry-etch the first flat layer exposed by the first opening to form a via hole that penetrates the first flat layer and at least partially exposes the first pad; wherein the first material is different from the second material, and the first etching gas selectively etches the first material.

[0034] In the method provided in the present disclosure, dry etching the first passivation layer using a second etching gas to form a first opening exposing the first planar layer specifically includes:

[0035] coating a photoresist layer on a side of the first passivation layer facing away from the first planar layer, and developing the photoresist layer to form a photoresist pattern corresponding to the first opening;

[0036] Using the photoresist layer as a mask, dry-etching the first passivation layer with a second etching gas to form a first opening exposing the first planar layer;

[0037] Using the first passivation layer as a hard mask, dry etching the first planar layer exposed by the first opening using a first etching gas to form a via hole penetrating the first passivation layer and at least partially exposing the first pad specifically includes:

[0038] The photoresist layer is retained, and the first passivation layer is used as a hard mask. The first flat layer exposed by the first opening is dry-etched with a first etching gas to form a via hole that penetrates the first flat layer and at least partially exposes the first pad.

[0039] The beneficial effects of the present disclosure are as follows:

[0040] The present disclosure provides a circuit unit and a manufacturing method thereof, a light-emitting device, and a display panel. The circuit unit includes: a first planar layer, a first pad, a first passivation layer, and a circuit layer. The first pad is located on one side of the first planar layer. The first planar layer has a via extending through the first planar layer along its thickness. The via at least partially overlaps the first pad. The first passivation layer is located on a side of the first planar layer facing away from the first pad. The first passivation layer has first openings extending through the first passivation layer along its thickness and corresponding to the vias. The orthographic projections of the first openings on the first planar layer all fall within the corresponding vias. The first passivation layer has a protrusion that protrudes inward from the edge of the via, and the protrusion does not directly overlap the wall surface of the via. The circuit layer is located on the side of the first passivation layer facing away from the first pad. The circuit in the circuit layer is electrically connected to the first pad via the first opening in the first passivation layer and the via in the first planar layer. The first pad is used to connect to a signal source device. By integrating the pixel circuit into the modular circuit unit, the manufacturing difficulty of the driver backplane is greatly reduced. Moreover, when a pixel circuit fails, only the failed circuit unit can be replaced. The replacement and repair process is simple and easy, thereby avoiding the scrapping of the driver backplane due to the failure of the pixel circuit and reducing the repair difficulty and cost of the MLED display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the following briefly introduces the drawings required for use in the embodiments of the present disclosure. Obviously, the drawings introduced below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0042] FIG1a is a schematic diagram of a cross-sectional structure of a circuit unit according to an embodiment of the present disclosure;

[0043] FIG1b is a schematic diagram of the disassembled structure of the MLED display panel provided in an embodiment of the present disclosure;

[0044] FIG2 is a second schematic diagram of a cross-sectional structure of a circuit unit provided in an embodiment of the present disclosure;

[0045] FIG3 is an equivalent circuit diagram of a pixel circuit provided by an embodiment of the present disclosure;

[0046] FIG4 a is a schematic diagram of a manufacturing process of a circuit unit;

[0047] FIG4 b is a second schematic diagram of a manufacturing process of a circuit unit;

[0048] FIG4c is a third schematic diagram of a manufacturing process of a circuit unit;

[0049] FIG4 d is a microscopic morphology of a via hole in a circuit unit;

[0050] FIG5 is a schematic diagram of a top view of a circuit unit provided in an embodiment of the present disclosure;

[0051] FIG6 a is a schematic diagram of a manufacturing process of a circuit unit according to an embodiment of the present disclosure;

[0052] FIG6 b is a second schematic diagram of the manufacturing process of the circuit unit provided in an embodiment of the present disclosure;

[0053] FIG6 c is a third schematic diagram of the manufacturing process of the circuit unit provided in an embodiment of the present disclosure;

[0054] FIG6 d is a microscopic topography image of a via hole in a circuit unit according to an embodiment of the present disclosure;

[0055] FIG7 is a fourth schematic diagram of the manufacturing process of the circuit unit provided in an embodiment of the present disclosure;

[0056] FIG8a is a third schematic diagram of a cross-sectional structure of a circuit unit provided in an embodiment of the present disclosure;

[0057] FIG8 b is a fourth schematic diagram of a cross-sectional structure of a circuit unit provided in an embodiment of the present disclosure;

[0058] FIG9 is a schematic diagram of a cross-sectional structure of a light-emitting device provided in an embodiment of the present disclosure;

[0059] FIG10 is a schematic diagram of a cross-sectional structure of a display panel provided in an embodiment of the present disclosure;

[0060] FIG11 is a flow chart of a method for manufacturing a circuit unit provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0061] In order to make the above-mentioned purposes, features and advantages of the present disclosure more obvious and easy to understand, the present disclosure will be further described below with reference to the accompanying drawings and examples. However, the example embodiments can be implemented in various forms and should not be understood as being limited to the embodiments set forth herein; on the contrary, these embodiments are provided to make the present disclosure more comprehensive and complete, and to fully convey the concepts of the example embodiments to those skilled in the art. The same figure marks in the figures represent the same or similar structures, and their repeated descriptions will be omitted. The words expressing position and direction described in the present disclosure are all explained using the accompanying drawings as examples, but changes can be made as needed, and all changes are included in the scope of protection of the present disclosure. The drawings of the present disclosure are only used to illustrate relative position relationships and do not represent true proportions.

[0062] Mini LEDs (Mini Light Emitting Diodes) and Micro LEDs (Micro LEDs) are collectively referred to as MLEDs. Display panels using MLED chips as pixel units directly emit light through the MLED chips to display images. Compared to liquid crystal display (LCD) panels, they improve contrast and reduce panel thickness. Compared to organic light emitting diode (OLED) display panels, they can significantly extend the display panel's service life.

[0063] The driving methods of MLED display panels include passive matrix (PM) driving and active matrix (AM) driving. The PM driving method connects the anode (P-electrode) of the MLED chip in each column of the array to the column data line, and connects the cathode (N-electrode) of the MLED chip in each row of the array to the row scan line. When a current signal passes through a specific row and column, the pixel unit at the intersection of the row and column will be lit, and dynamic display can be achieved by scanning row by row. The use of PM driving has problems such as short pixel unit light-emitting time, crosstalk between lines, and high scanning frequency.

[0064] Using the AM drive method, each MLED chip is connected to a separate pixel circuit. The pixel circuit can store the data signal, thereby providing a stable current to the MLED chip within a frame, which is beneficial to improving the brightness of the picture and reducing crosstalk. At present, the MLED display panel can be based on a glass-based thin film transistor (TFT) driving backplane for active drive display. The pixel circuit in the TFT driving backplane includes multiple thin film transistors and capacitors. As the resolution of the MLED display panel increases, the number of MLED chips in a single MLED display panel increases greatly, and thus the number of pixel circuits in the TFT driving backplane also increases. The risk of the TFT driving backplane being scrapped due to a failure of the pixel circuit increases, and the maintenance cost of the display panel is high.

[0065] In view of this, the present disclosure provides a circuit unit, which can reduce the difficulty and cost of repairing a damaged circuit.

[0066] FIG1 a is a schematic diagram of a cross-sectional structure of a circuit unit according to an embodiment of the present disclosure.

[0067] In the embodiment of the present disclosure, as shown in FIG. 1 a , the circuit unit includes a first planar layer 11 , a first pad 12 , a first passivation layer 13 and a circuit layer 14 .

[0068] The first flat layer 11 provides support and bearing, and has a relatively flat surface, facilitating the fabrication of other film layers thereon. The shape of the first flat layer 11 adapts to the shape of the circuit unit, which in turn adapts to the shape of the electrical device bonded to it. In practice, the shape of the first flat layer 11 can be square, rectangular, or circular, among other shapes, without limitation.

[0069] The first pad 12 is located on one side of the first planar layer 11. The first planar layer 11 is provided with a via H extending through the first planar layer 11 along its thickness direction. The via H at least partially overlaps with the first pad 12, thereby at least partially exposing the first pad 12 so that the circuit in the subsequent circuit layer 14 can be connected to the first pad 12 through the via H. In the disclosed embodiment, the thickness direction specifically refers to the direction in which the film layers in the circuit unit are stacked, for example, the direction in which the first pad 12, first planar layer 11, first passivation layer 13, and circuit layer 14 are stacked.

[0070] The first passivation layer 13 is located on the side of the first flat layer 11 away from the first pad 12. The first passivation layer 13 is provided with a first opening K that penetrates the first passivation layer 13 along the thickness direction and corresponds one-to-one to the via H. The orthographic projection of the first opening K on the first flat layer 11 all falls within the corresponding via H, and the first passivation layer 13 does not overlap with the hole wall of the via H. In the embodiment of the present disclosure, the first passivation layer 13 has a protective effect on the first flat layer 11, and can protect the first flat layer 11 when the circuit in the circuit layer 14 is subsequently manufactured, thereby preventing high-temperature processes and etching processes from damaging the structure of the first flat layer 11. The first passivation layer 13 is also used as a hard mask when the via H is opened in the first flat layer 11 to reduce etching deviation, which will be described in detail in the subsequent content.

[0071] Circuit layer 14 is located on the side of first passivation layer 13 facing away from first pad 12. Circuit layer 14 contains circuitry for transmitting drive signals. The circuitry in circuit layer 14 is electrically connected to first pad 12 via first opening K in first passivation layer 13 and via H in first planar layer 11. First pad 12 is used to connect to a signal source device. The signal source device provides a drive signal, which is then input into the circuitry within the circuit unit via first pad 12.

[0072] FIG1 b is a schematic diagram of the disassembled structure of the MLED display panel provided in an embodiment of the present disclosure.

[0073] In the embodiment of the present disclosure, the circuit unit can be used to make an MLED display panel, wherein the circuit provided in the circuit layer 14 may include a pixel circuit, and the signal source device connected to the first pad 12 may be a driving backplane. As shown in FIG1b , a docking pad 201 for bonding with the first pad 12 of the circuit unit 1 is provided on the driving backplane 200. In specific implementation, the embodiment of the present disclosure makes the pixel circuit provided in the driving backplane in the related art into the circuit unit 1, thereby avoiding making the pixel circuit directly on the driving backplane. The driving backplane only needs to be provided with a driving chip for providing a driving signal to the circuit unit 1 and related signal transmission lines, and is connected to the first pad 12 of the circuit unit 1 through the docking pad 201 to transmit the driving signal to the pixel circuit provided in the circuit unit 1, which greatly reduces the difficulty of making the driving backplane. In the embodiment of the present disclosure, the driving backplane 200 and the circuit unit 1 are respectively made into two independent modules. When a pixel circuit in the circuit unit 1 fails, the bonding structure between the first pad 12 of the circuit unit 1 and the docking pad 201 on the driving backplane 200 can be destroyed, thereby peeling the failed circuit unit 1 from the driving backplane 200 and replacing it with a new circuit unit. The replacement and repair process is simple and easy, thereby avoiding the driver backplane from being scrapped due to the failure of the pixel circuit and reducing the repair cost of the MLED display panel.

[0074] FIG2 is a second schematic diagram of the cross-sectional structure of the circuit unit provided in an embodiment of the present disclosure; FIG3 is an equivalent circuit diagram of the pixel circuit provided in an embodiment of the present disclosure.

[0075] Specifically, as shown in Figure 2, the circuit in the circuit layer also includes a fan-out trace 141. One end of the fan-out trace 141 is electrically connected to the pixel circuit of the circuit layer, and the other end is electrically connected to the first pad 12 through the first opening K of the first passivation layer 13 and the via H of the first flat layer 11, so that the driving signal output by the driving backplane can be transmitted to the pixel circuit through the first pad 12 and the fan-out trace 141. It should be noted that in order to highlight the main invention points of the present disclosure, in the cross-sectional structure of the circuit unit shown in Figure 2, the complete structure of the pixel circuit is not shown, but a thin film transistor TFT is used instead of the pixel circuit to simply illustrate the connection relationship between the first pad 12 and the pixel circuit through the fan-out trace 141. In specific implementation, the pixel circuit may include multiple thin film transistors and at least one capacitor to achieve specific functions, such as reducing the leakage current of the thin film transistor, improving the display quality, etc., which are not limited here.

[0076] In the disclosed embodiment, the number of first pads 12 corresponds to the number of signal input terminals in the circuit unit. For example, FIG3 illustrates a typical 2T1C pixel circuit, where portions connected by solid lines represent portions provided within the circuit unit, and portions connected by dashed lines represent portions not directly provided within the circuit unit. Portions connected by dashed lines, such as the MLED chip, can be connected to the circuit unit via bonding or other methods. As shown in FIG3 , the 2T1C pixel circuit includes a first thin-film transistor T10, a second thin-film transistor T20, and a storage capacitor C. The source of the first thin-film transistor T10 is connected to the data signal input terminal D for receiving a data signal, the gate of the first thin-film transistor T10 is connected to the scan signal input terminal S for receiving a scan signal, and the drain of the first thin-film transistor T10 is connected to the gate of the second thin-film transistor T20. The source of the second thin-film transistor T20 is connected to the high-potential power supply signal input terminal VDD for receiving a power supply voltage, and the drain of the second thin-film transistor T20 is electrically connected to the first connection terminal P, which is electrically connected to the anode of the MLED chip to input a drive current to the MLED chip. The cathode of the MLED chip is electrically connected to the second connection terminal N, which is connected to the low-potential power signal input terminal VSS. The low-potential power signal input terminal VSS is used to access a common voltage or a ground voltage. One end of the storage capacitor C is connected to the drain of the first thin-film transistor T10, and the other end is connected to the source of the second thin-film transistor T20. Among them, the data signal input terminal D, the scan signal input terminal S, the high-potential power signal input terminal VDD, and the low-potential power signal input terminal VSS all need to be electrically connected to the driver backplane to receive corresponding drive signals (such as data signals, scan signals, power supply voltages, common voltages, or ground voltages). Therefore, in a specific configuration, the circuit unit can include four first solder pads 12, each of which is electrically connected to the data signal input terminal D, the scan signal input terminal S, the high-potential power signal input terminal VDD, and the low-potential power signal input terminal VSS, for connecting to the driver backplane and receiving corresponding drive signals. Accordingly, a signal output terminal corresponding to the signal input terminal on the circuit unit needs to be provided on the driver backplane to output the corresponding drive signal to the circuit unit. It should be understood that the embodiment shown in Figure 3 only illustrates the embodiment of the present disclosure by setting a 2T1C pixel circuit in the circuit unit. In specific implementation, the pixel circuit in the circuit unit can also be set to a 6T1C pixel circuit, a 7T1C pixel circuit or a 10T2C pixel circuit, etc. The number of first pads 12 can be set according to the number of signal input terminals required by the circuit unit, and is not limited here.

[0077] In some embodiments, the circuit unit includes a plurality of first pads for receiving different drive signals, and the first flat layer also includes a plurality of vias. In a specific implementation, as shown in FIG2 , a first pad 12 corresponds to a via H, and the via H at least partially overlaps with the corresponding first pad 12, thereby exposing its corresponding first pad 12 through the via H, so as to facilitate subsequent connection with the pixel circuit through the fan-out trace 141. The plurality of first pads 12 provided on the circuit unit are used to receive different drive signals, so the plurality of first pads 12 need to be spatially spaced a certain distance apart and electrically insulated from each other. The plurality of first pads 12 are connected to the pixel circuit respectively through the fan-out trace 141 provided in the via H corresponding to the first pad 12, so that the fan-out trace 141 can be prevented from short-circuiting with the fan-out traces connected to other first pads when being routed in the via, thereby avoiding crosstalk between different drive signals.

[0078] In some embodiments, the circuit unit includes a plurality of first pads for receiving different drive signals, and the first flat layer may include at least one via, and at least one of the vias in the first flat layer corresponds to at least two first pads at the same time. The via at least partially overlaps with its corresponding first pad, thereby exposing its corresponding first pad through the via, facilitating subsequent connection with the pixel circuit through a fan-out trace. At least two first pads corresponding to the same via can be respectively connected to the pixel circuit through at least two fan-out traces provided in the same via, wherein one fan-out trace is connected to one first pad, thereby reducing the number of openings in the first flat layer.

[0079] In the disclosed embodiment, as shown in FIG2 , the circuit unit further includes a plurality of second solder pads 15 . The second solder pads 15 are located on a side of the circuit layer 14 facing away from the first solder pads 12 . The second solder pads 15 are electrically connected to the circuit layer 14 . The second solder pads 15 are used to connect to electrical devices, thereby electrically connecting the circuit unit to the electrical devices and supplying power to the electrical devices. The number of second solder pads 15 can be set based on the number of electrical devices connected to the circuit unit. For example, if the electrical device is an MLED chip, the MLED chip includes an anode and a cathode. As shown in FIG3 , the pixel circuit includes a first connection terminal P electrically connected to the anode of the MLED chip and a second connection terminal N electrically connected to the cathode of the MLED chip. Therefore, for each MLED chip, the circuit unit can include a second solder pad 15 connected to the first connection terminal P of the pixel circuit for connection to the anode of the MLED chip, and a second solder pad 15 connected to the second connection terminal N of the pixel circuit for connection to the cathode of the MLED chip. In specific implementations, the number of second solder pads 15 can be set based on the actual number of electrical devices connected to the circuit unit, and is not limited here.

[0080] Figure 4a is one schematic diagram of the manufacturing process of a circuit unit; Figure 4b is a second schematic diagram of the manufacturing process of a circuit unit; Figure 4c is a third schematic diagram of the manufacturing process of a circuit unit; and Figure 4d is a microscopic morphology diagram of a via hole in a circuit unit.

[0081] In one technical route, during the fabrication of the circuit unit, a via H may be opened in the first flat layer 11 after forming the first flat layer 11 and before forming the first passivation layer 13. As shown in FIG4a to FIG4c, the fabrication process of the circuit unit includes the following steps:

[0082] 1. Forming a sacrificial layer 120 on the base substrate 110; wherein the base substrate 110 serves as a substrate to support the film structure formed in the subsequent manufacturing process. The base substrate 110 can be made of materials such as glass, which are not limited here. The sacrificial layer 120 is used to temporarily connect the base substrate 110 with the film structure formed in the subsequent manufacturing process. After the circuit unit is manufactured, the sacrificial layer 120 can be removed to separate the circuit unit from the base substrate 110. The sacrificial layer 120 can be made of materials such as hot melt adhesive, which can be decomposed under heating conditions to separate the circuit unit from the base substrate 110.

[0083] 2. Depositing a conductive material layer on the side of the sacrificial layer 120 facing away from the base substrate 110 by a process such as sputtering deposition, and forming a plurality of first pads 12 separated from each other by a patterning process;

[0084] 3. Forming a first planar layer 11 on the side of the first pad 12 facing away from the sacrificial layer 120 by a coating process or other process. The material of the first planar layer 11 can be an organic material, such as polyimide (PI), which is not limited here. After coating, the first planar layer 11 is cured to improve structural strength.

[0085] 4. A first photoresist layer PR1 is coated on a side of the first planar layer 11 facing away from the first pad 12. Then, a first mask M1 is used to perform exposure and development processes on the first photoresist layer PR1 to form a photoresist pattern corresponding to the via H to be opened on the first photoresist layer PR1, that is, an opening is formed to expose the position of the first planar layer 11 where the via H is to be opened;

[0086] 5. Dry-etching the first planar layer 11 with a first etching gas to form a via H penetrating the first planar layer 11 and at least partially exposing the first pad 12;

[0087] 6. Remove the first photoresist layer PR1 and deposit a first passivation layer 13 on the side of the first planar layer 11 facing away from the first pad 12 by a process such as chemical vapor deposition. The first passivation layer 13 covers the surface of the first planar layer 11 and the wall surface of the via hole H in the first planar layer 11, and covers the first pad 12 exposed by the via hole H.

[0088] 7. A second photoresist layer PR2 is coated on a side of the first passivation layer 13 facing away from the first planar layer 11. Then, a second mask M2 is used to perform exposure and development processes on the second photoresist layer PR2 to form a photoresist pattern corresponding to the first opening K to be formed on the second photoresist layer PR2, that is, an opening is formed to expose the position of the first opening K to be formed in the first passivation layer 13;

[0089] 8. Dry-etching the first passivation layer 13 using a second etching gas to form a first opening K that penetrates the first passivation layer 13 and at least partially exposes the first pad 12; in the via hole H of the first passivation layer 11, in the area where the first opening K is not formed in the first passivation layer 13, the first passivation layer 13 still covers the hole wall surface of the via hole H;

[0090] 9. Remove the second photoresist layer PR2, deposit a conductive material layer on the side of the first passivation layer 13 away from the first planar layer 11 by a process such as sputtering deposition, and then form a fan-out trace 141 passing through the first opening K and connected to the first pad 12 by a patterning process;

[0091] Then, the circuit layer 14 is fabricated, and structures such as the second pad 15 are formed in sequence to form a complete circuit unit. Finally, the sacrificial layer 120 is removed to separate the base substrate 110 from the circuit unit.

[0092] The via H of the first planar layer 11 is manufactured using the process steps shown in Figures 4a to 4c. As shown in Figure 4b, when the first planar layer 11 is etched using the first etching gas, oxygen (O2) is usually used as the first etching gas. Since the materials of the first planar layer 11 and the first photoresist layer PR1 are both organic materials, the first etching gas has poor selectivity for the first planar layer 11 and the first photoresist layer PR1. That is, during the process of etching the first planar layer 11, the first etching gas simultaneously etches the first photoresist layer PR1 at a rate similar to that of etching the first planar layer 11. The opening of the first photoresist layer PR1 expands in a direction parallel to the first planar layer 11, thereby exposing an area of ​​the first planar layer 11 that should not be etched, resulting in a large etching deviation and poor size uniformity between different vias. Using other types of gases as the first etching gas is not only difficult to find, but also more expensive than oxygen. Furthermore, the selective etching effect on the first planar layer 11 and the first photoresist layer PR1 is not significantly improved, and a large etching deviation still exists. Furthermore, as the thickness of the first planar layer 11 increases, the etching time increases, and the etching deviation increases.

[0093] For example, the first planar layer 11 is configured as polyimide (PI) with a thickness of 5 μm. As shown in FIG4a , FIG4b , and FIG4d , after exposing the first photoresist layer PR1 and using the first mask M1 with an opening diameter CD1 of 10 μm, the via hole H is formed by etching the first planar layer 11 using the above-described method. The slope angle α of the via hole H (the angle between the via hole H wall and the first surface S1 of the first planar layer 11, where the first surface S1 is the surface of the first planar layer 11 near the first pad 12) is approximately 30° to 70°. On the first surface S1, i.e., the side of the via hole H near the first pad 12, the aperture diameter CD2 of the via hole H is approximately 14 μm to 20 μm. On the second surface S2 (the surface of the first planar layer 11 near the first passivation layer 13), i.e., the side of the via hole H near the first passivation layer 13, the aperture diameter CD3 of the via hole H is approximately 30 μm to 44 μm. Compared to the designed aperture (opening diameter CD1 of the first mask M1), the actual aperture of via H significantly exceeds the design range, and the dimensional uniformity of different vias is poor. As shown in Figure 4d, the microscopic morphology of via H reveals that the sidewalls of via H are steeply sloped, occupying a large area.

[0094] The thickness of the first pad 12 is usually less than 1 μm. When the thickness of the first planar layer 11 is set to 5 μm, the depth of the via H is more than 4 μm. Due to the long leveling time, it is difficult to use the planar layer material to effectively fill the via H within an acceptable process time. In addition, to completely fill the via H, it is necessary to form a thicker planar layer, thereby increasing the overall thickness of the circuit unit, which is not conducive to further reducing the size of the pixel unit. In addition, since high-temperature processes are required in the process of manufacturing pixel circuits, such as the 450°C excimer laser annealing (ELA) process required when manufacturing thin-film transistors, it is easy to damage organic materials. Therefore, before the pixel circuit is completed, the via H cannot be filled with the planar layer. As shown in Figure 2, even after the pixel circuit is completed, the surface of the circuit unit is flattened by the second planar layer 142, and the depression formed at the via H cannot be completely filled. Given that the step difference formed by the depression of the various film layers of the circuit unit in the area corresponding to the via H is large, the pixel circuit cannot be set in this area. For example, if a thin-film transistor is placed in the area corresponding to the via H, it may easily cause abnormal crystallization of the thin-film transistor during the ELA process. If a capacitor is placed in the area corresponding to the via H, it may easily cause the actual size of the capacitor to differ from the designed size, thereby affecting the actual capacitance value. If the connection traces used for connecting thin-film transistors and for connecting capacitors to thin-film transistors are placed in the area corresponding to the via H, the connection traces may easily break at the location where the film layer step difference is large corresponding to the via H, causing pixel circuit failure. Therefore, the pixel circuit needs to be placed away from the area corresponding to the via H.

[0095] FIG5 is a schematic diagram of a top view of a circuit unit provided in an embodiment of the present disclosure.

[0096] In the manufacturing process of Figures 4a to 4c, due to the large size deviation of the via H, the via H occupies a large area of ​​the circuit unit, thereby greatly reducing the area of ​​the pixel circuit setting area. For example, as shown in Figure 5, in a circuit unit provided in an embodiment of the present disclosure, the shape of the orthographic projection of the circuit unit on the plane is a square, and the side length W of the square is 315μm. Then the area S of the orthographic projection of the circuit unit on the plane is: S = 315μm × 315μm = 99225μm 2 The circuit unit includes 9 via holes H, and the aperture CD3 of the orthographic projection of each via hole H on the plane is about 30 μm to 44 μm. Therefore, the minimum total area S of the orthographic projection of the 9 via holes H on the plane is min For: S mi n = 30 μm × 30 μm × 9 = 8100 μm 2 , the maximum total area S of the orthographic projection of the 9 vias H on the plane max For: Smax =44μm×44μm×9=14400μm 2 , that is, the area occupied by the orthographic projection of the 9 vias H on the plane is about 8100μm 2 ~14400μm 2 The area occupancy rate of the via H relative to the orthographic projection of the circuit unit on a plane is approximately 8% to 17.5%. This high area occupancy rate of the via H results in a smaller pixel circuit layout area, hindering pixel circuit design and further reducing the size of the pixel unit. Therefore, reducing the size deviation of the via H, thereby reducing the aperture of the via H and reducing the area occupancy rate of the orthographic projection of the via H relative to the orthographic projection of the circuit unit on a plane, is beneficial for increasing the design space of the pixel circuit, reducing the difficulty of pixel circuit design, further reducing the size of the pixel unit, and improving resolution.

[0097] Figure 6a is one of the schematic diagrams of the manufacturing process of the circuit unit provided in the embodiment of the present disclosure; Figure 6b is the second schematic diagram of the manufacturing process of the circuit unit provided in the embodiment of the present disclosure; Figure 6c is the third schematic diagram of the manufacturing process of the circuit unit provided in the embodiment of the present disclosure; Figure 6d is a microscopic morphology diagram of the via of the circuit unit provided in the embodiment of the present disclosure.

[0098] In the manufacturing process of the circuit unit provided by the embodiment of the present disclosure, after forming the first flat layer 11, a via hole exposing the first pad 12 is not immediately opened in the first flat layer 11. Instead, a first passivation layer 13 is first formed on the side of the first flat layer 11 away from the first pad 12. Then, a first opening K is opened in the first passivation layer 13, corresponding to the position of the opening H designed in the first flat layer 11, and the first flat layer 11 is dry-etched using the first passivation layer 13 with the first opening K as a hard mask. As shown in Figures 6a to 6c, the manufacturing process of the circuit unit provided by the embodiment of the present disclosure includes the following steps:

[0099] 1. Forming a sacrificial layer 120 on the base substrate 110; wherein the base substrate 110 serves as a substrate to support the film structure formed in the subsequent manufacturing process. The base substrate 110 can be made of materials such as glass, which are not limited here. The sacrificial layer 120 is used to temporarily connect the base substrate 110 with the film structure formed in the subsequent manufacturing process. After the circuit unit is manufactured, the sacrificial layer 120 can be removed to separate the circuit unit from the base substrate 110. The sacrificial layer 120 can be made of materials such as hot melt adhesive, which can be decomposed under heating conditions to separate the circuit unit from the base substrate 110.

[0100] 2. Depositing a conductive material layer on the side of the sacrificial layer 120 facing away from the base substrate 110 by a process such as sputtering deposition, and forming a plurality of first pads 12 separated from each other by a patterning process;

[0101] 3. Forming a first planar layer 11 on the side of the first pad 12 facing away from the sacrificial layer 120 by a coating process or other process. The material of the first planar layer 11 can be an organic material, such as polyimide (PI), which is not limited here. After coating, the first planar layer 11 is cured to improve structural strength.

[0102] 4. Depositing a first passivation layer 13 on the side of the first planar layer 11 away from the first pad 12 by a process such as chemical vapor deposition;

[0103] 5. A photoresist layer PR is coated on the side of the first passivation layer 13 facing away from the first planar layer 11. Then, a mask M is used to perform exposure and development processes on the photoresist layer PR to form a photoresist pattern on the photoresist layer PR corresponding to the first opening K to be formed in the first passivation layer 13. That is, an opening is formed to expose the position of the first opening K to be formed in the first passivation layer 13.

[0104] 6. Dry-etching the first passivation layer 13 using a second etching gas to form a first opening K penetrating the first passivation layer 13 and partially exposing the first planar layer 11;

[0105] 7. Remove the photoresist layer PR, use the first passivation layer 13 as a hard mask, and use a first etching gas to dry-etch the first planar layer 11 exposed by the first opening K to form a via H that penetrates the first planar layer 11 and at least partially exposes the first pad 12;

[0106] 8. Depositing a conductive material layer on the side of the first passivation layer 13 facing away from the first planar layer 11 by a process such as sputtering deposition, and then forming a fan-out trace 141 passing through the first opening K and connected to the first pad 12 by a patterning process;

[0107] Then, the circuit layer 14 is fabricated, and structures such as the second pad 15 are formed in sequence to form a complete circuit unit. Finally, the sacrificial layer 120 is removed to separate the base substrate 110 from the circuit unit.

[0108] In the embodiment of the present disclosure, the first flat layer 11 and the first passivation layer 13 are made of different types of materials. For example, the first flat layer 11 is usually made of an organic material, and the first passivation layer 13 is usually made of an inorganic material. The physical and chemical properties between the first flat layer 11 and the first passivation layer 13 are quite different, and it is easy to use different etching gases for selective etching. For example, the material of the first passivation layer 13 can be silicon dioxide (SiO2), and the material of the first flat layer 11 can be PI. When etching the first passivation layer 13, the second etching gas can be CF4, and when etching the first flat layer 11, the first etching gas can be O2. O2 has an extremely high etching selectivity ratio for the first flat layer 11 and the first passivation layer 13, that is, the etching rate of O2 for the first flat layer 11 is much greater than the etching rate for the first passivation layer 13, so that selective etching of the first flat layer 11 can be achieved.

[0109] When the second etching gas is used to etch the first passivation layer 13 to form the first opening K, due to the relatively thin thickness of the first passivation layer 13, approximately 100 nm to 300 nm, the etching time is short, and the deviation of the diameter of the first opening K from the opening diameter CD of the mask M is relatively small, resulting in a high opening precision of the first opening K. In the process of etching the first planar layer 11 to form the via H using the first passivation layer 13 as a hard mask and the first etching gas, due to the extremely low etching rate of the first etching gas on the first passivation layer 13, the diameter of the first opening K in the first passivation layer 13 does not significantly expand. Compared to etching the first planar layer 11 directly using a photoresist as a mask, the etching precision of the first planar layer 11 can be greatly improved, and etching deviation can be reduced. Furthermore, the first passivation layer 13 is used as a hard mask to etch the first planar layer 11 , and only one mask is needed to form the first opening K and the via H, which can reduce the number of masks and the production cost.

[0110] For example, the thickness of the first planar layer 11 can be set to 2 μm to 10 μm. As shown in Figures 6b, 6c, and 6d, after exposing the photoresist layer PR and using the mask M with an opening diameter CD of 10 μm, the via hole H is formed by etching the first planar layer 11 using the above method. The slope angle α of the via hole H wall is greater than 80°. On the first surface S1, i.e., the side of the via hole H near the first pad 12, the aperture diameter CD2 of the via hole H is approximately 9 μm to 13 μm. On the second surface S2, i.e., the side of the via hole H near the first passivation layer 13, the aperture diameter CD3 of the via hole H is approximately 11 μm to 13 μm. The size difference between the bottom (near the first pad 12) and top (near the first passivation layer 13) of the via hole H is small. Compared to the designed aperture diameter (the opening diameter CD of the mask M), the actual aperture diameter of the via hole H deviates slightly from the designed aperture diameter, significantly improving etching accuracy. As shown in FIG6 d , by observing the microscopic morphology of the via H, it can be found that the sidewall of the via H is steep and the area occupied by the via is small.

[0111] In the circuit unit provided by the embodiment of the present disclosure, the aperture of the via hole opened in the first flat layer 11 can be set according to actual conditions. For example, on the first surface S1 of the first flat layer 11, the aperture of the via hole H can be set to 5μm to 30μm; on the second surface S2 of the first flat layer 11, the aperture of the via hole H can be set to 4μm to 30μm. The aperture of the via hole depends on the opening diameter of the mask M and the etching time. For different via hole sizes, masks with different opening sizes can be used to achieve the opening of via holes with corresponding apertures in the first flat layer 11. For example. Using a mask with an opening diameter slightly smaller than 5μm, a via hole with an aperture of approximately 5μm on the first surface S1 and an aperture of approximately 4μm on the second surface S2 can be opened; using a mask with an opening diameter slightly smaller than 30μm, a via hole with an aperture of approximately 30μm on the first surface S1 and an aperture slightly smaller than 30μm on the second surface S2 can be opened. In practice, to avoid excessive area occupied by the via, the diameter of the via on the second surface S2 can be set to no more than 30 μm. However, regardless of the size of the via, the circuit unit provided by the embodiment of the present disclosure is conducive to increasing the steepness of the via sidewall and reducing the area occupied by the via.

[0112] In the circuit unit provided in the embodiment of the present disclosure, the first passivation layer 13 protects the first planar layer 11 and can protect the first planar layer 11 during the fabrication of the circuit in the circuit layer 14, preventing damage to the structure of the first planar layer 11 caused by high-temperature and etching processes. In the circuit unit provided in the embodiment of the present disclosure, when a via H is formed in the first planar layer 11, the first passivation layer 13 is also reused as a hard mask to reduce etching deviation, thereby reducing the aperture of the via H and the occupancy rate of the orthographic projection of the via H on a plane relative to the orthographic projection of the circuit unit on a plane. This helps to expand the design space of the pixel circuit, reduce design difficulty, further reduce the size of the pixel unit, and improve resolution. In addition, the first passivation layer 13 is used as a hard mask to etch the first flat layer 11 to open a via H. The sidewalls of the via H are steeper and shorter than those formed by conventional etching methods. When fan-out traces are subsequently produced in the circuit layer, the fan-out traces have a shorter routing distance on the sidewalls of the vias, which is beneficial to reducing the resistance of the fan-out traces, reducing power consumption and improving signal transmission efficiency.

[0113] Since, in the circuit unit provided by the embodiment of the present disclosure, the first passivation layer 13 is formed on the surface of the first flat layer 11 before the via H is opened in the first flat layer 11, and the first flat layer 11 is etched using the first passivation layer 13 as a hard mask to form the via H, in the circuit unit provided by the embodiment of the present disclosure, the orthographic projections of the first opening K on the first flat layer 11 all fall within the corresponding via H.

[0114] When a via hole is formed in the first planar layer 11, because the etching time of the first planar layer 11 on the side closer to the first passivation layer 13 is longer than that on the side farther from the first passivation layer 13, as shown in FIG6c , the via hole on the side closer to the first passivation layer 13 is overetched to a certain extent toward the coverage area of ​​the first passivation layer 13, forming a protrusion T in the first passivation layer 13 that protrudes toward the inside of the via hole H relative to the edge of the via hole H. As shown in FIG6c , because the first passivation layer 13 below the protrusion T is etched away, after the via hole H is etched, the protrusion T is suspended relative to the via hole wall, so that the protrusion T does not directly cover the surface of the via hole wall. In a specific implementation, as shown in FIG6c , on the surface of the first planar layer 11 facing the first passivation layer 13 (second surface S2), the orthographic projection of the first opening in the first passivation layer 13 falls entirely within the via hole of the first planar layer 11, and the edge of the first opening is separated from the edge of the via hole by a predetermined distance, which is the width W1 of the protrusion T protruding inward from the edge of the via hole. Because the etching time of the first planar layer 11 on the side away from the first passivation layer 13 is shorter than that on the side close to the first passivation layer 13, on the surface of the first planar layer 11 facing away from the first passivation layer 13 (first surface S1), the orthographic projection of the first opening in the first passivation layer 13 can fall entirely or partially within the via hole of the first planar layer 11, without limitation herein.

[0115] In some embodiments, as shown in FIG. 6 c , the fan-out trace 141 covers the protrusion T and extends along the sidewalls of the first opening K of the first passivation layer 13 and the wall of the via H of the first planar layer 11 , thereby being electrically connected to the first pad 12 .

[0116] In some embodiments, as shown in FIG6c , the thickness W2 of the fan-out trace 141 attached to the wall of the via H in the first planar layer 11 can be set to be greater than the width W1 of the protrusion T protruding inward from the edge of the via H. This ensures that the fan-out trace 141 can completely cover the protrusion T, reducing the risk of disconnection of the fan-out trace 141. The width of the protrusion T depends on the etching time. When the first planar layer 11 is 5μm thick polyimide and oxygen is used as the first etching gas, the etching time for the via H is approximately 260s to 440s, and the width of the resulting protrusion T is approximately 0.2μm.

[0117] FIG. 7 is a fourth schematic diagram of the manufacturing process of the circuit unit provided in an embodiment of the present disclosure.

[0118] During the manufacturing process of the circuit unit provided by the embodiment of the present disclosure, as shown in FIG7 , when dry etching the first flat layer 11, the photoresist layer PR can be retained, and the first flat layer 11 can be etched using the photoresist PR as a mask and the first passivation layer 13 as a hard mask. The photoresist PR can play a certain protective role on the first passivation layer 13, preventing the first etching gas from further etching the first passivation layer 13 to increase the diameter of the first opening K, and can avoid the first etching gas from etching the surface of the first passivation layer 13 and generating defects such as pinholes, thereby ensuring that the surface of the first passivation layer 13 is smooth and flat. In specific implementation, the thickness of the photoresist layer PR can be set to 1.5 μm to 10 μm, for example, to 5 μm, to ensure that the photoresist layer PR has sufficient thickness to protect the first passivation layer 13 during the etching of the via H.

[0119] In the embodiment of the present disclosure, the material of the first flat layer 11 can be an organic material, such as polyimide. The thickness of the first flat layer 11 can be set to 2μm to 10μm. If the thickness of the first flat layer 11 is set too low, the coating uniformity of the organic material will be poor, and the strength of the film structure after curing will be low; if the thickness of the first flat layer 11 is set too high, the etching time will increase, the etching difficulty will increase, and it will not be conducive to reducing the overall thickness of the circuit unit. In specific implementation, the thickness of the first flat layer 11 is set to 5μm, which can achieve better overall effects.

[0120] In the embodiment of the present disclosure, the material of the first passivation layer 13 can be an inorganic material, for example, silicon nitride (SiN x ), silicon oxide (SiO x ) etc. The first passivation layer 13 can be a single layer structure or a stacked structure of multiple film layers, which is not limited here. In a specific implementation, since in the process of etching the first flat layer 11 using the first passivation layer 13 as a hard mask, the first flat layer 11 reacts with the etching gas to produce a large amount of volatile gas (Outgas), the gas product is difficult to escape and easily causes bubbling, so the material of the first passivation layer 13 can be silicon oxide with low density and good gas permeability, such as silicon oxide (SiO x ) etc., to improve the escape efficiency of the gas products. The thickness of the first passivation layer 13 can be set to 100nm to 300nm. For example, the first passivation layer 13 can be set to silicon dioxide (SiO2) with a thickness of 150nm, which is not limited here.

[0121] In the embodiment of the present disclosure, the first pad 12 is made of a material with good conductive properties. Specifically, the first pad 12 can be made of metal materials such as titanium (Ti), aluminum (Al), molybdenum (Mo), etc., which are not limited here. The first pad 12 can adopt a single-layer structure or a stacked structure. For example, the first pad 12 can adopt a Mo / Al / Mo stacked layer, a Ti / Al / Ti stacked layer, an Al / Ti stacked layer and other structures, which are not limited here. The first pad 12 adopts a stacked material containing Al, which is beneficial to reducing the resistivity of the fan-out trace, and at the same time can be deposited with a higher thickness, which is beneficial to the conduction of a larger drive current. The thickness of the first pad 12 can be set to 100nm-1000nm. For example, when the first pad 12 adopts a Mo / Al / Mo stacked layer structure, the thickness of each film layer can be set to 20nm / 300nm / 80nm in sequence, which are not limited here.

[0122] FIG8 a is a third schematic diagram of the cross-sectional structure of the circuit unit provided in an embodiment of the present disclosure; FIG8 b is a fourth schematic diagram of the cross-sectional structure of the circuit unit provided in an embodiment of the present disclosure.

[0123] In some embodiments, as shown in Figures 8a and 8b, a surface of the first pad 12 facing the first passivation layer 13 has a plurality of microstructures 120, and the fan-out trace 141 also has a plurality of microstructures at positions corresponding to the microstructures on the first pad 12. The microstructures 120 formed on the surface of the first pad 12 facing the first passivation layer 14 facilitate improving the connection performance and connection strength between the first pad 12 and the fan-out trace 141.

[0124] In some embodiments, as shown in Figures 8a and 8b, the plurality of microstructures 120 include a plurality of recessed structures 121. The recessed structures 121 can be formed in the region exposed by the via. For example, after etching the first planar layer 11 to form the via, the first etching gas can partially etch the surface of the first pad 12, thereby forming the plurality of recessed structures 121. This is not limited herein.

[0125] In some embodiments, as shown in Figures 8a and 8b, the plurality of microstructures 120 include a plurality of protruding structures 122. For example, the material of the first pad 12 can be a single-layer structure of aluminum or a laminated structure of aluminum and other metals. During the curing process of the first passivation layer 11, the aluminum material in the first pad 12 forms a hillock-like protrusion under the action of high temperature, thereby forming the protruding structure 122. This is not limited here.

[0126] In the disclosed embodiment, the material of the fan-out trace 141 can be made of a material with good conductive properties. Specifically, the fan-out trace 141 can be made of metal materials such as titanium (Ti), aluminum (Al), and molybdenum (Mo), which are not limited here. The fan-out trace 141 can adopt a single-layer structure or a stacked structure. For example, the fan-out trace 141 can adopt a Mo / Al / Mo stacked layer, a Ti / Al / Ti stacked layer, an Al / Ti stacked layer and other structures, which are not limited here. The fan-out trace 141 adopts a stacked material containing Al, which is beneficial to reducing the resistivity of the fan-out trace, and at the same time can deposit a higher thickness, which is beneficial to the conduction of a larger driving current. In addition, aluminum has good ductility and coverage, and has good wrapping properties for the morphology of the formed protrusions. The thickness of the fan-out trace 141 can be set to 100nm-1000nm. For example, when the fan-out trace 141 adopts a Mo / Al / Mo stacked structure, the thickness of each film layer can be set to 20nm / 300nm / 80nm in sequence, thereby effectively covering the protrusion T of the first passivation layer 13, which is not limited here.

[0127] In some embodiments, the circuit layer includes at least one thin film transistor, and an orthographic projection of an active layer of the thin film transistor on the first planar layer is located outside the via hole, thereby preventing abnormal crystallization of the active layer of the thin film transistor during the ELA process.

[0128] In some embodiments, the circuit layer further includes at least one capacitor, and the orthographic projection of the capacitor on the first planar layer is located outside the via hole, thereby avoiding a large deviation between the capacitor size and the designed size and ensuring an accurate capacitance value.

[0129] In some embodiments, the circuit layer further includes connecting traces. The connecting traces are used to connect thin-film transistors and capacitors to thin-film transistors. The orthographic projections of the connecting traces on the first planar layer are located outside the vias, thereby preventing the connecting traces from breaking when routing in the area corresponding to the vias, thereby preventing circuit malfunctions.

[0130] In some embodiments, as shown in FIG2 , the circuit layer 14 further includes a second planarizing layer 142 and a second passivation layer 143. The second planarizing layer 142 is located on the side of the circuit layer 14 facing away from the first planarizing layer 11, and the second passivation layer 143 is located on the side of the second planarizing layer 142 facing away from the first planarizing layer 11. The second planarizing layer 142 can flatten the surface of the circuit layer 14, filling in the step differences caused by the circuitry in the circuit layer 14. This creates a relatively flat surface on the side of the circuit layer 14 facing away from the first planarizing layer 11, facilitating the subsequent fabrication of the second solder pads 15 and facilitating subsequent connections between the circuit unit and the electrical device. The second passivation layer 143 can protect the second planarizing layer 142, preventing damage to the structure of the second planarizing layer 142 during the subsequent fabrication process of the second solder pads 15. The second solder pads 15 are located on the side of the second passivation layer 143 facing away from the second planarizing layer 142. The second solder pads 15 are connected to the circuitry in the circuit layer 14 via vias extending through the second passivation layer 143 and the second planarizing layer 142.

[0131] In some embodiments, as shown in FIG2 , the circuit unit further includes a third passivation layer 16. The third passivation layer 16 is located on a side of the second pad 15 facing away from the first planar layer 11. The third passivation layer 16 has a second opening that at least partially exposes the second pad 15 to facilitate subsequent connection between the second pad 15 and an electrical device.

[0132] In the embodiments of the present disclosure, the circuit in the circuit unit is used as a pixel circuit to form an MLED display panel, and the specific structure of the circuit unit is illustrated. In specific implementation, the circuit unit provided by the embodiments of the present disclosure is not limited to application in display panels. The circuit in the circuit unit can also be other circuits used to achieve specific purposes, thereby realizing a modular circuit design and achieving the purpose of reducing maintenance difficulty and maintenance costs, which is not limited here. The circuit unit provided by the embodiments of the present disclosure can also include other structures that are well known to those skilled in the art and are necessary to achieve complete circuit functions, which will not be described in detail here.

[0133] FIG9 is a schematic diagram of the cross-sectional structure of a light-emitting device provided in an embodiment of the present disclosure.

[0134] The present disclosure also provides a light-emitting device. As shown in Figure 9, the light-emitting device includes a light-emitting unit 2 and a circuit unit 1 provided in any of the above embodiments. The light-emitting unit 2 is electrically connected to the circuit unit 1. Specifically, the light-emitting unit 2 is electrically connected to the circuit unit 1 through the second pad 15 of the circuit unit 1. Among them, the light-emitting unit 2 can be an MLED chip, such as a Mini LED chip or a Mciro LED chip. Each light-emitting device provided in the embodiment of the present disclosure integrates a circuit unit, and the pixel circuit can be provided in the circuit unit, which is conducive to reducing the difficulty of manufacturing the driving backplane and reducing the difficulty and cost of repairing the MLED display panel when manufacturing the MLED display panel. The light-emitting device provided by the present disclosure also has the same or similar technical effects as the circuit unit provided in any of the above embodiments, which will not be repeated here.

[0135] FIG10 is a schematic diagram of the cross-sectional structure of a display panel provided in an embodiment of the present disclosure.

[0136] The present disclosure also provides a display panel. As shown in Figure 10, the display panel includes a driving backplane 200 and a light-emitting device 100 provided in any of the above embodiments. The light-emitting device 100 is electrically connected to the driving backplane 200. Specifically, a docking pad 201 for bonding to the first pad 12 of the circuit unit 1 is provided on the driving backplane 200. The light-emitting device 100 is electrically connected by bonding to the docking pad 201 of the driving backplane 200 through the first pad 12 of the circuit unit. A driving chip for providing a driving signal to the light-emitting device 100 and related signal transmission lines are provided on the driving backplane 200. The driving signal is transmitted to the pixel circuit in the circuit unit through the electrically connected docking pad 201 and the first pad 12, thereby driving the light-emitting unit to emit light for image display. In a specific implementation, the driving backplane 200 can be a TFT driving backplane, a printed circuit board (PCB) or a complementary metal oxide semiconductor (CMOS) substrate, which is not limited here. The display panel provided in the present disclosure has the same or similar technical effects as the light-emitting device provided in any of the above embodiments, and will not be described in detail here.

[0137] FIG11 is a flow chart of a method for manufacturing a circuit unit provided in an embodiment of the present disclosure.

[0138] The present disclosure also provides a method for manufacturing a circuit unit, which is used to manufacture the circuit unit provided by any of the above embodiments. As shown in FIG11 , the method for manufacturing a circuit unit provided by an embodiment of the present disclosure includes the following steps:

[0139] S111: making the first pad;

[0140] S112: Covering the first pad with a first material to form a first flat layer;

[0141] S113: depositing a second material on a side of the first planar layer away from the first pad to form a first passivation layer;

[0142] S114: dry-etching the first passivation layer using a second etching gas to form a first opening exposing the first planar layer;

[0143] S115: using the first passivation layer as a hard mask, dry-etching the first planar layer exposed by the first opening with a first etching gas to form a via hole penetrating the first planar layer and at least partially exposing the first pad.

[0144] In the method for manufacturing a circuit unit provided in an embodiment of the present disclosure, the first material used to form the first flat layer and the second material used to form the first passivation layer are different materials, for example, the first material is an organic material and the second material is an inorganic material. Referring to Figures 6a to 6c, when etching the first flat layer 11 to form a via H, the first passivation layer 13 is used as a hard mask and the first flat layer 11 is etched using a first etching gas. The first etching gas has a high etching selectivity ratio for the first material and the second material, that is, the first etching gas can selectively etch the first material while almost not etching the second material. This can reduce the process deviation when etching the first flat layer 11 and improve the dimensional accuracy of the via H. This is ultimately beneficial to reducing the size of the via H and reducing the occupancy rate of the orthographic projection of the via H on the plane relative to the area of ​​the orthographic projection of the circuit unit on the plane, which is beneficial to increasing the design space of the circuit in the circuit unit.

[0145] In some embodiments, dry etching the first passivation layer using a second etching gas to form a first opening exposing the first planar layer specifically includes the following steps:

[0146] S1141: coating a photoresist layer on a side of the first passivation layer facing away from the first planar layer, and developing the photoresist layer to form a photoresist pattern corresponding to the first opening;

[0147] S1142: using the photoresist layer as a mask, dry-etching the first passivation layer with a second etching gas to form a first opening exposing the first planar layer.

[0148] Using the first passivation layer as a hard mask, dry etching the first planar layer exposed by the first opening using a first etching gas to form a via hole penetrating the first passivation layer and at least partially exposing the first pad specifically includes the following steps:

[0149] The photoresist layer is retained, and the first passivation layer is used as a hard mask. The first flat layer exposed by the first opening is dry-etched with a first etching gas to form a via hole that penetrates the first flat layer and at least partially exposes the first pad.

[0150] During the specific fabrication process, referring to Figures 6a to 6c and 7 , the first passivation layer 13 is first etched using the photoresist layer PR as a mask to form a first opening K. The photoresist layer PR is then retained, and the first planar layer 11 is etched using the photoresist layer PR as a mask and the first passivation layer 13 as a hard mask to form a via H. During the etching process of the first planar layer 11, the photoresist layer PR protects the first passivation layer 13, preventing the first opening K from increasing in size during the etching process and preventing the first etching gas from etching the surface of the first passivation layer 13, forming defects such as pinholes.

[0151] The specific structure of the circuit unit provided in the embodiment of the present disclosure has been described in detail in the above content. The specific manufacturing process of the circuit unit provided in the embodiment of the present disclosure can refer to the specific structure of the circuit unit, as well as the relevant description of the embodiment shown in Figures 6a to 6c and Figure 7, and will not be repeated here.

[0152] Although the preferred embodiments of the present disclosure have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concepts. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present disclosure.

[0153] Obviously, those skilled in the art may make various changes and modifications to the present disclosure without departing from the spirit and scope of the present disclosure. Thus, if these modifications and variations of the present disclosure fall within the scope of the claims of the present disclosure and their equivalents, the present disclosure is intended to include these modifications and variations.

Claims

1. A circuit unit, wherein, include: First flat layer; A first pad, located at one side of the first flat layer; The first flat layer is provided with a via hole penetrating the first flat layer along a thickness direction; the via hole at least partially overlaps with the first pad; a first passivation layer, located on a side of the first flat layer away from the first pad; the first passivation layer is provided with a first opening penetrating the first passivation layer along the thickness direction and corresponding to the via holes one by one; the first passivation layer has a protrusion protruding toward the inner side of the via hole compared to the edge of the via hole, and the protrusion does not directly cover the hole wall surface of the via hole; A circuit layer is located on a side of the first passivation layer away from the first pad; the circuit in the circuit layer is electrically connected to the first pad through the first opening of the first passivation layer and the via hole of the first flat layer; the first pad is used to connect a signal source device.

2. The circuit unit according to claim 1, wherein, The first flat layer includes a first surface close to the first pad and a second surface close to the first passivation layer; an angle between the hole wall of the via hole and the first surface is greater than 80°.

3. The circuit unit according to claim 2, wherein, On the first surface, the aperture of the via hole is 5 μm to 30 μm; on the second surface, the aperture of the via hole is 4 μm to 30 μm.

4. The circuit unit according to claim 2 or 3, wherein, The thickness of the first planar layer is 2 μm to 10 μm.

5. The circuit unit according to any one of claims 1 to 4, wherein, The circuit in the circuit layer includes a fan-out trace; the fan-out trace covers the protrusion and is attached to the side wall of the first opening of the first passivation layer and the hole wall of the via hole of the first flat layer, and extends to be electrically connected to the first pad.

6. The circuit unit according to claim 5, wherein, The thickness of the fan-out trace attached to the hole wall of the via hole of the first flat layer is greater than the width of the protrusion protruding toward the inside of the via hole relative to the edge of the via hole.

7. The circuit unit according to any one of claims 1 to 6, wherein, The circuit layer includes at least one thin film transistor; the orthographic projection of the active layer of the thin film transistor on the first planar layer is located in a region outside the via hole.

8. The circuit unit according to claim 7, wherein, The circuit layer further includes at least one capacitor; the orthographic projection of the capacitor on the first flat layer is located in a region outside the via hole.

9. The circuit unit according to claim 8, wherein, The circuit layer also includes connecting wires; the connecting wires are used for connecting between the thin film transistors and for connecting between the capacitor and the thin film transistor; the orthographic projection of the connecting wires on the first flat layer is located in a region outside the via hole.

10. The circuit unit according to any one of claims 1 to 9, wherein, The circuit unit includes a plurality of the first pads; the first planar layer includes a plurality of the via holes; one of the first pads corresponds to one of the via holes; and the via holes at least partially overlap with the corresponding first pads.

11. The circuit unit according to any one of claims 1 to 10, wherein, A surface of the first pad facing the first passivation layer has a plurality of recessed structures.

12. The circuit unit according to any one of claims 1 to 11, wherein, A surface of the first pad facing the first passivation layer has a plurality of protrusion structures.

13. The circuit unit according to any one of claims 1 to 12, wherein, The circuit unit further comprises a plurality of second pads; the second pads are located on a side of the circuit layer away from the first pads; the second pads are electrically connected to the circuit layer; and the second pads are used to connect electrical devices.

14. The circuit unit according to any one of claims 1 to 3, wherein, The material of the first planarization layer is an organic material; the material of the first passivation layer is an inorganic material.

15. The circuit unit according to claim 14, wherein, The material of the first flat layer is polyimide; the material of the first passivation layer is silicon oxide.

16. A light-emitting device, wherein, Comprising: a light-emitting unit and the circuit unit according to any one of claims 1 to 15; the light-emitting unit is electrically connected to the circuit unit.

17. The light-emitting device according to claim 16, wherein, The light-emitting unit is a Mini LED chip or a Micro LED chip.

18. A display panel, wherein, Comprising: a driving backplane and the light-emitting device according to claim 17; the light-emitting device is electrically connected to the driving backplane.

19. A manufacturing method of a circuit unit, wherein, Comprising: fabricating a first pad; covering the first pad with a first material to form a first flat layer; depositing a second material on a side of the first flat layer facing away from the first pad to form a first passivation layer; performing dry etching on the first passivation layer with a second etching gas to form a first opening exposing the first flat layer; using the first passivation layer as a hard mask, performing dry etching on the first flat layer exposed by the first opening with a first etching gas to form a via hole penetrating through the first flat layer and at least partially exposing the first pad; wherein the first material is different from the second material, and the first etching gas selectively etches the first material.

20. The method according to claim 19, wherein The performing dry etching on the first passivation layer with the second etching gas to form a first opening exposing the first flat layer specifically includes: coating a photoresist layer on a side of the first passivation layer facing away from the first flat layer, and developing the photoresist layer to form a photoresist pattern corresponding to the first opening; using the photoresist layer as a mask, performing dry etching on the first passivation layer with the second etching gas to form a first opening exposing the first flat layer; The using the first passivation layer as a hard mask, performing dry etching on the first flat layer exposed by the first opening with the first etching gas to form a via hole penetrating through the first passivation layer and at least partially exposing the first pad specifically includes: retaining the photoresist layer, using the photoresist layer as a mask and using the first passivation layer as a hard mask, performing dry etching on the first flat layer exposed by the first opening with the first etching gas to form a via hole penetrating through the first flat layer and at least partially exposing the first pad.

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