Method and device for assigning pins in chip design

Abstract

The present application discloses a method and device for assigning pins in chip design. The method in embodiments of the present application comprises: converting an I / O bus list into a bit list on the basis of a preset conversion feature; on the basis of the number of metal layers allowed to be used and the distance between wiring tracks of the metal layers, calculating a placement length required for placing all I / O bits in the bit list under each wiring track condition; if an obtained placement length is less than an available length, selecting a wiring track condition with fewer metal layers and more wiring tracks; on the basis of the available length, a placement length corresponding to the selected wiring track condition and the number of groups of I / O buses in the bit list, determining the space between groups of the I / O buses; and on the basis of the selected wiring track condition and the determined space between the groups of the I / O buses, assigning metal layers for placement to each I / O bit in the bit list.

Description

A Method and Device for Implementing Pin Assignment in Chip Design Technical Field This application relates to, but is not limited to, integrated circuit design, and particularly refers to a method and device for implementing pin assignment in chip design. Background Art As the scale of integrated circuits becomes larger and the process becomes more advanced, the design and implementation process of chips becomes more complex and the design and implementation time becomes longer. How to quickly and effectively complete the design of a chip has become a bottleneck for products to enter the market. To shorten the chip design cycle and improve the chip design efficiency, large-scale chip design generally adopts a top-down or bottom-up design method, and divides the chip into small modules for parallel implementation. Although this parallel implementation method shortens the chip implementation cycle, it also brings some challenges. For example, how to quickly allocate the physical positions and layouts of the I / O pins of these small modules is a technical problem that needs to be solved urgently. Summary of the Invention This application provides a method and device for implementing pin assignment in chip design, which can solve any of the above technical problems. An embodiment of this application provides a method for implementing pin assignment in chip design, including: Converting an I / O bus list into a bit list according to a preset conversion feature, where the preset conversion feature indicates that the I / O signals in the identified I / O bus group have corresponding input signals and output signals one by one; Calculating the placement length required to place all I / O bits in the bit list under each trace condition according to the allowed number of metal layers and the distance between trace tracks of each metal layer; For the case where the obtained placement length is less than the available length, select the trace condition with fewer metal layers and more trace tracks; Determining the space between I / O bus groups according to the available length, the placement length corresponding to the selected trace condition, and the number of I / O bus groups in the bit list; Allocating a placement metal layer for each I / O bit in the bit list according to the selected trace condition and the determined space between I / O bus groups. In an exemplary example, the converting the I / O bus list into a bit list according to the preset conversion feature includes: For an I / O group with the preset conversion feature, when converting the I / O bus list into continuous bit information, each input signal is followed by the output signal corresponding to the input signal. In an exemplary instance, it further includes: for an I / O bus group that does not have the preset conversion feature, when converting the I / O bus list into bit information, each input signal is listed. In an exemplary instance, calculating the placement length required to place all I / O bits in the bit list under each trace track condition includes: For a first trace track condition where the number of metal layers allowed to be used is two and the number of tracks in each metal layer is 4, the placement length is the first placement length. pin_length_2layers_4track = ioNu × Ma_Mb_track_pitch × 4 / 2; Wherein, pin_length_2layers_4track represents the first placement length; ioNu represents the total number of I / Os in the bit list; metal layer Ma represents one of the two metal layers, and metal layer Mb represents the other of the two metal layers; Ma_Mb_track_pitch represents the distance between trace tracks in one metal layer in the current situation, and the distance between trace tracks in metal layer Ma and metal layer Mb is the same. In an exemplary instance, calculating the placement length required to place all I / O bits in the bit list under each trace track condition includes: For a second trace track condition where the number of metal layers allowed to be used is two and the number of tracks in each metal layer is 2, the placement length is the second placement length. pin_length_2layers_2track = ioNu × Ma_Mb_track_pitch × 2 / 2; Wherein, pin_length_2layers_2track represents the second placement length; ioNu represents the total number of I / Os in the bit list; metal layer Ma represents one of the two metal layers, and metal layer Mb represents the other of the two metal layers; Ma_Mb_track_pitch represents the distance between trace tracks in one metal layer in the current situation, and the distance between trace tracks in metal layer Ma and metal layer Mb... ...is the same. In an exemplary instance, calculating the placement length required to place all I / O bits in the bit list under each trace track condition includes: For a third trace track condition where the number of metal layers allowed to be used is three and the number of tracks in each metal layer is 3, the placement length is the third placement length. Among them, pin_length_3layers_3track represents the third placement length; ioNu represents the total number of I / Os in the bit list; metal layer Ma represents one of the three metal layers, metal layer Mb represents another one of the three metal layers, and metal layer Mc represents the third one of the three metal layers; Ma_Mb_track_pitch represents the distance between the trace tracks of one metal layer in the current case, and the distance between the trace tracks of metal layer Ma and metal layer Mb is the same; limit represents the available length; Mc_track_pitch represents the distance between the trace tracks of one metal layer Md. In an exemplary example, calculating the placement length required for placing all I / O bits in the bit list under each trace track condition includes: For the fourth trace track condition where the number of metal layers allowed to be used is three and the number of Tracks in each metal layer is 2, the placement length is the fourth placement length. Among them, pin_length_3layers_2track represents the fourth placement length; metal layer Ma represents one of the three metal layers, metal layer Mb represents another one of the three metal layers, and metal layer Mc represents the third one of the three metal layers; Ma_Mb_track_pitch represents the distance between the trace tracks of one metal layer in the current case, and the distance between the trace tracks of metal layer Ma and metal layer Mb is the same; limit represents the available length; Mc_track_pitch represents the distance between the trace tracks of one metal layer Md. In an exemplary example, the trace track conditions include the first trace track condition, the second trace track condition, the third trace track condition, and the fourth trace track condition arranged in sequence; selecting the trace track condition with fewer metal layers and more trace tracks includes: According to the sequence of the first trace track condition, the second trace track condition, the third trace track condition, and the fourth trace track condition, determine whether the obtained placement length is less than the available length, and from the trace track conditions where the placement length is less than the available length, select the trace track condition with fewer metal layers and more trace tracks to place all I / O bits in the bit list. In an exemplary example, the space between the I / O bus groups is determined by the following formula: space = (limit - L - para1) / pinGroup; Among them, space represents the space between I / O bus groups, limit represents the available length, L represents the placement length corresponding to the selected routing track condition, and pinGroup represents the number of I / O bus groups included in the bit list; the parameter para1 is a parameter related to chip design. In an exemplary instance, allocating a metal layer for each I / O bit in the bit list includes: For each bit taken from the bit list, compare and determine the metal layer with the shortest occupied placement length among the allowed metal layers, and use this metal layer as the metal layer for allocating the placement of this bit, and place this bit in the bit list corresponding to this metal layer, so as to implement allocating a metal layer for each I / O bit in the bit list. The embodiment of the present application further provides a computer-readable storage medium storing computer-executable instructions for executing the method for implementing pin allocation in the chip design described in any one of the above. The embodiment of the present application further provides a computer device including a memory and a processor, wherein the memory stores the following instructions executable by the processor: steps for executing the method for implementing pin allocation in the chip design described in any one of the above. The embodiment of the present application further provides a device for implementing pin allocation in a chip design, including: a preprocessing module, a calculation module, a first determination module, a second determination module, and an allocation module; wherein, The preprocessing module is configured to convert the I / O bus list into a bit list according to a preset conversion feature, where the preset conversion feature indicates that the I / O signals in the identified I / O bus group have one-to-one corresponding input signals and output signals; The calculation module is configured to calculate the placement length required for placing all I / O bits in the bit list under each routing track condition according to the number of allowed metal layers and the distance between routing tracks of each metal layer of the placement length; The first determination module is configured to, for the case where the obtained placement length is less than the available length, select a routing track condition with fewer metal layers and more routing tracks; The second determination module is configured to determine the space between I / O bus groups according to the available length, the placement length corresponding to the selected routing track condition, and the number of I / O buses in the bit list; The allocation module is configured to allocate a metal layer for placing each I / O bit in the bit list according to the selected routing track condition and the determined space between I / O bus groups. Other features and advantages of the present invention will be set forth in the following description, and in part will be obvious from the description, or may be learned by practice of the present invention. The objectives and other advantages of the present invention may be realized and attained by the structure particularly pointed out in the specification, claims and drawings. BRIEF DESCRIPTION OF THE DRAWINGS The drawings are used to provide a further understanding of the technical solutions of the present application, and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the technical solutions of the present application, and do not constitute a limitation to the technical solutions of the present application. FIG. 1 is a schematic flowchart of a method for implementing pin assignment in chip design according to an embodiment of the present application; FIG. 2 is an exemplary schematic diagram of a list of I / O buses provided by a front end in an embodiment of the present application; FIG. 3 is an exemplary schematic diagram of another list of I / O buses provided by a front end in an embodiment of the present application; FIG. 4 is an exemplary display schematic diagram of a metal layer assigned in implementing pin assignment in chip design according to an embodiment of the present application; FIG. 5 is a schematic structural diagram of a device for implementing pin assignment in chip design according to an embodiment of the present application. DETAILED DESCRIPTION In order to make the objectives, technical solutions and advantages of the present application clearer and more understandable, the embodiments of the present application will be described in detail below with reference to the drawings. It should be noted that, without conflict, the embodiments and features in the embodiments of the present application may be combined arbitrarily with each other. For ease of understanding of the present application, the present application will be described more comprehensively below with reference to the relevant drawings. Embodiments of the present application are shown in the drawings. However, the present application may be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided to make the disclosure of the present application more thorough and comprehensive. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the technical field to which the present application belongs. The terms used in the specification of the present application herein are only for the purpose of describing specific embodiments and are not intended to limit the present application. FIG. 1 is a schematic flowchart of a method for implementing pin assignment in chip design according to an embodiment of the present application. As shown in FIG. 1, it may include: Step 100: Convert the I / O bus list into a bit list according to a preset conversion feature, where the preset conversion feature indicates that the I / O signals in the identified I / O bus group have one-to-one corresponding input signals and output signals. In an exemplary example, for an I / O group with preset conversion characteristics, when converting an I / O bus list into continuous bit information, each input signal is followed by the output signal corresponding to that input signal. To save wiring resources and improve timing performance, etc., for such I / O buses in the embodiments of the present application, when converting to bit information, an output (out) signal of the same bit should follow the input (in) signal. The alternating arrangement between the input signal and the output signal facilitates the subsequent placement of I / O bits. In one embodiment, taking the preset conversion characteristic as the character "i" as an example, FIG. 2 shows an I / O bus list provided by the front end. As shown in the 3rd row of FIG. 2, it indicates that the I / O bus group of ai_wen has only one bit of information. Also, because this group of I / O buses has the conversion characteristic with the i identifier, when converting to bit information, in the bit list, a corresponding ao_wen signal will be generated for the ai_wen signal and appended to the I / O list following the ai_wen signal. That is to say, the bit information obtained after converting the 3rd row in FIG. 2 includes: ai_wen, ao_wen. As shown in the 4th row of FIG. 2, it represents a group of I / O buses of ai_wdata, where 0 indicates that the bit starts from 0, and 511 indicates that this group of I / O buses ends at bit 511. At the same time, this group of I / O buses has the conversion characteristic with the i identifier. Then, when converting to bit information, the bit list sequentially includes: ai_wdata[0], ao_wdata[0], ai_wdata[1], ao_wdata[1], ai_wdata[2], ao_wdata[2]…ai_wdata

[0510] , ao_wdata

[0510] , ai_wdata

[0511] , ao_wdata

[0511] . After the processing of step 100 in the embodiments of the present application, for the I / O bus group with one-to-one corresponding input and output signals for I / O signals, the alternating arrangement between the input signal and the output signal is cleverly realized, which facilitates the subsequent placement of I / O bits and provides a strong technical guarantee for saving wiring resources and improving timing performance, etc. In an exemplary example, for an I / O bus group without preset conversion characteristics, when converting an I / O bus list into bit information, only list each input signal. In one embodiment, taking the preset conversion feature as the character "i" as an example, FIG. 3 shows a list of I / O buses provided by the front end. As shown in the third row of FIG. 3, it indicates that the group of I / O buses bcc0_ba1_l1_arvalid[1] has only one bit, because this group of I / O buses does not carry the conversion feature with the i identifier. Therefore, when converting to bit information, in the bit list, the input signal does not need to be immediately followed by the corresponding output signal. Only the input signal bcc0_ba1_l1_arvalid[1] needs to be added to the I / O list. Again, as shown in the fourth row of FIG. 3, it indicates that the group of I / O buses bcc0_ba1_l1_arid starts from the 15th bit to the 29th bit, and this group of I / O buses does not carry the conversion feature with the i identifier. Then, when converting to bit signals, the bit list sequentially includes: bcc0_ba1_l1_arid

[0015] , bcc0_ba1_l1_arid

[0016] …bcc0_ba1_l1_arid

[0028] , bcc0_ba1_l1_arid

[0029] . Through step 100, a bit list composed of each I / O list converted from the I / O bus list can be obtained. This bit list is a two-dimensional array, which includes the I / O bit information to be placed arranged in order, and the total number of groups of I / O buses. Moreover, for the I / O bus group with the preset conversion feature, in the converted bit information, each input signal is immediately followed by the output signal corresponding to the input signal, which provides a strong technical guarantee for saving wiring resources and improving timing performance. Step 101: Calculate the placement length required to place all the I / O bits in the bit list under each wiring track condition according to the number of metal layers allowed to be used and the distance between the wiring tracks of each metal layer. In chip production, the wiring tracks of the metal layer are called tracks, and the distance from the center to the center of two adjacent tracks is called Pitch. The distance between the wiring tracks in the embodiments of the present application refers to the length of the Pitch between tracks. In an exemplary example, the number of metal layers allowed to be used is related to the chip design and is a definite piece of information. For example: Generally, the placement of each I / O bit in the I / O bus should be as close as possible to facilitate timing convergence and save placement length. However, at the same time, the placement of each I / O bit in the I / O bus cannot be too close, because being too close will affect wiring, thus causing design rule check (DRC) problems. In an exemplary instance, according to the number of metal layers allowed to be used and the distance between the trace tracks of each metal layer, there are four ways to arrange the positions (space) of the bits within the same group of I / O buses in the bit list, and the placement lengths of the I / O bits required under various trace track conditions are calculated respectively in the following ways: For the number of metal layers allowed to be used including two layers, and the number of tracks of each metal layer being 4, that is, 4 tracks can be used on each metal layer, this situation can be called the first trace track condition. Then, step 101 may include: pin_length_2layers_4track = ioNu × Ma_Mb_track_pitch × 4 / 2; Among them, pin_length_2layers_4track represents the first placement length in the case where the number of metal layers allowed to be used includes two layers and the number of tracks of each metal layer is 4; ioNu represents the total number of I / Os in the bit list; metal layer Ma represents one of the two metal layers, and metal layer Mb represents the other of the two metal layers; Ma_Mb_track_pitch represents the distance between the trace tracks of one metal layer in the current case, and the distance between the trace tracks of metal layer Ma and metal layer Mb is the same. In one embodiment, when horizontal (horizontal) trace, metal layer Ma can be M5 and metal layer Mb can be M7. In one embodiment, when vertical (Vertical) trace, metal layer Ma can be M4 and metal layer Mb can be M6. For the number of metal layers allowed to be used including two layers, and the number of tracks of each metal layer being 2, that is, 2 tracks can be used on each metal layer, this situation can be called the second trace track condition. Then, step 101 may include: pin_length_2layers_2track = ioNu × Ma_Mb_track_pitch × 2 / 2; Among them, pin_length_2layers_2track represents the second placement length in the case where the number of metal layers allowed to be used includes two layers and the number of tracks of each metal layer is 2, and the distance between the trace tracks of metal layer Ma and metal layer Mb is the same. In one embodiment, when horizontal trace, metal layer Ma can be M5 and metal layer Mb can be M7. In one embodiment, when vertical trace, metal layer Ma can be M4 and metal layer Mb can be M6. For the allowable number of metal layers including three layers, the number of tracks for each metal layer is 3, that is, 3 tracks can be used on each metal layer. This situation can be called the third routing track condition. Then, step 101 may include: Among them, pin_length_3layers_3track represents the third placement length in the case where the allowable number of metal layers includes three layers and the number of tracks for each metal layer is 3; limit represents the allowable boundary length, that is, the available length allowed by the design; Mc_track_pitch represents the distance between the routing tracks of the metal layer Mc in the current situation. In one embodiment, when routing horizontally, the metal layer Ma can be M5, the metal layer Mb can be M7, and the metal layer Mc can be M3. In one embodiment, when routing vertically, the metal layer Ma can be M4, the metal layer Mb can be M6, and the metal layer Mc can be M2. For the allowable number of metal layers including three layers, the number of tracks for each metal layer is 2, that is, 2 tracks can be used on each metal layer. This situation can be called the fourth routing track condition. Then, step 101 may include: Among them, pin_length_3layers_2track represents the fourth placement length in the case where the allowable number of metal layers includes three layers and the number of tracks for each metal layer is 2; limit represents the allowable boundary length, that is, the available length allowed by the design. In one embodiment, when routing horizontally, the metal layer Ma can be M5, the metal layer Mb can be M7, and the metal layer Mc can be M3. In one embodiment, when routing vertically, the metal layer Ma can be M4, the metal layer Mb can be M6, and the metal layer Mc can be M2. Step 102: For the case where the obtained placement length is less than the available length, select the routing track condition with fewer metal layers and more routing tracks. In an exemplary example, if the obtained placement lengths are all not less than the available length, then an error message is obtained, and the design needs to be re-planned and this process is exited. In this step, a large number of tracks means a large space between bit positions. When the same number of metal layers is used, the routing track condition with a large number of tracks is preferentially selected to place all I / O bit positions in the bit position list. In an exemplary example, step 102 may include: In the order of the first routing track condition, the second routing track condition, the third routing track condition, and the fourth routing track condition, determine whether the obtained placement length is less than the available length. From the routing track conditions where the placement length is less than the available length, select the routing track condition with fewer metal layers and more routing tracks to place all the I / O bits in the bit list. For example, the calculated placement lengths, i.e., the first placement length pin_length_2layers_4track, the second placement length pin_length_2layers_2track, the third placement length pin_length_3layers_3track, and the fourth placement length pin_length_3layers_2track, are judged in descending order of priority. For instance: when the first placement length pin_length_2layers_4track is less than the available length, it means that using two layers of metal wires with a space of 4 tracks between each bit can accommodate all the I / O bits; another example: if the first placement length pin_length_2layers_4track is not less than the available length, then judge whether the second placement length pin_length_2layers_2track is less than the available length. When the second placement length pin_length_2layers_2track is less than the available length, it means that using two layers of metal wires with a space of 2 tracks between each bit can accommodate all the I / O bits; yet another example: if both the first placement length pin_length_2layers_4track and the second placement length pin_length_2layers_2track are not less than the available length, and when the third placement length pin_length_3layers_3track is less than the available length, it means that using three layers of metal wires with a space of 3 tracks between each bit can accommodate all the I / O bits; also, if the first placement length pin_length_2layers_4track, the second placement length pin_length_2layers_2track, and the third placement length pin_length_3layers_3track are all not less than the available length, and when the fourth placement length pin_length_3layers_2track is less than the available length, it means that using three layers of metal wires with a space of 2 tracks between each bit can accommodate all the I / O bits. If the first placement length pin_length_2layers_4track, the second placement length pin_length_2layers_2track, the third placement length pin_length_3layers_3track, and the fourth placement length pin_length_3layers_2track are all not less than the available length, then an error message is given to indicate that re-planning and design are required and the current process After selecting the track conditions, depending on whether it is placed horizontally or vertically, it is possible to determine which metal layers to use, information such as the space between bit positions. For example: When the first track condition is selected, the metal layers used for horizontal placement are M5 and M7, and the metal layers used for vertical placement are M4 and M6. It can be determined that the space between bit positions is 4 tracks. That is to say, it indicates that 2 metal layers are required to place all the current I / O bit positions, and the placement pitch of each bit position is 4 times the metal layer track. Another example: When the third track condition is selected, the metal layers used for horizontal placement are M5, M7, and M3, and the metal layers used for vertical placement are M4, M6, and M2. It can be determined that the space between bit positions is 3 tracks. That is to say, it indicates that 3 metal layers are required to place all the current I / O bit positions, and the placement pitch of each bit position is 3 times the metal layer track. Step 103: Determine the space between I / O bus groups based on the available length, the placement length corresponding to the selected routing track condition, and the number of I / O buses in the bit position list. In an exemplary example, the space between I / O bus groups can be determined by the following formula: space = (limit - L - para1) / pinGroup; Where space represents the space between I / O bus groups, limit represents the available length, L represents the placement length corresponding to the selected routing track condition, and pinGroup represents the number of I / O bus groups included in the bit position list. The parameter para1 is a parameter related to chip design and can be determined according to the actual chip design. For example, para1 can be set to 20. It should be noted that the parameter para1 refers to leaving a length margin such as 20μm. The value of the parameter para1 can be determined according to experience in the project. The parameter para1 means leaving a space distance such as 20μm as much as possible compared to the allowable length limit. In one embodiment, for the case of selecting the first routing track condition, L is the first placement length pin_length_2layers_4track; for the case of selecting the second routing track condition, L is the second placement length pin_length_2layers_2track; for the case of selecting the third routing track condition, L is the third placement length pin_length_3layers_3track; for the case of selecting the fourth routing track condition, L is the fourth placement length pin_length_3layers_2track. In an exemplary instance, further, when the calculated space between I / O bus groups is greater than 4 and less than or equal to 6, the value of the space between I / O bus groups can be taken as 4; when the calculated space between I / O bus groups is greater than or equal to 4 and less than or equal to 4, the value of the space between I / O bus groups can be taken as 2; when the calculated space between I / O bus groups is less than 2, the value of the space between I / O bus groups can be taken as 0.5. By such processing, the placement of I / O bits can be made as compact as possible, thereby saving space. Step 104: According to the selected routing track conditions and the determined space between I / O bus groups, allocate the metal layers for placing each I / O bit in the bit list. In an exemplary instance, the selected routing track conditions include: the number of metal layers for placing I / O bits, the distance between the routing tracks of these metal layers for placing I / O bits, i.e., the length of the Pitch between track and track (track pitch), the number of tracks per metal layer, and the space between each bit is the distance of the number of tracks of the track metal layer per metal layer. In one embodiment, step 104 may include: For each bit taken from the bit list, compare and determine the metal layer with the shortest occupied placement length among the allowed metal layers, and use this metal layer as the metal layer for placing this bit, and place this bit in the bit list corresponding to this metal layer, so as to allocate the metal layers for placing each I / O bit in the bit list. In an exemplary instance, the one-dimensional I / O bus bit information can be retrieved from each two-dimensional array of I / O bus groups in the bit list through a for loop, and then the other-dimensional bit information of each group of I / O bus groups can be retrieved through another for loop; by selecting the available metal layers, the space between I / O buses, and the space between each I / O bit in the selected routing track conditions, the metal layer assigned to each I / O bit can be determined according to the implementation process of step 104. In an exemplary instance, each bit in the ioBusGroup can be retrieved through a two-layer for loop. The first for loop retrieves the ioBus, and the second for loop retrieves the bit elements in the ioBus. For each retrieved bit, it is compared which of the allowed metal layers, such as layer1, layer2, and layer3, has the shortest occupied placement length currently. Then, this metal layer is used as the metal layer for the placement of this bit, and the retrieved bit is placed in the corresponding list of this metal layer. By doing so in a loop, the metal layer for placing each I / O bit in the bit list can be implemented. In one embodiment, the occupied placement length of each layer of layer can be determined according to the layer track pitch and the number of elements in the list corresponding to the layer. For example: the layer track pitch of layer1 is a μm, and the number of bit positions corresponding to layer1 is d. Then, the occupied placement length of layer1, layer1_length = a * b. As shown in the example of Figure 4, first, compare the metal layer with the shorter currently occupied placement length in every two layers, and add 3 tracks to this metal layer. For example: if layer1 is the shortest in the layer, the length of layer1_length is increased by the length of 3 tracks (i.e., 3a). Another example: if layer2 is the shortest in the layer, then the length of layer2_length is increased by the length of 3 tracks (i.e., 3b); after increasing the length, compare which layer has a larger length after the increase, and take the maximum length as the length for placement; after such calculation, reset to zero and start a new round of comparison until the comparison is completed. In the bit list generated by the embodiment of the present application, for the I / O bus group with one-to-one input and output signals for I / O signals, the alternate arrangement between input signals and output signals is cleverly realized. According to the placement length calculated from the bit list, the routing track condition with fewer metal layers and more routing tracks is selected to place all I / O bits in the bit list, greatly shortening the implementation cycle of the chip and accelerating the implementation time of complex chips. The present application further provides a computer-readable storage medium storing computer-executable instructions for executing the method for implementing pin assignment in the chip design described in any one of the above. The present application further provides a computer device including a memory and a processor. The memory stores instructions executable by the processor for performing the steps of the method for implementing pin assignment in the chip design described in any one of the above. FIG. 5 is a schematic structural diagram of the composition of the device for implementing pin assignment in the chip design according to an embodiment of the present application. As shown in FIG. 5, it may include: a preprocessing module, a calculation module, a first determination module, a second determination module, and an assignment module. The preprocessing module is configured to convert the I / O bus list into a bit list according to a preset conversion feature, where the preset conversion feature indicates that the I / O signals in the identified I / O bus group have corresponding input signals and output signals one by one. The calculation module is configured to calculate the placement length required to place all I / O bits in the bit list under each routing track condition according to the allowed number of metal layers and the distance between routing tracks of each metal layer. The first determination module is configured to, for the case where the obtained placement length is less than the available length, select the routing track condition with fewer metal layers and more routing tracks. The second determination module is configured to determine the space between I / O bus groups according to the available length, the placement length corresponding to the selected routing track condition, and the number of I / O bus groups in the bit list. The assignment module is configured to assign a placement metal layer to each I / O bit in the bit list according to the selected routing track condition and the determined space between I / O bus groups. In the bit list generated by the embodiment of the present application, for the I / O bus group in which the I / O signals have corresponding input and output signals one by one, the input signals and output signals are alternately arranged ingeniously. According to the placement length calculated from the bit list, the routing track condition with fewer metal layers and more routing tracks is selected to place all I / O bits in the bit list, greatly shortening the implementation cycle of the chip and accelerating the implementation time of complex chips. Although the disclosed embodiments of the present application are as above, the described content is only an embodiment adopted for facilitating the understanding of the present application and is not intended to limit the present application. Any person skilled in the art within the scope of the present application can make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed by the present application. However, the scope of patent protection of the present application shall still be subject to the scope defined by the appended claims.

Claims

1. A method for implementing pin assignment in chip design, characterized in that Including: Converting the I / O bus list into a bit list according to a preset conversion feature, where the preset conversion feature indicates that the I / O signals in the identified I / O bus group have corresponding input signals and output signals one by one; Calculating the placement length required for placing all I / O bits in the bit list under each trace condition according to the allowable number of metal layers and the distance between trace tracks of each metal layer; For the case where the obtained placement length is less than the available length, select the trace condition with fewer metal layers and more trace tracks; Determining the space between I / O bus groups according to the available length, the placement length corresponding to the selected trace condition, and the number of I / O bus groups in the bit list; Allocating the metal layer for placement to each I / O bit in the bit list according to the selected trace condition and the determined space between I / O bus groups.

2. The method according to claim 1, wherein The converting the I / O bus list into a bit list according to the preset conversion feature includes: For the I / O group with the preset conversion feature, when converting the I / O bus list into continuous bit information, each input signal is followed immediately by the output signal corresponding to the input signal.

3. The method according to claim 2 further comprises: For the I / O bus group without the preset conversion feature, when converting the I / O bus list into bit information, list each input signal.

4. The method according to claim 1, wherein, The calculating the placement length required for placing all I / O bits in the bit list under each trace condition includes: For the first trace condition where the allowable number of metal layers includes two layers and the number of Tracks in each metal layer is 4, the placement length is the first placement length, pin_length_2layers_4track = ioNu × Ma_Mb_track_pitch × 4 / 2; where pin_length_2layers_4track represents the first placement length; ioNu represents the total number of I / O in the bit list; metal layer Ma represents one of the two metal layers, and metal layer Mb represents the other of the two metal layers; Ma_Mb_track_pitch represents the distance between trace tracks of one metal layer in the current situation, and the distance between trace tracks of metal layers Ma and Mb is the same. The calculating the placement length required for placing all I / O bits in the bit list under each trace condition includes:

5. The method according to claim 1, wherein For the second trace condition where the allowable number of metal layers includes two layers and the number of Tracks in each metal layer is 2, the placement length is the second placement length, pin_length_2layers_2track = ioNu × Ma_Mb_track_pitch × 2 / 2; pin_length_2layers_2track = ioNu × Ma_Mb_track_pitch × 2 / 2; Among them, pin_length_2layers_2track represents the second placement length; ioNu represents the total number of I / Os in the bit list; metal layer Ma represents one of the two metal layers, and metal layer Mb represents the other of the two metal layers; Ma_Mb_track_pitch represents the distance between the trace tracks of one metal layer in the current situation, and the distance between the trace tracks of metal layer Ma and metal layer Mb is the same.

6. The method according to claim 1, wherein, Calculating the placement length required to place all I / O bits in the bit list under each trace track condition includes: For the third routing track condition where the number of permitted metal layers is three and the number of tracks in each metal layer is 3, the placement length is the third placement length, Among them, pin_length_3layers_3track represents the third placement length; ioNu represents the total number of I / Os in the bit list; metal layer Ma represents one of the three metal layers, metal layer Mb represents another of the three metal layers, and metal layer Mc represents the third of the three metal layers; Ma_Mb_track_pitch represents the distance between the trace tracks of one metal layer in the current situation, and the distance between the trace tracks of metal layer Ma and metal layer Mb is the same; limit represents the available length; Mc_track_pitch represents the distance between the trace tracks of one metal layer Md.

7. The method according to claim 1, wherein, Calculating the placement length required to place all I / O bits in the bit list under each trace track condition includes: For the case where the number of metal layers allowed to be used is three and the number of Tracks in each metal layer is 2 The fourth wiring track condition, where the placement length is the fourth placement length, Among them, pin_length_3layers_2track represents the fourth placement length; metal layer Ma represents one of the three metal layers, metal layer Mb represents another of the three metal layers, and metal layer Mc represents the third of the three metal layers; Ma_Mb_track_pitch represents the distance between the trace tracks of one metal layer in the current situation, and the distance between the trace tracks of metal layer Ma and metal layer Mb is the same; limit represents the available length; Mc_track_pitch represents the distance between the trace tracks of one metal layer Md.

8. The method according to claim 1, wherein The trace track conditions include a first trace track condition, a second trace track condition, a third trace track condition, and a fourth trace track condition arranged in sequence. Selecting the trace track condition with fewer metal layers and more trace tracks includes: In the order of the first trace track condition, the second trace track condition, the third trace track condition, and the fourth trace track condition, determine whether the obtained placement length is less than the available length. From the trace track conditions where the placement length is less than the available length, select the trace track condition with fewer metal layers and more trace tracks to place all I / O bits in the bit list.

9. The method according to claim 1, wherein Determine the space between the I / O bus groups through the following formula: space = (limit - L - para1) / pinGroup; Among them, space represents the space between I / O bus groups, limit represents the available length, L represents the placement length corresponding to the selected routing track condition, and pinGroup represents the number of I / O bus groups included in the bit list; the parameter para1 is a parameter related to chip design.

10. The method according to claim 1, wherein Allocating a metal layer for each I / O bit in the bit list includes: For each bit taken from the bit list, comparing and determining the metal layer with the shortest occupied placement length among the allowed metal layers, using this metal layer as the metal layer for allocating the placement of this bit, and placing this bit in the bit list corresponding to this metal layer, so as to implement allocating a metal layer for each I / O bit in the bit list.

11. A computer-readable storage medium storing computer-executable instructions for executing the method for implementing pin allocation in the chip design according to any one of claims 1 to 10.

12. A computer device, comprising a memory and a processor, wherein, The memory stores the following instructions executable by the processor: steps for executing the method for implementing pin allocation in the chip design according to any one of claims 1 to 10.

13. A device for implementing pin assignment in chip design, characterized in that, Including: A preprocessing module, a calculation module, a first determination module, a second determination module, and an allocation module; among them, The preprocessing module is configured to convert the I / O bus list into a bit list according to a preset conversion feature, where the preset conversion feature indicates that the I / O signals in the identified I / O bus group have one-to-one corresponding input signals and output signals; The calculation module is configured to calculate the placement length required to place all I / O bits in the bit list under each routing track condition according to the number of allowed metal layers and the distance between routing tracks of each metal layer; The first determination module is configured to, for the case where the obtained placement length is less than the available length, select a routing track condition with fewer metal layers and more routing tracks; The second determination module is configured to determine the space between I / O bus groups according to the available length, the placement length corresponding to the selected routing track condition, and the number of I / O buses in the bit list; The allocation module is configured to allocate a metal layer for each I / O bit in the bit list according to the selected routing track condition and the determined space between I / O bus groups.

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