Gate driving circuit and display panel

Abstract

The present application provides a gate driving circuit and a display panel. Before a first pull-up module transmits a first power supply signal to a first node on the basis of a first starting signal, a second pull-down module transmits a second power supply signal to a third node on the basis of a second starting signal, and a pull-down retention module disconnects the electrical connection between a first power supply end and the second node on the basis of the potential of the third node.

Description

Gate drive circuit and display panel Technical Field

[0001] The present application relates to the field of display technology, and in particular to a gate drive circuit and a display panel. Background Art

[0002] A gate drive circuit often uses a two-output transistor design, i.e., the gate drive circuit includes a first output transistor and a second output transistor. The control terminal of the first output transistor is connected to a first node, and the input terminal of the first output transistor receives a first voltage. The control terminal of the second output transistor is connected to a second node, and the input terminal of the second output transistor receives a second voltage. The output terminals of the first and second output transistors are both electrically connected to the output terminal of the gate drive circuit. When the first output transistor is turned on by the potential of the first node, the second output transistor should be turned off by the potential of the second node.

[0003] However, when the potential of the first node changes from a first level to a second level, and the potential of the second node changes from the second level to the first level, the potential difference between the first and second nodes causes the change speed of the second node to be slower than expected, causing the first and second output transistors to be turned on simultaneously, causing the output end of the gate drive circuit to receive the first and second voltages simultaneously. At the same time, the remaining transistors in the gate drive circuit that are electrically connected to the first and second nodes may also be turned on, causing the second node and other nodes in the gate drive circuit to receive high and low voltages simultaneously, affecting the normal operation of the gate drive circuit and causing burn-in problems in display panels using the gate drive circuit. SUMMARY OF THE INVENTION

[0004] The embodiments of the present application provide a gate drive circuit and a display panel, which can improve the problem that a key node in the gate drive circuit receives high and low voltages simultaneously, causing burn-in of a display panel using the gate drive circuit.

[0005] An embodiment of the present application provides a gate drive circuit and a display panel, wherein the gate drive circuit includes a first pull-up module, a second pull-down module, a pull-down maintenance module, and an output module. The first pull-up module is electrically connected to a first node and a first power supply terminal, and is configured to transmit a first power signal supplied by the first power supply terminal to the first node according to a first start signal. The second pull-down module is electrically connected to a second node, a third node, and a second power supply terminal, and is configured to transmit a second power signal supplied by the second power supply terminal to the second node according to the first start signal. The pull-down maintenance module is electrically connected to the second node, the third node, and the first power supply terminal, and is configured to control the electrical connection between the first power supply terminal and the second node according to the potential of the third node. The output module is electrically connected to the first node and the second node, and is configured to output a gate control signal according to the potentials of the first node and the second node. Wherein, before the first pull-up module is configured to transmit the first power signal to the first node according to the first start signal, the second pull-down module is configured to transmit the second power signal to the third node according to the second start signal, and the pull-down maintenance module is configured to disconnect the electrical connection between the first power terminal and the second node according to the potential of the third node.

[0006] An embodiment of the present application further provides a display panel, comprising a first gate drive unit and a second gate drive unit. The first gate drive unit comprises a plurality of any of the aforementioned gate drive circuits; the second gate drive unit is electrically connected to the first gate drive unit and configured to generate a plurality of start-up signals for output to the plurality of gate drive circuits of the first gate drive unit. The start-up signals comprise the first start-up signal and the second start-up signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] FIG1 is a block diagram of a gate drive circuit according to an embodiment of the present invention;

[0008] FIG2 is a structural diagram of a gate drive circuit provided in an embodiment of the present application;

[0009] FIG3 is a timing diagram of a corresponding gate drive circuit provided in an embodiment of the present application;

[0010] FIG4 is a schematic structural diagram of a display panel provided in an embodiment of the present application;

[0011] FIG5 is a structural diagram of an m-th stage gate driving circuit provided in an embodiment of the present application;

[0012] FIG6 is a timing diagram of the m-th stage gate driving circuit provided in an embodiment of the present application;

[0013] FIG7 is a schematic structural diagram of a pixel driving circuit provided in an embodiment of the present application;

[0014] FIG8 is a verification diagram provided in an embodiment of the present application. Modes for Carrying Out the Invention

[0015] To make the purpose, technical solutions and effects of this application clearer and more specific, the following further describes this application in detail with reference to the accompanying drawings and examples. It should be understood that the specific examples described herein are only used to explain this application and are not intended to limit this application.

[0016] The gate drive circuit and display panel provided by the present application include a first pull-up module, a second pull-down module, a pull-down maintenance module, and an output module. Before the first pull-up module transmits the first power signal to the first node according to the first start signal, the second pull-down module transmits the second power signal to the third node according to the second start signal, so that the pull-down maintenance module disconnects the electrical connection between the first power end and the second node according to the potential of the third node. When the first pull-up module transmits the first power signal to the first node according to the first start signal, the second pull-down module transmits the second power signal supplied by the second power end to the second node according to the first start signal, so that the second node only receives the second power signal when the first power signal is transmitted to the first node, thereby improving the problem that when the first power signal is transmitted to the first node, the second node receives the first power signal and the second power signal at the same time due to the difference in potential changes between the first node and the second node, which affects the normal operation of the gate drive circuit. When the gate drive circuit is applied to a display panel, the burn-in problem of the display panel can also be improved.

[0017] 1 is a block diagram of a gate drive circuit according to an embodiment of the present invention. The gate drive circuit includes a first node control module 10 , a second node control module 20 , and an output module 30 .

[0018] The first node control module 10 is electrically connected to the first node N1, the first power supply terminal VGH1 and the second power supply terminal VGL1. The first node control module 10 is used to transmit the first power signal supplied by the first power supply terminal VGH1 to the first node N1 according to the first start signal INI1, or transmit the second power signal supplied by the second power supply terminal VGL1 to the first node N1 according to the pull-down control signal Gn.

[0019] The second node control module 20 is electrically connected to the second node N2, the first power terminal VGH1 and the second power terminal VGL1. The second node control module 20 is used to transmit the second power signal to the second node N2 according to the first start signal INI1, or transmit the first power signal to the second node N2 according to the pull-down control signal Gn.

[0020] The output module 30 is electrically connected to the first node N1 and the second node N2 , and is configured to output a gate control signal REF according to the potentials of the first node N1 and the second node N2 .

[0021] Among them, before the first node control module 10 is used to transmit the first power signal to the first node N1 according to the first start signal INI1, the second node control module 20 is used to disconnect the electrical connection between the first power terminal VGH1 and the second node N2 according to the second start signal INI2, so that when the first power signal is transmitted to the first node N1, the second node N2 only receives the second power signal but not the first power signal, thereby improving the problem that the second node N2 receives the second power signal and the first power signal at the same time, affecting the normal operation of the gate drive circuit.

[0022] Optionally, please continue to refer to FIG. 1 , the first node control module 10 includes a first pull-up module 101 , and the second node control module 20 includes a second pull-down module 201 and a pull-down maintaining module 202 .

[0023] The first pull-up module 101 is electrically connected to the first node N1 and the first power terminal VGH1 . The first pull-up module 101 is configured to transmit a first power signal supplied from the first power terminal VGH1 to the first node N1 according to a first start-up signal INI1 .

[0024] The second pull-down module 201 is electrically connected to the second node N2, the third node N3 and the second power terminal VGL1. The second pull-down module 201 is configured to transmit the second power signal supplied from the second power terminal VGL1 to the second node N2 according to the first start signal INI1.

[0025] The pull-down maintaining module 202 is electrically connected to the second node N2, the third node N3 and the first power terminal VGH1. The pull-down maintaining module 202 is used to control the electrical connection between the first power terminal VGH1 and the second node N2 according to the potential of the third node N3.

[0026] Wherein, before the first pull-up module 101 is used to transmit the first power signal to the first node N1 according to the first start signal INI1, the second pull-down module 201 is used to transmit the second power signal to the third node N3 according to the second start signal INI2, and the pull-down maintaining module 202 is used to disconnect the electrical connection between the first power terminal VGH1 and the second node N2 according to the potential of the third node N3, so that when the first pull-up module 101 transmits the first power signal to the first node N1 according to the first start signal INI1, the second pull-down module 201 disconnects the electrical connection between the first power terminal VGH1 and the second node N2 according to the potential of the third node N3. INI1 transmits the second power signal supplied by the second power terminal VGL1 to the second node N2. When the first power signal is transmitted to the first node N1, the second node N2 only receives the second power signal, and the first power signal cannot act on the third node N3. This improves the problem that when the first power signal is transmitted to the first node N1, the change speed of the second node N2 is slower than expected due to the difference in potential changes between the first node N1 and the second node N2, causing the second node N2 to receive both the first and second power signals simultaneously, thus affecting the normal operation of the gate drive circuit. When the gate drive circuit is applied to a display panel, it can also improve the burn-in problem that may occur on the display panel.

[0027] Figure 2 is a structural diagram of a gate drive circuit provided in an embodiment of the present application. Optionally, the first pull-up module 101 includes a first pull-up transistor Tu1, wherein a control terminal of the first pull-up transistor Tu1 is configured to receive the first start signal INI1, an input terminal of the first pull-up transistor Tu1 is electrically connected to the first power supply terminal VGH1, and an output terminal of the first pull-up transistor Tu1 is electrically connected to the first node N1.

[0028] Continuing to refer to FIG. 2 , the second pull-down module 201 includes a first pull-down transistor Td1 , a second pull-down transistor Td2 , and a third pull-down transistor Td3 .

[0029] The control end of the first pull-down transistor Td1 is configured to receive the second start-up signal INI2 , and the input end of the first pull-down transistor Td1 is electrically connected to the second power end VGL1 .

[0030] The control end of the second pull-down transistor Td2 is used to receive the second start signal INI2, the input end of the second pull-down transistor Td2 is electrically connected to the output end of the first pull-down transistor Td1, and the output end of the second pull-down transistor Td2 is electrically connected to the third node N3.

[0031] The control end of the third pull-down transistor Td3 is used to receive the first start signal INI1, the input end of the third pull-down transistor Td3 is electrically connected to the second power end VGL1, and the output end of the third pull-down transistor Td3 is electrically connected to the second node N2.

[0032] The first pull-down transistor Td1 and the second pull-down transistor Td2 are configured to electrically connect the second power terminal VGL1 and the third node N3 according to the second start-up signal INI2, or disconnect the second power terminal VGL1 from the third node N3 according to the second start-up signal INI2. The third pull-down transistor Td3 is configured to electrically connect the second power terminal VGL1 and the second node N2 according to the first start-up signal INI1, or disconnect the second power terminal VGL1 from the second node N2 according to the first start-up signal INI1.

[0033] Continuing to refer to FIG. 2 , the pull-down maintaining module 202 includes a first transistor T1 , a second transistor T2 , and a first capacitor C1 .

[0034] The control ends of the first transistor T1 and the second transistor T2 are electrically connected to the third node N3, the input end of the first transistor T1 and the input end of the second transistor T2 are electrically connected to the first power supply end VGH1, the output end of the first transistor T1 is electrically connected to the output end of the first pull-down transistor Td1, and the output end of the second transistor T2 is electrically connected to the second node N2.

[0035] A first end of the first capacitor C1 is electrically connected to the third node N3 , and a second end of the first capacitor C1 is electrically connected to the input end of the second transistor T2 .

[0036] The second transistor T2 electrically connects the first power supply terminal VGH1 and the second node N2 according to the potential of the third node N3, or disconnects the first power supply terminal VGH1 and the second node N2 according to the potential of the third node N3.

[0037] Continuing to refer to FIG. 2 , the output module 30 includes a first output transistor To1 , a second output transistor To2 , and a second capacitor C2 .

[0038] The control terminal of the first output transistor To1 is electrically connected to the first node N1, the input terminal of the first output transistor To1 is electrically connected to the third power supply terminal VGH2, and the output terminal of the first output transistor To1 is electrically connected to the output terminal of the gate drive circuit. The first output transistor To1 is configured to electrically connect the third power supply terminal VGH2 and the output terminal of the gate drive circuit according to the potential of the first node N1, or to disconnect the third power supply terminal VGH2 from the output terminal of the gate drive circuit according to the potential of the first node N1.

[0039] The control terminal of the second output transistor To2 is electrically connected to the second node N2, the input terminal of the second output transistor To2 is electrically connected to the fourth power supply terminal VGL2, and the output terminal of the second output transistor To2 is electrically connected to the output terminal of the gate drive circuit. The second output transistor To2 is configured to electrically connect the fourth power supply terminal VGL2 and the output terminal of the gate drive circuit according to the potential of the second node N2, or to disconnect the fourth power supply terminal VGL2 from the output terminal of the gate drive circuit according to the potential of the second node N2.

[0040] A first end of the second capacitor C2 is electrically connected to the control end of the first output transistor To1 , and a second end of the second capacitor C2 is electrically connected to the output end of the first output transistor To1 .

[0041] When the first pull-up module 101 transmits the first power signal to the first node N1 according to the first start-up signal INI1, the second pull-down module 201 transmits the second power signal to the second node N2 according to the first start-up signal INI1. Therefore, when the first output transistor To1 is turned on according to the potential of the first node N1, the second output transistor To2 can be turned off according to the potential of the second node N2. This can alleviate the problem of the first output transistor To1 and the second output transistor To2 being turned on at the same time, causing the output end of the gate driver circuit to simultaneously receive the third power signal supplied by the third power terminal VGH2 and the fourth power signal supplied by the fourth power terminal VGL2.

[0042] Optionally, please continue to refer to Figure 1. In order to make the gate control signal REF output by the gate drive circuit stop maintaining the valid level state after the valid level state maintained by the gate control signal REF meets the designed time length, the first node control module 10 also includes a first pull-down module 102, and the first pull-down module 102 is electrically connected to the first node N1 and the second power supply terminal VGL1. The first pull-down module 102 is used to transmit the second power supply signal to the first node N1 according to the pull-down control signal Gn.

[0043] Optionally, please continue to refer to FIG. 2 , the first pull-down module 102 includes a fourth pull-down transistor Td4 and a fifth pull-down transistor Td5 .

[0044] The control end of the fourth pull-down transistor Td4 is configured to receive the pull-down control signal Gn, and the input end of the fourth pull-down transistor Td4 is electrically connected to the second power end VGL1 .

[0045] The control end of the fifth pull-down transistor Td5 is used to receive the pull-down control signal Gn, the input end of the fifth pull-down transistor Td5 is electrically connected to the output end of the fourth pull-down transistor Td4, and the output end of the fifth pull-down transistor Td5 is electrically connected to the first node N1.

[0046] Optionally, please continue to refer to Figure 1. In order to restore the gate control signal REF output by the gate drive circuit to an invalid level state after outputting a valid level state, the second node control module 20 also includes a second pull-up module 203. The second pull-up module 203 is electrically connected to the third node N3. The second pull-up module 203 is used to transmit the pull-down control signal Gn to the third node N3 according to the pull-down control signal Gn, so that after the gate control signal REF output by the gate drive circuit has a valid level state that meets the required time length, the gate control signal REF has an invalid level state.

[0047] Optionally, please continue to refer to FIG. 2 , the second pull-up module 203 includes a second pull-up transistor Tu2 and a third pull-up transistor Tu3 .

[0048] The control end of the second pull-up transistor Tu2 is used to receive the pull-down control signal Gn, the input end of the second pull-up transistor Tu2 is electrically connected to the control end of the second pull-up transistor Tu2, and the output end of the second pull-up transistor Tu2 is electrically connected to the output end of the first transistor T1.

[0049] The control end of the third pull-up transistor Tu3 is used to receive the pull-down control signal Gn, the input end of the third pull-up transistor Tu3 is electrically connected to the output end of the second pull-up transistor Tu2, and the output end of the third pull-up transistor Tu3 is electrically connected to the third node N3.

[0050] Optionally, when the first pull-down transistor Td1 and the second pull-down transistor Td2 are turned on, the first transistor T1 is turned off. When the first transistor T1 is turned on, the second pull-down transistor Td2 is turned off, and thus the first power signal cannot be transmitted to the third node N3 via the second pull-down transistor Td2. Therefore, in some embodiments, the output terminal of the first transistor T1 may be electrically connected only to the output terminal of the second pull-up transistor Tu2, and not to the output terminal of the first pull-down transistor Td1. This reduces the number of traces during the manufacturing process of the gate drive circuit, saving cost and wiring space.

[0051] Optionally, please continue to refer to Figure 1. In some embodiments, in order to ensure that the gate control signal REF can be stably maintained in the invalid level state after having the valid level state, the first pull-down module 102 is also electrically connected to the second node N2 to electrically connect the second power supply terminal VGL1 and the first node N1 according to the potential of the second node N2.

[0052] Optionally, please continue to refer to FIG. 2 , the first pull-down module 102 includes a sixth pull-down transistor Td6 , a seventh pull-down transistor Td7 , and an eighth pull-down transistor Td8 .

[0053] The control end of the sixth pull-down transistor Td6 is electrically connected to the first node N1, the input end of the sixth pull-down transistor Td6 is electrically connected to the first power supply end VGH1, and the output end (i.e., No) of the sixth pull-down transistor Td6 is electrically connected to the output end of the fourth pull-down transistor Td4.

[0054] The control end of the seventh pull-down transistor Td7 is electrically connected to the second node N2 , the input end of the seventh pull-down transistor Td7 is electrically connected to the output end of the sixth pull-down transistor Td6 , and the output end of the seventh pull-down transistor Td7 is electrically connected to the first node N1 .

[0055] The control end of the eighth pull-down transistor Td8 is electrically connected to the second node N2, the input end of the eighth pull-down transistor Td8 is electrically connected to the second power supply end VGL1, and the output end of the eighth pull-down transistor Td8 is electrically connected to the input end of the seventh pull-down transistor Td7.

[0056] Optionally, please continue to refer to Figure 1. In some embodiments, in order to keep the gate control signal REF in a stable valid level state, the second pull-down module 201 is also electrically connected to the first node N1 to transmit the second power signal to the second node N2 according to the potential of the first node N1.

[0057] Optionally, please continue to refer to Figure 2, the second pull-down module 201 includes a ninth pull-down transistor Td9, the control end of the ninth pull-down transistor Td9 is electrically connected to the first node N1, the input end of the ninth pull-down transistor Td9 is electrically connected to the second power supply end VGL1, and the output end of the ninth pull-down transistor Td9 is electrically connected to the second node N2.

[0058] Optionally, in some embodiments, the voltage corresponding to the first power signal is greater than the voltage corresponding to the third power signal supplied by the third power terminal VGH2, and the voltage corresponding to the second power signal is less than the voltage corresponding to the fourth power signal supplied by the fourth power terminal VGL2, so that the first output transistor To1 and the second output transistor To2 can be effectively turned off or turned on, thereby improving the reliability of transistor closing and opening.

[0059] It can be understood that each transistor included in the gate driving circuit can be one of an N-type transistor and a P-type transistor, and each transistor included in the gate driving circuit can be one of an oxide transistor and a silicon transistor.

[0060] Figure 3 is a timing diagram of a gate drive circuit according to an embodiment of the present invention. Taking the case where all transistors included in the gate drive circuit are N-type transistors as an example, the working principle of the gate drive circuit will be described.

[0061] Continuing to refer to FIG. 2 and FIG. 3 , the operation process of the gate driving circuit includes a first stage t1 to a sixth stage t6 .

[0062] In the first phase t1 , the second start signal INI2 has a high level state, and the first start signal INI1 and the pull-down control signal Gn have a low level state.

[0063] The first pull-down transistor Td1 and the second pull-down transistor Td2 are turned on, the second power signal is transmitted to the third node N3, the first transistor T1 and the second transistor T2 are turned off, and the electrical connection between the first power terminal VGH1 and the third node N3 is disconnected.

[0064] In the second phase t2 , the first start-up signal INI1 and the second start-up signal INI2 are in a high level state, and the pull-down control signal Gn is in a low level state.

[0065] The first pull-up transistor Tu1, the third pull-down transistor Td3, the first pull-down transistor Td1, and the second pull-down transistor Td2 are turned on, the first power signal is transmitted to the first node N1, the first output transistor To1, the sixth pull-down transistor Td6, and the ninth pull-down transistor Td9 are turned on, the second power signal is transmitted to the second node N2 and the third node N3, and the third power signal is transmitted to the output terminal of the gate drive circuit, so that the gate control signal REF has an active level state. The first transistor T1, the second transistor T2, the fourth pull-down transistor Td4, the fifth pull-down transistor Td5, the seventh pull-down transistor Td7, the eighth pull-down transistor Td8, the second pull-up transistor Tu2, the third pull-up transistor Tu3, and the second output transistor To2 are turned off.

[0066] In the third phase t3 , the first start signal INI1 is in a high level state, and the pull-down control signal Gn and the second start signal INI2 are in a low level state.

[0067] The first pull-up transistor Tu1, the third pull-down transistor Td3, the first output transistor To1, the sixth pull-down transistor Td6, and the ninth pull-down transistor Td9 remain turned on, and the gate control signal REF remains at an active level. The first transistor T1, the second transistor T2, the fourth pull-down transistor Td4, the fifth pull-down transistor Td5, the seventh pull-down transistor Td7, the eighth pull-down transistor Td8, the second pull-up transistor Tu2, the third pull-up transistor Tu3, and the second output transistor To2 remain turned off, and the first pull-down transistor Td1 and the second pull-down transistor Td2 are turned off.

[0068] In the fourth phase t4 , the pull-down control signal Gn, the first start-up signal INI1 , and the second start-up signal INI2 are in a low level state.

[0069] The second capacitor C2 maintains the potential of the first node N1, so that the first output transistor To1, the sixth pull-down transistor Td6, and the ninth pull-down transistor Td9 remain turned on, and the gate control signal REF remains at an active level. The first transistor T1, the second transistor T2, the first pull-down transistor Td1, the second pull-down transistor Td2, the third pull-down transistor Td3, the fourth pull-down transistor Td4, the fifth pull-down transistor Td5, the seventh pull-down transistor Td7, the eighth pull-down transistor Td8, the first pull-up transistor Tu1, the second pull-up transistor Tu2, the third pull-up transistor Tu3, and the second output transistor To2 are turned off.

[0070] In the fifth stage t5 , the pull-down control signal Gn is in a high level state, and the first start-up signal INI1 and the second start-up signal INI2 are in a low level state.

[0071] The second pull-up transistor Tu2, the third pull-up transistor Tu3, the fourth pull-down transistor Td4, and the fifth pull-down transistor Td5 are turned on, the pull-down control signal Gn is transmitted to the third node N3, the second power signal is transmitted to the first node N1, and the sixth pull-down transistor Td6, the ninth pull-down transistor Td9, and the first output transistor To1 are turned off. Due to the influence of the first capacitor C1, it takes a certain amount of time for the potential of the third node N3 to rise, and thus it also takes a certain amount of time for the first transistor T1 and the second transistor T2 to transition from an off state to an on state. After the first transistor T1 and the second transistor T2 are turned on, the first power signal is transmitted to the second node N2, the seventh pull-down transistor Td7, the eighth pull-down transistor Td8, and the second output transistor To2 are turned on, the second power signal is transmitted to the first node N1, and the fourth power signal is transmitted to the output terminal of the gate drive circuit, causing the gate control signal REF to have an inactive level. The first pull-up transistor Tu1 , the first pull-down transistor Td1 , the second pull-down transistor Td2 , and the third pull-down transistor Td3 are turned off.

[0072] In the sixth phase t6 , the pull-down control signal Gn, the first start-up signal INI1 , and the second start-up signal INI2 are in a low level state.

[0073] The potential of the third node N3 is maintained at a high level by the first capacitor C1 and the first transistor T1. The second transistor T2, the seventh pull-down transistor Td7, the eighth pull-down transistor Td8, and the second output transistor To2 remain turned on. The gate control signal REF remains at an inactive level. The first to third pull-up transistors Tu1 to Tu3, the first to sixth pull-down transistors Td1 to Td6, the ninth pull-down transistor Td9, and the first output transistor To1 remain turned off.

[0074] The gate drive circuit provided in an embodiment of the present application utilizes the second pull-down module 201 to transmit the second power signal to the third node N3 according to the second start signal INI2 before the first power signal is transmitted to the first node N1. This accelerates the lowering of the potential of the third node N3 using the second power signal, thereby effectively turning off the first transistor T1 and the second transistor T2, thereby disconnecting the electrical connection between the first power terminal VGH1 and the second node N2. This prevents the first power signal from acting on the third node N3 when the first pull-up module 101 transmits the first power signal to the first node N1 according to the first start signal INI1. This alleviates the problem of the second node N2 receiving both the first and second power signals simultaneously, causing the first output transistor To1 and the second output transistor To2 to be turned on simultaneously, thereby affecting the normal operation of the gate drive circuit. When the gate drive circuit is applied to a display panel, it can also alleviate the display dark line and burn-in issues that may occur on the display panel.

[0075] In some embodiments, the gate drive circuit shown in FIG2 may be used in medium- to large-sized display panels. The display panels may include passively emitting display panels (e.g., liquid crystal display panels) or self-emitting display panels (e.g., display panels including at least one of organic light-emitting diodes, sub-millimeter light-emitting diodes, and micro-light-emitting diodes).

[0076] FIG4 is a schematic diagram of the structure of a display panel provided by an embodiment of the present application. The embodiment of the present application further provides a display panel including a first gate driving unit GA, wherein the first gate driving unit GA includes a plurality of any of the above-mentioned gate driving circuits (such as Ga1 in FIG4 ).

[0077] Optionally, the display panel further includes a second gate driving unit GB, the second gate driving unit GB being electrically connected to the first gate driving unit GA, and the second gate driving unit GB being configured to generate a plurality of start signals INI for output to the plurality of gate driving circuits Ga1 of the first gate driving unit GA. The start signals INI include the first start signal INI1 and the second start signal INI2.

[0078] Optionally, the second gate driving unit GB includes a plurality of first gate driving circuits Gb1, each of which is configured to generate the startup signal INI. The first startup signal INI1 and the second startup signal INI2 are generated by different first gate driving circuits Gb1.

[0079] Figure 5 is a structural diagram of the m-th level gate drive circuit provided in an embodiment of the present application, and Figure 6 is a timing diagram of the corresponding m-th level gate drive circuit provided in an embodiment of the present application. Optionally, the n-th level start signal INI(n) generated by the n-th level first gate drive circuit Gb1(n) is used as the second start signal INI2 of the m-th gate drive circuit Ga1(m), and the n+1-th level start signal INI(n+1) generated by the n+1-th level first gate drive circuit Gb1(n+1) is used as the first start signal INI1 of the m-th gate drive circuit Ga1(m). Among them, the m-th gate drive circuit Ga1(m) outputs the m-th level gate control signal REF(m), and the effective pulse of the n-th level start signal INI(n) is ahead of the effective pulse INI(n+1) of the n+1-th level start signal. Among them, n>0, m>0.

[0080] Optionally, in some embodiments, each of the first gate driver circuits Gb1 is configured to generate a pull-down control signal Gn. Optionally, the n-1th-stage pull-down control signal Gn(n-1) generated by the n-1th-stage first gate driver circuit Gb1(n-1) is used as the pull-down control signal Gn of the mth gate driver circuit Ga1(m).

[0081] Optionally, the timing of the n-1th level pull-down control signal Gn(n-1) generated by the n-1th level first gate drive circuit Gb1(n-1) and the nth level pull-down control signal Gn(n) generated by the nth level first gate drive circuit Gb1(n) is shown in Figure 6.

[0082] Optionally, in some embodiments, the display panel further includes a third gate driving unit GC, which is electrically connected to the first gate driving unit GA, and the third gate driving unit GC is used to generate a plurality of the pull-down control signals Gn to output to the plurality of the gate driving circuits Ga1 of the first gate driving unit GA.

[0083] Optionally, the third gate driving unit GC includes a plurality of second gate driving circuits, each of the second gate driving circuits is configured to generate the pull-down control signal Gn.

[0084] Optionally, the x-1th stage pull-down control signal Gn(x-1) generated by the x-1th stage second gate driving circuit Gc1(x-1) is used as the pull-down control signal Gn of the mth gate driving circuit Ga1(m), where x>0.

[0085] When the gate drive circuit is applied in the display panel, since the second pull-up transistor Tu2, the third pull-up transistor Tu3, the fourth pull-down transistor Td4 and the fifth pull-down transistor Td5 are all controlled by the pull-down control signal Gn, the resistive and capacitive load corresponding to each of the second gate drive circuits is large, which can reduce the probability of the pull-down control signal Gn having a small pulse width effective pulse, which is beneficial to reducing the risk of leakage, reducing the probability of short circuit between the low voltage of the pull-down control signal Gn and the first power supply signal, and is beneficial to improving the stability of the gate drive circuit.

[0086] Optionally, in some embodiments, the display panel may be used to implement designs such as variable refresh rate, high resolution, or low power consumption.

[0087] Optionally, please continue to refer to FIG. 4 , the display panel further includes a plurality of sub-pixels Spi, and the plurality of sub-pixels Spi are electrically connected to the first gate driving unit GA and the second gate driving unit GB.

[0088] Optionally, each of the sub-pixels Spi includes a light-emitting device Di and a pixel driving circuit electrically connected to the light-emitting device Di.

[0089] 7 is a schematic diagram of the structure of a pixel driving circuit provided by an embodiment of the present application. The pixel driving circuit includes a driving transistor Tdr, a data transistor Tda, a reset transistor Ti1, an initialization transistor Ti2, a switch transistor Ts, and a storage capacitor Cst.

[0090] The control end of the driving transistor Tdr is electrically connected to the output end of the data transistor Tda, the input end of the driving transistor Tdr is electrically connected to the output end of the switching transistor Ts, and the output end of the driving transistor Tdr is electrically connected to the anode of the light emitting device Di.

[0091] The control end of the data transistor Tda is used to receive a write control signal, and the input end of the data transistor Tda is used to receive a corresponding data signal Vdata.

[0092] The control end of the reset transistor Ti1 is used to receive a reset control signal, the input end of the reset transistor Ti1 is used to receive a reset signal Vini, and the output end of the reset transistor Ti1 is electrically connected to the anode of the light-emitting device Di.

[0093] The control terminal of the initialization transistor Ti2 is used to receive a compensation control signal, the input terminal of the initialization transistor Ti2 is used to receive an initialization signal Vref, and the output terminal of the reset transistor Ti1 is electrically connected to the control terminal of the driving transistor Tdr.

[0094] The control end of the switch transistor Ts is used to receive a light emitting control signal EM, the input end of the switch transistor Ts is electrically connected to the first voltage end VDD, and the output end of the switch transistor Ts is electrically connected to the input end of the driving transistor Tdr.

[0095] The cathode of the light emitting device Di is electrically connected to the second voltage terminal VSS.

[0096] Optionally, in some embodiments, the control end of the initialization transistor Ti2 is electrically connected to the corresponding gate drive circuit Ga1, so as to utilize the gate control signal REF generated by the corresponding gate drive circuit Ga1 as the compensation control signal to control the conduction and cutoff of the initialization transistor Ti2.

[0097] Optionally, in some embodiments, the control end of the data transistor Tda is electrically connected to the corresponding first gate drive circuit Gb1, so as to use the pull-down control signal Gn generated by the corresponding first gate drive circuit Gb1 as the write control signal to control the conduction and cutoff of the data transistor Tda.

[0098] Optionally, in some embodiments, the control end of the reset transistor Ti1 is electrically connected to the corresponding first gate drive circuit Gb1, so as to utilize the start signal INI generated by the corresponding first gate drive circuit Gb1 as the reset control signal to control the conduction and cutoff of the reset transistor Ti1.

[0099] By electrically connecting the control end of the initialization transistor Ti2 to the corresponding gate drive circuit Ga1, the control end of the data transistor Tda to the corresponding first gate drive circuit Gb1, the control end of the reset transistor Ti1 to the corresponding first gate drive circuit Gb1, and electrically connecting the gate drive circuit Ga1 to the first gate drive circuit Gb1, the first gate drive circuit Gb1 can simultaneously control the gate drive circuit Ga1 and the pixel drive circuit, which is beneficial to reducing the circuit complexity of the display panel, saving wiring space, and reducing power consumption and cost.

[0100] Optionally, in some embodiments, the control end of the data transistor Tda is electrically connected to the second gate driving circuit Gc1 corresponding to the control end, so as to utilize the pull-down control signal Gn generated by the corresponding second gate driving circuit Gc1 as the write control signal to control the conduction and cutoff of the data transistor Tda.

[0101] By electrically connecting the control end of the initialization transistor Ti2 to the corresponding gate drive circuit Ga1, electrically connecting the control end of the data transistor Tda to the corresponding second gate drive circuit Gc1, electrically connecting the control end of the reset transistor Ti1 to the corresponding first gate drive circuit Gb1, and electrically connecting the gate drive circuit Ga1 to the first gate drive circuit Gb1 and the second gate drive circuit Gc1, the first gate drive circuit Gb1 and the second gate drive circuit Gc1 can simultaneously control the gate drive circuit Ga1 and the pixel drive circuit, which is beneficial to reducing the circuit complexity of the display panel, saving wiring space, and reducing power consumption and cost.

[0102] Optionally, designs of the first gate driving circuit Gb1 and the second gate driving circuit Gc1 may be obtained by referring to related designs.

[0103] Optionally, the gate driving circuit provided in the embodiment of the present application may be integrated on a substrate (ie, Gate On Array, GOA).

[0104] FIG8 is a verification diagram provided by an embodiment of the present application. The inventors verified the gate drive circuit provided by the embodiment of the present application in an actual high temperature and high humidity experiment. The verification results show that when the existing gate drive circuit is used in both 14-inch and 17-inch display panels, dark line problems will appear during the display process of the display panel, and the yield of the display panel is about 50% to 60%. However, when the gate drive circuit shown in FIG2 is used in 14-inch and 17-inch display panels, the display effect of the display panel is better, and the yield of the display panel is about 93.3%. Therefore, the gate drive circuit provided by the embodiment of the present application can reduce the risk of high voltage and low voltage short circuits at key nodes of the gate drive circuit (such as the second node N2, the third node N3, and the output end of the first transistor T1), and the product yield can be increased from 50% to 60% to 93.3%.

[0105] The gate drive circuit provided in this application has been applied to a 14-inch rigid high-resolution display panel.

[0106] The gate drive circuit provided in the embodiment of the present application utilizes the second start signal INI2 to control the decrease of the potential of the third node N3, then utilizes the first start signal INI1 to control the increase of the potential of the first node N1 and the decrease of the potential of the second node N2, and finally utilizes the pull-down control signal Gn to control the decrease of the potential of the first node N1 and the increase of the potential of the second node N2. This is conducive to achieving the stability of the operation of the second pull-down module 201 and the pull-down maintaining module 202, and can reduce the probability of dark lines and burn-in problems occurring on the display panel using the gate drive circuit.

[0107] This document uses specific examples to illustrate the principles and implementation methods of this application. The description of the above embodiments is only used to help understand the method and core ideas of this application. At the same time, for technical personnel in this field, based on the ideas of this application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as limiting this application.

Claims

1. A gate driving circuit, wherein, Including: A first pull-up module, electrically connected to a first node and a first power supply terminal, configured to transmit a first power signal supplied by the first power supply terminal to the first node according to a first start signal; A second pull-down module, electrically connected to a second node, a third node and a second power supply terminal, configured to transmit a second power signal supplied by the second power supply terminal to the second node according to the first start signal; A pull-down maintenance module, electrically connected to the second node, the third node and the first power supply terminal, configured to control the electrical connection between the first power supply terminal and the second node according to the potential of the third node; And An output module, electrically connected to the first node and the second node, configured to output a gate control signal according to the potentials of the first node and the second node; Wherein, before the first pull-up module transmits the first power signal to the first node according to the first start signal, the second pull-down module transmits the second power signal to the third node according to a second start signal, and the pull-down maintenance module disconnects the electrical connection between the first power supply terminal and the second node according to the potential of the third node.

2. The gate driving circuit according to claim 1, wherein, Further including: A first pull-down module, electrically connected to the first node and the second power supply terminal, configured to transmit the second power signal to the first node according to a pull-down control signal; A second pull-up module, electrically connected to the third node, configured to transmit the pull-down control signal to the third node according to the pull-down control signal.

3. The gate driving circuit according to claim 2, wherein, The second pull-down module includes: A first pull-down transistor, the control terminal of the first pull-down transistor is configured to receive the second start signal, and the input terminal of the first pull-down transistor is electrically connected to the second power supply terminal; A second pull-down transistor, the control terminal of the second pull-down transistor is configured to receive the second start signal, the input terminal of the second pull-down transistor is electrically connected to the output terminal of the first pull-down transistor, and the output terminal of the second pull-down transistor is electrically connected to the third node; and A third pull-down transistor, the control terminal of the third pull-down transistor is configured to receive the first start signal, the input terminal of the third pull-down transistor is electrically connected to the second power supply terminal, and the output terminal of the third pull-down transistor is electrically connected to the second node.

4. The gate driving circuit according to claim 3, wherein The first pull-up module includes a first pull-up transistor, the control terminal of the first pull-up transistor is configured to receive the first start signal, the input terminal of the first pull-up transistor is electrically connected to the first power supply terminal, and the output terminal of the first pull-up transistor is electrically connected to the first node; The pull-down maintaining module includes a first transistor, a second transistor, and a first capacitor. The control terminals of the first transistor and the second transistor are electrically connected to the third node. The input terminals of the first transistor and the second transistor are electrically connected to the first power supply terminal. The output terminal of the first transistor is electrically connected to the output terminal of the first pull-down transistor. The output terminal of the second transistor is electrically connected to the second node. The first end of the first capacitor is electrically connected to the third node, and the second end of the first capacitor is electrically connected to the input terminal of the second transistor.

5. The gate driving circuit according to claim 4, wherein The second pull-up module includes: A second pull-up transistor, the control terminal of the second pull-up transistor is configured to receive the pull-down control signal, the input terminal of the second pull-up transistor is electrically connected to the control terminal of the second pull-up transistor, and the output terminal of the second pull-up transistor is electrically connected to the output terminal of the first transistor; and A third pull-up transistor, the control terminal of the third pull-up transistor is configured to receive the pull-down control signal, the input terminal of the third pull-up transistor is electrically connected to the output terminal of the second pull-up transistor, and the output terminal of the third pull-up transistor is electrically connected to the third node.

6. The gate driving circuit according to claim 2, wherein, The first pull-down module includes: A fourth pull-down transistor, the control terminal of the fourth pull-down transistor is configured to receive the pull-down control signal, and the input terminal of the fourth pull-down transistor is electrically connected to the second power supply terminal; and A fifth pull-down transistor, the control terminal of the fifth pull-down transistor is configured to receive the pull-down control signal, the input terminal of the fifth pull-down transistor is electrically connected to the output terminal of the fourth pull-down transistor, and the output terminal of the fifth pull-down transistor is electrically connected to the first node.

7. The gate driving circuit according to claim 6, wherein, The first pull-down module includes: A sixth pull-down transistor, the control terminal of the sixth pull-down transistor is electrically connected to the first node, the input terminal of the sixth pull-down transistor is electrically connected to the first power supply terminal, and the output terminal of the sixth pull-down transistor is electrically connected to the output terminal of the fourth pull-down transistor; A seventh pull-down transistor, the control terminal of the seventh pull-down transistor is electrically connected to the second node, the input terminal of the seventh pull-down transistor is electrically connected to the output terminal of the sixth pull-down transistor, and the output terminal of the seventh pull-down transistor is electrically connected to the first node; and An eighth pull-down transistor, the control terminal of the eighth pull-down transistor is electrically connected to the second node, the input terminal of the eighth pull-down transistor is electrically connected to the second power supply terminal, and the output terminal of the eighth pull-down transistor is electrically connected to the input terminal of the seventh pull-down transistor.

8. The gate driving circuit according to claim 1, wherein The second pull-down module includes a ninth pull-down transistor, the control terminal of the ninth pull-down transistor is electrically connected to the first node, the input terminal of the ninth pull-down transistor is electrically connected to the second power supply terminal, and the output terminal of the ninth pull-down transistor is electrically connected to the second node; The output module includes a first output transistor, a second output transistor, and a second capacitor. The control terminal of the first output transistor is electrically connected to the first node. The input terminal of the first output transistor is electrically connected to a third power supply terminal. The output terminal of the first output transistor is electrically connected to the output terminal of the gate driving circuit. The control terminal of the second output transistor is electrically connected to the second node. The input terminal of the second output transistor is electrically connected to a fourth power supply terminal. The output terminal of the second output transistor is electrically connected to the output terminal of the gate driving circuit. The first end of the second capacitor is electrically connected to the control terminal of the first output transistor, and the second end of the second capacitor is electrically connected to the output terminal of the first output transistor.

9. The gate driving circuit according to claim 8, wherein, The voltage corresponding to the first power signal is greater than the voltage corresponding to the third power signal supplied by the third power supply terminal, and the voltage corresponding to the second power signal is less than the voltage corresponding to the fourth power signal supplied by the fourth power supply terminal.

10. A display panel, wherein, Comprising: A first gate driving unit, including a plurality of gate driving circuits. The gate driving circuit includes a first pull-up module, a second pull-down module, a pull-down maintaining module, and an output module. The first pull-up module is electrically connected to the first node and a first power supply terminal. The first pull-up module is configured to transmit the first power signal supplied by the first power supply terminal to the first node according to a first start signal. The second pull-down module is electrically connected to the second node, the third node, and a second power supply terminal. The second pull-down module is configured to transmit the second power signal supplied by the second power supply terminal to the second node according to the first start signal. The pull-down maintaining module is electrically connected to the second node, the third node, and the first power supply terminal. The pull-down maintaining module is configured to control the electrical connection between the first power supply terminal and the second node according to the potential of the third node. The output module is electrically connected to the first node and the second node. The output module is configured to output a gate control signal according to the potentials of the first node and the second node. Wherein, before the first pull-up module transmits the first power signal to the first node according to the first start signal, the second pull-down module transmits the second power signal to the third node according to a second start signal, and the pull-down maintaining module disconnects the electrical connection between the first power supply terminal and the second node according to the potential of the third node; and A second gate driving unit, electrically connected to the first gate driving unit, configured to generate a plurality of start signals for output to the plurality of gate driving circuits of the first gate driving unit; wherein, the start signals include the first start signal and the second start signal.

11. The display panel according to claim 10, wherein, The nth-level start signal generated by the nth-level first gate driving circuit is used as the second start signal of the mth-level gate driving circuit, and the (n + 1)th-level start signal generated by the (n + 1)th-level first gate driving circuit is used as the first start signal of the mth gate driving circuit.

12. The display panel according to claim 10, wherein, The plurality of the first gate driving circuits are configured to generate a plurality of pull-down control signals for output to the plurality of gate driving circuits of the first gate driving unit.

13. The display panel according to claim 12, wherein, The (n-1)-th level pull-down control signal generated by the (n-1)-th level first gate driving circuit is used as the pull-down control signal of the m-th level gate driving circuit.

14. The display panel according to claim 10, wherein, The display panel includes: A plurality of sub-pixels, each sub-pixel including a light-emitting device and a pixel driving circuit electrically connected to the light-emitting device; the pixel driving circuit includes a driving transistor, a data transistor, a reset transistor, and an initialization transistor, an input end of the data transistor is configured to receive a corresponding data signal, a control end of the driving transistor is electrically connected to an output end of the data transistor, an input end of the reset transistor is configured to receive a reset signal, an output end of the reset transistor, an output end of the driving transistor are electrically connected to an anode of the light-emitting device, an input end of the initialization transistor is configured to receive an initialization signal, and an output end of the reset transistor is electrically connected to a control end of the driving transistor; Wherein, a control end of the initialization transistor is electrically connected to a corresponding gate driving circuit, a control end of the data transistor is electrically connected to a corresponding first gate driving circuit, and a control end of the reset transistor is electrically connected to a corresponding first gate driving circuit.

15. The display panel according to claim 14, wherein, The pixel driving circuit includes a switching transistor, a control end of the switching transistor is configured to receive a light emission control signal, an input end of the switching transistor is electrically connected to a first voltage terminal, and an output end of the switching transistor is electrically connected to an input end of the driving transistor.

Images