3c-sic epitaxial wafer having high crystal quality and high uniformity

Abstract

The present application relates to the technical field of semiconductor manufacturing, and discloses a 3C-SiC epitaxial wafer having high crystal quality. The 3C-SiC epitaxial wafer is heteroepitaxial, and the 3C-SiC epitaxial wafer has a DPB less than 100 pieces / cm2, has a much higher crystal quality than existing 3C-SiC epitaxial wafers and has more available area, increasing the utilization rate of the 3C-SiC epitaxial wafer, reducing the costs of a semiconductor device manufactured by using the 3C-SiC epitaxial wafer, facilitating industrial popularization and use.

Description

A high-quality, crystallized, and uniform 3C-SiC epitaxial wafer

[0001] This application claims priority to the Chinese patent application filed with the Patent Office of China on December 25, 2023, with application number 202311802415.6 and invention name “A high-quality crystalline 3C-SiC epitaxial wafer”, and the Chinese patent application filed with the Patent Office of China on December 25, 2023, with application number 202311803985.7 and invention name “A high-uniformity 3C-SiC epitaxial wafer”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of semiconductor manufacturing technology, and in particular to a 3C-SiC epitaxial wafer with high-quality crystallization and high uniformity. Background Art

[0003] Silicon carbide has many crystal forms, the most common of which are 4H, 6H, and 3C. Currently, the majority of commercially available silicon carbide is 4H-SiC. 3C-SiC is the only one of these polymorphs with a cubic structure, and therefore has several potential applications.

[0004] In addition to having the same wide bandgap properties as other polytypes, the 3C-SiC crystal form also has higher electron mobility and better electron drift velocity, which will benefit MOSFET and HEMT devices. In addition, due to the high electron drift velocity of 3C-SiC, it can also be used as a conducting electrode to reduce resistivity.

[0005] However, traditional 3C-SiC heteroepitaxial growth is performed on Si substrates via CVD (chemical vapor deposition) methods, which can result in severe lattice mismatch, such as an 8% incompatibility in the thermal expansion coefficient and a 20% mismatch in the lattice constant. This results in poor 3C-SiC crystallization quality and a high density of defects, such as stacking faults, voids, and antiphase defects (APDs).

[0006] Therefore, researchers now tend to choose hexagonal substrates for epitaxial growth of 3C-SiC, such as 4H-SiC and 6H-SiC. However, this will introduce a new type of defect, namely DPB (Double Position Boundary). The cause of the DPB defect is that 3C-SiC has two different arrangements, namely ABC and ACB. Therefore, when epitaxial growth is carried out on 4H-SiC or 6H-SiC, these two crystal forms will inevitably grow, and their boundary is the DPB defect. Therefore, the 3C-SiC epitaxial wafers currently obtained by epitaxial growth on 4H-SiC and 6H-SiC have a high density of DPB defects, which seriously hinder the further application of 3C-SiC substrates.

[0007] Currently, the temperature fields during 3C-SiC epitaxial growth are mainly divided into two types: high center temperature and low edge temperature and low center temperature and high edge temperature. Both of the above two types result in uneven temperature distribution at the edge and center of the epitaxial wafer during growth. Temperature has a great impact on the growth rate and doping of the epitaxial wafer. Therefore, the thickness and doping uniformity of the epitaxial wafers grown by previous processes are difficult to control, which reduces the quality of the epitaxial wafers. In addition, the uneven temperature field distribution is more likely to introduce stress into the epitaxial wafer, resulting in a higher defect density in the epitaxial wafer, thereby affecting the use of 3C-SiC epitaxial wafers.

[0008] Summary of the Invention

[0009] In order to solve the above technical problems, the present application provides a high-quality crystalline and highly uniform 3C-SiC epitaxial wafer, wherein the DPB of the 3C-SiC epitaxial wafer is less than 100 per cm 2 The crystal quality and uniformity are much higher than those of existing 3C-SiC epitaxial wafers, and it has more available area, which improves its utilization rate, thereby reducing the cost of semiconductor devices made using it and facilitating its industrial promotion and use.

[0010] The present application provides a high-quality, crystalline, and highly uniform 3C-SiC epitaxial wafer, wherein the 3C-SiC epitaxial wafer is heteroepitaxial and has a DPB of less than 100 per cm 2 .

[0011] Optionally, at least 40 cm 2 There is no DPB in the entire area.

[0012] The entire area refers to an area defined by a smooth curve or straight line. The shape of the entire area can be any one of a triangle, rectangle, circle, ellipse, or polygon (with a side length not exceeding 8). The larger the area of ​​the entire area without DPB, the larger the available area of ​​the 3C-SiC epitaxial wafer. Therefore, the same epitaxial wafer can be cut into a greater number of qualified products, and the number of devices made using the qualified products is greater, thereby reducing the manufacturing cost of the device and expanding production on a large scale. Compared with the area with good crystallization quality, the increase in DPB density can be clearly seen at the edge position. It can be considered that while reducing the DPB density, the DPB is limited to the edge position for growth, thereby increasing the area of ​​the DPB-free area.

[0013] Optionally, the 3C-SiC epitaxial wafer is divided into concentric regions every 15 mm from the center, and the DPB density in the concentric regions increases from the center to the edge.

[0014] Optionally, the difference in DPB density between adjacent concentric areas is 0-500 / cm 2 .

[0015] Optionally, the difference in DPB density between adjacent concentric areas is 0-350 / cm 2 .

[0016] Optionally, the closer to the edge, the greater the difference in DPB density between adjacent concentric regions.

[0017] The center of the 3C-SiC epitaxial wafer to 15mm is taken as the central circle, and every 15mm from the edge of the central circle outward is a concentric ring. The DPB density, doping uniformity and thickness uniformity within the central circle and each concentric ring are calculated separately. The concentric area here refers to the central circle and multiple concentric rings collectively.

[0018] Optionally, the resistivity of the 3C-SiC epitaxial wafer is 0.001-100Ω·cm.

[0019] Optionally, the resistivity of the 3C-SiC epitaxial wafer decreases from the center to the edge, with the highest point being the center.

[0020] The resistivity of 3C-SiC epitaxial wafer reflects the conductive performance of the product. The lower the resistivity, the better the quality of the epitaxial wafer and the higher the quality of the prepared device.

[0021] Optionally, the surface roughness Ra of the 3C-SiC epitaxial wafer is less than 0.2 nm.

[0022] The smaller the surface roughness of the 3C-SiC epitaxial wafer, the better the surface quality of the epitaxial wafer and the higher its application value.

[0023] Optionally, the diameter of the 3C-SiC epitaxial wafer is not less than 6 inches.

[0024] Optionally, the diameter of the 3C-SiC epitaxial wafer is not less than 8 inches.

[0025] The larger the diameter of the 3C-SiC epitaxial wafer, the larger the area without DPB, that is, the more effectively utilized area, the more qualified products obtained after cutting the same epitaxial wafer, and the more devices prepared, which can improve the utilization rate of the epitaxial wafer and reduce the production cost of the device.

[0026] Optionally, the off-angle of the 3C-SiC epitaxial wafer is ≤4°.

[0027] Optionally, the off-angle of the 3C-SiC epitaxial wafer is ≤1°.

[0028] Optionally, the thickness of the 3C-SiC epitaxial wafer is greater than 0.5 μm.

[0029] Optionally, the thickness of the 3C-SiC epitaxial wafer is 0.5-30 μm. The 3C-SiC epitaxial wafer comprises a buffer layer and an epitaxial layer, and the thickness of the buffer layer is 0.1-3 μm.

[0030] Optionally, the thickness distribution of the 3C-SiC epitaxial wafer is gradually thinner from the center to the edge, with the highest point at the center.

[0031] The thicker the 3C-SiC epitaxial wafer is, the higher its withstand voltage is and the wider its application is.

[0032] Optionally, the 3C-SiC epitaxial wafer is obtained by epitaxial growth on a SiC substrate.

[0033] Optionally, the surface roughness Ra of the SiC substrate is less than 1 nm.

[0034] Optionally, the off-angle of the SiC substrate is ≤4°.

[0035] Optionally, the off-angle of the SiC substrate is ≤1°.

[0036] Optionally, the SiC substrate is semi-insulating or conductive.

[0037] Optionally, the conductivity type includes N-type doping and P-type doping.

[0038] Optionally, the crystal orientation of the 3C-SiC epitaxial wafer is (111), and the epitaxial wafer is grown in the (0001) direction of the 4H-SiC or 6H-SiC substrate, and the crystal orientation of the obtained epitaxial wafer is (111), and the crystal orientation changes.

[0039] Optionally, the half-value width of the 3C-SiC epitaxial wafer is less than 60 arcsec.

[0040] Optionally, the half-value width of the 3C-SiC epitaxial wafer is less than 40 arcsec.

[0041] Optionally, the number of micropipes, stacking faults and scratches on the 3C-SiC epitaxial wafer is 0, and the number of surface particles is less than 100 / cm 2 .

[0042] Optionally, the Bow value of the 3C-SiC epitaxial wafer is greater than -10 μm and less than 10 μm, and the Warp value is less than 30 μm.

[0043] Optionally, the Bow value of the 3C-SiC epitaxial wafer is greater than -2.5 μm and less than 5.5 μm, and the Warp value is less than 15 μm.

[0044] Optionally, the uniformity of the doping concentration of the 3C-SiC epitaxial wafer is less than 2%.

[0045] Optionally, the doping concentration is N doping concentration.

[0046] The smaller the uniformity of the doping concentration of the 3C-SiC epitaxial wafer, the more uniform the quality of the epitaxial wafer in various regions, and the more it can improve the conductivity of the epitaxial wafer, thereby improving the quality and service life of the semiconductor device manufactured therefrom.

[0047] Optionally, the thickness uniformity of the 3C-SiC epitaxial wafer is less than 1%.

[0048] The smaller the thickness uniformity of the 3C-SiC epitaxial wafer, the smaller the thickness deviation of the epitaxial wafer, which can increase the number of qualified products obtained from the same epitaxial wafer, that is, improve the utilization rate of the epitaxial wafer and reduce the production cost of semiconductor devices.

[0049] Optionally, the 3C-SiC epitaxial wafer is divided into concentric regions every 15 mm from the center, and the thickness uniformity and doping uniformity of the concentric regions decrease from the center to the edge.

[0050] Optionally, the difference in thickness uniformity between adjacent concentric regions is 0-0.5%, and the difference in doping uniformity between adjacent concentric regions is 0-1.0%, and the closer to the edge, the greater the difference in thickness uniformity and doping uniformity between adjacent concentric regions.

[0051] The DPB density, doping uniformity and thickness uniformity in the central circle are the lowest. The farther away from the center, the DPB density, doping uniformity and thickness uniformity in the concentric rings increase, and the increase is greater.

[0052] The calculation formulas for the above thickness uniformity and doping uniformity are as follows:

[0053]

[0054] U represents uniformity. The smaller the value, the better the uniformity. is the average value of the test points, σ ​​is the standard deviation, and the calculation formula of σ is as follows:

[0055] Among them, x i is the test value at each point, and n is the number of test points. In actual testing, 10-15 points are usually tested along the diameter.

[0056] The production process of the above-mentioned 3C-SiC epitaxial wafer includes the following steps:

[0057] (1) Fixing the SiC substrate;

[0058] (2) Etching the SiC substrate using H2 or HCl at 1600-1700°C for 1-30 min;

[0059] (3) Cooling to 1300-1550°C, introducing a carbon source at a flow rate of 1-20 ml / min, stopping the carbon source after 1-10 minutes, and continuing for 1-3 minutes, introducing nitrogen at a flow rate of 10-500 ml / min, and introducing the carbon source and silicon source according to a carbon-silicon ratio of the carbon source to the silicon source in the range of 0.5-3, controlling the flow rates of the carbon source and the silicon source, first growing a 3C-SiC buffer layer at a growth rate of 0.1-3 μm / h and a growth time of 2-10 minutes; then growing an epitaxial layer at a growth rate of 10-60 μm / h and a growth time of 1-30 minutes, to obtain a 3C-SiC epitaxial wafer.

[0060] At least one of the above technical solutions adopted in the embodiments of the present application can achieve the following beneficial effects:

[0061] 1. The 3C-SiC epitaxial wafer of the present application, which has a thickness of at least 40 cm 2 The entire area is free of DPB, and the available area is greatly increased. In the subsequent device manufacturing, more qualified products can be obtained by cutting the 3C-SiC epitaxial wafer.

[0062] 2. The 3C-SiC epitaxial wafer of the present application has high doping uniformity and thickness uniformity, which can improve the quality of the epitaxial wafer, thereby improving the performance of semiconductor devices prepared using the epitaxial wafer and improving the application value of the 3C-SiC epitaxial wafer.

[0063] 3. The 3C-SiC epitaxial wafer of the present application has a size of at least 6 inches and a thickness of at least 0.3 μm, which increases the effective area available for manufacturing semiconductor devices, thereby saving the production cost of semiconductor devices and improving the utilization rate of the 3C-SiC epitaxial wafer.

[0064] 4. The 3C-SiC epitaxial wafer of the present application solves the problem of severe lattice mismatch in heteroepitaxial 3C-SiC on Si wafers. It is obtained by epitaxial growth on SiC substrates, and can reduce the DPB defect density, thereby expanding the application prospects of 3C-SiC epitaxial wafers. BRIEF DESCRIPTION OF THE DRAWINGS

[0065] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments described in the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0066] In the picture:

[0067] FIG1 is a Raman spectrum of the 3C-SiC epitaxial wafer involved in Example 2 of the present application.

[0068] FIG2 is a picture of the 3C-SiC epitaxial wafer involved in Example 2 of the present application.

[0069] FIG3 is a microscopic enlarged view of point A in FIG2 .

[0070] FIG4 is a microscopic enlarged view of point B in FIG2 .

[0071] FIG5 is a microscopic enlarged image of point C in FIG2 .

[0072] FIG6 is a microscopic enlarged view of point D in FIG2 .

[0073] FIG7 is a microscopic enlarged view of point E in FIG2 .

[0074] FIG8 is a microscopic enlarged view of point F in FIG2 .

[0075] FIG9 is a microscopic enlarged image of point G in FIG2 .

[0076] FIG10 is an AFM test image of the 3C-SiC epitaxial wafer involved in Example 3.

[0077] FIG11 is a schematic diagram of the structure of the graphite disk used in the epitaxial process of Examples 1-9 of the present application.

[0078] FIG12 is a schematic diagram of the structure of the graphite disk used in the epitaxial process of Examples 10-18 of the present application.

[0079] FIG13 is an AFM test image of the 3C-SiC epitaxial wafer involved in Example 10.

[0080] FIG14 is a Raman spectrum of the 3C-SiC epitaxial wafer involved in Example 10 of the present application.

[0081] List of parts and reference numerals:

[0082] In Figure 11: 1, first graphite disk body; 2, first groove; 3, protrusion; 4, first step;

[0083] In Figure 12: 11, second graphite disk body; 12, second groove; 13, second step. DETAILED DESCRIPTION

[0084] The embodiments of the present application provide a 3C-SiC epitaxial wafer with high quality crystallinity and high uniformity.

[0085] In order to enable those skilled in the art to better understand the technical solutions in this application, the technical solutions in the embodiments of this application will be clearly and completely described below in conjunction with the drawings in the embodiments of this application. Obviously, the described embodiments are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of this application.

[0086] The following Examples 1 to 9 utilize the graphite disk shown in FIG. 11 for epitaxial growth. This graphite disk is primarily designed for use in temperature fields with low center temperatures and high edge temperatures. The graphite disk comprises: a first graphite disk body 1, the upper surface of which is recessed downward to form a first groove 2. A protrusion 3 is provided at the center of the first groove 2, the height of which is no greater than that of the first groove 2. Two first steps 4 are circumferentially disposed around the protrusion 3, the height of which is less than that of the protrusion 3 and gradually decreases from the protrusion 3 toward the edge of the first groove 2. Both the protrusion 3 and the first steps 4 are made of graphite. The width of the first step 4 between adjacent protrusions 3 is A, and the diameter of the protrusion 3 is B, with A:B = 1:2. The width of each first step 4 is equal, and the height difference between a protrusion 3 and the first step 4 of an adjacent protrusion 3 is 1 mm. The height difference between adjacent first steps 4 is also 1 mm. When producing 6-inch epitaxial wafers, the diameter of the first graphite disk body 1 is 150 mm, and the diameter of the first groove 2 is 145 mm; when producing 8-inch epitaxial wafers, the diameter of the first graphite disk body 1 is 200 mm, and the diameter of the first groove 2 is 195 mm.

[0087] The graphite disk structure makes the temperature field distribution more uniform and the radial temperature gradient smaller during the epitaxial growth of 3C-SiC epitaxial wafers, so that the obtained 3C-SiC epitaxial wafers have lower defect density and higher crystal quality.

[0088] Example 1

[0089] This embodiment relates to the production and processing of high-quality, crystalline, and uniform 3C-SiC epitaxial wafers, including the following steps:

[0090] (1) Grinding and polishing a semi-insulating SiC substrate to obtain a SiC substrate with good surface flatness, a surface roughness Ra of less than 1 nm, a substrate size of 6 inches, and a deflection angle of ≤4°, and fixing the SiC substrate;

[0091] (2) Etching the SiC substrate using H2 at 1600°C for 30 min;

[0092] (3) Cooling to 1300°C, introducing a carbon source at a flow rate of 1 ml / min, stopping the carbon source after 10 minutes, and continuing for 1 minute, introducing nitrogen at a flow rate of 10 ml / min, and introducing a carbon source and a silicon source at a carbon-silicon ratio of 0.5, controlling the flow rates of the carbon source and the silicon source, first growing a 3C-SiC buffer layer at a growth rate of 0.1 μm / h and a growth time of 10 minutes; then growing an epitaxial layer at a growth rate of 10 μm / h and a growth time of 30 minutes, to obtain a 3C-SiC epitaxial wafer.

[0093] Example 2

[0094] This embodiment relates to the production and processing of high-quality, crystalline, and uniform 3C-SiC epitaxial wafers, including the following steps:

[0095] (1) grinding and polishing an N-type doped SiC substrate to obtain a SiC substrate with good surface flatness, a surface roughness Ra of less than 1 nm, a substrate size of 8 inches, and a deflection angle of ≤1°, and fixing the SiC substrate;

[0096] (2) Etching the SiC substrate using H2 at 1650°C for 20 min;

[0097] (3) Cooling to 1450°C, introducing a carbon source at a flow rate of 10 ml / min, stopping the carbon source after 5 minutes, and continuing for 3 minutes, introducing nitrogen at a flow rate of 300 ml / min, and introducing the carbon source and silicon source at a carbon-silicon ratio of 1. Control the flow rates of the carbon source and silicon source, first grow a 3C-SiC buffer layer, control the growth rate to 2 μm / h, and the growth time to 5 minutes; then grow the epitaxial layer, control the growth rate to 40 μm / h, and the growth time to 20 minutes, to obtain a 3C-SiC epitaxial wafer.

[0098] Example 3

[0099] This embodiment relates to the production and processing of high-quality, crystalline, and uniform 3C-SiC epitaxial wafers, including the following steps:

[0100] (1) Grinding and polishing a P-type doped SiC substrate to obtain a SiC substrate with good surface flatness, a surface roughness Ra of less than 1 nm, a substrate size of 6 inches, and a deflection angle of ≤1°, and fixing the SiC substrate;

[0101] (2) Etching the SiC substrate with HCl at 1700°C for 1 min;

[0102] (3) Cooling to 1550°C, introducing a carbon source at a flow rate of 20 ml / min, stopping the carbon source after 1 minute, and continuing for 3 minutes, introducing nitrogen at a flow rate of 500 ml / min, and introducing a carbon source and a silicon source at a carbon-silicon ratio of 3, controlling the flow rates of the carbon source and the silicon source, first growing a 3C-SiC buffer layer at a growth rate of 3 μm / h and a growth time of 2 minutes; then growing an epitaxial layer at a growth rate of 60 μm / h and a growth time of 1 minute, to obtain a 3C-SiC epitaxial wafer.

[0103] Example 4

[0104] The difference between this embodiment and embodiment 2 is that the carbon-silicon ratio of the carbon source to the silicon source in step (3) is 2, and the remaining steps are the same as those in embodiment 2 to obtain a 3C-SiC epitaxial wafer.

[0105] Example 5

[0106] The difference between this embodiment and embodiment 2 is that the growth rate of the 3C-SiC buffer layer in step (3) is 3 μm / h, and the remaining steps are the same as those in embodiment 2 to obtain a 3C-SiC epitaxial wafer.

[0107] Example 6

[0108] The difference between this embodiment and embodiment 2 is that the growth rate of the epitaxial layer in step (3) is 50 μm / h, and the remaining steps are the same as those in embodiment 2 to obtain a 3C-SiC epitaxial wafer.

[0109] Example 7

[0110] The difference between this embodiment and embodiment 2 is that the flow rate of nitrogen in step (3) is 100 ml / min, and the remaining steps are the same as those in embodiment 2 to obtain a 3C-SiC epitaxial wafer.

[0111] Example 8

[0112] The difference between this embodiment and embodiment 2 is that step (2) is not performed, and the remaining steps are the same as those in embodiment 2 to obtain a 3C-SiC epitaxial wafer.

[0113] Example 9

[0114] The difference between this embodiment and embodiment 2 is that in step (3), no carbon source is introduced in advance, and nitrogen and a carbon source and a silicon source with a carbon-silicon ratio of 1 are directly introduced. The remaining steps are the same as those in embodiment 2 to obtain a 3C-SiC epitaxial wafer.

[0115] The 3C-SiC epitaxial wafer obtained in Example 2 was subjected to Raman testing. The results are shown in Figure 1. The Raman characteristic peak of 3C-SiC is 972 cm -1 , according to the test results of Figure 1, it can be seen that the 3C-SiC epitaxial wafer has been successfully prepared; referring to Figure 2, the 3C-SiC epitaxial wafer obtained in Example 2 is positioned, and a total of 7 test points AG are selected, and the above test points are observed under a microscope. The observation results are shown in Figures 3-9 respectively. It can be seen that the DPB density of the 3C-SiC epitaxial wafer prepared in this application is low. There is no DPB in Figure 3 (point A) to Figure 7 (point E), and there is no DPB in Figures 5-7 (points CE). Instead, there are some 3C nucleation points, which are not defects of the epitaxial wafer. DPB appears in Figure 8 (point F), and DPB increases further in Figure 9 (point G). However, even in the area with more DPBs at point G, the DPB defect density is better than the result of the 3C-SiC epitaxial wafer currently made with SiC substrates, and the G point is at the edge position. The edge position can be cut off in subsequent use, and the epitaxial wafer still has a very large usable area.

[0116] The 3C-SiC epitaxial wafer obtained in the above embodiment was tested. The test results are shown in Tables 1 and 2 below. The number of micropipes, stacking faults, scratches and triangular defects of the 3C-SiC epitaxial wafer was 0, and the number of surface particles was less than 100 / cm 2 The surface roughness Ra in Table 2 was tested using AFM. The AFM test image of the epitaxial wafer of Example 3 is shown in FIG10 , and it can be seen that the surface roughness Ra is 0.191.

[0117] Table 1

[0118] Table 2

[0119] The graphite disk shown in Figure 12 was used in the epitaxial growth described in Examples 10 to 18 below. This disk is primarily designed for use in temperature fields with high center temperatures and low edge temperatures. The disk includes a second graphite disk body 11. The upper surface of the disk body 11 is recessed downward to form a second groove 12. Three second steps 13 are provided from the edge of the groove 12 to its center. These steps 13 are made of graphite and are each less than the height of the groove 12. The heights of the steps 13 decrease gradually and evenly from the edge of the groove 12 to its center, with a height difference of 1 mm between adjacent steps 13. When producing 6-inch epitaxial wafers, the diameter of the second graphite disk body 11 is 150 mm, the diameter of the second groove 12 is 145 mm, and the width of each second step 13 is equal. When producing 8-inch epitaxial wafers, the diameter of the second graphite disk body 11 is 200 mm, the diameter of the second groove 12 is 195 mm, and the width of each second step 13 is equal.

[0120] The graphite disk structure makes the temperature field distribution more uniform and the radial temperature gradient smaller during the epitaxial growth of 3C-SiC thin films, so that the obtained 3C-SiC epitaxial wafers have lower defect density, more uniform thickness distribution, and more uniform doping distribution.

[0121] Example 10

[0122] This embodiment relates to the production and processing of high-quality, crystalline, and highly uniform 3C-SiC epitaxial wafers, including the following steps:

[0123] S1: Grind and polish the semi-insulating SiC substrate to obtain a SiC substrate with good surface flatness and a surface roughness Ra of less than 1 nm. The substrate has a size of 6 inches and a deflection angle of ≤1°, and the SiC substrate is fixed.

[0124] S2: Etching the SiC substrate with HCl at 1700°C for 10 min.

[0125] S3: Cool down to 1400℃, introduce carbon source, the flow rate of carbon source is 20ml / min, stop introducing carbon source after 1min, continue for 2min, introduce nitrogen, the flow rate of nitrogen is 500ml / min, and introduce carbon source and silicon source according to the carbon-silicon ratio of carbon source and silicon source within the range of 1, control the flow rate of carbon source and silicon source, first grow 3C-SiC buffer layer, control the growth rate to 1μm / h, and the growth time is 7min; then grow epitaxial layer, control the growth rate to 30μm / h, and the growth time is 15min, to obtain 3C-SiC epitaxial wafer. Raman test was performed on the 3C-SiC epitaxial wafer obtained in Example 1, and the results are shown in Figure 14. The Raman characteristic peak of 3C-SiC is 972cm -1 According to the test results in FIG14 , it can be seen that the 3C-SiC epitaxial wafer has been successfully prepared.

[0126] Example 11

[0127] This embodiment relates to the production and processing of high-quality, crystalline, and highly uniform 3C-SiC epitaxial wafers, including the following steps:

[0128] S1: Grind and polish the semi-insulating SiC substrate to obtain a SiC substrate with good surface flatness and a surface roughness Ra of less than 1 nm. The substrate size is 8 inches and the deflection angle is ≤1°. The SiC substrate is fixed.

[0129] S2: Etching the SiC substrate with HCl at 1600°C for 30 min.

[0130] S3: Cool down to 1300°C, introduce a carbon source at a flow rate of 15 ml / min, stop introducing the carbon source after 5 minutes, continue introducing nitrogen for 3 minutes, and introduce nitrogen at a flow rate of 100 ml / min. The carbon source and silicon source are introduced according to the carbon-silicon ratio of the carbon source and the silicon source within the range of 3, and the flow rates of the carbon source and the silicon source are controlled. First, grow a 3C-SiC buffer layer at a growth rate of 0.1 μm / h and a growth time of 2 minutes; then grow an epitaxial layer at a growth rate of 60 μm / h and a growth time of 1 minute to obtain a 3C-SiC epitaxial wafer.

[0131] Example 12

[0132] This embodiment relates to the production and processing of high-quality, crystalline, and highly uniform 3C-SiC epitaxial wafers, including the following steps:

[0133] S1: Grind and polish the semi-insulating SiC substrate to obtain a SiC substrate with good surface flatness and a surface roughness Ra of less than 1 nm. The substrate has a size of 6 inches and a deflection angle of ≤4°, and the SiC substrate is fixed.

[0134] S2: Etch the SiC substrate using H2 at 1650°C for 1 min.

[0135] S3: Cool down to 1550℃, introduce carbon source with a flow rate of 1ml / min, stop introducing carbon source after 10min, continue introducing nitrogen with a flow rate of 10ml / min, and introduce carbon source and silicon source according to the carbon-silicon ratio of carbon source to silicon source within the range of 0.5, control the flow rate of carbon source and silicon source, first grow 3C-SiC buffer layer, control the growth rate to 3μm / h, and the growth time to 10min; then grow epitaxial layer, control the growth rate to 10μm / h, and the growth time to 30min, to obtain 3C-SiC epitaxial wafer.

[0136] Example 13

[0137] The difference between this embodiment and embodiment 10 is that the carbon-silicon ratio of the carbon source to the silicon source in step S3 is 2, and the remaining steps are the same as those in embodiment 10 to obtain a 3C-SiC epitaxial wafer.

[0138] Example 14

[0139] The difference between this embodiment and embodiment 10 is that the growth rate of the 3C-SiC buffer layer in step S3 is 3 μm / h, and the remaining steps are the same as those in embodiment 10 to obtain a 3C-SiC epitaxial wafer.

[0140] Example 15

[0141] The difference between this embodiment and embodiment 10 is that the growth rate of the epitaxial layer in step S3 is 45 μm / h, and the remaining steps are the same as those in embodiment 10, to obtain a 3C-SiC epitaxial wafer.

[0142] Example 16

[0143] The difference between this embodiment and embodiment 10 is that the flow rate of nitrogen in step S3 is 300 ml / min, and the remaining steps are the same as those in embodiment 10 to obtain a 3C-SiC epitaxial wafer.

[0144] Example 17

[0145] The difference between this embodiment and embodiment 10 is that step S2 is not performed, and the remaining steps are the same as those in embodiment 10 to obtain a 3C-SiC epitaxial wafer.

[0146] Example 18

[0147] The difference between this embodiment and embodiment 10 is that in step S3, no carbon source is introduced in advance, and nitrogen and a carbon source and a silicon source with a carbon-silicon ratio of 1 are directly introduced. The remaining steps are the same as those in embodiment 10 to obtain a 3C-SiC epitaxial wafer.

[0148] The 3C-SiC epitaxial wafer obtained in the above embodiment was tested. The test results are shown in Tables 3 and 4 below. The number of micropipes, stacking faults, scratches and triangular defects of the 3C-SiC epitaxial wafer was 0, and the number of surface particles was less than 100 / cm 2 The surface roughness Ra in Table 4 was tested using AFM. The AFM test image of the epitaxial wafer of Example 10 is shown in FIG13 , and it can be seen that the surface roughness Ra is 0.174.

[0149] Table 3

[0150] Table 4

[0151] The various embodiments in this application are described in a progressive manner. Similar portions between the various embodiments can be referenced to each other, and each embodiment focuses on the differences from the other embodiments. In particular, the device, apparatus, and non-volatile computer storage medium embodiments are generally similar to the method embodiments, so their descriptions are relatively simple. For relevant portions, refer to the descriptions of the method embodiments.

[0152] Finally, it should be understood that the above embodiments of the present application are intended only to illustrate the technical solutions of the present invention, and are not intended to limit the present invention. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that they may still modify the technical solutions described in the above embodiments, or replace some of the technical features therein with equivalents; and such modifications or replacements do not deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A 3C-SiC epitaxial wafer with high-quality crystallization and high uniformity, wherein, The 3C-SiC epitaxial wafer is heteroepitaxial, and the DPB of the 3C-SiC epitaxial wafer is less than 100 / cm 2 .

2. The 3C-SiC epitaxial wafer according to claim 1, wherein, At least 40 cm of the 3C-SiC epitaxial wafer 2 has no DPB in the entire area.

3. The 3C-SiC epitaxial wafer according to claim 2, wherein, The 3C-SiC epitaxial wafer is divided into a concentric region every 15 mm from the center, and the DPB density in the concentric region increases from the center to the edge direction.

4. The 3C-SiC epitaxial wafer according to claim 3, wherein, The difference in DPB density between adjacent concentric regions is 0 - 500 per cm 2 .

5. The 3C-SiC epitaxial wafer according to claim 1, wherein, The resistivity of the 3C-SiC epitaxial wafer is 0.001 - 100 Ω·cm.

6. The 3C-SiC epitaxial wafer according to claim 1, wherein, The diameter of the 3C-SiC epitaxial wafer is not less than 6 inches.

7. The 3C-SiC epitaxial wafer according to claim 1, wherein, The thickness of the 3C-SiC epitaxial wafer is greater than 0.5 μm.

8. The 3C-SiC epitaxial wafer according to claim 1, wherein, The 3C-SiC epitaxial wafer is obtained by epitaxial growth on a SiC substrate.

9. The 3C-SiC epitaxial wafer according to claim 1, wherein, The number of microtubes, stacking faults, and scratches on the 3C-SiC epitaxial wafer is 0.

10. The 3C-SiC epitaxial wafer according to claim 1, wherein, The full width at half maximum of the 3C-SiC epitaxial wafer is less than 60 arcsec.

11. The 3C-SiC epitaxial wafer according to claim 1, wherein, The uniformity of the doping concentration of the 3C-SiC epitaxial wafer is less than 2%.

12. The 3C-SiC epitaxial wafer according to claim 11, wherein, The doping concentration of the 3C-SiC epitaxial wafer is 1×10 15 / cm 3 -1×10 20 / cm 3 .

13. The 3C-SiC epitaxial wafer according to claim 11, wherein, The doping concentration is the doping concentration of N.

14. The 3C-SiC epitaxial wafer according to claim 11, wherein, The thickness uniformity of the 3C-SiC epitaxial wafer is less than 1%.

15. The 3C-SiC epitaxial wafer according to claim 14, wherein, The 3C-SiC epitaxial wafer is divided into a concentric region every 15 mm from the center, and the thickness uniformity and doping uniformity in the concentric region decrease from the center to the edge direction.

16. The 3C-SiC epitaxial wafer according to claim 15, wherein, The difference in thickness uniformity between adjacent concentric regions is 0 - 0.5%, and the difference in doping uniformity is 0 - 1.0%.

17. The 3C-SiC epitaxial wafer according to claim 1, wherein, The thickness of the 3C-SiC epitaxial wafer is 0.3 - 30 μm.

18. The 3C-SiC epitaxial wafer according to claim 1, wherein, The tilt angle of the SiC substrate is ≤4°.

Images