Processing method and apparatus for processor information, non-volatile readable storage medium, and electronic device

Abstract

Provided are a processing method and apparatus for processor information, a non-volatile readable storage medium, and an electronic device. The method comprises: reading a register value of a specified register by means of a baseboard management controller on a target device, wherein the specified register is located in a specified processor of the target device, and the specified register is a register for storing, on the basis of the register value, error information generated by a group of components in the specified processor (S202); by means of the baseboard management controller and on the basis of a group of specified parameters, analyzing a target register value that has been read, so as to obtain a target analysis result, wherein the group of specified parameters are parameters used for performing error information analysis (S204); and when it is determined, on the basis of the target analysis result, that at least one component in the specified processor generates the error information, recording the target analysis result in a system event log of the baseboard management controller (S206).

Description

Processor information processing method and device, non-volatile readable storage medium and electronic device

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to the Chinese patent application filed with the China Patent Office on December 28, 2023, with application number 202311839058.0 and application name “Processor Information Processing Method and Device, Storage Medium and Electronic Device”, all contents of which are incorporated by reference into this application. Technical Field

[0003] Embodiments of the present application relate to the field of computers, and in particular, to a method and apparatus for processing processor information, a non-volatile readable storage medium, and an electronic device. Background Art

[0004] Processor chips are key chips inside devices such as servers. They contain multiple key components. When errors occur in these components, they will cause serious errors in the entire system of the device. Therefore, these error information needs to be reported to the operating system of the device in a timely manner.

[0005] Currently, the operating system will use specific files (such as dmes g These error messages are recorded in the processor's memory (database file). However, these error messages are usually expressed in binary form, making it difficult to quickly and accurately locate the component within the processor that caused the error. They require analysis of each component using relevant technical documentation. This method of processing processor information significantly reduces work efficiency, especially when dealing with tens of thousands of devices, where probabilistic error reporting significantly reduces fault handling efficiency.

[0006] It can be seen that the method for processing processor information in the related art has the problem of low efficiency in processing processor failures.

[0007] Summary of the Invention

[0008] Embodiments of the present application provide a method and apparatus for processing processor information, a non-volatile readable storage medium, and an electronic device, to at least address the problem of low efficiency in processing processor failures in methods for processing processor information in related technologies.

[0009] According to a first aspect of an embodiment of the present application, a method for processing processor information is provided, comprising: reading a register value of a specified register through a baseboard management controller on a target device, wherein the specified register is located in a specified processor of the target device, and the specified register is a register for storing error information generated by a group of components in the specified processor through register values; parsing the read target register value through the baseboard management controller according to a set of specified parameters to obtain a target parsing result, wherein the set of specified parameters are parameters used for error information parsing; and when it is determined that at least one component in the specified processor has generated error information according to the target parsing result, recording the target parsing result in a system event log of the baseboard management controller.

[0010] According to a second aspect of an embodiment of the present application, a processor information processing device is provided, comprising: a reading unit, configured to read a register value of a specified register through a baseboard management controller on a target device, wherein the specified register is located in a specified processor of the target device, and the specified register is a register for storing error information generated by a group of components in the specified processor through register values; a parsing unit, configured to parse the read target register value according to a set of specified parameters through the baseboard management controller to obtain a target parsing result, wherein the set of specified parameters are parameters used for error information parsing; and a recording unit, configured to record the target parsing result in a system event log of the baseboard management controller when it is determined that at least one component in the specified processor has generated error information based on the target parsing result.

[0011] According to a third aspect of the embodiments of the present application, a non-volatile readable storage medium is further provided, in which a computer program is stored, wherein the computer program is configured to execute the steps of any of the above method embodiments when running.

[0012] According to a fourth aspect of the embodiments of the present application, an electronic device is also provided, including a memory and a processor, wherein a computer program is stored in the memory, and the processor is configured to run the computer program to execute the steps in any of the above method embodiments.

[0013] Through the present application, a method of parsing register values ​​into corresponding character information is adopted. Since the register values ​​that record the error information generated by the components in the processor are binary, it is impossible to quickly and accurately locate the position information of the faulty components of the processor. By parsing the binary values ​​according to certain rules, converting the binary values ​​into corresponding character information and recording them, it is possible to efficiently and quickly locate the processor fault location information. Therefore, it is possible to solve the problem of low processor fault processing efficiency in the processor information processing method in the related art, and achieve the technical effect of improving the processor fault processing efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] FIG1 is a schematic diagram of a hardware environment of a method for processing processor information according to an embodiment of the present application;

[0015] FIG2 is a flow chart of a method for processing processor information according to an embodiment of the present application;

[0016] FIG3 is a schematic diagram of a method for processing processor information according to an embodiment of the present application;

[0017] FIG4 is a schematic diagram of another method for processing processor information according to an embodiment of the present application;

[0018] FIG5 is a schematic diagram of another method for processing processor information according to an embodiment of the present application;

[0019] FIG6 is a schematic diagram of another method for processing processor information according to an embodiment of the present application;

[0020] FIG7 is a schematic diagram of another method for processing processor information according to an embodiment of the present application;

[0021] FIG8 is a schematic diagram of a device for processing processor information according to an embodiment of the present application. DETAILED DESCRIPTION

[0022] The embodiments of the present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0023] It should be noted that the terms "target", "second", etc. in the description and claims of this application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0024] Before describing the embodiments of the present application in detail, the nouns and terms involved in the embodiments of the present application are explained. The nouns and terms involved in the embodiments of the present application are subject to the following interpretations.

[0025] BIOS: Basic Input Output System.

[0026] ARM: Advanced RISC Machine, advanced reduced instruction set processor, a processor architecture.

[0027] CPU: Central Processing Unit, central processing unit.

[0028] dmesg: kernel ring buffer message, a program used to detect and control the kernel ring buffer. The program is used to help users understand the system startup information.

[0029] 0S:Operating System, operating system.

[0030] CPM: Cluster Processor Module, cluster processor module.

[0031] MCU: Memory Controller Unit, memory controller unit.

[0032] Mesh: A CPU internal bus.

[0033] CCIX: Cache Coherent Interconnect for Accelerators, a high-speed cache coherent interconnect technology for accelerators. The CCIX bus is a data transmission method with a layered architecture that is extended from the PCIe architecture.

[0034] Transmission mode can greatly improve data transmission speed.

[0035] 2P ALI: 2P Ampere Link Interconnect, 2P Ampere Link Interconnect.

[0036] GIC: Generic Interrupt Controller, general interrupt controller.

[0037] SMMU: System Memory Management Unit, system memory management unit.

[0038] PCIe AER: PCI Express Advanced Error Reporting, PCI Express Advanced Error Reporting.

[0039] PCIe RC: PCI Express Root Complex.

[0040] OCM: 0n-Chip Memory, on-chip memory.

[0041] SMpro: System Management Processor, system management controller.

[0042] PMpro: Power Panagement Processor, power management controller.

[0043] ARM Processor: standard Arm processor error types, standard ARM processor error types.

[0044] Memory: Memory.

[0045] ATF: Arm Trusted Firmware, ARM security firmware.

[0046] SMpro Firmware: System Management Controller Firmware.

[0047] BERT: Boot Error Record Table, boot error record table.

[0048] I2C: Inter-Integrated Circuit, two-wire serial bus.

[0049] SCP: System Control Processor, system control processor.

[0050] The method embodiments provided in the embodiments of the present application can be executed in a server device or a similar computing device. Taking operation on a server device as an example, FIG1 is a hardware structure block diagram of a server device of a method for processing processor information in an embodiment of the present application. As shown in FIG1 , the server device may include one or more (only one is shown in FIG1 ) processors 102 (the processor 102 may include but is not limited to a processing device such as a microprocessor MCU or a programmable logic device FPGA) and a memory 104 configured to store data, wherein the above-mentioned server device may also include a transmission device 106 and an input and output device 108 for communication functions. It will be understood by those skilled in the art that the structure shown in FIG1 is only for illustration and does not limit the structure of the above-mentioned server device. For example, the server device may also include more or fewer components than those shown in FIG1 , or have a configuration different from that shown in FIG1 .

[0051] The memory 104 can be configured to store computer programs, for example, software programs and modules of application software, such as the computer program corresponding to the method for processing processor information in the embodiment of the present application. The processor 102 executes various functional applications and data processing by running the computer program stored in the memory 104, that is, implementing the above method. The memory 104 may include a high-speed random access memory, and may also include a non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some instances, the memory 104 includes a memory remotely located relative to the processor 102, and these remote memories can be connected to a server device via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0052] The transmission device 106 is configured to receive or transmit data via a network. Examples of such a network may include a wireless network provided by a communication provider of a server device. In one embodiment, the transmission device 106 includes a NIC (Network Interface Controller) that can be connected to other network devices via a base station to communicate with the Internet. In another embodiment, the transmission device 106 may be an RF (Radio Frequency) module that is configured to communicate with the Internet wirelessly.

[0053] In this embodiment, a method for processing processor information is provided. FIG2 is a flow chart of a method for processing processor information according to an embodiment of the present application. As shown in FIG2 , the flow chart includes the following steps:

[0054] Step S202 , reading a register value of a designated register through a baseboard management controller on a target device, wherein the designated register is located in a designated processor of the target device and is a register for storing error information generated by a group of components in the designated processor through register values.

[0055] The method for processing processor information in this embodiment can be applied to a scenario where the location information of a component that generates error information within a processor is determined. For example, in this embodiment, the processor may be an ARM (Advanced RISC Machines, a processor architecture) architecture processor. The ARM architecture processor internally contains multiple components, such as a memory bus device, a PCI link device, an ARM core chip, an SMpro management component, a PMpro management component, a Mesh bus, an OCM device, a CCIX bus, a GIC interrupt error, and other core key components. Once these components generate errors, they will inevitably cause serious or fatal errors to the ARM server system. Therefore, these error messages must be reported to the operating system in a timely manner, and the operating system will record these error messages through the dmesg file. However, these error messages are represented by binary values, and it is impossible to quickly and accurately locate the component location information of the ARM processor. It is necessary to parse and analyze them one by one through relevant technical documents for location analysis, which greatly reduces work efficiency.

[0056] In order to solve at least some of the above problems, in this embodiment, the error register value of the processor is parsed according to certain rules, the binary value is converted into corresponding character information and recorded, so as to facilitate rapid parsing and positioning to achieve efficient and rapid positioning of the processor fault location information. Taking the processor as an ARM processor as an example, the errors generated in the ARM server system are quickly parsed through the BMC firmware and SEL (System Event Log) log is recorded, which facilitates subsequent R&D and operation and maintenance personnel to quickly locate the problem, clarify the components and location information of the problem, and is convenient and fast, reducing the loss of R&D resources of R&D personnel who analyze each device that causes the error, thereby improving work efficiency.

[0057] In this embodiment, the processor is the core computing and control unit of the target device, and the register is an important component of the processor, used to store temporary data and instructions. Here, the target device can be an ARM server, and the designated processor can be an ARM processor. When the designated register is a register used to store error information generated by a group of components in the designated processor through a register value, the register value of the designated register can be read through the baseboard management controller BMC on the target device, and the register value can be expressed in binary form.

[0058] In step S204 , the baseboard management controller parses the read target register value according to a set of specified parameters to obtain a target parsing result, wherein the set of specified parameters is parameters used for error information parsing.

[0059] In order to improve the readability of processor error information, the binary register value read by the BMC can be converted into corresponding character information. In this embodiment, the BMC can parse the read target register value according to a set of specified parameters. The target register value can be used to represent the binary value of the error information generated by a group of components in the specified processor. Different values ​​correspond to different error types and error information.

[0060] For example, in this embodiment, the error information generated by a group of components within the ARM processor includes but is not limited to Mesh bus errors, SMpro error information, PMpro error information, GIC interrupt errors, SMMU error information, CPM error information, OCM error information and other error information of ARM architecture internal buses and components.

[0061] A set of designated parameters is used for error information parsing, so that the BMC can classify register values ​​according to different error types and error messages corresponding to different values. Optionally, in conjunction with FIG3 , the designated parameters may include but are not limited to event type parameters, event identification parameters, error information location parameters, etc., and the parameter values ​​of the designated parameters may be character information corresponding to the binary register values.

[0062] Step S206 : When it is determined according to the target analysis result that at least one component in the designated processor generates error information, the target analysis result is recorded in the system event log of the baseboard management controller.

[0063] The SEL typically records logs of system events and errors, including hardware failures, system crashes, error messages, etc. Similar to the aforementioned embodiment, the target parsing result may be character information corresponding to error information generated by a group of components within a specified processor. If it is determined based on the target parsing result that at least one component within the specified processor has generated error information, the parsed error information character string may be recorded in the BMC's SEL.

[0064] Through the above steps, the register value of the specified register is read by the baseboard management controller on the target device, wherein the specified register is located in the specified processor of the target device, and the specified register is a register used to store error information generated by a group of components in the specified processor through the register value; the read target register value is parsed by the baseboard management controller according to a set of specified parameters to obtain a target parsing result, wherein the set of specified parameters is the parameters used for error information parsing; when it is determined according to the target parsing result that at least one component in the specified processor has generated error information, the target parsing result is recorded in the system event log of the baseboard management controller, which solves the problem of low processor fault processing efficiency in the processor information processing method in the related art and improves the processor fault processing efficiency.

[0065] In an exemplary embodiment, the baseboard management controller parses the read target register value according to a set of specified parameters to obtain a target parsing result, including:

[0066] The baseboard management controller uses a preset parsing tool to parse the read target register value according to a set of specified parameters to obtain a target parsing result, wherein the preset parsing tool is a parsing tool that matches the data structure used by the specified register for data storage.

[0067] Currently, ARM processor error information can be recorded in the dmesg file under conventional systems, but this requires logging into the system and using parsing tools, which is time-consuming and labor-intensive. The Intel platform's BMC obtains CPU (Central Processing Unit) internal register values ​​through a bus and then uses out-of-band tools to parse these values ​​to obtain CPU fault information. This method is similar to parsing fault information on ARM systems and is also time-consuming.

[0068] To at least partially resolve the above technical issues, the BMC on the ARM processor architecture can include a parsing tool in it to form a BMC code program. The register values ​​obtained through I2C are synchronously parsed by the BMC code program and displayed in the BMC's SEL log, which can facilitate R&D and maintenance personnel to quickly locate fault problems.

[0069] For example, the parsing tools correspond to the table shown in Table 1:

[0070] Table 1

[0071] According to this embodiment, by using a parsing tool to parse the read register value, the parsing efficiency of the processor error information can be improved and the labor cost can be reduced.

[0072] In an exemplary embodiment, the baseboard management controller parses the read target register value according to a set of specified parameters to obtain a target parsing result, including:

[0073] The baseboard management controller parses the value of at least one byte corresponding to each specified parameter in a set of specified parameters in the target register value to obtain a parsing result corresponding to each specified parameter, wherein the target parsing result includes the parsing result corresponding to each specified parameter.

[0074] The values ​​of different fields in the target register value may correspond to different specified parameters in a set of specified parameters, and the obtained binary register value may be parsed by the BMC code program. For example, in this embodiment, the BMC code program may parse the data structure of the target register value of the fixed 48-byte payload structure value one-to-one according to the system event, the record number, and the target register value to obtain character information corresponding to the value. The parsing result corresponding to the specified parameter may refer to the character information corresponding to the register value.

[0075] In an exemplary embodiment, parsing, by the baseboard management controller, at least one byte value corresponding to each specified parameter in a set of specified parameters in a target register value, and obtaining a parsing result corresponding to each specified parameter includes:

[0076] In the case where a set of specified parameters includes an event type parameter, the baseboard management controller parses the value of the first specified byte in the target register value to obtain target event type information, wherein the first specified byte is at least one byte corresponding to the event type parameter, and the event type parameter is a parameter corresponding to the event type of the system event occurring in the specified processor.

[0077] For example, in this embodiment, the BMC performs system event analysis on the acquired register value to determine which system event has occurred. For confirmation of the system event, reference may be made to Table 2.

[0078] Table 2

[0079] In an exemplary embodiment, parsing, by the baseboard management controller, at least one byte value corresponding to each specified parameter in a set of specified parameters in a target register value, and obtaining a parsing result corresponding to each specified parameter includes:

[0080] In the case where a set of specified parameters includes an event ID (Identity document) parameter, the baseboard management controller parses the value of the second specified byte in the target register value to obtain the target event ID, wherein the second specified byte is at least one byte corresponding to the record number, and there is a mapping relationship between the record number and the event ID, and the event ID parameter is a parameter corresponding to the event ID corresponding to the system event occurring in the specified processor.

[0081] For example, in this embodiment, the record number is parsed to confirm the corresponding event identification information, as shown in Table 3.

[0082] Table 3

[0083] In an exemplary embodiment, parsing, by the baseboard management controller, at least one byte value corresponding to each specified parameter in a set of specified parameters in a target register value, and obtaining a parsing result corresponding to each specified parameter includes:

[0084] In the case where a set of specified parameters includes an error information location parameter, the baseboard management controller parses the value of the third specified byte in the target register value to obtain target location information, wherein the third specified byte is at least one byte corresponding to the error information location parameter, and the error information location parameter is a parameter used to locate the source component of the error information, the error position in the source component, and the type of the error information.

[0085] For example, in this embodiment, the value of the third designated byte may be a 48-byte payload structure value. The BMC parses the payload structure value of the acquired register to obtain target location information. The error information location parameter is a parameter used to locate the source component of the error information, the error location within the source component, and the type of the error information. For example, it can determine the component in the processor that generated the error information, the location within the component, and the type of error.

[0086] Optionally, the error value register for ARM architecture processors is a 48-byte value, of which 4 bytes are used to identify the component that caused the error, and the remaining 44 bytes are used to locate the faulty component. Due to the large number of cores in ARM processors and the uniqueness of memory slots, accurate location information can be accurately located by parsing the 34 bytes. The remaining 44 bytes are parsed in a similar manner to refine the error type and source.

[0087] In an exemplary embodiment, the error information location parameter includes a set of sub-location parameters, the set of sub-location parameters including an error type parameter, an error sub-type parameter, and an error location parameter, wherein the error type parameter is used to record a source component of the error information, the error sub-type parameter is used to record a source sub-component within a source component of the error information, and the error location parameter is used to record an error location where the error information is located;

[0088] In the case where a set of specified parameters includes an error information location parameter, the baseboard management controller parses the value of the third specified byte in the target register value to obtain target location information including:

[0089] In a case where a set of specified parameters includes an error information location parameter, the baseboard management controller sequentially parses the values ​​in at least one byte corresponding to each sub-location parameter in a set of sub-location parameters in the third specified byte of the target register value to obtain a parsing result corresponding to each sub-location parameter, wherein the target location information includes the parsing result corresponding to each sub-location parameter.

[0090] For example, in this embodiment, the four bytes include a one-byte error type, a one-byte error subtype, and a two-byte error location information type. The BMC program code parses the value of the processor error information generated in the SCP, first parsing the first byte of the first four bytes. After the component parsing is completed, the component error is parsed, that is, the second byte is parsed to determine the subtype type to more accurately locate the internal error information of the component. After parsing the second byte, the next two bytes are parsed to confirm that the error comes from the component location information.

[0091] Optionally, the first byte of the 48-byte value is obtained and the string information of the processor component is recorded and displayed according to the numerical parsing correspondence preset in the BMC program. The BMC program obtains the second byte of the 48-byte value and parses it, and records and displays the corresponding string information based on the Subtype value. The third and fourth bytes of the 48-byte value are parsed. The third and fourth bytes must be parsed together to accurately locate the location of the error, such as the source of an uncorrectable memory error and slot 0 of channel 1 of CPU0, or the source of a CPM Snoop-Lgic error from the CPU CPM1 module group. Other information is similar. The remaining 44 bytes of the 48-byte value are not described or elaborated in detail here. The BMC program verification scheme and principle are similar to those of the first 4 bytes. Their function is to more deeply locate the source of the error.

[0092] In an exemplary embodiment, parsing, by the baseboard management controller, at least one byte value corresponding to each specified parameter in a set of specified parameters in a target register value, and obtaining a parsing result corresponding to each specified parameter includes:

[0093] The baseboard management controller uses the value of at least one byte corresponding to each specified parameter in the target register value to search the parsing table corresponding to each specified parameter, and the parsing result corresponding to each specified parameter, wherein the parsing table corresponding to each specified parameter is used to record the correspondence between the value corresponding to each specified parameter stored in the target register and the parameter value of each specified parameter.

[0094] The register value and the parameter value of the specified parameter can be matched one-to-one through a parsing table, that is, the parsing table corresponding to each specified parameter is used to record the correspondence between the value corresponding to each specified parameter stored in the target register and the parameter value of each specified parameter.

[0095] In this embodiment, the baseboard management controller uses the value of at least one byte corresponding to each specified parameter in the target register value to search the parsing table corresponding to each specified parameter and obtain the parsing result corresponding to each specified parameter.

[0096] For example, in this embodiment, the parsing table corresponding to the specified parameter system event is shown in Table 2, and the parsing table corresponding to the specified parameter event ID parameter is shown in Table 3.

[0097] In an exemplary embodiment, reading a register value of a specified register by a baseboard management controller on a target device includes:

[0098] The baseboard management controller reads the register value of the designated register via the integrated circuit bus of the designated clock frequency. Here, the designated register may refer to an internal error register of the ARM processor.

[0099] In one exemplary embodiment, the specified register is registered in a specified component of the specified processor;

[0100] Before reading the register value of the designated register via the integrated circuit bus of the designated clock frequency by the baseboard management controller, the method further includes:

[0101] During the initialization of the baseboard management controller, the frequency of the integrated circuit bus used for the baseboard management controller to communicate with the designated component is set to a designated clock frequency.

[0102] For example, in this embodiment, the internal error registers of the ARM processor are all stored in the SCP component. The BMC initializes the I2C bus clock frequency for communicating with the SCP and sets it to 100 kHz (kilohertz). The BMC can read the register information of the SCP through the I2C bus at a clock frequency of 100k.

[0103] In an exemplary embodiment, reading a register value of a specified register by a baseboard management controller on a target device includes:

[0104] The baseboard management controller uses a periodic polling mechanism to read the register value of a specified register. This polling mechanism facilitates real-time tracking and location to determine whether a target device (e.g., a server) has failed. For example, in this embodiment, a periodic polling mechanism (reading the SCP register every 2 seconds) can be used to poll the SCP register value.

[0105] In an exemplary embodiment, during the execution of the designated processor, the method further includes:

[0106] Register values ​​stored in designated registers are updated in real time by designated processors based on error information generated by a group of components.

[0107] The designated processor may be a reduced instruction set processor, such as an ARM processor. When a group of components within the ARM processor generates error information, the register value stored in the internal error register of the ARM processor may be updated in real time based on the generated error information.

[0108] For example, in combination with Figure 4, a timing diagram of a processor information processing method of the present application can be shown in Figure 4. When the BMC is initialized, the I2C bus clock frequency for communicating with the SCP is set to 100khz. During the running phase after the server is started, a periodic 2s polling mechanism is adopted to read the register value of the SCP. The designated processor updates the register value stored in the error register in real time based on the error information generated by a group of components. The SCP register value is updated accordingly. The obtained register value is parsed by the BMC code program, and the parsed error information result is confirmed and recorded and displayed through the BMC's SEL log. If there is no error, it is not recorded in the BMC's SEL log and the polling of the SCP's register value continues.

[0109] In an exemplary embodiment, the target register value and the target parsing result are recorded in a system event log of a baseboard management controller, where the target parsing result is target string information obtained by parsing the target register value. After recording the target parsing result in the system event log of the baseboard management controller, the method further includes:

[0110] In response to the acquired fault information display request, the target register value and target character string information recorded in the system event log of the baseboard management controller are displayed through the designated display terminal.

[0111] For example, in this embodiment, after the system event and record number and conventional parsing (48 bytes) are completed, the above-mentioned combined information can be displayed one by one in the BMC SEL log according to the corresponding values ​​and corresponding interpretations. If no error occurs, the BMC SEL log does not record any error information.

[0112] The following explains the method for processing processor information in the embodiment of the present application with reference to optional examples.

[0113] This optional example provides a method for BMC to parse ARM processor error information. Optionally, in conjunction with Figure 5, when the server is turned on, the I2C bus clock frequency for communicating with the SCP is set to 100 kHz through BMC initialization. During the operation phase after the server is started, the BMC adopts a periodic 2s polling mechanism to read the register value of the SCP through the I2C bus, and parses the obtained SCP register value through the BMC code program (built-in script program). After the SCP register value is parsed, it is determined whether an error occurs. If an error occurs, the parsed error information result (the erroneous register value and the parsed character information) is recorded and displayed through the BMC SEL log. If no error occurs, it is not recorded in the BMC SEL log and the SCP register value continues to be polled. The BMC code program parses the fixed 48-byte data structure one by one according to the system event, record number and the corresponding character information of the value, and records and displays the character information corresponding to the value, so as to clearly display the ARM processor error information in a timely manner (BMC web (webpage) display), output and record.

[0114] In conjunction with Figure 6, the physical architecture of a method for processing processor information according to the present application can be shown in Figure 6. In conjunction with Figure 6, BIOS is the firmware of a computer system, which is used to initialize the hardware and start the operating system. The CPU is the central processing unit of a computer, which is used to execute programs and process data. The BMC is an embedded management controller used to monitor and manage the hardware of the computer system. The BIOS is responsible for starting the system and initializing the hardware, the CPU performs calculations and processing tasks, and the SCP and BMC are used to manage and monitor the hardware and services of the system. For example, in this embodiment, the I2C clock can be set to 100khz through the BIOS, and the BMC polls the SCP register of the ARM server through the I2C protocol.

[0115] The BMC firmware and the BMC read the SCP register of the ARM server via I2C at a 100k clock frequency to determine the location information of the ARM server error. Combined with the BMC's built-in corresponding gate of the error register, it quickly verifies and captures the core location information for display and recording in the SEL log. This can achieve direct problem location without R&D and operation and maintenance personnel collecting and parsing error information, saving labor costs.

[0116] The traditional method of BMC reading SCP registers and polling to determine whether any errors occur, capturing the error registers and parsing them one by one according to the specification document is integrated into the BMC firmware, and automatically parses and displays the actual location information and component information of the SCP register errors. This improves the efficiency of R&D personnel in parsing and analyzing problems. The parsing method and steps are integrated into the management firmware BMC that reads SCP, reducing human involvement in problem analysis.

[0117] The BMC polls the SCP register of the ARM server through the I2C protocol, parses the read SCP register value, displays the parsed error information, type, and location information, and records it in the BMC's SEL log. Even if it is physically impossible to collect serial port logs and error logs, because the BMC has completed the parsing and located the error and displayed it, R&D and operation and maintenance personnel only need to download the SEL log to analyze and locate the component causing the problem.

[0118] Optionally, the BMC parsing logic may be as shown in FIG7 , and optionally:

[0119] Step 1: The BMC program code compares and verifies the obtained SCP register according to the system event table;

[0120] Step 2: parse the system information corresponding to the record number;

[0121] Step 3: The BMC program numerically parses the first byte of the 48-byte payload structure data and displays the corresponding character information according to the corresponding table.

[0122] Step 4: The BMC program obtains the second byte of the 48-byte sequence and parses it, recording and displaying the corresponding string information based on the Subtype value.

[0123] Step 5: The BMC program performs numerical analysis on the third and fourth bytes of the acquired 48 bytes, and displays the character information corresponding to the numerical analysis according to the corresponding table;

[0124] Step 6: The BMC program performs numerical analysis on the remaining 44 bytes of the acquired 48 bytes, and displays the character information corresponding to the numerical analysis according to the corresponding table;

[0125] Step 7: The BMC program can be used to quickly locate the location and source of the error information and take appropriate repair measures.

[0126] Through this optional example, real-time polling and parsing of SCP register values ​​can quickly locate the detailed fault location information and error type. This facilitates maintenance personnel to quickly locate faults and replace related core components when batch deploying ARM architecture servers in a data center, improving operation and maintenance efficiency and reducing the labor costs of operation and maintenance personnel. At the same time, it meets the stability and reliability requirements during system operation.

[0127] It should be noted that for the aforementioned method embodiments, for the sake of simplicity, they are all expressed as a series of action combinations, but those skilled in the art should be aware that this application is not limited by the order of the actions described, because according to this application, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in this specification are optional embodiments, and the actions and modules involved are not necessarily required for this application.

[0128] Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus the necessary general hardware platform, and of course it can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art can be embodied in the form of a software product, which is stored in a non-volatile readable storage medium (such as ROM / RAM, magnetic disk, optical disk), including a number of instructions for enabling a terminal device (which can be a mobile phone, computer, server, or network device, etc.) to execute the methods of each embodiment of the present application.

[0129] In this embodiment, a device for processing processor information is also provided. The device is configured to implement the above-mentioned embodiments and optional implementation methods. Details already described are not repeated here. As used below, the term "module" may refer to a combination of software and / or hardware that implements a predetermined function. Although the devices described in the following embodiments are preferably implemented in software, implementation using hardware, or a combination of software and hardware, is also possible and contemplated.

[0130] FIG8 is a structural block diagram of a device for processing processor information according to an embodiment of the present application. As shown in FIG8 , the device includes:

[0131] a reading unit 802 configured to read a register value of a specified register through a baseboard management controller on a target device, wherein the specified register is located in a specified processor of the target device, and the specified register is a register for storing error information generated by a group of components in the specified processor through the register value;

[0132] The parsing unit 804 is configured to parse the read target register value according to a set of specified parameters through the baseboard management controller to obtain a target parsing result, wherein the set of specified parameters is parameters used for error information parsing;

[0133] The recording unit 806 is configured to record the target parsing result in a system event log of the baseboard management controller when it is determined that error information has been generated by at least one component in the designated processor according to the target parsing result.

[0134] Through the embodiments of the present application, the register value of the specified register is read by the baseboard management controller on the target device, wherein the specified register is located in the specified processor of the target device, and the specified register is a register used to store error information generated by a group of components in the specified processor through the register value; the read target register value is parsed by the baseboard management controller according to a set of specified parameters to obtain a target parsing result, wherein the set of specified parameters is the parameters used for error information parsing; when it is determined according to the target parsing result that at least one component in the specified processor has generated error information, the target parsing result is recorded in the system event log of the baseboard management controller, thereby solving the problem of low processor fault processing efficiency in the processor information processing method in the related art and improving the processor fault processing efficiency.

[0135] Optionally, the parsing unit includes:

[0136] The first parsing module is configured to parse the read target register value according to a set of specified parameters using a preset parsing tool through a baseboard management controller to obtain a target parsing result, wherein the preset parsing tool is a parsing tool that matches the data structure used by the specified register for data storage.

[0137] Optionally, the parsing unit includes:

[0138] The second parsing module is configured to parse the value of at least one byte corresponding to each specified parameter in a set of specified parameters in the target register value through the baseboard management controller to obtain a parsing result corresponding to each specified parameter, wherein the target parsing result includes the parsing result corresponding to each specified parameter.

[0139] Optionally, the second parsing module includes:

[0140] The first parsing submodule is configured to parse the value of the first specified byte in the target register value through the baseboard management controller to obtain target event type information when a set of specified parameters includes an event type parameter, wherein the first specified byte is at least one byte corresponding to the event type parameter, and the event type parameter is a parameter corresponding to the event type of the system event occurring in the specified processor.

[0141] Optionally, the second parsing module includes:

[0142] The second parsing submodule is configured to parse the value of the second specified byte in the target register value through the baseboard management controller when a set of specified parameters includes an event identification ID parameter to obtain a target event ID, wherein the second specified byte is at least one byte corresponding to a record number, there is a mapping relationship between the record number and the event ID, and the event ID parameter is a parameter corresponding to the event ID corresponding to the system event occurring in the specified processor.

[0143] Optionally, the second parsing module includes:

[0144] The third parsing submodule is configured to parse the value of the third specified byte in the target register value through the baseboard management controller to obtain target positioning information when a set of specified parameters includes an error information positioning parameter, wherein the third specified byte is at least one byte corresponding to the error information positioning parameter, and the error information positioning parameter is a parameter for locating the source component of the error information, the error position in the source component, and the type of the error information.

[0145] Optionally, the error information location parameter includes a set of sub-location parameters, each of which includes an error type parameter, an error sub-type parameter, and an error location parameter, wherein the error type parameter is used to record a source component of the error information, the error sub-type parameter is used to record a source sub-component within a source component of the error information, and the error location parameter is used to record an error location where the error information is located;

[0146] The third parsing submodule includes:

[0147] The parsing subunit is configured to, when a set of specified parameters includes an error information location parameter, parse, through a baseboard management controller, the values ​​in at least one byte corresponding to each sub-location parameter in a set of sub-location parameters in a third specified byte of a target register value in sequence, to obtain a parsing result corresponding to each sub-location parameter, wherein the target location information includes the parsing result corresponding to each sub-location parameter.

[0148] Optionally, the second parsing module includes:

[0149] The search submodule is configured to use the value of at least one byte corresponding to each specified parameter in the target register value through the baseboard management controller to search the parsing table corresponding to each specified parameter and the parsing result corresponding to each specified parameter, wherein the parsing table corresponding to each specified parameter is used to record the correspondence between the value corresponding to each specified parameter stored in the target register and the parameter value of each specified parameter.

[0150] Optionally, the reading unit includes:

[0151] The first reading module is configured to read a register value of a specified register via an integrated circuit bus with a specified clock frequency through a baseboard management controller.

[0152] Optionally, the specified register is registered in a specified component of the specified processor;

[0153] The above device also includes:

[0154] The setting unit is configured to set the frequency of the integrated circuit bus for communicating between the baseboard management controller and the specified component to the specified clock frequency during the initialization of the baseboard management controller before reading the register value of the specified register via the integrated circuit bus of the specified clock frequency through the baseboard management controller.

[0155] Optionally, the reading unit includes:

[0156] The second reading module is configured to read a register value of a designated register by using a baseboard management controller in a timed polling manner.

[0157] Optionally, during the operation of the designated processor, the apparatus further includes:

[0158] The execution unit is configured to update register values ​​stored in designated registers in real time based on error information generated by a group of components through a designated processor.

[0159] Optionally, the target register value and the target parsing result are recorded in the system event log of the baseboard management controller, and the target parsing result is target character string information obtained by parsing the target register value;

[0160] The above device also includes:

[0161] The display unit is configured to, after recording the target parsing result in the system event log of the baseboard management controller, display the target register value and target string information recorded in the system event log of the baseboard management controller through a designated display terminal in response to an acquired fault information display request.

[0162] Optionally, the designated register is stored in a system control processor component of a designated processor, and the designated processor is a reduced instruction set processor.

[0163] An embodiment of the present application further provides a non-volatile readable storage medium, in which a computer program is stored. The computer program is configured to execute the steps of any of the above method embodiments when running.

[0164] In an exemplary embodiment, the non-volatile readable storage medium may include, but is not limited to, various media that can store computer programs, such as a USB flash drive, a ROM (Read-Only Memory), a RAM (Random Access Memory), a mobile hard disk, a magnetic disk, or an optical disk.

[0165] An embodiment of the present application further provides an electronic device, comprising a memory and a processor, wherein the memory stores a computer program, and the processor is configured to run the computer program to execute the steps in any one of the above method embodiments.

[0166] In an exemplary embodiment, the electronic device may further include a transmission device and an input / output device, wherein the transmission device is connected to the processor, and the input / output device is connected to the processor.

[0167] For optional examples in this embodiment, reference may be made to the examples described in the above embodiments and exemplary implementations, and this embodiment will not be described in detail here.

[0168] Obviously, those skilled in the art should understand that the modules or steps of the present application described above can be implemented using a general-purpose computing device, they can be concentrated on a single computing device, or distributed across a network composed of multiple computing devices, they can be implemented using program code executable by the computing device, and thus, they can be stored in a storage device and executed by the computing device, and in some cases, the steps shown or described can be performed in a different order than herein, or they can be fabricated into separate integrated circuit modules, or multiple modules or steps can be fabricated into a single integrated circuit module for implementation. Thus, the present application is not limited to any specific combination of hardware and software.

[0169] The above are merely optional embodiments of the present application and are not intended to limit the present application. For those skilled in the art, the present application may be subject to various modifications and variations. Any modifications, equivalent replacements, improvements, etc. made within the principles of the present application shall be included in the scope of protection of the present application.

Claims

1. A method for processing processor information, characterized in that: It includes: Reading the register value of a specified register through a baseboard management controller on a target device, where the specified register is located in a specified processor of the target device, and the specified register is a register for storing error information generated by a group of components in the specified processor through the register value; Parsing the read target register value by the baseboard management controller according to a group of specified parameters to obtain a target parsing result, where the group of specified parameters is a parameter used for error information parsing; When it is determined according to the target parsing result that at least one component in the specified processor has generated error information, recording the target parsing result in the system event log of the baseboard management controller.

2. The method according to claim 1, characterized in that: The parsing the read target register value by the baseboard management controller according to a group of specified parameters to obtain a target parsing result includes: Parsing the read target register value by the baseboard management controller using a preset parsing tool according to the group of specified parameters to obtain the target parsing result, where the preset parsing tool is a parsing tool matching the data structure used for data storage of the specified register.

3. The method according to claim 1, characterized in that: The parsing the read target register value by the baseboard management controller according to a group of specified parameters to obtain a target parsing result includes: Parsing the value of at least one byte corresponding to each specified parameter in the group of specified parameters in the target register value by the baseboard management controller to obtain a parsing result corresponding to each specified parameter, where the target parsing result includes the parsing result corresponding to each specified parameter.

4. The method according to claim 3, characterized in that: The parsing the value of at least one byte corresponding to each specified parameter in the group of specified parameters in the target register value by the baseboard management controller to obtain a parsing result corresponding to each specified parameter includes: When the group of specified parameters includes an event type parameter, parsing the value of the first specified byte in the target register value by the baseboard management controller to obtain target event type information, where the first specified byte is at least one byte corresponding to the event type parameter, and the event type parameter is a parameter corresponding to the event type of the system event occurring in the specified processor.

5. The method according to claim 3, characterized in that: The parsing the value of at least one byte corresponding to each specified parameter in the group of specified parameters in the target register value by the baseboard management controller to obtain a parsing result corresponding to each specified parameter includes: When the set of specified parameters includes an event identification ID parameter, the baseboard management controller parses the value of the second specified byte in the target register value to obtain a target event ID, where the second specified byte is at least one byte corresponding to a record number, and there is a mapping relationship between the record number and the event ID, and the event ID parameter is a parameter corresponding to the event ID corresponding to the system event that occurs within the specified processor.

6. The method according to claim 3, wherein: The parsing, by the baseboard management controller, of the value of at least one byte corresponding to each specified parameter in the set of specified parameters in the target register value to obtain a parsing result corresponding to each specified parameter includes: When the set of specified parameters includes an error information location parameter, the baseboard management controller parses the value of the third specified byte in the target register value to obtain a target location information, where the third specified byte is at least one byte corresponding to the error information location parameter, and the error information location parameter is a parameter for locating the source component of the error information, the error location in the source component, and the type of the error information.

7. The method according to claim 6, wherein: The error information location parameter includes a set of sub-location parameters, and the set of sub-location parameters includes an error type parameter, an error subtype parameter, and an error location parameter, where the error type parameter is used to record the source component of the error information, the error subtype parameter is used to record the source sub-component within the source component of the error information, and the error location parameter is used to record the error location where the error information is located; The parsing, by the baseboard management controller, of the value of the third specified byte in the target register value to obtain a target location information when the set of specified parameters includes an error information location parameter includes: When the set of specified parameters includes the error information location parameter, the baseboard management controller sequentially parses the value of at least one byte corresponding to each sub-location parameter in the set of sub-location parameters in the third specified byte in the target register value to obtain a parsing result corresponding to each sub-location parameter, where the target location information includes the parsing result corresponding to each sub-location parameter.

8. The method according to claim 3, wherein: The parsing, by the baseboard management controller, of the value of at least one byte corresponding to each specified parameter in the set of specified parameters in the target register value to obtain a parsing result corresponding to each specified parameter includes: The baseboard management controller uses the values of at least one byte corresponding to each specified parameter in the target register value to look up a parsing table corresponding to each specified parameter, and a parsing result corresponding to each specified parameter, wherein the parsing table corresponding to each specified parameter is used to record the correspondence between the values stored in the target register corresponding to each specified parameter and the parameter values of each specified parameter.

9. The method according to claim 1, wherein the reading of the register value of the specified register by the baseboard management controller on the target device includes: the baseboard management controller reads the register value of the specified register via an integrated circuit bus with a specified clock frequency.

10. The method according to claim 9, wherein the specified register is stored in a specified component of the specified processor; before the baseboard management controller reads the register value of the specified register via an integrated circuit bus with a specified clock frequency, the method further includes: during the initialization of the baseboard management controller, setting the frequency of the integrated circuit bus for the baseboard management controller to communicate with the specified component to the specified clock frequency.

11. The method according to claim 1, wherein the reading of the register value of the specified register by the baseboard management controller on the target device includes: the baseboard management controller reads the register value of the specified register in a timed polling manner.

12. The method according to claim 1, wherein during the operation of the specified processor, the method further includes: the specified processor updates the register value stored in the specified register in real time based on the error information generated by the set of components.

13. The method according to claim 1, wherein the target register value and the target parsing result are recorded together in the system event log of the baseboard management controller, and the target parsing result is the target string information obtained by parsing the target register value; after the target parsing result is recorded in the system event log of the baseboard management controller, the method further includes: in response to a fault information display request obtained, displaying the target register value and the target string information recorded in the system event log of the baseboard management controller through a specified display terminal.

14. The method according to any one of claims 1 to 13, characterized in that, The specified register is stored in the system control processor component of the specified processor, and the specified processor is a reduced instruction set processor.

15. The method according to claim 3, wherein The values of different fields in the target register value correspond to different specified parameters in the set of specified parameters.

16. The method according to claim 6, wherein The parsing of the value of the third specified byte in the target register value by the baseboard management controller to obtain target location information includes: the baseboard management controller parses the payload structure value of the obtained register to obtain the target location information.

17. The method according to claim 6, wherein Before parsing the value of the third specified byte in the target register value by the baseboard management controller, the method further includes: Obtaining a payload structure value of 48 bytes as the value of the third specified byte.

18. A processing device for processor information, characterized in that: It includes: A reading unit, configured to read the register value of a specified register through the baseboard management controller on a target device, where the specified register is located in a specified processor of the target device, and the specified register is a register used to store error information generated by a group of components in the specified processor through the register value; An analysis unit, configured to analyze the read target register value according to a group of specified parameters through the baseboard management controller to obtain a target analysis result, where the group of specified parameters are parameters used for error information analysis; A recording unit, configured to record the target analysis result in the system event log of the baseboard management controller when it is determined according to the target analysis result that at least one component in the specified processor has generated error information.

19. A non-volatile readable storage medium, characterized in that: A computer program is stored in the non-volatile readable storage medium, where the computer program, when executed by a processor, implements the method according to any one of claims 1 to 17.

20. An electronic device, including a memory, a processor, and a computer program stored on the memory and executable on the processor, characterized in that: When the processor executes the computer program, the method according to any one of claims 1 to 17 is implemented.

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