Clock generation circuit and memory

Abstract

Provided in the embodiments of the present disclosure are a clock generation circuit and a memory. An ith clock generation sub-circuit is configured to perform sampling processing and latching processing on an ith register input signal on the basis of an inverted clock signal, so as to generate an ith register signal, and perform first logic processing on the ith register signal and a delayed clock signal, so as to generate an ith target clock signal. A jth clock generation sub-circuit is configured to perform sampling processing and latching processing on a (j-1)th register signal on the basis of a preset clock signal, so as to generate a jth register signal, and perform second logic processing on the jth register signal and the delayed clock signal, so as to generate a jth target clock signal.

Description

A clock generating circuit and memory

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on December 26, 2023, with application number 202311829264.3 and application name “A clock generation circuit and memory”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present disclosure relates to the field of semiconductor technology, and in particular to a clock generation circuit and a memory. Background Art

[0003] For double data transmission, two data transmission clock signals are generated through a single read command, allowing two data records to be transmitted in the same time as a single record, thereby doubling the data transmission rate. In the prior art, the circuitry required to generate the two data transmission clock signals for double data transmission requires a large area, resulting in a waste of circuit resources.

[0004] Summary of the Invention

[0005] Embodiments of the present disclosure provide a clock generation circuit and a memory.

[0006] In a first aspect, an embodiment of the present disclosure provides a clock generation circuit, wherein the clock generation circuit is configured to generate N target clock signals, where N is a positive even number, and the clock generation circuit includes N clock generation sub-circuits; wherein:

[0007] The i-th clock generation sub-circuit is configured to receive an i-th register input signal, an inverted clock signal, and a delayed clock signal; perform sampling and latching processing on the i-th register input signal according to the inverted clock signal to generate an i-th register signal; perform a first logic processing on the i-th register signal and the delayed clock signal to generate an i-th target clock signal; wherein i is a positive odd number greater than or equal to 1 and less than N, and when i=1, the i-th register input signal is an initial register signal; and when i>1, the i-th register input signal is an i-1-th register signal;

[0008] The jth clock generation sub-circuit is configured to receive the j-1th register signal, the preset clock signal, and the delayed clock signal; perform sampling and latching processing on the j-1th register signal according to the preset clock signal to generate the jth register signal; perform a second logic processing on the jth register signal and the delayed clock signal to generate the jth target clock signal; wherein j is a positive even number greater than 1 and less than or equal to N;

[0009] The preset clock signal and the inverted clock signal are a pair of inverted signals, and the delayed clock signal is a delayed signal of the preset clock signal.

[0010] In a second aspect, an embodiment of the present disclosure provides a memory, which at least includes a clock generation circuit as described in any one of the first aspects.

[0011] The embodiment of the present disclosure provides a clock generation circuit and a memory, wherein the clock generation circuit is used to generate N target clock signals, where N is a positive even number, and the clock generation circuit includes N clock generation sub-circuits; the i-th clock generation sub-circuit is used to receive the i-th register input signal, the inverted clock signal and the delayed clock signal; perform sampling processing and latch processing on the i-th register input signal according to the inverted clock signal to generate the i-th register signal; perform a first logic processing on the i-th register signal and the delayed clock signal to generate the i-th target clock signal; i is a positive odd number greater than or equal to 1 and less than N, and when i=1, the i-th register input signal The number is the initial register signal. When i>1, the input signal of the i-th register is the i-1-th register signal. The j-th clock generation subcircuit is used to receive the j-1-th register signal, the preset clock signal, and the delayed clock signal. According to the preset clock signal, the j-1-th register signal is sampled and latched to generate the j-th register signal. The j-1-th register signal and the delayed clock signal are subjected to a second logic process to generate the j-th target clock signal. j is a positive even number greater than 1 and less than or equal to N. The preset clock signal and the inverted clock signal are a pair of inverted signals, and the delayed clock signal is a delayed signal of the preset clock signal. In this way, the clock generation circuit generates a set of target clock signals based on the odd-numbered clock generation subcircuit and a set of target clock signals based on the even-numbered clock generation subcircuit. Thus, two sets of target clock signals can be obtained using only one clock generation circuit, saving circuit resources. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] FIG1 is a timing diagram of full data and its clock signal;

[0013] FIG2 is a timing diagram of double data and its clock signal;

[0014] FIG3 is a schematic diagram of the structure of a clock generating circuit;

[0015] FIG4 is a first schematic diagram of the structure of a clock generation circuit provided by an embodiment of the present disclosure;

[0016] FIG5 is a second schematic diagram of the structure of a clock generation circuit provided in an embodiment of the present disclosure;

[0017] FIG6 is a schematic diagram of the structure of an initial register signal generating circuit provided by an embodiment of the present disclosure;

[0018] FIG7 is a third structural diagram of a clock generation circuit provided in an embodiment of the present disclosure;

[0019] FIG8 is a schematic diagram of the structure of a signal generating circuit provided by an embodiment of the present disclosure;

[0020] FIG9 is a first timing diagram of a clock generating circuit provided by an embodiment of the present disclosure;

[0021] FIG10 is a fourth structural diagram of a clock generation circuit provided in an embodiment of the present disclosure;

[0022] FIG11 is a second timing diagram of a clock generating circuit provided by an embodiment of the present disclosure;

[0023] FIG12 is a timing analysis diagram of a clock generation circuit provided by an embodiment of the present disclosure;

[0024] FIG13 is a fifth structural diagram of a clock generation circuit provided in an embodiment of the present disclosure;

[0025] FIG14 is a schematic diagram of the composition structure of a memory provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0026] The following will be combined with the accompanying drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. It should be understood that the specific embodiments described herein are only used to illustrate the relevant disclosure and are not intended to limit the disclosure. It should also be noted that for ease of description, only the portions relevant to the relevant disclosure are shown in the drawings.

[0027] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art in the art of the present disclosure. The terms used herein are only for the purpose of describing the embodiments of the present disclosure and are not intended to limit the present disclosure.

[0028] In the following description, reference is made to “some embodiments”, which describes a subset of all possible embodiments, but it will be understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0029] It should be pointed out that the terms "first\second\third" involved in the embodiments of the present disclosure are only used to distinguish similar objects and do not represent a specific order for the objects. It can be understood that "first\second\third" can be interchanged with a specific order or sequence where permitted, so that the embodiments of the present disclosure described here can be implemented in an order other than that illustrated or described here.

[0030] Before further explaining the embodiments of the present disclosure in detail, the nouns and terms involved in the embodiments of the present disclosure are explained first. The nouns and terms involved in the embodiments of the present disclosure are subject to the following interpretations:

[0031] Static Random Access Memory (SRAM);

[0032] Dynamic Random Access Memory (DRAM);

[0033] Synchronous Dynamic Random Access Memory (SDRAM);

[0034] Double Data Rate SDRAM (DDR SDRAM);

[0035] Double Data Rate (DDR);

[0036] Fifth-generation double data rate (DDR5);

[0037] Read (RD);

[0038] Command (CMD);

[0039] Data (DQ);

[0040] Full Data;

[0041] Doubling Data;

[0042] bit;

[0043] Data Window;

[0044] First Input First Output (FIFO);

[0045] Column Address Strobe (CAS);

[0046] Burst

[0047] Nanosecond (ns);

[0048] D flip-flop (Data Flip-Flop or Delay Flip-Flop, DFF);

[0049] Latch;

[0050] High level (High, H);

[0051] Low level (Low, L);

[0052] Gigabyte (GB, G);

[0053] Positive channel Metal Oxide Semiconductor field effect transistor (PMOS transistor);

[0054] N-type metal oxide semiconductor field effect transistor / N-type transistor (Negative channel Metal Oxide Semiconductor field effect transistor, NMOS tube).

[0055] The data bus is used for data transmission. One data bus can transmit 1 bit of data or multiple bits of data. For example, in a read operation, full data is transmitted on a data bus with 1 bit of data. The data window of this data is the time length tCCD between the current read command and the next read command, that is, the time interval between the current CAS command and the next CAS command. However, full data occupies too many channel resources, that is, the number of data buses is too large, and when the full data is stored in the FIFO structure through the data transmission clock signal, the clock signal loading will be very heavy.

[0056] Double data transfer involves transmitting 2 bits of data on a single data bus. For some embodiments, the data window for the first bit of double data (i.e., the first burst) can be 4T, and correspondingly, the data window for the second bit of data (i.e., the second burst) is tCCD-4T. Double data can save half the channel resources, but a read command requires two data transmission clock signals to store the double data in the FIFO structure for subsequent output. This reduces the load on the data transmission clock signal by half. Here, the shortest delay time, tCCD_S, between consecutive read commands can be 8T; where the clock period of the system clock signal is represented by T.

[0057] Refer to Figure 1, which shows a timing diagram of full data and its clock signal. As shown in Figure 1, there are two full data DATA_1st and DATA_2nd. For full data DATA_1st and DATA_2nd, their data windows are both tCCD, and each burst pulse of full data is used to transmit 1 bit of data. There are two data transmission clock signals PDL <0> and PDL <1> , through PDL <0> The signal writes the full data DATA_1st into the FIFO structure through PDL <1> The signal writes the full data DATA_2nd into the FIFO structure. Here, the FIFO structure is a D flip-flop, which works on the rising edge of the data transmission clock signal and writes the full data into the FIFO structure.

[0058] It should be noted that, for full data, a read command is usually used to generate a data transmission clock signal of a FIFO structure, which can be achieved by simple shift processing.

[0059] Refer to Figure 2, which shows a timing diagram of double data and its clock signal. As shown in Figure 2, two adjacent burst pulses in the double data DATA are used to transmit 2it data; the data window of the first burst pulse of DATA is 4T, the data window of the second burst pulse is tCCD-4T, the data window of the third burst pulse is 4T, ..., and so on. There are two sets of data transmission clock signals, PDL <0> Signals and PDL <2> The even-numbered levels of the signal are a set of data transmission clock signals, which are used to write the burst pulse with a data window of 4T in the double data DATA into the FIFO structure; <1> Signals and PDL <3> The odd-numbered levels of the signal are a set of data transmission clock signals used to write burst pulses with a data window of tCCD-4T in the double data DATA into the FIFO structure. Here, the FIFO structure is a latch, which has the characteristics of transmitting data in the high-level state and latching data in the low-level state. In other words, when the clock signal received by the latch is in the low-level state, the output signal of the latch is the output signal of the latch before the clock signal changes to the low-level state; and when the clock signal received by the latch is in the high-level state, the output signal of the latch is the input signal of the latch.

[0060] It should be noted that for double data, two data transmission clock signals need to be generated by one read command. As shown in Figure 2, PDL <0> Signals and PDL <1> The signal comes from the first read command, PDL <2> Signals and PDL <3> The signal comes from the second read command; in addition, PDL <0> Signals and PDL <2> The signal can match the corresponding data window 4T in the double data, PDL <1> Signals and PDL <3> The signal can match the corresponding data window tCCD-4T in the double data.

[0061] Referring to FIG3 , a schematic diagram of the structure of a clock generating circuit is shown. As shown in FIG3 , the clock generating circuit 10 includes two groups of shift registers Shift0 and Shift1. The first group of shift registers Shift0 generates a PDL signal according to the FRP_PDL_D signal. <0> Signal, PDL <2> Signal equal to the even-level data transmission clock signal; through the second group of shift register Shift1, the PDL is generated through the FRP_PDL_4T_D signal <1> Signal, PDL <3> The FRP_PDL_4T_D signal is an odd-level data transmission clock signal, and the FRP_PDL_D signal is a signal obtained by delaying the FRP_PDL_D signal by 4T.

[0062] Here, two sets of shift registers are usually used to shift the FRP_PDL_D signal with a pulse length of 4T generated by the read command and the FRP_PDL_4T_D signal obtained by delaying the FRP_PDL_D signal by 4T to obtain two sets of data transmission clock signals, thereby realizing the above-mentioned function of writing double data into the FIFO structure. However, this will result in a waste of circuit resources.

[0063] Based on this, an embodiment of the present disclosure provides a clock generating circuit, which generates a set of target clock signals according to the odd-level clock generating sub-circuit, and generates a set of target clock signals according to the even-level clock generating sub-circuit, so that two sets of target clock signals can be obtained with only one clock generating circuit, thereby realizing double data writing and saving circuit resources.

[0064] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

[0065] In one embodiment of the present disclosure, referring to FIG4 , a schematic diagram of the structure of a clock generation circuit according to an embodiment of the present disclosure is shown. As shown in FIG4 , the clock generation circuit 20 is configured to generate N target clock signals, where N is a positive even number. The clock generation circuit 20 includes N clock generation sub-circuits; wherein:

[0066] The i-th clock generation sub-circuit 21 is configured to receive an i-th register input signal, an inverted clock signal, and a delayed clock signal; perform sampling and latching processing on the i-th register input signal according to the inverted clock signal to generate an i-th register signal; and perform a first logic processing on the i-th register signal and the delayed clock signal to generate an i-th target clock signal. Here, i is a positive odd number greater than or equal to 1 and less than N. When i=1, the i-th register input signal is the initial register signal; and when i>1, the i-th register input signal is the i-1-th register signal.

[0067] The j-th clock generation sub-circuit 22 is configured to receive the j-1-th register signal, the preset clock signal, and the delayed clock signal; perform sampling and latching processing on the j-1-th register signal according to the preset clock signal to generate the j-th register signal; and perform a second logic processing on the j-th register signal and the delayed clock signal to generate the j-th target clock signal; wherein j is a positive even number greater than 1 and less than or equal to N;

[0068] The preset clock signal and the inverted clock signal are a pair of inverted signals, and the delayed clock signal is a delayed signal of the preset clock signal.

[0069] It should be noted that the i-th clock generation subcircuit 21 is an odd-numbered clock generation subcircuit, such as the 1st clock generation subcircuit 21, the 3rd clock generation subcircuit 21, the 5th clock generation subcircuit 21, ..., and so on; and the j-th clock generation subcircuit 22 is an even-numbered clock generation subcircuit, such as the 2nd clock generation subcircuit 22, the 4th clock generation subcircuit 22, the 6th clock generation subcircuit 22, ..., and so on. For example, FIG4 only shows the 1st clock generation subcircuit 21, the 2nd clock generation subcircuit 22, ..., the N-1th clock generation subcircuit 21, and the Nth clock generation subcircuit 22; the remaining clock generation subcircuits are not shown. Please combine the above description with FIG4 for an adaptive understanding.

[0070] It should also be noted that when i>1, the i-1th register signal is the register signal generated by the previous even-level clock generation sub-circuit; the j-1th register signal is the register signal generated by the previous odd-level clock generation sub-circuit.

[0071] In the disclosed embodiments, clock generation circuit 20 is specifically a circuit related to a read data cache in a DRAM chip within an integrated circuit design, and more particularly, relates to the implementation of a clock generation circuit for writing double data into a FIFO structure in a 16Gb DDR5 SDRAM chip. Furthermore, clock generation circuit 20 can be applied to the clock generation circuit for a cache used for reading data from a DRAM chip, and can also be used to implement clocks related to writing double data into a FIFO structure in other DRAM chips, without specific limitation.

[0072] As shown in FIG4 , in clock generation circuit 20, the first target clock signal is generated by the first clock generation sub-circuit 21, the second target clock signal is generated by the second clock generation sub-circuit 22, ..., the N-1th target clock signal is generated by the N-1th clock generation sub-circuit 21, and the Nth target clock signal is generated by the Nth clock generation sub-circuit 22. Furthermore, the target clock signals generated by the odd-numbered clock generation sub-circuits are grouped together, and the target clock signals generated by the even-numbered clock generation sub-circuits are grouped together. This allows a single clock generation circuit to generate two groups of target clock signals by performing a shift operation on the initial register signal through specific logic, significantly conserving circuit resources.

[0073] In some embodiments, the first logic process is an OR logic process, and the second logic process is a NAND logic process.

[0074] That is to say, for the odd-numbered clock generation sub-circuit, the i-th register signal and the delayed clock signal are subjected to an OR logic process to obtain the i-th target clock signal; for the even-numbered clock generation sub-circuit, the j-th register signal and the delayed clock signal are subjected to an AND-NOT logic process to obtain the j-th target clock signal.

[0075] In some embodiments, referring to FIG5 , which shows a second schematic diagram of the structure of a clock generation circuit provided by an embodiment of the present disclosure. As shown in FIG5 , the i-th clock generation sub-circuit 21 includes the i-th latch 211 and the i-th first logic circuit 212, and the j-th clock generation sub-circuit 22 includes the j-th latch 221 and the j-th second logic circuit 222;

[0076] The i-th latch 211 is configured to receive the i-th register input signal and the inverted clock signal, and perform sampling and latching processing on the i-th register input signal according to the inverted clock signal to generate an i-th register signal;

[0077] The i-th first logic circuit 212 is configured to receive the i-th register signal and the delayed clock signal, and perform an OR logic operation on the i-th register signal and the delayed clock signal to generate an i-th target clock signal;

[0078] The j-th latch 221 is configured to receive the j-1-th register signal and a preset clock signal, and perform sampling and latching processing on the j-1-th register signal according to the preset clock signal to generate the j-th register signal;

[0079] The j-th second logic circuit 222 is configured to receive the j-th register signal and the delayed clock signal, and perform a NAND logic process on the j-th register signal and the delayed clock signal to generate a j-th target clock signal.

[0080] FIG5 illustrates N=16 as an example, but N can be any positive even number. As shown in FIG5 , there are 16 cascaded latches; there are eight first logic circuits 212, each used to perform an OR logic operation on the i-th register signal generated by the odd-numbered latches and the delayed clock signal; there are eight second logic circuits 222, each used to perform an AND-NOT logic operation on the j-th register signal generated by the even-numbered latches and the delayed clock signal. Furthermore, for ease of illustration, FIG5 only shows the numbers of the third latch, the third first logic circuit, the fourth latch, and the fourth second logic circuit; the remaining clock generation subcircuits are not numbered.

[0081] Here, the target clock signal is represented by REGB <n>Indicates that the first target clock signal is represented by REGB <0> Indicates that the second target clock signal is represented by REGB <1> Indicates that, ..., the 16th target clock signal is represented by REGB <15> Indicates; the register signal is represented by net n, the first register signal is represented by net0, the second register signal is represented by net1, ..., the 16th register signal is represented by net15; the preset clock signal is represented by CLK, the inverted clock signal is represented by CLKB, and the delayed clock signal is represented by CLKD.

[0082] It should be noted that for the latch, it may include a clock terminal (CK), an input terminal (D), an inverting output terminal (QB) and a reset terminal (RST); in addition, it may also include a set terminal (SET), etc., but it is not shown in the figure.

[0083] In some embodiments, for example, as shown in FIG5 , the i-th first logic circuit 212 includes a NOR gate and three NOT gates, the first input of the NOR gate is used to receive the i-th register signal, the second input of the NOR gate is used to receive the delayed clock signal, and the signal output by the NOR gate passes through three NOT gates to obtain the i-th target clock signal.

[0084] It should be noted that the signal output by the NOR gate may also pass through an odd number of NOR gates, such as one NOR gate, five NOR gates, or seven NOR gates, to obtain the i-th target clock signal; or, the i-th first logic circuit 212 may only include one OR gate, the first input end of the OR gate being used to receive the i-th register signal, the second input end of the OR gate being used to receive the delayed clock signal, and the output end of the OR gate being used to output the i-th target clock signal. The embodiments of the present disclosure do not specifically limit this.

[0085] Exemplarily, as shown in FIG5 , the j-th second logic circuit 222 includes a NAND gate, a transmission gate, and two NOT gates. The first input of the NAND gate is used to receive the j-th register signal, and the second input of the NAND gate is used to receive the delayed clock signal. The signal output by the NAND gate is driven and transmitted by the transmission gate, and then passes through two NOT gates to obtain the j-th target clock signal.

[0086] It should be noted that the transmission gate consists of a PMOS transistor and an NMOS transistor connected in parallel. The gates of the PMOS and NMOS transistors serve as the two control terminals, each receiving a pair of mutually anti-phase signals. The sources of the PMOS and NMOS transistors are connected as the input terminals, and the drains are connected as the output terminals. Since the drains and sources of the PMOS and NMOS transistors are interchangeable, the input and output terminals of the transmission gate are also interchangeable. As shown in Figure 5, the gate of the PMOS transistor receives the ground signal VSS, and the gate of the NMOS transistor receives the power signal VDD.

[0087] It should also be noted that the signal output by the transmission gate can also pass through an even number of NOT gates, such as four NOT gates, six NOT gates, or eight NOT gates, to obtain the j-th target clock signal; or, the j-th second logic circuit 222 can include only one NAND gate, and the output end of the NAND gate is used to output the j-th target clock signal. The embodiments of the present disclosure do not specifically limit this.

[0088] In one possibility, as shown in FIG5 , the clock generating circuit 20 may further include an initial register signal generating circuit 23 , which may include a first NAND gate u1 and a seventh NOT gate u2 ;

[0089] The first input end of the first NAND gate u1 is used to receive the first target clock signal, the second input end of the first NAND gate u1 is used to receive the Nth register signal, the output end of the first NAND gate u1 is connected to the input end of the seventh NAND gate u2, and the output end of the seventh NAND gate u2 is used to output the initial register signal.

[0090] In another possibility, as shown in FIG6 , the first NAND gate u1 and the seventh NOT gate u2 are equivalently replaced by the first AND gate u3 ;

[0091] The first input end of the first AND gate u3 is used to receive the first target clock signal, the second input end of the first AND gate u3 is used to receive the Nth register signal, and the output end of the first AND gate u3 is used to output the initial register signal.

[0092] FIG6 also shows N=16 as an example, and the Nth register signal is the 16th register signal net15.

[0093] In some embodiments, the j-th latch 221 is further configured to receive a reset signal and reset the j-th register signal output by the latch according to the reset signal.

[0094] It should be noted that when the DRAM chip is powered on, the reset terminals of the even-numbered latches are used to receive reset signals and reset the corresponding output register signals.

[0095] Further, in some embodiments, as shown in FIG5 , the reset signal includes a first reset signal and a second reset signal;

[0096] When j<N, the j-th latch 221 is used to receive the first reset signal, and according to the first reset signal, the j-th register signal output by the latch is in the first level state;

[0097] When j=N, the Nth latch 221 is used to receive the second reset signal, and to make the Nth register signal output by the latch be in the second level state according to the second reset signal.

[0098] Here, the first reset signal is represented by RSETB, and the second reset signal is represented by RSETD. In addition, the first level state can be a low level state (logic "0"), and the second level state can be a high level state (logic "1").

[0099] It should be noted that, except for the last level latch which sets the net15 signal to 1 according to the RSETD signal, the other even-numbered level latches will reset the net1 signal, net3 signal, net5 signal, net7 signal, net9 signal, net11 signal and net13 signal to 0 according to the RSETB signal.

[0100] In some embodiments, as shown in FIG7 , the initial reset signal RESET is inverted by the eighth NOT gate b1 to generate the first reset signal RSETB. The first reset signal RSETB is further inverted by the ninth NOT gate b2 to generate the second reset signal RSETD. In other words, the initial reset signal RESET is delayed by two NOT gates (the eighth NOT gate b1 and the ninth NOT gate b2) to generate the second reset signal RSETD. It can be understood that the initial reset signal RESET and the first reset signal RSETB are a pair of inverted signals, and the second reset signal RSETD is a delayed signal of the initial reset signal RESET.

[0101] In some embodiments, when the received inverted clock signal or preset clock signal is in a first level state, the register signal output by the latch is the register signal output by the latch before the inverted clock signal or preset clock signal becomes the first level state; and, when the received inverted clock signal or preset clock signal is in a second level state, the register signal output by the latch is the signal received at the input end of the latch.

[0102] In other words, the latch in the clock generation circuit 20 has the characteristics of high-level transmission and low-level latching (high-deliver-low latch). It can be understood that when the inverted clock signal or the preset clock signal received by the latch is in a high-level state, the output signal of the latch is the input signal of the latch, the latch acts as a long-pass signal, and the output signal changes with the input signal; when the inverted clock signal or the preset clock signal received by the latch is in a low-level state, the output signal of the latch is the output signal sampled by the latch just after or before the inverted clock signal or the preset clock signal changes to a low-level state, the latch acts as a latch, and the output signal does not change with the input signal.

[0103] In some embodiments, referring to FIG8 , which shows a schematic diagram of the structure of a signal generating circuit provided by an embodiment of the present disclosure. As shown in FIG8 , the clock generating circuit 20 may further include a signal generating circuit 24;

[0104] The signal generating circuit 24 is used to receive an initial clock signal, perform a first delay processing on the initial clock signal, and generate a preset clock signal; and perform a second delay processing and an inversion processing on the initial clock signal to generate an inverted clock signal; and perform a third delay processing on the initial clock signal to generate a delayed clock signal; wherein the duration of the first delay processing and the second delay processing is the same and both are less than the duration of the third delay processing, and the difference between the duration of the first delay processing and the second delay processing and the duration of the third delay processing is the delay duration of the latch.

[0105] It should be noted that the i-th latch 211 receives an inverted clock signal, which samples the input signal of the i-th latch 211 with the inverted clock signal to generate the i-th register signal, which is then subjected to an OR logic process with the delayed clock signal; the j-th latch 221 receives a preset clock signal, which samples the input signal of the j-th latch 221 with the preset clock signal to generate the j-th register signal, which is then subjected to an AND-NOT logic process with the delayed clock signal. It can be understood that when the difference between the duration of the first delay process and the third delay process is the delay duration of the latch, and the difference between the duration of the second delay process and the third delay process is the delay duration of the latch, the signal sampled by the inverted clock signal or the preset clock signal can just undergo corresponding logic processing with the delayed clock signal, thereby meeting the timing requirements.

[0106] Further, in some embodiments, as shown in FIG8 , the signal generating circuit 24 may include a first NOT gate a1, a first transmission gate a2, a second NOT gate a3, a third NOT gate a4, a fourth NOT gate a5, a fifth NOT gate a6, a second transmission gate a7, and a sixth NOT gate a8;

[0107] The input end of the first NOT gate a1 is used to receive the initial clock signal, the output end of the first NOT gate a1 is connected to the first end of the first transmission gate a2 and the input end of the third NOT gate a4, the second end of the first transmission gate a2 is connected to the input end of the second NOT gate a3, and the output end of the second NOT gate a3 is used to output a preset clock signal;

[0108] The output end of the third NOT gate a4 is connected to the input end of the fourth NOT gate a5 and the input end of the fifth NOT gate a6, and the output end of the fourth NOT gate a5 is used to output an inverted clock signal;

[0109] The output end of the fifth NOT gate a6 is connected to the first end of the second transmission gate a7 , the second end of the second transmission gate a7 is connected to the input end of the sixth NOT gate a8 , and the output end of the sixth NOT gate a8 is used to output the delayed clock signal.

[0110] Here, the initial clock signal is represented by FRP_PDL_D.

[0111] As shown in Figure 8, the first transmission gate a2 and the second transmission gate a7 are each composed of a PMOS transistor and an NMOS transistor connected in parallel. The gate of the PMOS transistor is used to receive the ground signal VSS, and the gate of the NMOS transistor is used to receive the power signal VDD. In addition, in the embodiment of the present disclosure, the first end is the input end, and the second end is the output end.

[0112] It can be understood that the FRP_PDL_D signal is subjected to a first delay processing through the first NOT gate a1, the first transmission gate a2 and the second NOT gate a3 to generate the CLK signal; the FRP_PDL_D signal is subjected to a second delay processing and inversion processing through the first NOT gate a1, the third NOT gate a4 and the fourth NOT gate a5 to generate the CLKB signal; the FRP_PDL_D signal is subjected to a third delay processing through the first NOT gate a1, the third NOT gate a4, the fifth NOT gate a6, the second transmission gate a7 and the sixth NOT gate a8 to generate the CLKD signal.

[0113] Because the FRP_PDL_D signal passes through two NOT gates and a transmission gate (first NOT gate a1, first transmission gate a2, and second NOT gate a3) to obtain the CLK signal, and the FRP_PDL_D signal passes through three NOT gates (first NOT gate a1, third NOT gate a4, and fourth NOT gate a5) to obtain the CLKB signal, and because both the transmission gate and the NOT gate include a PMOS transistor and an NMOS transistor, the duration of the first delay processing and the second delay processing is the same.

[0114] It should be noted that the clock signals generated from the FRP_PDL_D signal utilize a special design. Both the CLK and CLKB signals are derived from the FRP_PDL_D signal plus three levels of logic gates. Specifically, the CLK signal is the FRP_PDL_D signal plus the first NOT gate a1, the first transmission gate a2, and the second NOT gate a3, totaling three levels of logic gates. The CLKB signal is the FRP_PDL_D signal plus the first NOT gate a1, the third NOT gate a4, and the fourth NOT gate a5, totaling three levels of logic gates. The CLKD signal is the FRP_PDL_D signal plus the first NOT gate a1, the third NOT gate a4, the fifth NOT gate a6, the second transmission gate a7, and the sixth NOT gate a8, totaling five levels of logic gates. Because each latch includes two levels of logic gates, the net0-net15 signals and the CLKD signal both have the delay length of the FRP_PDL_D signal plus the five levels of logic gates. This prevents glitches when performing logical OR or NOT operations on the two signals, thus meeting timing requirements.

[0115] In some embodiments, the i-th target clock signal is used to control the timing of writing the first data, and the j-th target clock signal is used to control the timing of writing the second data; the first data is one bit of the two-bit data transmitted on the data bus, and the second data is the other bit of the two-bit data transmitted on the data bus.

[0116] It should be noted that in the disclosed embodiments, the generated target clock signals are used to control the timing of writing double data. Double data refers to two bits of data transmitted on a single data bus, namely, first data and second data. Here, a set of target clock signals is generated by the odd-level clock generation subcircuit to control the timing of writing the first data; a set of target clock signals is generated by the even-level clock generation subcircuit to control the timing of writing the second data.

[0117] Furthermore, in some embodiments, the effective level time of the i-th target clock signal is a first duration, and the effective level time of the j-th target clock signal is a second duration;

[0118] The sum of the first time length and the second time length satisfies the time interval between a column address strobe pulse command and a next column address strobe pulse command.

[0119] It should be noted that the sum of the first duration and the second duration is tCCD; wherein the first duration may be 4T, the second duration may be tCCD-4T, and T is the clock period of the system clock signal, but this is not specifically limited.

[0120] It should also be noted that when the data window of the first data in the double data is 4T, the first time length is also 4T, which can match the data window of the first data and meet the timing of writing the first data; when the data window of the second data in the double data is tCCD-4T, the second time length is also tCCD-4T, which can match the data window of the second data and meet the timing of writing the second data.

[0121] In some embodiments, the initial clock signal is generated according to a read command, and one read command corresponds to a pulse in the initial clock signal having a pulse length of the first duration and a level state of the second level state.

[0122] It can be understood that each time the DRAM receives a read command, the FRP_PDL_D signal generates a high-level pulse with a pulse length of 4T.

[0123] The FRP_PDL_D signal is first delayed to generate the CLK signal. In other words, the CLK signal is derived from the FRP_PDL_D signal, which has a pulse length of 4T. Since the FRP_PDL_D signal is low by default and only generates a high pulse with a pulse length of 4T when the DRAM receives a read command, the CLK signal is also low by default. The CLKB signal and the CLK signal are a pair of inverted signals, with the CLKB signal being high by default. The CLKD signal is a delayed version of the CLK signal and is low by default.

[0124] Refer to Figure 9, which shows a timing diagram of a clock generation circuit provided by an embodiment of the present disclosure. Because when the DRAM chip is powered on, the ne15 signal is set to 1, and the net1 signal, net3 signal, net5 signal, net7 signal, net9 signal, net11 signal and net13 signal are reset to 0, and the latch has the characteristics of high-level transmission and low-level latching, and the latch is an inverting output terminal, so when the entire circuit is in the initial state, the level state of the net0~net15 signals is 0010101010101011. Because the net1 signal is low, the net1 signal and the CLKD signal are logically processed in the non-AND, as shown in Figure 9, and the resulting REGB <0> The signal is high level; because REGB <0> The signal is high, the net15 signal is high, and the initial register signal obtained by the first NAND gate u1 and the seventh NOT gate u2 is high, that is, the signal received by the input end of the first latch is high, then the net0 signal is low; in this way, the net0 signal and the CLKD signal are processed by OR logic, and the obtained REGB <15> The signal is low level. Similarly, REGB<0~14>(REGB <0> ~REGB <14> The combined writing method) signals are all high level.

[0125] When the high-level pulse with a pulse length of 4T of the FRP_PDL_D signal arrives, the CLK signal is high, the CLKB signal is low, and the CLKD signal is high. After the action of each latch, the level state of the net0~net15 signals of the entire circuit changes to 011010101010101010 when the high-level pulse with a pulse length of 4T arrives. The net0~net15 signals are respectively processed with the CLKD signal through logical OR or logical NAND, as shown in Figure 9. <0> The signal becomes low level, REGB<1~15>(REGB <1> ~REGB <15> The combined writing method) signals are all high level.

[0126] When the high level pulse with a pulse length of 4T of the FRP_PDL_D signal ends, the CLK signal is low again, the CLKB signal is high, and the CLKD signal is low. After the action of each latch, the level state of the net0~net15 signals of the entire circuit becomes 110010101010101010 at the end of the high level pulse with a pulse length of 4T, as shown in Figure 9. At this time, REGB <0> The signal becomes high, REGB <1> Changes to low level, REGB<2~15>(REGB <2> ~REGB <15> When the next read command arrives, the same logic is applied and no further details will be given here.

[0127] In summary, the clock generating circuit 20 can be considered as a shift register, and the CLK signal comes from the FRP_PDL_D signal with a pulse length of 4T. When the DRAM chip is powered on, the shift register is reset, and REGB <0> The signal and net15 signal are both 1, the initial register signal received by the input end of the first latch is high level, and the latch in the clock generation circuit 20 has the characteristics of high level transmission and low level latching, so the net0 signal is 0 after the shift register is reset; and when each read command arrives thereafter, the FRP_PDL_D signal will generate a high level pulse with a pulse length of 4T, during which the potential of the net1 signal will be changed to 1, and the level state of the net1 signal will last for 4T, and then it will be processed with the CLKD signal with a pulse length of 4T by logical AND NOT, and finally REGB <0> The signal generates a low-level pulse with a pulse length of 4T; when the FRP_PDL_D signal returns to a low level, the CLKB signal is high, the high level of the net1 signal continues to shift back to the low level of the net2 signal, and the net2 signal is then processed with the CLKD signal in an OR logic manner, REGB <1> The signal becomes low level and lasts until the next read command arrives, that is, when the high level pulse of the FRP_PDL_D signal with a pulse length of 4T arrives, the above shift process continues. That is, the clock generating circuit 20 converts the 4T high level pulse of the input FRP_PDL_D signal into two pulses through the latch and logic circuit, for example, REGB <0> Signaling and REGB <1> The signal is generated from a 4T high-level pulse of the FRP_PDL_D signal.

[0128] As shown in Figure 10, REGB<15:0> (REGB <0> ~REGB <15> The signal is inverted by the tenth NOT gate b3 to obtain PDL<15:0> (PDL <0> ~PDL <15> The PDL<15:0> signal is used to write double data to the FIFO structure. The PDL<15:0> signal waveform is the inverse of the REGB<15:0> signal. The timing of the PDL<15:0> signal is shown in Figure 11.

[0129] Through the circuit design of the clock generation circuit 20, the odd-numbered latches can be regarded as a group of shift devices that operate on the rising edge of the CLK signal; the even-numbered latches can be regarded as a group of shift devices that operate on the falling edge of the CLK signal. The odd-numbered latches form the PDL shown in FIG11. <0> Signal, PDL <2> Signal, ..., PDL <14> By shifting the signal, the even-numbered latches form the PDL shown in Figure 11. <1> Signal, PDL <3> Signal, ..., PDL <13> Shift of the signal.

[0130] Refer to Figure 12, which shows a timing analysis diagram of a clock generation circuit provided by an embodiment of the present disclosure. As shown in Figure 12, the 16-bit digits represent the level status of the net0-net15 signals, respectively, and D represents the level status of the net15 signal; the initial state (Initial) is the level status of the net0-net15 signals when the DRAM chip is powered on. When the CLK rising edge (rising) box is 1, the PDL signal generated by the corresponding bit is ultimately high; when the CLK falling edge (falling) box is 0, the PDL signal generated by the corresponding bit is high.

[0131] Based on the clock generating circuit 20 in the aforementioned embodiment, referring to FIG13, a schematic diagram of the structure of a clock generating circuit provided by the embodiment of the present disclosure is shown. As shown in FIG13, the clock generating circuit 20 only uses a set of shift circuits (Shift), and through the latch and logic circuit therein, a PDL signal is obtained according to the FRP_PDL_D signal, thereby writing double data, saving circuit resources, and ensuring PDL <0> PDL after signal ends <1> The timing conditions for the signal to start.

[0132] In another embodiment of the present disclosure, referring to Figure 14, which shows a schematic diagram of the composition structure of a memory provided by an embodiment of the present disclosure, as shown in Figure 14, the memory 30 may include the clock generation circuit 20 according to any one of the aforementioned embodiments.

[0133] The memory 30 may be, for example, SRAM, DRAM, SDRAM, DDR SDRAM, etc., and is not specifically limited thereto.

[0134] Furthermore, in some embodiments, the memory 30 may include a DRAM chip. The DRAM chip may conform not only to memory specifications such as DDR, DDR2, DDR3, DDR4, DDR5, and DDR6, but also to memory specifications such as LPDDR, LPDDR2, LPDDR3, LPDDR4, LPDDR5, and LPDDR6, which are not specifically limited here.

[0135] In the embodiment of the present disclosure, for the memory 30 , only one clock generating circuit 20 can be used to obtain two sets of target clock signals, thereby saving circuit resources.

[0136] The above description is merely a preferred embodiment of the present disclosure and is not intended to limit the scope of protection of the present disclosure.

[0137] It should be noted that, in this disclosure, the terms "comprise," "include," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not preclude the presence of other identical elements in the process, method, article, or apparatus comprising the element.

[0138] The serial numbers of the above-mentioned embodiments of the present disclosure are for description only and do not represent the advantages or disadvantages of the embodiments.

[0139] The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0140] The features disclosed in the several product embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new product embodiments.

[0141] The features disclosed in several method or device embodiments provided in this disclosure may be arbitrarily combined without conflict to obtain new method embodiments or device embodiments.

[0142] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.< / n>

Claims

1. A clock generation circuit (20), characterized in that, The clock generation circuit is used to generate N target clock signals, where N is a positive even number, and the clock generation circuit includes N clock generation sub-circuits; among them: The i-th clock generation sub-circuit (21) is used to receive the i-th register input signal, the inverted clock signal (CLKB), and the delayed clock signal (CLKD); sample and latch the i-th register input signal according to the inverted clock signal to generate the i-th register signal; perform a first logic process on the i-th register signal and the delayed clock signal to generate the i-th target clock signal; where i is a positive odd number greater than or equal to 1 and less than N, when i = 1, the i-th register input signal is the initial register signal, and when i > 1, the i-th register input signal is the (i - 1)-th register signal; The j-th clock generation sub-circuit (22) is used to receive the (j - 1)-th register signal, the preset clock signal (CLK), and the delayed clock signal; sample and latch the (j - 1)-th register signal according to the preset clock signal to generate the j-th register signal; perform a second logic process on the j-th register signal and the delayed clock signal to generate the j-th target clock signal; where j is a positive even number greater than 1 and less than or equal to N; Among them, the preset clock signal and the inverted clock signal are a pair of anti-phase signals, and the delayed clock signal is a delayed signal of the preset clock signal.

2. The clock generation circuit according to claim 1, wherein The first logic process is an OR logic process, and the second logic process is a NAND logic process.

3. The clock generation circuit according to claim 2, characterized in that, The i-th clock generation sub-circuit includes the i-th latch (211) and the i-th first logic circuit (212), and the j-th clock generation sub-circuit includes the j-th latch (221) and the j-th second logic circuit (222); The i-th latch is used to receive the i-th register input signal and the inverted clock signal, and sample and latch the i-th register input signal according to the inverted clock signal to generate the i-th register signal; The i-th first logic circuit is used to receive the i-th register signal and the delayed clock signal, and perform an OR logic process on the i-th register signal and the delayed clock signal to generate the i-th target clock signal; The j-th latch is used to receive the (j - 1)-th register signal and the preset clock signal, and sample and latch the (j - 1)-th register signal according to the preset clock signal to generate the j-th register signal; The j-th second logic circuit is used to receive the j-th register signal and the delayed clock signal, and perform a NAND logic process on the j-th register signal and the delayed clock signal to generate the j-th target clock signal.

4. The clock generation circuit according to any one of claims 1-3, characterized in that, The clock generation circuit further includes a first AND gate (u3); The first input terminal of the first AND gate is used to receive the first target clock signal, the second input terminal of the first AND gate is used to receive the Nth register signal, and the output terminal of the first AND gate is used to output the initial register signal.

5. The clock generation circuit according to claim 3 or 4, wherein The jth latch is further configured to receive a reset signal and reset the jth register signal output by the latch according to the reset signal.

6. The clock generation circuit according to claim 5, wherein The reset signal includes a first reset signal (RSETB) and a second reset signal (RSETD); When j < N, the jth latch is configured to receive the first reset signal and make the jth register signal output by the latch in a first level state according to the first reset signal; When j = N, the Nth latch is configured to receive the second reset signal and make the Nth register signal output by the latch in a second level state according to the second reset signal.

7. The clock generation circuit according to claim 6, wherein When the received inverted clock signal or the preset clock signal is in the first level state, the register signal output by the latch is the register signal output by the latch before the inverted clock signal or the preset clock signal changes to the first level state; and when the received inverted clock signal or the preset clock signal is in the second level state, the register signal output by the latch is the signal received at the input terminal of the latch.

8. The clock generation circuit according to any one of claims 3-7, characterized in that, The clock generation circuit further includes a signal generation circuit (24); The signal generation circuit is configured to receive an initial clock signal (FRP_PDL_D), perform a first delay process on the initial clock signal to generate the preset clock signal; perform a second delay process and an inversion process on the initial clock signal to generate the inverted clock signal; and perform a third delay process on the initial clock signal to generate the delayed clock signal; wherein, the durations of the first delay process and the second delay process are the same and are both less than the duration of the third delay process, and the difference between the durations of the first delay process and the second delay process and the duration of the third delay process is the delay duration of the latch.

9. The clock generation circuit according to claim 8, wherein The signal generation circuit includes a first NOT gate (a1), a first transmission gate (a2), a second NOT gate (a3), a third NOT gate (a4), a fourth NOT gate (a5), a fifth NOT gate (a6), a second transmission gate (a7) and a sixth NOT gate (a8); The input terminal of the first NOT gate is used to receive the initial clock signal, the output terminal of the first NOT gate is connected to the first end of the first transmission gate and the input terminal of the third NOT gate, the second end of the first transmission gate is connected to the input terminal of the second NOT gate, and the output terminal of the second NOT gate is used to output the preset clock signal; The output terminal of the third NOT gate is connected to the input terminal of the fourth NOT gate and the input terminal of the fifth NOT gate, and the output terminal of the fourth NOT gate is used to output the inverted clock signal; The output terminal of the fifth NOT gate is connected to the first terminal of the second transmission gate, the second terminal of the second transmission gate is connected to the input terminal of the sixth NOT gate, and the output terminal of the sixth NOT gate is used to output the delayed clock signal.

10. The clock generation circuit according to claim 8 or 9, characterized in that, The ith target clock signal is used to control the timing of writing the first data, and the jth target clock signal is used to control the timing of writing the second data; the first data is one bit of the two-bit data transmitted on the data bus, and the second data is the other bit of the two-bit data transmitted on the data bus.

11. The clock generation circuit according to claim 10, wherein The effective level time of the ith target clock signal is a first duration, and the effective level time of the jth target clock signal is a second duration; The sum of the first duration and the second duration satisfies the time interval between a column address strobe pulse command and the next column address strobe pulse command.

12. The clock generation circuit according to claim 11, wherein The initial clock signal is generated according to a read command, and one read command corresponds to a pulse in the initial clock signal with a pulse length of the first duration and a level state of the second level state.

13. A memory (30), characterized in that, The memory includes the clock generation circuit (20) according to any one of claims 1 to 12.

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