Physical address query method, flash memory device controller and flash memory device

Abstract

The present application relates to the technical field of storage application, and discloses a physical address query method, a flash memory device controller and a flash memory device. The physical address query method comprises: acquiring a logical address; by querying a compact array, determining whether the compact array can map the logical address to a corresponding physical address; if the compact array cannot map the logical address to the corresponding physical address, querying a range bucket hash structure to determine whether a range bucket node corresponding to the logical address exists in a least recently used cache; and if the range bucket node corresponding to the logical address exists in the least recently used cache, querying the logical address from the range bucket node to obtain the physical address corresponding to the logical address. By querying from the compact array and the range bucket hash structure the physical address corresponding to the logical address, the present application can save DRAM resources and also maintain high indexing performance, thereby improving the query efficiency of the physical address.

Description

Physical address query method, flash memory device controller and flash memory device

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to the Chinese patent application filed with the China Patent Office on December 30, 2023, with application number 202311873817.5, and entitled “Physical Address Query Method, Flash Memory Device Controller and Flash Memory Device”, all contents of which are incorporated by reference into this application. Technical Field

[0003] The present application relates to the field of storage application technology, and in particular to a physical address query method, a flash memory device controller, and a flash memory device. Background Art

[0004] In modern solid-state drives (SSDs), the logical-to-physical address mapping table (L2P table) is a crucial component of the FTL (Flash Transfer Layer). This mapping table not only directly impacts data access performance but also consumes the vast majority of the FTL's DRAM resources. With the advent of the big data era, the demand for large-capacity SSDs is continuously increasing, making FTL DRAM resources even more valuable.

[0005] In modern technology, SSD manufacturers are continuously increasing SSD capacity by adopting fast stacking processes and manufacturing techniques, as well as increasing the number of flash channels and chips. To ensure high address translation performance, SSD manufacturers cache mapping tables in the device's DRAM. Typically, a 1TB SSD requires 1GB of DRAM resources. The mapping table not only determines the efficiency of indexing flash pages but also affects SSD DRAM usage. Due to the cost and power constraints of SSD controllers, to expand the DRAM capacity within the SSD, existing solutions have proposed new mapping table structures such as DFTL (demand-based Flash Translation Layer) and LeaFTL (Learning-Based Flash Translation Layer) to reduce DRAM resource usage. However, DFTL has a significant performance impact, while LeaFTL has performance overhead and modifies the FTL's page allocation logic. Neither of these solutions can maintain high indexing performance while also conserving DRAM resources.

[0006] Application Contents

[0007] An embodiment of the present application provides a physical address query method, a flash memory device controller, and a flash memory device. By querying the physical address corresponding to the logical address in a compact array and a range bucket hash structure, the present application can maintain high indexing performance and improve the query efficiency of the physical address while saving DRAM resources.

[0008] The embodiments of this application provide the following technical solutions:

[0009] In a first aspect, an embodiment of the present application provides a physical address query method, which is applied to a flash memory device, wherein the flash memory device includes a cache space, the cache space stores a compact array and a range bucket hash structure, and the physical address query method includes:

[0010] Get the logical address;

[0011] Query the compact array to determine whether the compact array can map the logical address to the corresponding physical address;

[0012] If the compact array cannot map the logical address to the corresponding physical address, the range bucket hash structure is queried to determine whether the range bucket node corresponding to the logical address exists in the least recently used cache;

[0013] If the range bucket node corresponding to the logical address exists in the least recently used cache, the logical address is queried in the range bucket node to obtain the physical address corresponding to the logical address.

[0014] In some embodiments, the method further comprises:

[0015] Constructing a compact array, wherein the compact array is composed of compact array nodes, and a compact array node includes at least a first address, a first bitmap, and a second bitmap, specifically including:

[0016] Obtain a preset number of consecutive logical addresses;

[0017] According to the logical address, obtain the physical address corresponding to the logical address;

[0018] Identify a corresponding compact array node according to the logical address, and store the first physical address in the first address of the compact array node;

[0019] According to the physical address corresponding to the logical address, obtain the address state corresponding to every two adjacent physical addresses, and store the address state in the first bitmap, wherein the address state includes a continuous state and a discontinuous state, and each address state occupies one bit of storage space;

[0020] Obtaining an expression state corresponding to the physical address, and storing the expression state corresponding to the physical address in a second bitmap to obtain a second bitmap, wherein the expression state corresponding to the physical address includes an initial state and an unexpressible state, and each state corresponding to the physical address occupies one bit of storage space;

[0021] Construct a compact array node based on the first address, the first bitmap, and the second bitmap.

[0022] In some embodiments, determining whether the compact array can map a logical address to a corresponding physical address by querying the compact array includes:

[0023] Obtaining a first physical address according to the first bitmap, wherein the first physical address is continuous with a physical address corresponding to the logical address;

[0024] Obtaining an address distance between the first physical address and the physical address corresponding to the logical address and an expression state corresponding to the first physical address;

[0025] According to an address distance between the first physical address and a physical address corresponding to the logical address and an expression state corresponding to the first physical address, it is determined whether the compact array can map the logical address to the corresponding physical address.

[0026] In some embodiments, the method further comprises:

[0027] Construct a range bucket hash structure, wherein the range bucket hash structure includes a global range table and a range bucket node, the range bucket node includes a hash bucket, a storage bucket, and a split bucket, and the hash bucket includes a first hash bucket and a second hash bucket, specifically including:

[0028] Calculate the target bucket addresses of the first hash bucket and the second hash bucket according to the logical address, including: A = (key)% LEN, B = (key + LEN / 2)% LEN,

[0029] Among them, key is the logical address, LEN is the total number of hash buckets, A is the target bucket address of the first hash bucket, and B is the target bucket address of the second hash bucket.

[0030] In some embodiments, the method further comprises:

[0031] Determining whether there is a first empty slot in the first hash bucket according to the target bucket address of the first hash bucket;

[0032] If there is a first empty slot in the first hash bucket, the physical address corresponding to the logical address is stored in the first empty slot;

[0033] If the first hash bucket does not have a first empty slot, determining whether the second hash bucket has a second empty slot according to the target bucket address of the first hash bucket;

[0034] If there is a second empty slot in the second hash bucket, the physical address corresponding to the logical address is stored in the second empty slot;

[0035] If the second hash bucket does not have a second empty slot, linearly probe the first hash bucket and the second hash bucket to obtain a third empty slot;

[0036] If the hash bucket does not have a third empty slot, determine whether the storage bucket has a fourth empty slot;

[0037] If the storage bucket does not have a fourth empty slot, the range bucket node is split and expanded to obtain a split range bucket node, and the physical address corresponding to the logical address is stored in the split range bucket node.

[0038] In some embodiments, performing a linear probe on the first hash bucket and the second hash bucket to obtain a third empty slot includes:

[0039] Get the linear detection distance;

[0040] A third empty slot is obtained according to the linear detection distance, the target bucket address of the first hash bucket and the target bucket address of the second hash bucket, wherein the bucket address corresponding to the third empty slot is (the target bucket address of the first hash bucket, the target bucket address of the first hash bucket + the linear detection distance) or (the target bucket address of the second hash bucket, the target bucket address of the second hash bucket + the linear detection distance).

[0041] In some embodiments, the global range table includes a storage state of the range bucket, the storage state of the range bucket includes a first state and a second state, and the method further includes:

[0042] If the storage state of the range bucket is the first state, it is determined that the range bucket node is stored in the flash memory space, and the range bucket node is read into the least recently used cache.

[0043] In some embodiments, the method further comprises:

[0044] Get the range bucket node corresponding to the logical address, including:

[0045] According to the global range table, obtain the red-black tree structure;

[0046] According to the logical address, the red-black tree structure is queried to obtain the range bucket node corresponding to the logical address.

[0047] In some embodiments, querying a range bucket node for a logical address to obtain a physical address corresponding to the logical address includes:

[0048] According to the target bucket addresses of the first hash bucket and the second hash bucket, query whether there is a physical address corresponding to the logical address in the first hash bucket and the second hash bucket;

[0049] If the physical address corresponding to the logical address does not exist in the first hash bucket and the second hash bucket, the storage bucket and the split range bucket node are queried in sequence until the physical address corresponding to the logical address is found.

[0050] In a second aspect, an embodiment of the present application provides a flash memory device controller, comprising:

[0051] at least one processor; and

[0052] a memory communicatively connected to at least one processor; wherein,

[0053] The memory stores instructions that can be executed by at least one processor. The instructions are executed by the at least one processor to enable the at least one processor to perform the physical address query method according to the first aspect.

[0054] In a third aspect, an embodiment of the present application provides a flash memory device, including:

[0055] The flash memory device controller according to the second aspect;

[0056] At least one flash memory medium is communicatively coupled to the flash memory device controller.

[0057] In a fourth aspect, an embodiment of the present application provides a non-volatile computer-readable storage medium, which stores computer-executable instructions. The computer-executable instructions are used to enable a flash memory device to execute the physical address query method of the first aspect.

[0058] The beneficial effects of the embodiments of the present application are: different from the related art, the embodiments of the present application provide a physical address query method, which is applied to a flash memory device, and the flash memory device includes a cache space, and the cache space stores a compact array and a range bucket hash structure. The physical address query method includes: obtaining a logical address; judging whether the compact array can map the logical address to the corresponding physical address by querying the compact array; if the compact array cannot map the logical address to the corresponding physical address, querying the range bucket hash structure to judge whether the range bucket node corresponding to the logical address exists in the least recently used cache; if the range bucket node corresponding to the logical address exists in the least recently used cache, querying the logical address in the range bucket node to obtain the physical address corresponding to the logical address. The present application can maintain high indexing performance and improve the query efficiency of the physical address by querying the physical address corresponding to the logical address in the compact array and the range bucket hash structure while saving DRAM resources.

[0059] Additional aspects and advantages of the embodiments of the present application will be described, shown, or explained in part in the following description through implementation of the embodiments of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0060] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without creative work.

[0061] One or more embodiments are exemplarily described by corresponding drawings, which do not constitute limitations on the embodiments. Elements with the same reference numerals in the drawings are represented as similar elements, and unless otherwise stated, the dimensions in the drawings do not constitute proportional limitations.

[0062] FIG1 is a schematic structural diagram of a flash memory device provided in an embodiment of the present application;

[0063] FIG2 is a schematic diagram of a flash memory device controller provided in an embodiment of the present application;

[0064] FIG3 is a flow chart of a physical address query method provided in an embodiment of the present application;

[0065] FIG4 is a schematic diagram of a compact array and range bucket hash structure provided by an embodiment of the present application;

[0066] FIG5 is a schematic diagram of a process for constructing a compact array provided by an embodiment of the present application;

[0067] FIG6 is a schematic diagram of a detailed flow chart of step S501 in FIG5 ;

[0068] FIG7 is a schematic diagram of a structure for constructing a compact array provided by an embodiment of the present application;

[0069] FIG8 is a schematic diagram of a detailed process of step S302 in FIG3 ;

[0070] FIG9 is a schematic diagram of a process for constructing a range bucket hash structure provided by an embodiment of the present application;

[0071] FIG10 is a schematic diagram of a detailed flow chart of step S901 in FIG9 ;

[0072] FIG11 is a schematic diagram of a detailed flow chart of step S916 in FIG9 ;

[0073] FIG12 is a schematic diagram of a process for obtaining a range bucket node corresponding to a logical address provided by an embodiment of the present application;

[0074] FIG13 is a schematic diagram of a detailed flow chart of step S1201 in FIG12 ;

[0075] FIG14 is a schematic diagram of the structure of a red-black tree provided in an embodiment of the present application;

[0076] FIG15 is a schematic diagram of the structure of a global range table and cache space provided in an embodiment of the present application;

[0077] FIG16 is a schematic diagram of the structure of a range bucket node provided in an embodiment of the present application;

[0078] FIG17 is a schematic diagram of a range bucket node splitting and merging provided by an embodiment of the present application;

[0079] FIG18 is a schematic diagram of a range bucket node splitting and merging provided by an embodiment of the present application;

[0080] FIG19 is a schematic diagram of a detailed process of step S304 in FIG3 ;

[0081] FIG20 is a schematic structural diagram of another flash memory device provided in an embodiment of the present application.

[0082] Description of reference numerals: DETAILED DESCRIPTION

[0083] In order to make the purpose, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly described below in combination with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments.

[0084] References to "embodiments" in this application mean that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the application. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor does it constitute an independent or alternative embodiment that is mutually exclusive of other embodiments.

[0085] In the description of the embodiments of this application, the technical terms "first" and "second" are used only to distinguish different objects and should not be understood to indicate or imply relative importance or implicitly specify the quantity, specific order, or primary and secondary relationship of the indicated technical features. In the description of the embodiments of this application, the meaning of "plurality" is more than two, unless otherwise clearly and specifically defined.

[0086] In the description of the embodiments of this application, the term "and / or" is simply a description of the association relationship between associated objects, indicating that three relationships can exist. For example, A and / or B can represent the following three situations: A exists alone, A and B exist simultaneously, and B exists alone. In addition, the character " / " in this document generally indicates that the associated objects are in an "or" relationship.

[0087] Next, the terms "upper", "lower", "top", "bottom", etc. used below to indicate directions or positional relationships are all relative to the first direction X. The technical features involved in the different embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.

[0088] The technical solution of this application is described in detail below with reference to the accompanying drawings:

[0089] In an embodiment of the present application, the flash memory device includes a solid-state drive or other storage device using flash memory as a storage medium, and the flash memory device controller includes a controller of a solid-state drive or other storage device using flash memory as a storage medium.

[0090] Specifically, please refer to FIG1 , which is a schematic structural diagram of a flash memory device provided in an embodiment of the present application.

[0091] As shown in Figure 1, a flash memory device 100 includes a flash memory medium 110 and a flash memory device controller 120 connected to the flash memory medium 110. The flash memory device 100 is connected to a host 200 via a wired or wireless communication method to implement data exchange.

[0092] Flash memory medium 110, as the storage medium of flash memory device 100, is also called flash memory, Flash, Flash memory or Flash particles. It is a type of storage device and a non-volatile memory that can store data for a long time even without current supply. Its storage characteristics are equivalent to those of a hard disk, making flash memory medium 110 the basis of storage media for various portable digital devices.

[0093] Among them, the flash memory medium 110 can be Nand Flash. Nand Flash uses a single transistor as a storage unit for binary signals. Its structure is very similar to that of ordinary semiconductor transistors. The difference is that the single transistor of Nand Flash has a floating gate and a control gate. The floating gate is used to store electrons. Its surface is covered by a layer of silicon oxide insulator and is coupled to the control gate through a capacitor. When negative electrons are injected into the floating gate under the action of the control gate, the storage state of the Nand Flash single crystal changes from "1" to "0". When the negative electrons are removed from the floating gate, the storage state changes from "0" to "1". The insulator covering the floating gate surface is used to trap the negative electrons in the floating gate, realizing data storage. In other words, the storage unit of Nand Flash is a floating gate transistor, which uses the floating gate transistor to store data in the form of charge. The amount of stored charge is related to the voltage applied to the floating gate transistor.

[0094] A Nand Flash includes at least one Chip chip, each Chip chip is composed of several Block physical blocks, and each Block physical block includes several Page pages. Among them, the Block physical block is the smallest unit for Nand Flash to perform erase operations, and the Page page is the smallest unit for Nand Flash to perform read and write operations. The capacity of a Nand Flash is equal to the number of its Block physical blocks * the number of Page pages contained in a Block physical block * the capacity of a Page page. Specifically, the flash memory medium 10 can be divided into single-level cells (SLC), multi-level cells (MLC), triple-level cells (TLC) and quad-level cells (QLC) according to the different levels of voltage of the storage cells.

[0095] The flash memory device controller 120 includes a data converter 121 , a processor 122 , a memory 123 , a flash memory controller 124 , and an interface 125 .

[0096] The data converter 121 is connected to the processor 122 and the flash memory controller 124 respectively, and the data converter 121 is used to convert binary data into hexadecimal data, and convert hexadecimal data into binary data. Specifically, when the flash memory controller 124 writes data to the flash memory medium 110, the binary data to be written is converted into hexadecimal data by the data converter 121, and then written into the flash memory medium 110. When the flash memory controller 124 reads data from the flash memory medium 110, the hexadecimal data stored in the flash memory medium 110 is converted into binary data by the data converter 121, and then the converted data is read from the binary data page register. The data converter 121 may include a binary data register and a hexadecimal data register. The binary data register can be used to store data converted from hexadecimal to binary, and the hexadecimal data register can be used to store data converted from binary to hexadecimal.

[0097] The processor 122 is respectively connected to the data converter 121, the memory 123, the flash memory controller 124 and the interface 125, wherein the processor 122 and the data converter 121, the memory 123, the flash memory controller 124 and the interface 125 can be connected through a bus or other means. The processor is used to run the non-volatile software programs, instructions and modules stored in the memory 123, thereby implementing any method embodiment of the present application.

[0098] The memory 123 is mainly used to cache the read / write instructions sent by the host 200 and the read data or write data obtained from the flash memory medium 110 according to the read / write instructions sent by the host 200. The memory 123 is a non-volatile computer-readable storage medium that can be used to store non-volatile software programs, non-volatile computer executable programs and modules. The memory 123 may include a program storage area, which can store an operating system and application programs required for at least one function. In addition, the memory 123 may include a high-speed random access memory and may also include a non-volatile memory, such as at least one disk storage device, a flash memory device, or other non-volatile solid-state storage device. In some embodiments, the memory 123 may optionally include a memory remotely located relative to the processor 124. Examples of the above-mentioned network include but are not limited to the Internet, an intranet, a local area network, a mobile communication network and a combination thereof. The memory 123 may be a static random access memory (SRAM), a tightly coupled memory (TCM), or a double data rate synchronous dynamic random access memory (DDR SRAM).

[0099] The flash memory controller 124 is connected to the flash memory medium 110, the data converter 121, the processor 122, and the memory 123. It is used to access the back-end flash memory medium 110 and manage various parameters and data I / O of the flash memory medium 110. Alternatively, it is used to provide an access interface and protocol, implement the corresponding SAS / SATA target protocol end or NVMe protocol end, obtain I / O instructions issued by the host 200, decode and generate internal private data results for execution. Alternatively, it is responsible for the core processing of the FTL (Flash Translation Layer).

[0100] Interface 125 connects the host 200 and the data converter 121, the processor 122 and the memory 123, and is used to receive data sent by the host 200, or receive data sent by the processor 122 to realize data transmission between the host 200 and the processor 122. Interface 125 can be a SATA-2 interface, a SATA-3 interface, a SAS interface, an MSATA interface, a PCI-E interface, an NGFF interface, a CFast interface, an SFF-8639 interface and an M.2 NVME / SATA protocol.

[0101] Please refer to FIG. 2 again, which is a schematic structural diagram of a flash memory device controller provided in an embodiment of the present application; wherein the flash memory device controller belongs to the above-mentioned flash memory device.

[0102] As shown in Figure 2, the flash memory device controller 120 includes: a PCIe interface controller 126, a DDR controller 127, an NVMe interface controller 128, a processor 122, a peripheral module 129, a data path module 1210 and a flash memory controller 124.

[0103] Specifically, the PCIe interface controller 126 is used to control the PCIe communication protocol, the DDR controller 127 is used to control the dynamic random access memory, the NVMe interface controller 128 is used to control the NVMe communication protocol, the peripheral module 129 is used to control other related communication protocols, the data path module 1210 is used to control the data path, for example: write cache management, and the flash memory controller 124 is used for flash memory data processing.

[0104] The flash memory device controller 120 further includes a data converter 121 , a memory 123 , an interface 125 , and the like.

[0105] Specifically, the data converter 121 is connected to the processor and the flash memory controller, respectively, and the data converter is used to convert binary data into hexadecimal data, and convert hexadecimal data into binary data. Specifically, when the flash memory controller writes data to the flash memory medium, the binary data to be written is converted into hexadecimal data by the data converter, and then written into the flash memory medium. When the flash memory controller reads data from the flash memory medium, the hexadecimal data stored in the flash memory medium is converted into binary data by the data converter, and then the converted data is read from the binary data page register. The data converter may include a binary data register and a hexadecimal data register. The binary data register can be used to store data converted from hexadecimal to binary, and the hexadecimal data register can be used to store data converted from binary to hexadecimal.

[0106] Specifically, the processor 122 is connected to the data converter 121, the memory 123, the flash memory controller 124 and the interface 125, respectively, wherein the processor and the data converter, the memory, the flash memory controller and the interface can be connected through a bus or other means, and the processor is used to run the non-volatile software programs, instructions and modules stored in the memory, thereby implementing any method embodiment of the present application.

[0107] Specifically, the memory is mainly used to cache read / write instructions sent by the host and read data or write data obtained from the flash memory medium according to the read / write instructions sent by the host. The memory, as a non-volatile computer-readable storage medium, can be used to store non-volatile software programs, non-volatile computer executable programs, and modules. The memory may include a program storage area, which can store an operating system and at least one application required for a function. In addition, the memory may include a high-speed random access memory and may also include a non-volatile memory, such as at least one disk storage device, a flash memory device, or other non-volatile solid-state storage device. In some embodiments, the memory may optionally include a memory remotely located relative to the processor. Examples of the above-mentioned network include but are not limited to the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof. The memory may be a static random access memory (SRAM), a tightly coupled memory (TCM), or a double data rate synchronous dynamic random access memory (DDR SRAM).

[0108] Specifically, the flash memory controller 124 is connected to the flash memory medium, data converter, processor and memory, and is used to access the back-end flash memory medium and manage various parameters and data I / O of the flash memory medium; or, it is used to provide access interfaces and protocols, implement the corresponding SAS / SATAtarget protocol end or NVMe protocol end, obtain I / O instructions issued by the host and decode and generate internal private data results for execution; or, it is used to be responsible for the core processing of the flash translation layer (FTL).

[0109] Specifically, interface 125 connects the host 200 and the data converter 121, the processor 122 and the memory 123, and is used to receive data sent by the host, or receive data sent by the processor to realize data transmission between the host and the processor. The interface can be a SATA-2 interface, a SATA-3 interface, a SAS interface, an MSATA interface, a PCI-E interface, an NGFF interface, a CFast interface, an SFF-8639 interface and an M.2NVME / SATA protocol.

[0110] Please refer to FIG3 , which is a flow chart of a physical address query method provided in an embodiment of the present application;

[0111] The physical address query method is applied to a flash memory device, and the execution subject of the physical address query method is one or at least two processors of the flash memory device.

[0112] As shown in FIG3 , the physical address query method includes:

[0113] Step S301: Obtaining a logical address;

[0114] Specifically, a logical address to be queried is obtained, and a physical address corresponding to the logical address is queried according to the logical address.

[0115] Please refer to FIG4 again, which is a schematic diagram of a compact array and range bucket hash structure provided by an embodiment of the present application;

[0116] As shown in Figure 4, NAND includes bucket pages and data pages. The mapping table includes a compact array and a range bucket hash structure. The compact array is used to store continuous table entries, and the range hash bucket structure is used to store non-continuous table entries, where continuous table entries refer to adjacent logical addresses (LPAs). Based on this, the mapping table is completely composed of a compact array and a range bucket hash structure and stored in DRAM. In the following physical address query process, the compact array is first queried to determine whether the logical address can be mapped to the corresponding physical address. If the query is successful, the physical address is returned directly; if the mapping relationship cannot be expressed in the compact array, the range bucket hash structure is queried to obtain the physical address corresponding to the logical address.

[0117] In the embodiments of the present application, to address the problem of how to reduce the memory overhead of the mapping table in DRAM, the present application provides the following two technical solutions:

[0118] Solution 1: The DFTL (demand-based FTL) solution is a demand-based selective index caching solution. The specific content of the DFTL solution is to reduce the memory overhead of page-level mapping. DFTL takes advantage of the locality of the workload and sets up a small mapping cache in the SSD's internal memory to cache frequently accessed mapping relationships (logical address LPA, physical address PPA). When the cache misses, DFTL requires an additional flash memory read to obtain the corresponding physical address (read amplification), which incurs additional performance overhead. Therefore, under workloads with high locality, DFTL is less affected by read amplification, but when faced with scenarios with more random reads and writes, the SSD has a serious performance bottleneck. Overall, the disadvantage of DFTL is mainly reflected in read and write loads with poor locality. An additional access to the flash memory is required to obtain the corresponding physical address, resulting in performance degradation.

[0119] Solution 2: LeaFTL (learning-based FTL) is a solution that stores mapping relationships based on learning indexes to reduce the memory overhead of the mapping table in DRAM. LeaFTL generates learning index segments through a piecewise linear regression method and organizes them in a log-structured mapping table (LSMT). The shortcomings of this technology are mainly manifested in two aspects: First, it relies on modifying the logic of FTL page allocation. After LeaFTL sorts the logical addresses in the model buffer, it needs to allocate continuous physical addresses to these logical addresses. Modern SSDs are highly dependent on internal parallelism, and it is very difficult to allocate continuous physical addresses to sorted logical addresses. Second, LeaFTL's model training includes sorting, parameter fitting, and merging, which are on the critical path. These time-consuming operations will directly affect write performance.

[0120] Based on the shortcomings of the above two solutions, the inventive concept of this application is based on the observation that there are a large number of adjacent logical addresses in the mapping table and their corresponding physical addresses are also adjacent. A new data structure is used to store the mapping relationship, thereby realizing effective compression of the mapping table. Specifically, through the compact array structure, 8 consecutive table entries can be compressed from 32 bytes to a compact array node of 6 bytes, achieving a compression ratio of 5.33 times. Combined with the range bucket hash structure, discontinuous table entries are stored. While taking into account DRAM overhead and high indexing performance, it can also achieve high memory utilization and support dynamic update of indexes.

[0121] Please refer to FIG5 again, which is a schematic diagram of a process for constructing a compact array according to an embodiment of the present application;

[0122] As shown in Figure 5, the process of building a compact array includes:

[0123] Step S501: constructing a compact array;

[0124] Please refer to FIG6 again, which is a detailed flowchart of step S501 in FIG5 ;

[0125] As shown in FIG6 , step S501: constructing a compact array, including:

[0126] Step S511: Obtain a preset number of consecutive logical addresses;

[0127] Specifically, the compact array uses the logical address as the array subscript and the physical address as the array element. Each (LPA, PPA) table entry occupies 8 bytes of memory, and a preset number of consecutive logical addresses are grouped together. The preset number can be set according to actual needs. For example, the preset number is set to 8. When the preset number is 8, the compact array uses 6 bytes of cache space to store a group of table entries.

[0128] Step S512: Obtain the physical address corresponding to the logical address according to the logical address;

[0129] Specifically, in the process of building the compact array, the physical address corresponding to the logical address is obtained according to the L2P mapping table and the logical address.

[0130] In an embodiment of the present application, a compact array is composed of compact array nodes, and the compact array nodes include at least one first address, a first bitmap, and a second bitmap.

[0131] Step S513: confirming the corresponding compact array node according to the logical address, and storing the first physical address to the first address of the corresponding compact array node;

[0132] Specifically, the first 4 bytes of each compact array node are used to store the first physical address (PPA0) of the group of table entries. The first 4 bytes are named the first address, and the first physical address (PPA0) of the group of table entries is stored at the first address according to the physical address corresponding to the logical address.

[0133] Step S514: obtaining address states corresponding to every two adjacent physical addresses according to the physical addresses corresponding to the logical addresses, and storing the address states in the first bitmap;

[0134] Specifically, according to the physical address corresponding to the logical address, the address state corresponding to every two adjacent physical addresses is obtained, wherein the address state includes a continuous state and a discontinuous state, and the address state corresponding to every two adjacent physical addresses is stored in the first bit map, which occupies one byte, and each bit represents a continuous relationship with the previous table entry, that is, each bit is used to store the address state. For example, the address state can be represented by 0 and 1, wherein 1 represents a continuous state and 0 represents a discontinuous state.

[0135] Step S515: Obtain the expression state corresponding to the physical address, and store the expression state corresponding to the physical address in the second bitmap to obtain the second bitmap; of course, in other embodiments, if the corresponding physical address has been indicated in the first bitmap as continuous with the previous physical address, the corresponding state in the second bitmap does not need to be constructed and can remain in the initial state.

[0136] Specifically, the second bitmap occupies one byte, and each bit in the second bitmap is used to store the expression status corresponding to the physical address. The expression status is used to indicate whether the corresponding physical address can be queried through a compact array. When the expression status is the initial state, it indicates that the physical address is the initial value (INIT_PPA), that is, the physical address corresponding to the logical address can be queried through a compact array; when the expression status is the inexpressible state, it indicates that the physical address corresponding to the logical address is in the range bucket hash table and cannot be queried through a compact array. For example, the expression status can be represented by 0 and 1, where 1 indicates the initial state and 0 indicates the inexpressible state.

[0137] Step S516: constructing compact array nodes according to the first address, the first bitmap and the second bitmap, and the compact array nodes form a compact array;

[0138] Specifically, please refer to FIG7 , which is a schematic diagram of a structure for constructing a compact array provided by an embodiment of the present application;

[0139] As shown in Figure 7, the array-based mapping table uses logical addresses as array subscripts and physical addresses as array elements. Each (LPA, PPA) table entry occupies 8 bytes of memory. Figure 7 takes 8 consecutive logical addresses as an example, and uses a 6-byte compact array node to replace them. The first 4 bytes of the compact array node store the first physical address (PPA0) of the table entry in the group; the middle bitmap, that is, the first bitmap, occupies one byte, and each bit represents the continuity relationship with the previous table entry. 1 indicates a continuous state, and 0 indicates a discontinuous state; the last bitmap, that is, the second bitmap, occupies one byte, and each bit is used to indicate whether the corresponding physical address is the initial value. A bit value of 0 indicates that the physical address is the initial value (INIT_PPA), and a bit value of 1 indicates that the compact array cannot express it.

[0140] In an embodiment of the present application, the structure of the compact array is used to compress continuous table entries in the mapping table. The core of the structure is that 8 consecutive table entries can be compressed from 32 bytes to a 6-byte compact array node through the compact array structure, achieving a compression ratio of 5.33 times.

[0141] Step S302: by querying the compact array, determining whether the compact array can map the logical address to the corresponding physical address;

[0142] Specifically, please refer to FIG8 , which is a detailed flowchart of step S302 in FIG3 ;

[0143] As shown in FIG8 , step S302 : by querying the compact array, determining whether the compact array can map the logical address to the corresponding physical address, including:

[0144] Step S321: Obtaining the address distance between the first physical address and the physical address corresponding to the logical address and the expression state corresponding to the first physical address according to the first bitmap and the second bitmap;

[0145] Specifically, according to the first bitmap, the address distance between the first physical address and the physical address corresponding to the logical address and the expression state corresponding to the first physical address are obtained. For example, assuming that the first bitmap A = b'0011100, the second bitmap B = b'0000000, PPA[5] is the physical address corresponding to the logical address, and PPA[2] ​​is the first physical address. If PPA[5] needs to be found, it is necessary to first determine that the address distance between PPA[5] and PPA[2] ​​is 3 according to the first bitmap, and then determine that the expression state corresponding to the first physical address is the initial state according to the second bitmap.

[0146] Step S322: determining whether the compact array can map the logical address to the corresponding physical address based on the address distance between the first physical address and the physical address corresponding to the logical address and the expression state corresponding to the first physical address;

[0147] Specifically, based on the address distance between the first physical address and the physical address corresponding to the logical address and the expression state corresponding to the first physical address, it is determined whether the compact array can map the logical address to the corresponding physical address. If the expression state corresponding to the first physical address is the initial state, it means that the compact array can map the logical address to the corresponding physical address; if the expression state corresponding to the first physical address is the unexpressible state, it means that the compact array cannot map the logical address to the corresponding physical address.

[0148] Step S303: Obtain the physical address corresponding to the logical address from the compact array;

[0149] Specifically, if the expression state corresponding to the first physical address is the initial state, the physical address corresponding to the logical address is obtained from the compact array.

[0150] The following two examples illustrate the query process of the physical address in detail:

[0151] Example 1: Assume that the two bitmaps are first bitmap A = b'0011100 and second bitmap B = b'0000000, the bit value 0 indicates that the physical address is the initial value (INIT_PPA), and the bit value 1 indicates that the compact array cannot be expressed. Then, the process of finding PPA[5] is divided into three steps:

[0152] ① First check the first bitmap A and find that PPA[5] and PPA[2] ​​are continuous and the distance is 3, so PPA[5]=PPA[2]+3.

[0153] ② Since PPA[2] ​​is discontinuous with PPA[1], checking bitmap B shows that the bit corresponding to PPA[2] ​​is 0, indicating that the expression state of PPA[2] ​​is the initial state.

[0154] ③Return result INIT_PPA+3.

[0155] Example 2: Set two bitmaps as first bitmap A = b'0011100 and second bitmap B = b'0100000, where a bit value of 0 indicates that the physical address is the initial value (INIT_PPA), and a bit value of 1 indicates that the compact array cannot be expressed. Then, the process of finding PPA[5] is divided into three steps:

[0156] ① First check the first bitmap A and find that PPA[5] and PPA[2] ​​are continuous and the distance is 3, so PPA[5]=PPA[2]+3.

[0157] ② Since PPA[2] ​​is discontinuous with PPA[1], checking the second bitmap B shows that the expression state corresponding to PPA[2] ​​is an inexpressible state, indicating that the value of PPA[2] ​​exists in the range bucket hash structure.

[0158] ③After querying the range bucket hash structure to obtain its corresponding physical address PPA, return (PPA+3), which is the physical address corresponding to PPA[5].

[0159] In an embodiment of the present application, as shown in Example 2 above, for some non-continuous table entries, a compact array cannot be effectively expressed. Therefore, the present application uses a range bucket hash structure to store these non-continuous table entries. In a traditional hash structure, in the case of perfect hashing, storing each (LPA, PPA) table entry pair in the mapping table requires at least 8 bytes of overhead. Compared to the 4-byte overhead in the array, the utilization of the range bucket hash structure is crucial to the final compression efficiency of the mapping table.

[0160] Please refer to FIG9 again, which is a schematic diagram of a process for constructing a range bucket hash structure according to an embodiment of the present application;

[0161] As shown in Figure 9, the process of building a range bucket hash structure includes:

[0162] Step S901: construct a range bucket hash structure;

[0163] Please refer to FIG10 again, which is a detailed flowchart of step S901 in FIG9 ;

[0164] As shown in FIG10 , step S901: constructing a range bucket hash structure, including:

[0165] Step S911: Calculate the target bucket addresses of the first hash bucket and the second hash bucket according to the logical address;

[0166] Specifically, the range bucket hash structure includes a range bucket node, which uses two separate hash functions to calculate the target bucket address of the logical address. The table entry to be inserted can be inserted into any empty slot of the two hash buckets. For example, the remainder is used as the hash function. Assuming that the number of hash buckets is LEN, the first hash bucket is A, and the second hash bucket is B, the two hash functions are: A = (key)% LEN, B = (key+LEN / 2)% LEN, where key is the logical address, LEN is the total number of hash buckets, A is the target bucket address of the first hash bucket, and B is the target bucket address of the second hash bucket. When the logical address is 503 and the number of hash buckets is 100, 503%100=3, so the target bucket address of the first hash bucket A corresponding to the logical address is 3. Similarly, the target bucket address of the second hash bucket B is (503+50)%100=53.

[0167] Step S912: determining whether there is a first empty slot in the first hash bucket according to the target bucket address of the first hash bucket;

[0168] Specifically, there are a fixed number of buckets in the range bucket node, and each bucket has 4 slots. According to the target bucket address of the first hash bucket, it is determined whether there is a first empty slot in the first hash bucket, that is, whether there is an empty slot in the first hash bucket. If there is a first empty slot in the first hash bucket, step S913 is entered; if there is a second empty slot in the first hash bucket, step S914 is entered.

[0169] Step S913: storing the physical address corresponding to the logical address into the first empty slot;

[0170] Specifically, if there is a first empty slot in the first hash bucket, the physical address corresponding to the logical address is stored in the first empty slot.

[0171] Step S914: determining whether there is a second empty slot in the second hash bucket according to the target bucket address of the second hash bucket;

[0172] Specifically, according to the target bucket address of the second hash bucket, determine whether there is a second empty slot in the second hash bucket, that is, determine whether there is an empty slot in the second hash bucket. If there is a second empty slot in the second hash bucket, proceed to step S915; if there is a second empty slot in the second hash bucket, proceed to step S916. It can be understood that the solution of the present application is to first try to insert the physical address into the first hash bucket, and then try to insert it into the second hash bucket when the first hash bucket fails.

[0173] Step S915: storing the physical address corresponding to the logical address into the second empty slot;

[0174] Specifically, if there is a second empty slot in the second hash bucket, the physical address corresponding to the logical address is stored in the second empty slot.

[0175] Step S916: linearly probe the first hash bucket and the second hash bucket to obtain a third empty slot;

[0176] For details, please refer to FIG11 , which is a detailed flowchart of step S916 in FIG9 ;

[0177] As shown in FIG11 , step S916 : performing linear detection on the first hash bucket and the second hash bucket to obtain a third empty slot includes:

[0178] Step S9161: Obtaining the linear detection distance;

[0179] Specifically, a linear detection distance is obtained, where the unit distance of the linear detection distance is the distance of one bucket, and can be set according to actual conditions. For example, the linear detection distance is set to 10.

[0180] Step S9162: Acquire a third empty slot according to the linear detection distance, the target bucket address of the first hash bucket, and the target bucket address of the second hash bucket;

[0181] Specifically, if there are no empty slots in the first hash bucket and the second hash bucket, a linear detection is performed around the two hash buckets for a certain distance to obtain a third empty slot, where the bucket address corresponding to the third empty slot is (the target bucket address of the first hash bucket, the target bucket address of the first hash bucket + the linear detection distance) or (the target bucket address of the second hash bucket, the target bucket address of the second hash bucket + the linear detection distance). Assuming that the logical address is 503, the number of hash buckets is 100, the target bucket address of the first hash bucket is 3, and the target bucket address of the second hash bucket is 53, if there are no empty slots in the first hash bucket and the second hash bucket, an attempt can be made to insert into bucket 4 behind the first hash bucket. It should be noted that the buckets attempted to be inserted backward do not exceed the detection distance, such as 10 buckets. That is, A can insert into buckets with target bucket addresses of 4, 5, ..., 13. If the insertion fails, it can insert into buckets 54, 55, ..., 63 behind the second hash bucket.

[0182] Step S917: Determine whether there is a third empty slot in the hash bucket;

[0183] Specifically, it is determined whether there is a third empty slot in the hash bucket. If there is a third empty slot in the hash bucket, the process proceeds to step S918; if there is no third empty slot in the hash bucket, the process proceeds to step S919.

[0184] Step S918: storing the physical address corresponding to the logical address into the third empty slot;

[0185] Specifically, if there is a third empty slot in the hash bucket, the physical address corresponding to the logical address is stored in the third empty slot.

[0186] Step S919: Determine whether there is a fourth empty slot in the storage bucket;

[0187] Specifically, if there is no third empty slot in the hash bucket, it is determined whether there is a fourth empty slot in the storage bucket. If there is a fourth empty slot in the storage bucket, step S920 is performed; if there is no fourth empty slot in the storage bucket, step S921 is performed.

[0188] Step S920: storing the physical address corresponding to the logical address into the fourth empty slot;

[0189] Specifically, if there is a fourth empty slot in the storage bucket, the physical address corresponding to the logical address is stored in the fourth empty slot in the storage bucket. It can be understood that the design of the storage bucket effectively improves the tolerance of the range bucket node to hash conflicts and improves memory usage efficiency.

[0190] Step S921: Split and expand the range bucket node to obtain a split range bucket node, and store the physical address corresponding to the logical address in the split range bucket node;

[0191] Specifically, if there are no empty slots in the storage bucket, the range bucket node is split and expanded to obtain a split range bucket node, so that the table entry to be inserted can be inserted into the split range bucket node according to the range after the split. The split bucket is used to handle the hash conflict generated when the range bucket node is split. The number of such buckets will not exceed three percent of the number of buckets in the range bucket node.

[0192] In the embodiment itself, the range bucket hash structure can be used to store index entries that cannot be expressed by a compact array, supporting dynamic expansion, high memory usage, and high indexing performance.

[0193] Please refer to FIG12 again, which is a flowchart of obtaining a range bucket node corresponding to a logical address according to an embodiment of the present application;

[0194] As shown in Figure 12, the process of obtaining the range bucket node corresponding to the logical address includes:

[0195] Step S1201: Obtain the range bucket node corresponding to the logical address;

[0196] Specifically, please refer to FIG13 , which is a detailed flowchart of step S1201 in FIG12 ;

[0197] As shown in FIG13 , step S1201: obtaining a range bucket node corresponding to a logical address, including:

[0198] Step S1211: Obtain a red-black tree structure according to the global range table;

[0199] Specifically, the minimum value of all range bucket nodes is stored as a key in a global range table. To enable high-performance queries on the global range table, its underlying structure uses a red-black tree. Based on the global range table, a red-black tree structure is retrieved. A red-black tree is a binary search tree in which each node has a color attribute, either red or black. Each red-black tree is a binary sorted tree, so searches on a red-black tree can be performed using the same search algorithms used for ordinary binary sorted trees.

[0200] Step S1212: query the red-black tree structure according to the logical address to obtain the range bucket node corresponding to the logical address;

[0201] Specifically, during a query, the red-black tree structure is queried based on the logical address to obtain the key value of the corresponding range bucket node. This is then used to find the corresponding range bucket node in the LRU cache and perform the corresponding query operation. This design can effectively improve the performance and efficiency of the global range table.

[0202] Please refer to FIG14 again, which is a schematic diagram of the structure of a red-black tree provided in an embodiment of the present application;

[0203] As shown in Figure 14, a red-black tree is a binary search tree in which each node has a color attribute, where the color attribute is red or black. In an embodiment of the present application, the red-black tree is used to store the key value of the range bucket node, that is, the correspondence between the logical address and the physical address. The red-black tree has the following five properties: Property 1. The node is red or black; Property 2. The root node is black; Property 3. All leaves are black (the leaves are NIL nodes); Property 4. Both child nodes of each red node are black. (There cannot be two consecutive red nodes on all paths from each leaf to the root); Property 5. All paths from any node to each of its leaves contain the same number of black nodes.

[0204] Please refer to FIG15 again, which is a schematic diagram of the structure of a global range table and cache space provided by an embodiment of the present application;

[0205] As shown in Figure 15, the range bucket hash table consists of a global range table (GRT) and an LRU cache with range bucket nodes as the granularity. The global range table can quickly locate the range bucket node corresponding to the operation of the logical address based on the logical address.

[0206] Please refer to FIG16 again, which is a schematic diagram of the structure of a range bucket node provided in an embodiment of the present application;

[0207] As shown in Figure 16, the range bucket node is based on array hashing and finite linear probing technology. There are a fixed number of buckets in the range bucket node, and each bucket has 4 slots. The buckets in the range bucket node can be divided into three categories according to their functions: hash buckets, storage buckets, and split buckets.

[0208] Please refer to FIG17 again, which is a schematic diagram of a range bucket node splitting and merging provided by an embodiment of the present application;

[0209] As shown in Figure 17, the range-bucket hash table achieves efficient memory usage primarily due to the following four factors: ① Key range restriction and sparsity: Because each range-bucket node limits the range of inserted key values ​​and the inserted key values ​​are sparse, the probability of hash collisions is reduced to a certain extent. ② Storage bucket design: The storage bucket design effectively improves the range-bucket node's tolerance for hash collisions. ③ Impact of split-and-expand granularity: Unlike expanding the entire hash structure, the range-bucket hash table splits and expands at the granularity of the range-bucket node. The low load factor after the split is localized, reducing the impact on the overall load factor of the structure. ④ Merge strategy: After long-term use, the range-bucket hash table may have buckets with low load factors. This application uses a merge strategy to merge range-bucket nodes with low load factors to improve overall memory usage efficiency. A low load factor refers to the situation where a merge is attempted only if the combined load factors of two buckets do not exceed 90% of the total bucket capacity. Experiments have shown that the load factor of range-bucket nodes can reach over 95% before split-and-expand, and the overall load factor is between 70% and 80% under steady-state conditions.

[0210] The maximum value B and minimum value A of the range bucket to be split are both recorded in the bucket structure. Based on the maximum value B and the minimum value A, the intermediate value (B+A) / 2 of the split is calculated. First, all key-value pairs (logical address, physical address) in the bucket to be split are read out and sorted. Then, all values ​​with logical addresses greater than (B+A) / 2 are inserted into the range bucket [(B+A) / 2, B), and values ​​less than (B+A) / 2 are inserted into the range bucket [A, (B+A) / 2).

[0211] Step S304: query the range bucket hash structure to determine whether the range bucket node corresponding to the logical address exists in the least recently used cache;

[0212] For details, please refer to FIG18 , which is a detailed flowchart of step S304 in FIG3 ;

[0213] As shown in FIG18 , step S304 : querying the range bucket hash structure to determine whether the range bucket node corresponding to the logical address exists in the least recently used cache includes:

[0214] Step S341: Obtain the storage status of the range bucket;

[0215] Specifically, the storage state of the range bucket is obtained, wherein the storage state includes a first state and a second state, the first state indicates that the range bucket node is stored in the flash memory space, and the second state indicates that the range bucket node is stored in the cache space.

[0216] Step S342: determining whether the storage state of the range bucket is the first state;

[0217] Specifically, it is determined whether the storage state of the range bucket is the first state. If the storage state of the range bucket is the first state, the process proceeds to step S343; if the storage state of the range bucket is the second state, the process proceeds to step S344.

[0218] Step S343: determining that the range bucket node is stored in the flash memory space, and reading the range bucket node into the least recently used cache;

[0219] Specifically, when the storage state of the range bucket is the first state, it is determined that the range bucket node is stored in the flash memory space, and the range bucket node is read into the least recently used cache. It is determined that the range bucket node is stored in the flash memory space, and the range bucket node is read into the least recently used cache.

[0220] Step S344: determining that the range bucket node is stored in the least recently used cache;

[0221] Specifically, when the storage state of the range bucket is the first state, it is determined that the range bucket node is stored in the least recently used cache.

[0222] Step S305: query the logical address in the range bucket node to obtain the physical address corresponding to the logical address;

[0223] For details, please refer to FIG19 , which is a detailed flowchart of step S305 in FIG3 ;

[0224] As shown in FIG19 , step S305 : querying the logical address in the range bucket node to obtain the physical address corresponding to the logical address, including:

[0225] Step S351: Calculate the target bucket addresses of the first hash bucket and the second hash bucket according to the logical address;

[0226] Specifically, according to the logical address, the formula for calculating the target bucket address A of the first hash bucket is A=(key)%LEN, and the formula for calculating the target bucket address B of the first hash bucket is B=(key+LEN / 2%LEN, where key is the logical address, LEN is the total number of hash buckets, A is the target bucket address of the first hash bucket, and B is the target bucket address of the second hash bucket.

[0227] Step S352: According to the target bucket addresses of the first hash bucket and the second hash bucket, query whether there is a physical address corresponding to the logical address in the first hash bucket or the second hash bucket;

[0228] Specifically, according to the target bucket addresses of the first hash bucket and the second hash bucket, query whether there is a physical address corresponding to the logical address in the first hash bucket and the second hash bucket. If there is a physical address corresponding to the logical address in the first hash bucket or the second hash bucket, go to step S353; if there is no physical address corresponding to the logical address in either the first hash bucket or the second hash bucket, go to step S354.

[0229] Step S353: Obtain the physical address corresponding to the logical address from the first hash bucket or the second hash bucket;

[0230] Specifically, if the physical address corresponding to the logical address exists in the first hash bucket or the second hash bucket, the physical address corresponding to the logical address is obtained from the first hash bucket or the second hash bucket.

[0231] Step S354: query the storage bucket and the split range bucket node in sequence until the physical address corresponding to the logical address is found;

[0232] Specifically, if the physical address corresponding to the logical address does not exist in the first hash bucket or the second hash bucket, the storage bucket and the split range bucket node are queried in sequence until the physical address corresponding to the logical address is queried. Based on this, it can be understood that the query operation and the deletion operation are consistent with the order when constructing the range hash bucket structure. For example, when inserting, the order of attempted insertion is buckets A, B, C, and D. Then when querying and deleting, buckets A, B, C, and D are also traversed in sequence to find the physical address corresponding to the logical address.

[0233] Step S306: searching for a range bucket node corresponding to the logical address in the flash memory space, and reading the range bucket node into the least recently used cache;

[0234] Specifically, if the corresponding range bucket node is stored in the flash memory, it needs to be read into the LRU cache first, and then the physical address corresponding to the logical address is searched in the range bucket node and returned.

[0235] Step S307: Obtain the physical address corresponding to the logical address in the range bucket node;

[0236] Specifically, the corresponding range bucket node is searched in the LRU cache, and the physical address corresponding to the logical address is obtained in the range bucket node.

[0237] In summary, the technical solution of this application offers the following three beneficial effects: 1. It maintains high performance even for random reads, which have poor locality. 2. This solution is a lightweight design that only modifies the mapping table in the SSD and does not involve modifications to other modules. 3. It can further reduce the memory overhead of the mapping table in highly sequential scenarios.

[0238] In an embodiment of the present application, a physical address query method is provided, which is applied to a flash memory device. The flash memory device includes a cache space, and the cache space stores a compact array and a range bucket hash structure. The physical address query method includes: obtaining a logical address; determining whether the compact array can map the logical address to the corresponding physical address by querying the compact array; if the compact array cannot map the logical address to the corresponding physical address, querying the range bucket hash structure to determine whether the range bucket node corresponding to the logical address exists in the least recently used cache; if the range bucket node corresponding to the logical address exists in the least recently used cache, querying the logical address in the range bucket node to obtain the physical address corresponding to the logical address. The present application can maintain high indexing performance and improve the query efficiency of the physical address by querying the physical address corresponding to the logical address in the compact array and the range bucket hash structure while saving DRAM resources.

[0239] Please refer to FIG. 20 , which is a schematic structural diagram of a flash memory device provided in an embodiment of the present application;

[0240] As shown in Figure 20, the flash memory device 100 includes one or more processors 122 and a memory 123. Figure 20 takes one processor 122 as an example.

[0241] The processor 122 and the memory 123 may be connected via a bus or other means. FIG20 takes the bus connection as an example.

[0242] The processor 122 is used to provide computing and control capabilities to control the flash memory device 100 to perform corresponding tasks, for example, to control the flash memory device 100 to execute the physical address query method in any of the above-mentioned method embodiments, which is applied to a flash memory device, which includes a cache space, and the cache space stores a compact array and a range bucket hash structure. The physical address query method includes: obtaining a logical address; determining whether the compact array can map the logical address to the corresponding physical address by querying the compact array; if the compact array cannot map the logical address to the corresponding physical address, querying the range bucket hash structure to determine whether the range bucket node corresponding to the logical address exists in the least recently used cache; if the range bucket node corresponding to the logical address exists in the least recently used cache, querying the logical address in the range bucket node to obtain the physical address corresponding to the logical address.

[0243] By querying the physical address corresponding to the logical address in a compact array and range bucket hash structure, the application can improve the query efficiency of the physical address while saving DRAM resources and maintaining high indexing performance.

[0244] The processor 122 may be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), a hardware chip, or any combination thereof; it may also be a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a programmable logic device (PLD), or any combination thereof. The PLD may be a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL), or any combination thereof.

[0245] The memory 123 is a non-transitory computer-readable storage medium that can be used to store non-transitory software programs, non-transitory computer executable programs and modules, such as the program instructions / modules corresponding to the physical address query method in the embodiment of the present application. The processor 122 can implement the physical address query method in any of the following method embodiments by running the non-transitory software programs, instructions and modules stored in the memory 123. Specifically, the memory 123 may include a volatile memory (VM), such as a random access memory (RAM); the memory 123 may also include a non-volatile memory (NVM), such as a read-only memory (ROM), a flash memory, a hard disk drive (HDD) or a solid-state drive (SSD) or other non-transitory solid-state storage device; the memory 123 may also include a combination of the above types of memories.

[0246] The memory 123 may include high-speed random access memory and non-volatile memory, such as at least one disk storage device, flash memory device, or other non-volatile solid-state memory device. In some embodiments, the memory 123 may optionally include a memory remotely located relative to the processor 122, and such remote memory may be connected to the processor 122 via a network. Examples of such networks include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0247] One or more modules are stored in the memory 123, and when executed by one or more processors 122, perform the physical address query method in any of the above method embodiments, for example, perform the steps shown in FIG. 3 described above.

[0248] In an embodiment of the present application, the flash memory device 100 may also have components such as a wired or wireless network interface, a keyboard, and an input / output interface for input and output. The flash memory device 100 may also include other components for realizing device functions, which will not be described in detail here.

[0249] The present application also provides a non-volatile computer-readable storage medium, such as a memory including program code, wherein the program code can be executed by a processor to implement the physical address query method in the above embodiment. For example, the non-volatile computer-readable storage medium can be a read-only memory (ROM), a random access memory (RAM), a compact disc read-only memory (CDROM), a magnetic tape, a floppy disk, an optical data storage device, etc.

[0250] The present application also provides a computer program product comprising one or more program codes stored in a non-volatile computer-readable storage medium. A processor of a flash memory device reads the program codes from the non-volatile computer-readable storage medium and executes the program codes to perform the steps of the physical address query method provided in the above-described embodiment.

[0251] Those skilled in the art will understand that all or part of the steps for implementing the above embodiments may be accomplished by hardware, or by hardware related to program code, and the program may be stored in a non-volatile computer-readable storage medium, and the above-mentioned storage medium may be a read-only memory, a disk, or an optical disk, etc.

[0252] Through the description of the above embodiments, it can be clearly understood by those skilled in the art that each embodiment can be implemented by means of software plus a general hardware platform, or of course by hardware. It can be understood by those skilled in the art that all or part of the processes in the above embodiment methods can be implemented by instructing the relevant hardware through a computer program, and the program can be stored in a non-volatile computer-readable storage medium. When the program is executed, it can include the processes of the embodiments of the above methods. Among them, the storage medium can be a magnetic disk, an optical disk, a read-only memory (ROM) or a random access memory (RAM), etc.

[0253] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Based on the idea of ​​the present application, the technical features in the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other variations in different aspects of the present application as mentioned above. For the sake of simplicity, they are not provided in detail. Although the present application has been described in detail with reference to the aforementioned embodiments, ordinary technicians in this field should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A method for querying a physical address, characterized in that: The method is applied to a flash memory device, the flash memory device includes a cache space, the cache space stores a compact array and a range bucket hash structure, and the method includes: Get the logical address; Querying the compact array to determine whether the compact array can map the logical address to a corresponding physical address; If the compact array cannot map the logical address to the corresponding physical address, query the range bucket hash structure to determine whether the range bucket node corresponding to the logical address exists in the least recently used cache; If the range bucket node corresponding to the logical address exists in the least recently used cache, the logical address is queried in the range bucket node to obtain the physical address corresponding to the logical address.

2. The method according to claim 1, characterized in that: The method further comprises: Constructing the compact array, wherein the compact array is composed of compact array nodes, and a compact array node includes at least one first address, a first bitmap and a second bitmap, specifically including: Obtain a preset number of consecutive logical addresses; According to the logical address, obtaining a physical address corresponding to the logical address; Confirming the corresponding compact array node according to the logical address, and storing the first physical address to the first address of the compact array node; According to the physical address corresponding to the logical address, obtain the address state corresponding to every two adjacent physical addresses, and store the address state in the first bitmap, wherein the address state includes a continuous state and a discontinuous state, and each address state occupies one bit of storage space; Acquire the expression state corresponding to the physical address, and store the expression state corresponding to the physical address in the second bitmap to acquire the second bitmap, wherein the expression state corresponding to the physical address includes an initial state and an inexpressible state, and each state corresponding to the physical address occupies one bit of storage space; The compact array node is constructed according to the first address, the first bitmap and the second bitmap.

3. The method according to claim 2, characterized in that The querying the compact array to determine whether the compact array can map the logical address to the corresponding physical address includes: According to the first bitmap, obtaining a first physical address, wherein the first physical address is continuous with a physical address corresponding to the logical address; Acquire an address distance between the first physical address and a physical address corresponding to the logical address and an expression state corresponding to the first physical address; According to the address distance between the first physical address and the physical address corresponding to the logical address and the expression state corresponding to the first physical address, it is determined whether the compact array can map the logical address to the corresponding physical address.

4. The method according to claim 1, characterized in that: The method further comprises: Constructing a range bucket hash structure, wherein the range bucket hash structure includes a global range table and a range bucket node, the range bucket node includes a hash bucket, a storage bucket and a split bucket, the hash bucket includes a first hash bucket and a second hash bucket, specifically including: Calculating target bucket addresses of the first hash bucket and the second hash bucket according to the logical address includes: A=(key)%LEN, B=(key+LEN / 2)%LEN, Among them, key is the logical address, LEN is the total number of hash buckets, A is the target bucket address of the first hash bucket, and B is the target bucket address of the second hash bucket.

5. The method according to claim 4, characterized in that The method further comprises: Determining whether there is a first empty slot in the first hash bucket according to the target bucket address of the first hash bucket; If there is a first empty slot in the first hash bucket, storing the physical address corresponding to the logical address in the first empty slot; If the first hash bucket does not have a first empty slot, determining whether the second hash bucket has a second empty slot according to the target bucket address of the first hash bucket; If the second hash bucket has the second empty slot, storing the physical address corresponding to the logical address in the second empty slot; If the second empty slot does not exist in the second hash bucket, linearly detect the first hash bucket and the second hash bucket to obtain a third empty slot; If the hash bucket does not have the third empty slot, determining whether the storage bucket has a fourth empty slot; If the storage bucket does not have the fourth empty slot, the range bucket node is split and expanded to obtain a split range bucket node, and the physical address corresponding to the logical address is stored in the split range bucket node.

6. The method according to claim 5, characterized in that The linear detection of the first hash bucket and the second hash bucket to obtain a third empty slot includes: Get the linear detection distance; The third empty slot is obtained according to the linear detection distance, the target bucket address of the first hash bucket and the target bucket address of the second hash bucket, wherein the bucket address corresponding to the third empty slot is (the target bucket address of the first hash bucket, the target bucket address of the first hash bucket + the linear detection distance) or (the target bucket address of the second hash bucket, the target bucket address of the second hash bucket + the linear detection distance).

7. The method according to claim 4, characterized in that The global range table includes a storage state of a range bucket node, the storage state of the range bucket node includes a first state and a second state, and the method further includes: If the storage state of the range bucket is the first state, it is determined that the range bucket node is stored in the flash The range bucket node is stored in the storage space and read into the least recently used cache.

8. The method according to claim 4, characterized in that The method also includes: Obtaining the range bucket node corresponding to the logical address includes: According to the global range table, a red-black tree structure is obtained; According to the logical address, the red-black tree structure is queried to obtain a range bucket node corresponding to the logical address.

9. The method according to claim 4, characterized in that The querying the logical address in the range bucket node to obtain a physical address corresponding to the logical address includes: According to the target bucket addresses of the first hash bucket and the second hash bucket, query whether there is a physical address corresponding to the logical address in the first hash bucket and the second hash bucket; If the physical address corresponding to the logical address does not exist in the first hash bucket and the second hash bucket, the storage bucket and the split range bucket node are queried in sequence until the physical address corresponding to the logical address is queried.

10. A flash memory device controller, characterized in that: include: at least one processor; as well as, a memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to execute the physical address query method according to any one of claims 1 to 9.

11. A flash memory device, characterized in that: include: The flash memory device controller as claimed in claim 10; At least one flash memory medium is communicatively coupled to the flash memory device controller.

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