Computing device

Abstract

A computing device, comprising a mainboard, a first memory expansion board, a first memory module, a second memory expansion board, and a second memory module. A first CPU is provided on the mainboard, and the first CPU comprises a first interface and a second interface, wherein the first interface and the second interface are memory interfaces, and belong to a same interface group of the first CPU. A first memory expansion controller is provided on the first memory expansion board, and a second memory expansion controller is provided on the second memory expansion board. The first interface is electrically connected to the first memory module via the first memory expansion controller, and the second interface is electrically connected to the second memory module via the second memory expansion controller. In this way, since the first interface and the second interface of the first CPU belong to the same interface group, when the first CPU accesses the first memory module and the second memory module, cross-group access is not needed, so that an access path can be shortened, and data transmission speed can be increased.

Description

A computing device

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on December 28, 2023, with application number 202311841697.0 and application name “A Computing Device”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of communication technology, and in particular to a computing device. Background Art

[0003] A computing device (such as a server) may include a motherboard, which may be equipped with one or more central processing units (CPUs). Each CPU may be electrically connected to a memory module via a memory expansion controller, allowing the CPU to exchange data with the memory module. For example, the CPU can write data to the memory module and read data from the memory module.

[0004] As data storage grows, the speed at which CPUs and memory modules exchange data becomes increasingly important. However, current motherboard CPUs and memory modules experience slow data transfer speeds.

[0005] Therefore, how to increase the data transmission speed between the CPU and the memory module has become a technical problem that needs to be solved urgently.

[0006] Summary of the Invention

[0007] An embodiment of the present application provides a computing device that can increase the data transmission speed between a CPU and a memory module.

[0008] In the first aspect, the present application provides a computing device, which includes a mainboard, a first memory expansion board, a first memory module, a second memory expansion board, and a second memory module; a first CPU is provided on the mainboard, the first CPU includes a first interface and a second interface, the first interface and the second interface are memory interfaces, and belong to the same interface group of the first CPU; a first memory expansion controller is provided on the first memory expansion board, and a second memory expansion controller is provided on the second memory expansion board; the first memory expansion controller is electrically connected to the first interface and the first memory module, respectively, and the second memory expansion controller is electrically connected to the second interface and the second memory module, respectively. In this way, since the first interface and the second interface of the first CPU belong to the same interface group, the first CPU does not need to cross-group access when accessing the first memory module and the second memory module, which can shorten the access path and thus improve the data transmission speed.

[0009] In one possible implementation, the computing device further includes a third memory module and a fourth memory module; the first memory expansion board is further provided with a third memory expansion controller, and the second memory expansion board is further provided with a fourth memory expansion controller; the first interface is electrically connected to the third memory module via the third memory expansion controller, and the second interface is electrically connected to the fourth memory module via the fourth memory expansion controller. Thus, because the first interface and the second interface of the first CPU belong to the same interface group, the first CPU does not need to cross groups when accessing the first, second, third, and fourth memory modules, thereby shortening the access path and improving data transmission speed.

[0010] In one possible implementation, the computing device further includes a third memory expansion board, a fourth memory expansion board, a fifth memory module, and a sixth memory module; the mainboard further includes a second CPU, the second CPU including a third interface and a fourth interface, the third interface and the fourth interface being memory interfaces and belonging to the same interface group of the second CPU; the second CPU is electrically connected to the first CPU via an xGMI bus; the fifth memory expansion controller is electrically connected to the third interface and the fifth memory module, respectively, and the sixth memory expansion controller is electrically connected to the fourth interface and the sixth memory module, respectively. Thus, since the third interface and the fourth interface of the second CPU belong to the same interface group, when the first CPU or the second CPU accesses the fifth memory module and the sixth memory module, there is no need for cross-group access, which can shorten the access path and thus improve data transmission speed. Furthermore, when the second CPU accesses the memory modules connected to the first interface and the second interface of the first CPU, data transmission speed can also be improved.

[0011] In one possible implementation, the computing device further includes a seventh memory module and an eighth memory module; a seventh memory expansion controller is further provided on the third memory expansion board, and an eighth memory expansion controller is further provided on the fourth memory expansion board; the seventh memory expansion controller is electrically connected to the third interface and the seventh memory module, respectively, and the eighth memory expansion controller is electrically connected to the fourth interface and the eighth memory module, respectively. Therefore, when the first CPU or the second CPU accesses the fifth memory module, the sixth memory module, the seventh memory module, and the eighth memory module, there is no need for cross-group access, which can shorten the access path and thereby increase the data transmission speed.

[0012] In a possible implementation, the first interface and the second interface are CXL interfaces. Thus, the memory interface is specifically a CXL interface.

[0013] In one possible implementation, the first CPU accesses the first memory module and the second memory module in a memory interleaving manner. Thus, the first CPU accesses the first memory module and the second memory module in a memory interleaving manner to write (or read) data into the first memory module and the second memory module.

[0014] In one possible implementation, a first power module is provided on the mainboard; an output end of the first power module is electrically connected to the first memory expansion board and the second memory expansion board. In this way, the first power module on the mainboard can supply power to both the first memory expansion board and the second memory expansion board.

[0015] In one possible implementation, the first memory module includes at least one dual inline memory module (DIMM), and the second memory module includes at least one dual inline memory module (DIMM). The first memory module is plugged into the first memory expansion board, and the second memory module is plugged into the second memory expansion board. Thus, the first memory module can specifically be in the form of at least one dual inline memory module (DIMM).

[0016] In one possible implementation, a first connector is provided on the first memory expansion board, a second connector is provided on the mainboard, and a third connector is provided on the second memory expansion board. The first memory expansion board is electrically connected to the first interface via the first and second connectors, and the second memory expansion board is electrically connected to the second interface via the third and second connectors. Thus, the first interface is electrically connected to the memory expansion board via the first and second connectors, allowing the first CPU to exchange data with the DIMMs on the memory expansion board via the first interface.

[0017] In one possible implementation, the first memory module is a DDR4 memory or a DDR5 memory, and the second memory module is a DDR4 memory or a DDR5 memory. In this way, the first memory module can use either DDR4 memory or DDR5 memory. The same is true for the second memory module. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] FIG1 is a schematic diagram of the structure of a computing device provided in an embodiment of the present application;

[0019] FIG2 is a schematic diagram of the structure of a CPU in an embodiment of the present application;

[0020] FIG3 is a schematic structural diagram of a memory expansion board provided in an embodiment of the present application;

[0021] FIG4 is a schematic diagram of the structure of another computing device provided in an embodiment of the present application;

[0022] FIG5 is a schematic diagram of the structure of another computing device provided in an embodiment of the present application;

[0023] FIG6 is a schematic diagram of the structure of another computing device provided in an embodiment of the present application;

[0024] FIG7 is a schematic diagram of the structure of another computing device provided in an embodiment of the present application;

[0025] FIG8 is a schematic structural diagram of another computing device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0026] The term "and / or" as used herein describes an association between related objects, indicating that three possible relationships exist. For example, "A and / or B" can represent: A exists alone, A and B exist simultaneously, or B exists alone. The symbol " / " as used herein indicates that the related objects are in an "or" relationship, for example, A / B means either A or B.

[0027] The terms "first" and "second" in this specification and claims are used to distinguish different objects rather than to describe a specific order of objects. For example, "first response message" and "second response message" are used to distinguish different response messages rather than to describe a specific order of response messages.

[0028] In the embodiments of this application, words such as "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary" or "for example" in the embodiments of this application should not be interpreted as being preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0029] In the description of the embodiments of the present application, unless otherwise specified, "multiple" means two or more, for example, multiple processing units means two or more processing units, etc.; multiple elements means two or more elements, etc.

[0030] Compute Express Link (CXL) is a high-speed serial protocol that enables fast, reliable data transmission between different components within a computer system. It aims to address bottlenecks in high-performance computing, including memory capacity, memory bandwidth, and input / output latency. CXL also enables memory expansion and sharing, and can communicate with external devices such as computing accelerators (GPUs and FPGAs), providing faster and more flexible data transmission.

[0031] The CXL protocol is based on the PCIE 5.0 protocol. The CXL protocol is a new protocol optimized for cache and memory, built on the physical layer of the fifth-generation Peripheral Component Interconnect Express (PCIE 5.0). The CXL protocol shares the same electrical characteristics as the PCIE 5.0 protocol. The CXL feature requires a flexible interface (e.g., the CXL interface) that can determine whether to use the PCIE or CXL protocol based on link layer negotiation.

[0032] The computing device may include a motherboard, a CPU, and a plurality of memory interfaces. The computing device may also include a memory expansion board, a memory expansion controller (MXC) and a memory expansion board.

[0033] In related technologies, a memory expansion controller can be connected to a CPU's memory interface (e.g., a CXL interface). At the same time, the memory expansion controller can also be connected to a memory module. This allows the CPU to exchange data with the memory module through the memory expansion controller. Specifically, the CPU can read data from the memory module through the memory expansion controller, and can also write data to the memory module through the memory expansion controller. However, when the CPU and the memory module exchange data, a technical problem often arises: a low data transmission rate between the CPU and the memory module.

[0034] To facilitate understanding of the technical solutions in the embodiments of the present application, the terms involved in the embodiments of the present application are explained below.

[0035] Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM) is a type of SDRAM with a double data rate, allowing it to transfer data at twice the system clock speed. This increased speed improves performance compared to traditional SDRAM (Synchronous Dynamic Random Access Memory). DDR SDRAM can transfer data on both the rising and falling edges of the system clock. For simplicity, DDR SDRAM will be referred to as DDR below. DDR memory is commonly used in computers, servers, routers, and other devices. It is a high-performance, low-power memory technology that improves system performance and bandwidth, meeting the storage needs of various devices.

[0036] DDR has now reached its fifth generation, DDR5. Compared to DDR4, DDR5 offers stronger standards and lower power consumption. All DDR5 chips also feature Error Checking and Correcting (ECC), which detects and corrects errors before data is sent to the CPU. The memory chips in the memory modules of the present application use DDR5 as an example, but are not limited to DDR5 and may also be other memory chips.

[0037] Different generations of DDR memory have different interfaces. The first generation of DDR includes the DDR interface, the second generation DDR2 includes the DDR2 interface, the third generation DDR3 includes the DDR3 interface, the fourth generation DDR4 includes the DDR4 interface, and the fifth generation DDR5 includes the DDR5 interface. These interfaces are used to transmit high-speed signals, and each interface has different specifications and performance. The main features of the DDR interface are high speed transmission and low power consumption. It can transmit more data at the same frequency, thereby improving system performance.

[0038] The main advantages of DDR memory interface include the following:

[0039] 1. High-speed transmission: DDR memory can transmit data twice in each clock cycle, so it is faster than SDR memory.

[0040] 2. Low power consumption: DDR memory uses low voltage and therefore consumes less power.

[0041] 3. Higher bandwidth: DDR memory can transmit more data at the same frequency, thereby increasing the bandwidth of the system.

[0042] 4. Larger capacity: DDR memory can support larger capacity to meet higher storage requirements.

[0043] Memory interleaving is a technique for improving memory access performance by interleaving accesses between different memory modules. The memory controller in the CPU distributes data across different memory modules in an alternating pattern, allowing the memory controller to access each memory module to retrieve smaller bits of data, rather than accessing a single memory module to retrieve an entire block of data. This provides the memory controller with more bandwidth to access the same amount of data across channels (memory channels), rather than traversing a single channel to store all data in a single memory module.

[0044] Next, the computing device provided in the embodiments of the present application is introduced in detail.

[0045] For example, an embodiment of the present application provides a computing device 1, as shown in Figure 1. The computing device 1 is a device, equipment, or platform with data processing capabilities. In one example, the computing device 1 can be a server.

[0046] Computing device 1 may include a motherboard 11, on which a CPU 111 is disposed. CPU 111 includes multiple memory interfaces. Specifically, the memory interfaces may be PCIE interfaces or CXL interfaces, that is, interfaces that communicate with memory modules via the PCIE protocol or CXL protocol. For example, the four CXL interfaces are interface P0, interface P1, interface P2, and interface P3. Interfaces P0 and P1 belong to the same interface group, and interfaces P2 and P3 belong to the same interface group. The same interface group is referred to as the same corner.

[0047] The corner here refers to the corner of the chip. As shown in FIG2 , the interface P0 and the interface P1 in the embodiment of the present application belong to corner1, and the interface P2 and the interface P3 belong to corner2.

[0048] The computing device 1 further includes a memory expansion board A and a memory expansion board B. The memory expansion board A is provided with a memory expansion controller MXC0, and the memory expansion board B is provided with a memory expansion controller MXC1.

[0049] The interface of the memory expansion controller MXC0 supports connecting to DDR5 or DDR4, allowing it to communicate with DDR4 or DDR5 using the CXL or PCIE protocol, and MXC0 and CPU111 can also communicate using the CXL protocol or PCIE protocol. For example, when the CXL protocol is used, the interfaces that connect MXCO to CPU111 and memory module a respectively can be referred to as the first CXL interface and the second CXL interface; the embodiment of the present application takes the communication between the memory expansion controller MXCO and the CPU and memory module a using the CXL protocol as an example. The protocol of the memory expansion controller MXC1 is the same as that of MXCO and will not be repeated here. The first CXL interface of the memory expansion controller MXC0 can be connected to the interface P0 of the CPU, and the second CXL interface of the memory expansion controller MXC0 can be electrically connected to the memory module a. Among them, the memory module a is a DDR5 memory module or a DDR4 memory module.

[0050] In this way, CPU 111 can exchange data with memory module a through memory expansion controller MXC0. Specifically, CPU 111 can read data from memory module a through interface P0 and memory expansion controller MXC0, and can also write data to memory module a through interface P0 and memory expansion controller MXC0.

[0051] Similarly, the first CXL interface of the memory expansion controller MXC1 can be connected to the CPU's interface P1, and the second CXL interface of the memory expansion controller MXC1 can be electrically connected to the memory module b. In this way, the CPU 111 can read data from the memory module b and write data to the memory module b through the interface P1 and the memory expansion controller MXC1.

[0052] When using memory interleaving technology, consecutive memory addresses can be mapped to different CXL devices at uniform intervals, specifically memory module a and memory module b. If memory module a is connected to port P0 of CPU 111 and memory module b is connected to port P2 of CPU 111, because ports P0 and P2 do not belong to the same interface group, CPU 111 will experience a technical problem when accessing memory modules a and b: the access path is too long, resulting in slow data transmission.

[0053] In contrast, the interface P0 and interface P1 of the CPU 111 in the embodiment of the present application belong to the same interface group (the same group) of the CPU 111 interface. The interface group is defined in the product manual of the CPU of Advanced Micro Devices (AMD). Interfaces P0 and P1 belong to the same interface group, and interfaces P2 and P3 belong to another interface group. The functions of the P0-P3 interfaces are the same, and they are all used to connect to a memory stick or a memory expansion board to read or write data from the memory stick, wherein the memory stick can be DDR4, DDR5, and the memory expansion board can be a CXL expansion board. Therefore, when the CPU 111 accesses memory module a and memory module b, there is no need for cross-group access, which can shorten the access path and thus increase the data transmission speed.

[0054] It should be noted that the memory bars on the CXL expansion boards respectively connected to the same interface group of the CPU may or may not apply the memory interleaving technology, which is not specifically limited here.

[0055] Furthermore, when CPU 111 accesses memory module a, it is actually the core of CPU 111 that accesses memory module a through the CXL controller corresponding to interface P0. Similarly, when CPU 111 accesses memory module b, it is actually the core of CPU 111 that accesses memory module b through the CXL controller corresponding to interface P1.

[0056] It should be noted that memory interleaving is a technology used by AMD CPUs to increase the memory bandwidth available to applications. Without memory interleaving, consecutive memory blocks are read from the same physical memory, such as memory sticks in the same memory channel. The CPU obtains the entire data block by accessing consecutive memory blocks on one memory stick. With memory interleaving, consecutive memory blocks can be located on memory sticks in different memory channels. The CPU can concurrently access consecutive memory blocks on memory sticks in different channels to obtain the entire data block, thus improving the memory bandwidth available to applications and reducing memory latency.

[0057] For example, the aforementioned memory module a can be a DIMM (dual-inline memory module). The number of DIMMs is determined by the number of second CXL interfaces on the memory expansion controller and the size of the memory expansion board. Each second CXL interface can connect to one or two DIMMs. The structure of memory module b is the same as that of memory module a and will not be described in detail here.

[0058] The structure of the DIMM is described in detail below.

[0059] Inside a DIMM, memory data is written bit by bit into a large matrix of memory cells. Simply specifying a row and a column accurately locates a specific memory cell. This is the basic principle of memory chip addressing. This array is called a logical bank of memory.

[0060] Due to manufacturing limitations, this memory cell array cannot be made too large. Therefore, DIMMs are typically manufactured by dividing the memory capacity into several arrays. This means that multiple logical banks exist within the DIMM. As chip capacity continues to increase, the number of logical banks also increases. The address lines of the logical banks are universal, and different banks can be distinguished by their logical bank numbers. For example, a DIMM includes four logical banks, numbered Bank0 through Bank3, each containing 8M memory cells. Therefore, the storage capacity of a logical bank is 64Mbit (8M x 8bit), and the total storage capacity of the four logical banks is 256Mbit (32MB).

[0061] In addition, the interfaces P0 and P1 in the embodiments of the present application are merely exemplary. Memory expansion board A in the embodiments of the present application can be connected to interface P2, and memory expansion board B can be connected to interface P3. The implementation thereof is the same as that described above and will not be described in detail here.

[0062] The following is an exemplary introduction to the specific structure of the memory expansion board A. As shown in Figure 3, the memory expansion board A can be provided with a UBC connector 0, a memory expansion controller MXC0, a DIMM slot 1 and a DIMM slot 2. The pins of the UBC connector 0 can be electrically connected to MXC0 through metal traces. MXC0 can be electrically connected to the pins of the DIMM slot 1 and the pins of the DIMM slot 2 through metal traces. The memory module a can include two DIMMs. The P0 interface of the CPU 111 can be connected to another UBC connector on the motherboard. When the user connects the UBC connector to the UBC connector 0 through a cable and inserts two DIMMs into the DIMM slot 1 and the DIMM slot 2, the CPU 111 can exchange data with the two DIMMs through the interface P0.

[0063] It should be noted that the above examples are merely illustrative, and the UBC connector 0 may be replaced with other types of connectors, and the number of DIMM slots may also be one.

[0064] In addition, the structure of the memory expansion board B is the same as that of the memory expansion board A, and will not be described in detail here.

[0065] In the second embodiment of the present application, based on the first embodiment of the present application, a memory expansion controller MXC2 may be further provided on the memory expansion board A, and a memory expansion controller MXC3 may be further provided on the memory expansion board B, as shown in FIG4 .

[0066] The interface of the memory expansion controller MXC2 supports connecting to DDR5 or DDR4, and can communicate with DDR4 or DDR5 using the CXL or PCIE protocol. MXC0 and CPU111 can also communicate using the CXL protocol or PCIE protocol, and the interfaces that connect MXC2 to the CPU111 and memory module a are called the first CXL interface and the second CXL interface of MXC2 respectively. The embodiment of the present application takes the communication between the memory expansion controller MXC2 and the CPU and memory module a using the CXL protocol as an example. The protocol of the memory expansion controller MXC3 is the same as that of MXC2 and will not be repeated here. The first CXL interface of the memory expansion controller MXC2 can be connected to the interface P0 of the CPU, and the second CXL interface of the memory expansion controller MXC2 can be electrically connected to the memory module c. Among them, the memory module c is a DDR5 memory module or a DDR4 memory module. In this way, the CPU111 can exchange data with the memory module c through the interface P0 and the memory expansion controller MXC2.

[0067] Similarly, the first CXL interface of the memory expansion controller MXC3 can be connected to the CPU's interface P1, and the second CXL interface of the memory expansion controller MXC3 can be electrically connected to the memory module d. In this way, the CPU 111 can exchange data with the memory module d through the interface P1 and the memory expansion controller MXC3.

[0068] Among them, the structures of memory module c and memory module d are the same as those of the aforementioned memory module a. The structure of the memory expansion board of this application can also refer to the structure of the memory expansion board in the first embodiment, which will not be described in detail here.

[0069] Since interface P0 and interface P1 of CPU111 in the embodiment of the present application belong to the same interface group, CPU111 does not need to access across groups when accessing memory module a, memory module b, memory module c and memory module d, which can shorten the access path and thus improve the data transmission speed.

[0070] In the third embodiment of the present application, based on the first embodiment of the present application, the computing device 1 may further include a memory expansion board C and a memory expansion board D. The memory expansion board C is provided with a memory expansion controller MXC4, and the memory expansion board D is provided with a memory expansion controller MXC5, as shown in Figure 5.

[0071] The interface of the memory expansion controller MXC4 supports connection to DDR5 or DDR4, and can communicate with DDR4 or DDR5 using the CXL or PCIE protocol. MXC4 and CPU111 can also communicate through the CXL protocol or PCIE protocol, and the interfaces connecting MXC4 to CPU112 and memory module a are called the first CXL interface and the second CXL interface of MXC4 respectively; the embodiment of the present application takes the use of the CXL protocol for communication between the memory expansion controller MXC4 and the CPU and memory module a as an example. The protocol of the memory expansion controller MXC5 is the same as that of MXC4 and will not be repeated here.

[0072] The mainboard 1 is also provided with a CPU 112 , which is connected to the CPU 111 via a socket / inter-chip global memory interconnect (xGMI) bus to enable data exchange between the CPU 112 and the CPU 111 .

[0073] It's important to note that the xGMI bus, a new high-speed interconnect bus for socket-to-socket communication introduced by AMD (Core Architecture Zen platform), consists of four x16 links, each containing 16 lanes, and each lane containing two bidirectional high-speed differential pairs. Data exchange is achieved through a bidirectional communication connection, with each end of the connection being called a socket.

[0074] The structure of CPU 112 can be the same as that of CPU 111. CPU 112 can be provided with multiple CXL interfaces, for example, four CXL interfaces, namely interface P0, interface P1, interface P2, and interface P3. Interface P0 and interface P1 belong to the same interface group, and interface P2 and interface P3 belong to the same interface group.

[0075] The first CXL interface of the memory expansion controller MXC4 can be connected to the interface P0 of the CPU 112, and the second CXL interface of the memory expansion controller MXC4 can be electrically connected to the memory module e. The memory module e is a DDR5 memory module or a DDR4 memory module. In this way, the CPU 112 can exchange data with the memory module e through the interface P0 and the memory expansion controller MXC4.

[0076] Similarly, the first CXL interface of the memory expansion controller MXC5 can be connected to the interface P1 of the CPU 112, and the second CXL interface of the memory expansion controller MXC5 can be electrically connected to the memory module f. In this way, the CPU 112 can exchange data with the memory module f through the interface P1 and the memory expansion controller MXC5.

[0077] Among them, the structures of memory module e and memory module f are the same as the aforementioned memory module a. The structure of the memory expansion board of this application can also refer to the structure of the memory expansion board in the first embodiment, which will not be described in detail here.

[0078] Since interface P0 and interface P1 of CPU112 in the embodiment of the present application belong to the same interface group, CPU112 does not need to access across groups when accessing memory module e and memory module f, which can shorten the access path and thus improve the data transmission speed between CPU112 and memory module e and memory module f.

[0079] Similarly, when CPU 111 accesses memory modules e and f, it can exchange data with CPU 112 via the xGMI bus. CPU 112 then exchanges data with memory modules e and f. CPU 112 does not need to cross-bank access when accessing memory modules e and f, shortening the access path and thus increasing the data transfer speed between CPU 111 and memory modules e and f.

[0080] Similarly, when CPU112 accesses memory module a and memory module b, it can interact with CPU111 through the xGMI bus, and then CPU111 interacts with memory module a and memory module b. When CPU111 accesses memory module a and memory module b, it does not need to access across groups, which can shorten the access path and thus improve the data transmission speed between CPU112 and memory module a and memory module b.

[0081] In the fourth embodiment of the present application, the memory expansion board and memory module connected to the CPU 111 in the embodiment of the present application are the same as those in the second embodiment of the present application, and the memory expansion board and memory module connected to the CPU 112 in the embodiment of the present application are the same as those in the third embodiment of the present application, as shown in Figure 6.

[0082] In this way, since interface P0 and interface P1 of CPU111 in the embodiment of the present application belong to the same interface group, CPU111 does not need to access across groups when accessing memory module a, memory module b, memory module c and memory module d, and the access path can be shortened, thereby improving the data transmission speed between CPU111 and memory module a, memory module b, memory module c and memory module d.

[0083] Similarly, when CPU 112 accesses memory module e and memory module f, it does not need to cross-group access, which can shorten the access path and thus improve the data transmission speed between CPU 112 and memory module e and memory module f.

[0084] Similarly, when CPU 111 accesses memory modules e and f, it can exchange data with CPU 112 via the xGMI bus. CPU 112 then exchanges data with memory modules e and f. CPU 112 does not need to cross-bank access when accessing memory modules e and f, shortening the access path and thus increasing the data transfer speed between CPU 111 and memory modules e and f.

[0085] Similarly, when CPU 112 accesses memory modules a, b, c, and d, it can exchange data with CPU 111 via the xGMI bus. CPU 111 then exchanges data with memory modules a, b, c, and d. CPU 111 does not need to cross-group access when accessing memory modules a, b, c, and d, shortening the access path and thereby increasing the data transfer speed between CPU 112 and memory modules a, b, c, and d.

[0086] In the fifth embodiment of the present application, the memory expansion board and memory modules connected to the CPU 111 in this embodiment are the same as those in the second embodiment of the present application. Regarding the memory expansion board and memory modules connected to the CPU 112, compared to the CPU 112 and its connected memory expansion board and memory modules in the third embodiment, the memory expansion board C in this embodiment of the present application may further be provided with a memory expansion controller MXC6, and the memory expansion board D may further be provided with a memory expansion controller MXC7, as shown in FIG7 .

[0087] The interface of the memory expansion controller MXC6 supports connection to DDR5 or DDR4, allowing it to communicate with DDR4 or DDR5 using the CXL or PCIE protocol, and MXC4 and CPU111 can also communicate through the CXL protocol or PCIE protocol, and the interfaces connecting MXC6 to the CPU112 and memory module a are called the first CXL interface and the second CXL interface of MXC6 respectively; the embodiment of the present application takes the use of the CXL protocol for communication between the memory expansion controller MXC6 and the CPU and memory module a as an example, the protocol of the memory expansion controller MXC7 is the same as that of MXC6, and will not be repeated here.

[0088] The first CXL interface of the memory expansion controller MXC6 can be connected to the interface P0 of the CPU 112, and the second CXL interface of the memory expansion controller MXC6 can be electrically connected to the memory module g. The memory module g is a DDR5 memory module or a DDR4 memory module. In this way, the CPU 112 can exchange data with the memory module g through the interface P0 and the memory expansion controller MXC6.

[0089] Similarly, the first CXL interface of the memory expansion controller MXC7 can be connected to the interface P1 of the CPU 112, and the second CXL interface of the memory expansion controller MXC7 can be electrically connected to the memory module h. The memory module h is a DDR5 memory module or a DDR4 memory module. In this way, the CPU 112 can exchange data with the memory module h through the interface P1 and the memory expansion controller MXC7.

[0090] Among them, the structures of memory module g and memory module h are the same as the aforementioned memory module a. The structure of the memory expansion board of this application can also refer to the structure of the memory expansion board in the first embodiment, which will not be described in detail here.

[0091] In this way, since interface P0 and interface P1 of CPU111 in the embodiment of the present application belong to the same interface group, CPU111 does not need to access across groups when accessing memory module a, memory module b, memory module c and memory module d, and the access path can be shortened, thereby improving the data transmission speed between CPU111 and memory module a, memory module b, memory module c and memory module d.

[0092] Similarly, when CPU112 accesses memory module e, memory module f, memory module g and memory module h, it does not need to access across groups, which can shorten the access path and thus improve the data transmission speed between CPU112 and memory module e, memory module f, memory module g and memory module h.

[0093] Similarly, when CPU 111 accesses memory modules e, f, g, and h, it can exchange data with CPU 112 via the xGMI bus. CPU 112 then exchanges data with memory modules e, f, g, and h. When CPU 112 accesses memory modules e, f, g, and h, it does not need to cross-group access, shortening the access path and thus improving the data transmission speed between CPU 111 and memory modules e, f, g, and h.

[0094] Similarly, when CPU 112 accesses memory modules a, b, c, and d, it can exchange data with CPU 111 via the xGMI bus. CPU 111 then exchanges data with memory modules a, b, c, and d. CPU 111 does not need to cross-group access when accessing memory modules a, b, c, and d, shortening the access path and thereby increasing the data transfer speed between CPU 112 and memory modules a, b, c, and d.

[0095] The sixth embodiment of the present application is a specific implementation of the fifth embodiment. Specifically, as shown in Figure 8, a power module 1 is provided on the mainboard 11. Specifically, the power module 1 can be a switching power supply. Correspondingly, a power supply connector 1 is provided on the memory expansion board A, and a power supply connector 2 is provided on the memory expansion board B. When the user needs to use the memory expansion boards A and B, a cable can be used to connect the output end of the power module 1 to the power supply connector 1 and the power supply connector 2, so that the power module 1 can power the memory expansion boards A and B.

[0096] Similarly, the output end of the power module 2 on the motherboard 11 can supply power to the memory expansion board C via the power connector 3, and can also supply power to the memory expansion board D via the power connector 4. In the connection method shown in FIG8 , one memory channel connects two memory modules; for example, DIMM1 and DIMM2 are connected to MXC1 via the same memory channel, and DIMM3 and DIMM4 are connected to MXC2 via the same memory channel. The connection method for other memory modules is the same as that for DIMM1 and DIMM2, and will not be repeated here.

[0097] The mainboard 11 includes a UBC connector A0 , and the interface P0 is electrically connected to the UBC connector A0 via metal traces on the mainboard 1 .

[0098] Memory expansion board A is equipped with UBC connector B0 and UBC connector B1. UBC connector B0 is electrically connected to MXC0 via metal traces, and UBC connector B1 is electrically connected to MXC2 via metal traces. One memory channel of MXC0 can be connected to DIMM slot 1 and DIMM slot 2. Memory module A can include DIMM1 and DIMM2. DIMM slot 1 can be inserted into DIMM1, and DIMM slot 2 can also be inserted into DIMM2.

[0099] When the user connects UBC connector A0 to UBC connector B0 and UBC connector B1 with a cable, CPU111 can exchange data with DIMM1 and DIMM2 through interface P0 and MXC0. CPU111 can also exchange data with DIMM3 and DIMM4 through interface P0 and MXC2.

[0100] Similarly, the structure of memory expansion board B is the same as that of memory expansion board A. When the user connects UBC connector A1 to UBC connector B2 and UBC connector B3 using cables, CPU 111 can exchange data with DIMM5 and DIMM6 through interface P1 and MXC1. CPU 111 can also exchange data with DIMM7 and DIMM8 through interface P1 and MXC3.

[0101] Since interface P0 and interface P1 of CPU111 in the embodiment of the present application belong to the same interface group, CPU111 does not need to cross-group access when accessing DIMM1 to DIMM8, which can shorten the access path and thus improve the data transmission speed between CPU111 and DIMM1 to DIMM8.

[0102] Similarly, the structures of memory expansion boards C and D are the same as those of memory expansion board A. When the user connects UBC connector A2 to UBC connector B4 and UBC connector B5 with a cable, CPU 112 can exchange data with DIMM 9 and DIMM 10 through interface P0 and MXC4. CPU 112 can also exchange data with DIMM 11 and DIMM 12 through interface P0 and MXC6. Similarly, when the user connects UBC connector A3 to UBC connector B6 and UBC connector B7 with a cable, CPU 112 can exchange data with DIMM 13 and DIMM 14 through interface P1 and MXC5. CPU 112 can also exchange data with DIMM 15 and DIMM 16 through interface P1 and MXC7.

[0103] Since interface P0 and interface P1 of CPU112 in the embodiment of the present application belong to the same interface group, CPU112 does not need to cross-group access when accessing DIMM9 to DIMM16, which can shorten the access path and thus improve the data transmission speed between CPU112 and DIMM9 to DIMM16.

[0104] Similarly, when CPU 111 accesses DIMMs 9 to 16, it can exchange data with CPU 112 via the xGMI bus, and then CPU 112 can exchange data with DIMMs 9 to 16. When CPU 112 accesses DIMMs 9 to 16, it does not need to cross-group access, shortening the access path and thus improving the data transmission speed between CPU 111 and DIMMs 9 to 16.

[0105] When CPU 112 accesses DIMMs 1 to 8, it can exchange data with CPU 111 via the xGMI bus. CPU 111 then exchanges data with DIMMs 1 to 8. CPU 111 does not need to cross-group access when accessing DIMMs 1 to 8, shortening the access path and thus increasing the data transfer speed between CPU 112 and DIMMs 1 to 8.

[0106] The inventors used the computing device provided by the sixth embodiment to test the data transmission speed between the CPU and the memory module. The following describes the technical effects of the embodiment of the present application in detail using actual test data.

[0107] In the prior art, those skilled in the art might connect memory modules to CXL interfaces that do not belong to the same interface group. In one example, interface P2 (rather than interface P0) in CPU 111 connects memory modules a and c via memory expansion board A. The connection relationship of interface P1 of CPU 111 is shown in Figure 8. In this connection relationship, the CXL interface connecting memory modules a and c is interface P2, and the CXL interface connecting memory modules b and d is interface P1. Interfaces P1 and P2 do not belong to the same interface group.

[0108] In actual tests, the inventors found that the data transmission speed between CPU111 and memory module a, memory module b, memory module c and memory module d is 60G / s, and the data transmission speed between CPU112 and memory module a, memory module b, memory module c and memory module d is also 60G / s.

[0109] In contrast, when CPU 111 adopts the connection relationship described in the sixth embodiment, interface P0 and interface P1 belong to the same interface group. The inventors found in actual testing that the data transmission speed between CPU 111 and memory modules a, b, c, and d increased to 80 G / s, and the data transmission speed between CPU 112 and memory modules a, b, c, and d increased to 80 G / s.

[0110] Similarly, in one example, CPU 112's interface P2 (rather than interface P0) is connected to memory modules e and g via memory expansion board C, while the connection relationship of CPU 112's interface P1 is shown in FIG8 . In this case, the data transmission speed between CPU 111 and memory modules e, f, g, and h is 60 G / s, and the data transmission speed between CPU 112 and memory modules e, f, g, and h is also 60 G / s. When CPU 112 adopts the connection relationship described in the sixth embodiment, both of these data transmission speeds are increased to 80 G / s.

[0111] It should be understood that the structure of the computing device 1 illustrated in the embodiments of the present application does not constitute a specific limitation on the computing device 1. In other embodiments of the present application, the computing device 1 may include more or fewer components than illustrated, or may combine or separate certain components, or may have different component arrangements. The illustrated components may be implemented in hardware, software, or a combination of software and hardware.

[0112] In addition, the various numerical numbers involved in the embodiments of the present application are only for the convenience of description and are not used to limit the scope of the embodiments of the present application.

[0113] The above is only a specific implementation of the embodiment of the present application, but the protection scope of the embodiment of the present application is not limited to this. Any technician familiar with this technical field can easily think of changes or replacements within the technical scope disclosed in the embodiment of the present application, and they should all be covered by the protection scope of the embodiment of the present application.

Claims

1. A computing device, characterized in that, The computing device includes a main board, a first memory expansion board, a first memory module, a second memory expansion board, and a second memory module; a first CPU is provided on the main board, and the first CPU includes a first interface and a second interface, and the first interface and the second interface are memory interfaces and belong to the same interface group of the first CPU; A first memory expansion controller is provided on the first memory expansion board, and a second memory expansion controller is provided on the second memory expansion board; The first memory expansion controller is electrically connected to the first interface and the first memory module respectively, and the second memory expansion controller is electrically connected to the second interface and the second memory module respectively.

2. The computing device according to claim 1, wherein The computing device further includes a third memory module and a fourth memory module; A third memory expansion controller is further provided on the first memory expansion board, and a fourth memory expansion controller is further provided on the second memory expansion board; The third memory expansion controller is electrically connected to the first interface and the third memory module respectively, and the fourth memory expansion controller is electrically connected to the second interface and the fourth memory module respectively.

3. The computing device according to claim 1 or 2, characterized in that, The computing device further includes a third memory expansion board, a fourth memory expansion board, a fifth memory module, and a sixth memory module; A second CPU is further provided on the main board, and the second CPU includes a third interface and a fourth interface, and the third interface and the fourth interface are memory interfaces and belong to the same interface group of the second CPU; the second CPU is electrically connected to the first CPU through an xGMI bus; The fifth memory expansion controller is electrically connected to the third interface and the fifth memory module respectively, and the sixth memory expansion controller is electrically connected to the fourth interface and the sixth memory module respectively.

4. The computing device according to claim 3, wherein The computing device further includes a seventh memory module and an eighth memory module; A seventh memory expansion controller is further provided on the third memory expansion board, and an eighth memory expansion controller is further provided on the fourth memory expansion board; The seventh memory expansion controller is electrically connected to the third interface and the seventh memory module respectively, and the eighth memory expansion controller is electrically connected to the fourth interface and the eighth memory module respectively.

5. The computing device according to any one of claims 1 to 4, characterized in that The first interface and the second interface are CXL interfaces for fast computing links.

6. The computing device according to any one of claims 1 to 5, characterized in that The first CPU accesses the first memory module and the second memory module in a memory interleaving manner.

7. The computing device according to any one of claims 1 to 6, characterized in that A first power module is provided on the main board; The output end of the first power module is electrically connected to the first memory expansion board and the second memory expansion board.

8. The computing device according to claim 1, wherein The first memory module includes at least one dual in-line memory module DIMM, and the second memory module includes at least one dual in-line memory module DIMM; the first memory module is inserted on the first memory expansion board, and the second memory module is inserted on the second memory expansion board.

9. The computing device according to any one of claims 1 - 8, characterized in that, A first connector is provided on the first memory expansion board, a second connector is provided on the main board, and a third connector is provided on the second memory expansion board; the first memory expansion board is electrically connected to the first interface through the first connector and the second connector, and the second memory expansion board is electrically connected to the second interface through the third connector, the second connector. Electrically connected to the second connector.

10. The computing device according to any one of claims 1 to 9, characterized in that, The first memory module is a DDR4 memory or a DDR5 memory, and the second memory module is a DDR4 memory or a DDR5 memory.

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