Wiring structure of memory, and memory

Abstract

Provided in the present disclosure are a wiring structure of a memory, and a memory. The wiring structure of a memory comprises: a first operation unit, which is used for receiving an initial control signal and a first enable signal and generating a first control signal; a second operation unit, which is used for receiving the initial control signal and a second enable signal and generating a second control signal; a signal processing unit, which is used for receiving and separately processing the initial control signal, the first enable signal and the second enable signal; and a first transmission unit, wherein the first transmission unit and the signal processing unit are jointly used for transmitting the initial control signal to the first operation unit and the second operation unit, respectively, such that the difference in the delays of the initial control signal separately received by the first operation unit and the second operation unit is less than a preset threshold value.

Description

Memory wiring structure and memory

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on December 25, 2023, with application number 202311785507.8 and application name “Wiring structure of memory and memory”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The embodiments of the present disclosure relate to the field of semiconductor technology, and in particular to a wiring structure of a memory and a memory. Background Art

[0003] Typically, a semiconductor device includes a memory array area and a peripheral area. Many signal and power lines are arranged above the memory array and peripheral areas. The peripheral area includes multiple signal processing areas, such as the column decoding area and the row-column decoding area. With the growing demand for portability, computing power, memory capacity, and energy efficiency in modern electronic products, DRAM chip design aims to minimize the layout area of ​​the row decoding area.

[0004] However, as the layout area of ​​the row decoding area decreases, the space available for wiring above the row decoding area is further compressed, resulting in insufficient space resources for a certain number of wiring. Based on this, how to reduce the layout space required for wiring without affecting the transmission performance of the wiring has become an urgent problem to be solved.

[0005] Summary of the Invention

[0006] The embodiments of the present disclosure provide a wiring structure of a memory and a memory, which are at least beneficial to improving the transmission performance of the wiring structure and reducing the layout space occupied by the wiring structure.

[0007] According to some embodiments of the present disclosure, on one hand, an embodiment of the present disclosure provides a wiring structure of a memory, comprising: a first column decoding area and a second column decoding area arranged at intervals along a first direction, the first column decoder having a first operation unit configured to receive an initial control signal and a first enable signal and generate a first control signal; the second column decoding area having a second operation unit configured to receive the initial control signal and the second enable signal and generate a second control signal; a row decoding area located between the first column decoding area and the second column decoding area; a signal processing unit located on a side adjacent to the second column decoding area and away from the first column decoding area, configured to receive the initial control signal, the first enable signal, and the second enable signal, and process the initial control signal, the first enable signal, and the second enable signal respectively; and a first transmission unit, wherein the first transmission unit and the signal processing unit are jointly configured to transmit the initial control signal to the first operation unit and the second operation unit respectively, and ensure that the difference between a first delay of the initial control signal received by the first operation unit and a second delay of the initial control signal received by the second operation unit is less than a preset threshold.

[0008] In some embodiments, the first transmission unit includes a main path, a first branch, and a second branch; wherein, one end of the main path is electrically connected to the signal processing unit, the other end of the main path is electrically connected to the first branch and the second branch respectively, the other end of the first branch is electrically connected to the first computing unit, and the other end of the second branch is electrically connected to the second computing unit.

[0009] In some embodiments, the main path and the first branch together constitute a first transmission path, and the main path and the second branch together constitute a second transmission path; the first transmission path is used to transmit the initial control signal to the first operation unit, and the second transmission path is used to transmit the initial control signal to the second operation unit, and the ratio of the first length of the first transmission path to the second length of the second transmission path is 0.9 to 1.1.

[0010] In some embodiments, the first transmission unit is located in the row decoding area.

[0011] In some embodiments, the signal processing unit is configured to buffer the received initial control signal to obtain a first output signal and output the first output signal; the first transmission unit is configured to receive the first output signal and transmit the first output signal to the first operation unit and the second operation unit respectively.

[0012] In some embodiments, the main path, the first branch and the second branch are located in the same metal layer, and the main path and the first branch constitute a first transmission line that runs through the row decoding area, and the second branch is a second transmission line that is bent in a partial area; the wiring structure also includes: a first shielding line, located on a side of the first transmission line away from the second transmission line; a second shielding line, located between the first transmission line and the second transmission line; and a third shielding line, located on a side of the second transmission line away from the first transmission line.

[0013] In some embodiments, the wiring structure also includes: a second transmission unit, electrically connecting the signal processing unit and the first operation unit, and configured to transmit the first enable signal to the first operation unit; a third transmission unit, electrically connecting the signal processing unit and the second operation unit, and configured to transmit the second enable signal to the second operation unit; the initial control signal includes N sub-control signals, and the sub-control signals correspond one-to-one to the first transmission units. The N first transmission units are arranged at intervals along the second direction, the second direction intersects with the first direction, and the N first transmission units correspond to the same second transmission unit and the same third transmission unit, and N is a positive integer.

[0014] In some embodiments, the first transmission units, the first shielding lines, and the second shielding lines correspond to each other one by one, and there is one first shielding line between two adjacent first transmission units along the second direction.

[0015] In some embodiments, along the second direction, there is one third shielding line between one of the first transmission units closest to the second transmission unit and the second transmission unit.

[0016] In some embodiments, the wiring structure also includes a storage array area, the storage array area and the row decoding area are adjacent along a second direction and are located between the first column decoding area and the second column decoding area, and the second direction intersects with the first direction; the main path includes a first main path located in the storage array area, and a second main path extending from the storage array area to the row decoding area, the first main path is electrically connected to the signal processing unit, and the second main path is electrically connected to the first branch and the second branch, respectively.

[0017] In some embodiments, the signal processing unit includes a first inverter, which is configured to receive the initial control signal and invert the initial control signal to obtain a second output signal, and output the second output signal; the first main path is configured to receive and transmit the second output signal to the second main path; the second main path has a second inverter, which is configured to receive the second output signal and invert the second output signal to obtain a third output signal, and output the third output signal; the first branch is configured to receive and transmit the third output signal to the first operation unit; the second branch is configured to receive and transmit the third output signal to the second operation unit.

[0018] In some embodiments, the first branch and the second branch are located in the same metal layer, and the first branch and the second branch constitute a third transmission line that runs through the row decoding area; the wiring structure also includes: a fourth shielding line and a fifth shielding line, respectively located on two opposite sides of the third transmission line along the second direction.

[0019] In some embodiments, the wiring structure further includes: a second transmission unit, electrically connecting the signal processing unit and the first operation unit, and configured to transmit the first enable signal to the first operation unit; a third transmission unit, electrically connecting the signal processing unit and the second operation unit, and configured to transmit the second enable signal to the second operation unit; the initial control signal includes N sub-control signals, and the sub-control signals correspond one-to-one to the first transmission units. The N third transmission lines in the N first transmission units are arranged at intervals along the second direction, and the N first transmission units correspond to the same second transmission unit and the same third transmission unit, and N is a positive integer.

[0020] In some embodiments, the fourth shielding lines correspond to the third transmission lines in a one-to-one manner, and there is one fourth shielding line between two adjacent third transmission lines along the second direction.

[0021] In some embodiments, along the second direction, there is one fifth shielding line between the third transmission line closest to the second transmission unit and the second transmission unit.

[0022] According to some embodiments of the present disclosure, another aspect of the present disclosure further provides a memory, comprising the wiring structure according to any one of the above items.

[0023] The technical solution provided by the embodiments of the present disclosure has at least the following advantages:

[0024] On the one hand, a new first transmission unit and a new signal processing unit are designed. The first transmission unit and the signal processing unit work together to ensure that the difference between the first delay of the initial control signal received by the first operation unit and the second delay of the initial control signal received by the second operation unit is less than a preset threshold. In other words, the signal output by the signal processing unit is transmitted to the first operation unit and the second operation unit respectively via the first transmission unit. The first transmission unit controls signal transmission so that the difference between the times when the first and second operation units receive the initial control signal is within a preset threshold. In other words, the difference in the time it takes for the signal output by the signal processing unit to be transmitted via the first transmission unit to the first column decoding area and the second column decoding area is within a preset threshold, thereby improving the transmission performance of the wiring structure.

[0025] On the other hand, by designing a first operation unit in the first column decoding area and a second operation unit in the second column decoding area, not only does the signal processing unit initially process the initial control signal it receives, but the first column decoding area can also perform secondary processing on the initial control signal processed by the signal processing unit and the first transmission unit through the first operation unit to ultimately generate a first control signal that prompts the first column decoding area to perform subsequent operations. Furthermore, the second column decoding area can perform secondary processing on the initial control signal processed by the signal processing unit and the first transmission unit through the second operation unit to ultimately generate a second control signal that prompts the second column decoding area to perform subsequent operations. In this way, the first transmission unit only needs to transmit one signal: the initial control signal received and processed by the signal processing unit to the first operation unit and the second operation unit. This helps reduce the layout space required for the first transmission unit, thereby reducing the layout space occupied by the wiring structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] One or more embodiments are exemplarily illustrated by pictures in the corresponding drawings. These exemplifications do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are represented as similar elements. Unless otherwise stated, the figures in the drawings do not constitute a scale limitation. In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the traditional technology, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0027] FIG1 is a schematic diagram of a partial top view of a wiring structure;

[0028] FIG2 is a functional block diagram of a wiring structure provided by an embodiment of the present disclosure;

[0029] FIG3 is a schematic diagram of a partial top view of a wiring structure provided by an embodiment of the present disclosure;

[0030] FIG4 is a functional block diagram of a combination of a signal processing unit, a first transmission unit, a first operation unit, and a second operation unit in a wiring structure provided by an embodiment of the present disclosure;

[0031] FIG5 is another schematic top view of a wiring structure provided by an embodiment of the present disclosure;

[0032] FIG6 is a schematic top view of another wiring structure provided by an embodiment of the present disclosure;

[0033] FIG7 is a schematic top view of another wiring structure provided by an embodiment of the present disclosure;

[0034] FIG8 is a schematic top view of the structure of the first transmission unit in the wiring structure shown in FIG7;

[0035] FIG9a is a schematic top view of the structure of a first transmission path composed of a main path and a first branch path in the first transmission unit shown in FIG8 ;

[0036] FIG9 b is a schematic top view of the structure of the first transmission unit shown in FIG8 , in which the main path and the second branch path together constitute a second transmission path;

[0037] FIG10 is a schematic top view of a wiring structure in which shielding wires are added to the structure shown in FIG7;

[0038] FIG11 is a schematic top view of another wiring structure provided by an embodiment of the present disclosure;

[0039] FIG12 is a schematic top view of another wiring structure provided by an embodiment of the present disclosure;

[0040] FIG13 is a schematic top view of another wiring structure provided by an embodiment of the present disclosure;

[0041] 14 is a schematic top view of a structure of a combination of the first transmission unit, the first storage array area, the row decoding area, and the second storage array area in the wiring structure shown in FIG13 ;

[0042] FIG15 is a schematic top view of the structure of the first transmission unit in the wiring structure shown in FIG12;

[0043] FIG16 is a schematic top view of a wiring structure in which shielding wires are added to the structure shown in FIG13;

[0044] FIG17 is another schematic top view of the structure of the first transmission unit in the wiring structure provided in one embodiment of the present disclosure;

[0045] FIG18 is a schematic structural diagram of a memory according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0046] As known from the background art, under the premise of ensuring good transmission performance of the wiring, the layout space required for the wiring needs to be reduced.

[0047] After analysis, referring to Figure 1, which is a partial top view of a wiring structure, it was found that in a semiconductor device, signal processing unit 10 receives an initial signal and transmits the processed initial signal to first column decoding area 11 and second column decoding area 12, respectively. Based on this, it is necessary to design first wiring 13 to transmit the signal output by signal processing unit 10 to first column decoding area 11, and second wiring 14 to transmit the signal output by signal processing unit 10 to second column decoding area 12. The layout space occupied by first wiring 13 and second wiring 14 is wiring area 15 in Figure 1.

[0048] In some cases, after receiving an initial signal, signal processing unit 10 processes the initial signal to generate a first control signal that controls subsequent operations of first column decoding area 11 and a second control signal that controls subsequent operations of second column decoding area 12. Signal processing unit 10 then provides the generated first control signal to first column decoding area 11 via first wiring 13, and provides the generated second control signal to second column decoding area 12 via second wiring 14. First column decoding area 11 and second column decoding area 12 then perform subsequent operations based on their respective received control signals. Furthermore, the control signals provided by signal processing unit 10 to first column decoding area 11 and second column decoding area 12 differ based on different initial signals. This places high demands on the transmission performance of first wiring 13 and second wiring 14.

[0049] On the one hand, the time it takes for the first control signal output by the signal processing unit 10 to be transmitted to the first column decoding area 11 via the first wiring 13 is taken as the first time, and the time it takes for the second control signal output by the signal processing unit 10 to be transmitted to the second column decoding area 12 via the second wiring 14 is taken as the second time. Based on the difference in the distance between the signal processing unit 10 and the first column decoding area 11 and the second column decoding area 12, it is necessary to perform a routing process on at least one of the first wiring 13 and the second wiring 14 to reduce the difference between the first time and the second time. In Figure 1, the signal processing unit 10 is closer to the second column decoding area 12, and the second wiring 14 is routed as an example. It can be understood that performing a routing process on the second wiring 14 will increase the layout area occupied by the second wiring 14 in the wiring area 15.

[0050] On the other hand, the first column decoding area 11 and the second column decoding area 12 need to receive accurate control signals output by the signal processing unit 10 to facilitate subsequent operations. To this end, the first wiring 13 and the second wiring 14 must have a high transmission accuracy. In other words, the distortion rate of the control signal when transmitted in the first wiring 13 and the second wiring 14 must be reduced. Therefore, a shielding line 16 is required between any two adjacent wirings to reduce electrical interference between adjacent wirings. The wiring described here includes the first wiring 13 and the second wiring 14. It is understandable that the addition of shielding line 16 will increase the layout space required for wiring area 15.

[0051] Referring to Figure 1 , a shielding wire 16 is required between the first wiring 13 and the second wiring 14. Since the second wiring 14 itself is wound, at least one shielding wire 16 is required within the second wiring 14. Furthermore, a shielding wire 16 is required between the first wiring 13 and other external wiring, and a shielding wire 16 is also required between the second wiring 14 and other external wiring. Therefore, to reduce the distortion of control signals transmitted between the first and second wirings 13, 14, at least four shielding wires 16 are required for each first wiring 13 and each second wiring 14. Consequently, having more shielding wires 16 than first and second wirings 13, 14 further increases the layout space required for the wiring area 15.

[0052] It should be noted that in FIG. 1 , the first wiring 13 and the second wiring 14 are indicated by solid lines, and the shielding line 16 is indicated by dotted lines.

[0053] On the other hand, the signal processing unit 10 receives a variety of initial signals, and any of the initial signals will generate two output signals, namely a first control signal and a second control signal, through the signal processing unit 10. Since the signal processing unit 10 receives a variety of initial signals, for example, N types, where N is a positive integer, it is necessary to design N first wirings 13 and N second wirings 14 in the wiring area 15. Further, a first wiring 13 and a second wiring 14 are regarded as a group of signal transmission lines. Taking into account the shielding line 16, even if adjacent groups of signal transmission lines can share a shielding line 16, in order to transmit the 2N output signals generated by the N types of initial signals, the total number of wirings that need to be designed in the wiring area 15 is at least (6N+1) wirings, where the wiring includes the first wiring 13, the second wiring 14, and the shielding line 16.

[0054] From the above analysis, it can be seen that to ensure good transmission performance of the first wiring 13 and the second wiring 14, many lines need to be laid out in the wiring area 15. The required layout space of the wiring area 15 is relatively large, which is not conducive to achieving the limitation of semiconductor devices. It should be noted that one wiring line will occupy at least one line.

[0055] Therefore, how to reduce the layout space required for wiring without affecting the transmission performance of the wiring has become an urgent problem to be solved.

[0056] The present disclosure provides a wiring structure and a memory. In the wiring structure, on the one hand, by utilizing the cooperation of a first transmission unit and a signal processing unit, the difference between the first delay of the initial control signal received by the first operation unit and the second delay of the initial control signal received by the second operation unit is less than a preset threshold. In other words, the difference between the time taken for the signal output by the control signal processing unit to be transmitted to the first column decoding area and the second column decoding area via the first transmission unit is within the preset threshold, thereby improving the transmission performance of the wiring structure. On the other hand, by designing the first operation unit in the first column decoding area and the second operation unit in the second column decoding area, not only does the signal processing unit perform primary processing on the initial control signal it receives, but the first column decoding area also performs secondary processing on the initial control signal it receives through the first operation unit to ultimately generate a first control signal that prompts the first column decoding area to perform subsequent operations, and the second column decoding area performs secondary processing on the initial control signal it receives through the second operation unit to ultimately generate a second control signal that prompts the second column decoding area to perform subsequent operations. In this way, the first transmission unit only needs to transmit one signal, that is, to transmit the initial control signal received and processed by the signal processing unit to the first operation unit and the second operation unit, which is beneficial to reducing the layout space required for the first transmission unit, thereby helping to reduce the layout space occupied by the wiring structure.

[0057] The following describes various embodiments of the present disclosure in detail with reference to the accompanying drawings. However, those skilled in the art will appreciate that many technical details are provided in the various embodiments of the present disclosure to help readers better understand the embodiments of the present disclosure. However, even without these technical details and the various variations and modifications based on the following embodiments, the technical solutions claimed in the embodiments of the present disclosure can be implemented.

[0058] An embodiment of the present disclosure provides a wiring structure of a memory, which will be described in detail below with reference to the accompanying drawings.

[0059] FIG2 is a functional block diagram of a wiring structure provided by an embodiment of the present disclosure.

[0060] 2 , the wiring structure of the memory includes: a first column decoding area 101 and a second column decoding area 102 arranged at intervals along a first direction X, wherein the first column decoding area 101 includes a first operation unit 111 configured to receive an initial control signal Control and a first enable signal FAR_EN and generate a first control signal Control1; the second column decoding area 102 includes a second operation unit 112 configured to receive an initial control signal Control and a second enable signal NEAR_EN and generate a second control signal Control2; a row decoding area 103 located between the first column decoding area 101 and the second column decoding area 102; a signal processing unit 104 located adjacent to the second column decoding area 102 and away from the first column decoding area One side of the decoding area 101 is configured to receive the initial control signal Control, the first enable signal FAR_EN and the second enable signal NEAR_EN, and process the initial control signal Control, the first enable signal FAR_EN and the second enable signal NEAR_EN respectively; the first transmission unit 105, and the first transmission unit 105 and the signal processing unit 104 are jointly configured to transmit the initial control signal Control to the first operation unit 111 and the second operation unit 112 respectively, and make the difference between the first delay of the initial control signal Control received by the first operation unit 111 and the second delay of the initial control signal Control received by the second operation unit 112 less than a preset threshold.

[0061] It is worth noting that the first column decoding region 101, the second column decoding region 102, and the row decoding region 103 are divided into different areas within the wiring structure. Each area performs different primary functions. By dividing the wiring structure into different areas, the positional relationships between different electrical components can be determined. The first column decoding region 101 includes, but is not limited to, the first arithmetic unit 111, and the second column decoding region 102 includes, but is not limited to, the second arithmetic unit 112.

[0062] It is understood that the signal processing unit 104 and the first transmission unit 105 cooperate to transmit the initial control signal Control received by the signal processing unit 104 to the first operation unit 111 and the second operation unit 112, respectively. This transmission process is beneficial to improving the transmission performance of the wiring structure. The following is a detailed description: a new signal processing unit 104 and a new first transmission unit 105 are designed, and the signal processing unit 104 and the first transmission unit 105 cooperate to ensure that the difference between the first delay of the initial control signal Control received by the first operation unit 111 and the second delay of the initial control signal Control received by the second operation unit 112 is less than a preset threshold. In other words, the signal output by the signal processing unit 104 is transmitted to the first operation unit 111 and the second operation unit 112 respectively through the first transmission unit 105, and the difference between the moments when the first operation unit 111 and the second operation unit 112 receive the initial control signal Control by controlling the transmission of the signal by the first transmission unit 105 is within a preset threshold, that is, the difference in the time taken for the signal output by the control signal processing unit 104 to be transmitted to the first column decoding area 101 and the second column decoding area 102 via the first transmission unit 105 is within a preset threshold, thereby improving the transmission performance of the wiring structure.

[0063] On the other hand, the first operation unit 111 is designed in the first column decoding area 101, and the second operation unit 112 is designed in the second column decoding area 102. Then, not only does the signal processing unit 104 perform primary processing on the initial control signal Control it receives, but the first column decoding area 101 can perform secondary processing on the initial control signal Control processed by the signal processing unit 104 and the first transmission unit 105 through the first operation unit 111, so as to ultimately generate the first control signal Control1 that prompts the first column decoding area 101 to perform subsequent operations, and the second column decoding area 102 can perform secondary processing on the initial control signal Control processed by the signal processing unit 104 and the first transmission unit 105 through the second operation unit 112, so as to ultimately generate the second control signal Control2 that prompts the second column decoding area 102 to perform subsequent operations.

[0064] In other words, in the newly designed wiring structure, signal processing unit 104 is no longer solely responsible for processing the initial control signal Control to generate a control signal that prompts first column decoding area 101 and second column decoding area 102 to perform subsequent operations. Instead, first and second operation units 111 and 112 are respectively designed in first and second column decoding areas 101 and 102 to process the initial control signal Control. This allows first control signal Control1, used to prompt first column decoding area 101 to perform subsequent operations, to be generated in first column decoding area 101, while second control signal Control2, used to prompt second column decoding area 102 to perform subsequent operations, to be generated in second column decoding area 102. This allows first transmission unit 105 to transmit only one signal: the initial control signal Control, received and processed by signal processing unit 104, to first and second operation units 111 and 112. This reduces the layout space required for first transmission unit 105 and, consequently, the layout space occupied by the wiring structure.

[0065] Moreover, the signal processing unit 104 only needs to perform initial processing on the initial control signal Control it receives. There is no need to generate the first control signal Control1 based on the initial control signal Control and the first enable signal FAR_EN in the signal processing unit 104, nor is there any need to generate the second control signal Control2 based on the initial control signal Control and the second enable signal NEAR_EN in the signal processing unit 104. This is beneficial to simplifying the processing logic of the signal processing unit 104 on the initial control signal Control, thereby helping to reduce the complexity of the logic circuit in the signal processing unit 104, so as to reduce the layout space required for the signal processing unit 104, thereby helping to further reduce the layout space occupied by the wiring structure.

[0066] It should be noted that in Figure 2 , the first column decoding area 101 is indicated by YDEC_FAR, the second column decoding area 102 is indicated by YDEC_NEAR, the row decoding area 103 is indicated by XDEC, and the signal processing unit 104 is indicated by BANKLOGIC. Furthermore, to illustrate the transmission path of the initial control signal Control through the signal processing unit 104, the first transmission unit 105, the first operation unit 111, and the second operation unit 112, the first transmission unit 105 illustrated in Figure 2 is merely a simplified functional block diagram.

[0067] In some cases, since the row decoding area 103 is located between the first column decoding area 101 and the second column decoding area 102, and the signal processing unit 104 is located on a side adjacent to the second column decoding area 102 and away from the first column decoding area 101, in other words, the signal processing unit 104 is located outside the area formed by the first column decoding area 101, the second column decoding area 102, and the row decoding area 103, so when the signal output by the signal processing unit 104 is transmitted to the first column decoding area 101 and the second column decoding area 102 respectively via the first transmission unit 105, the signal transmission path will pass through the row decoding area 103 along the first direction X.

[0068] The wiring structure will be described in more detail below with reference to the accompanying drawings.

[0069] In some embodiments, a difference between a first delay of the initial control signal Control received by the first operation unit 111 and a second delay of the initial control signal Control received by the second operation unit 112 is smaller than a preset threshold, and the preset threshold is 0-30 ps.

[0070] In actual applications, first column decoding area 101 further includes a first column decoder (not shown), which performs subsequent operations based on a first control signal Control1 generated by first operation unit 111. Second column decoding area 102 further includes a second column decoder (not shown), which performs subsequent operations based on a second control signal Control2 generated by second operation unit 112. Furthermore, the smaller the difference between the time when the first column decoder receives the first control signal Control1 and the time when the second column decoder receives the second control signal Control2, the more conducive it is to ensuring that the first and second column decoders perform subsequent operations simultaneously.

[0071] Based on this, the smaller the difference between the first delay of the initial control signal Control received by the first operation unit 111 and the second delay of the initial control signal Control received by the second operation unit 112, that is, the smaller the preset threshold, the more conducive it is to reducing the difference between the time when the first column decoder receives the first control signal Control1 and the time when the second column decoder receives the second control signal Control2, thereby more conducive to ensuring that the first column decoder and the second column decoder perform subsequent operations simultaneously. In an optimal state, the excellent transmission performance of the first transmission unit 105 is used to ensure that the preset threshold is 0ps. Considering the influence of other factors in actual applications, the preset threshold is controlled to be no greater than 30ps, which is also conducive to ensuring that the first column decoder and the second column decoder perform subsequent operations almost simultaneously, avoiding errors in subsequent operations.

[0072] In some embodiments, referring to Figure 3, Figure 3 is a partial top-down structural schematic diagram of a wiring structure provided by an embodiment of the present disclosure, the first operation unit 111 includes a first AND gate circuit 121 and a first buffer 131 connected in series, the first AND gate circuit 121 receives the initial control signal Control provided by the first transmission unit 105 and the first enable signal FAR_EN provided by the signal processing unit 104, and the first AND gate circuit 121 generates a first control signal Control1 based on the initial control signal Control and the first enable signal FAR_EN, and transmits the first control signal Control1 to the first buffer 131.

[0073] It is worth noting that the first buffer 131 buffers the first control signal Control1, which is beneficial to reducing the distortion rate of the first control signal Control1 and increasing the driving capability of the first control signal Control1, for example, increasing the driving capability of the first decoder by the first control signal Control1.

[0074] In some embodiments, the first buffer 131 may include M pairs of inverters connected in series, where M is a positive integer. One pair of inverters connected in series includes two inverters connected in series. It is understood that the two inverters connected in series can effectively reduce the distortion rate of the first control signal Control1. Specifically, the first inverter of the two inverters connected in series can invert the first control signal Control1, and the second inverter will invert the inverted signal again to generate the buffered first control signal Control1. In this way, by inverting the first control signal Control1 twice, the influence of the transition time of the rising / falling edge in the first control signal Control1 is offset, thereby avoiding the influence on the duty cycle of the first control signal Control1 and reducing the distortion rate of the first control signal Control1.

[0075] In some embodiments, continuing to refer to Figure 3, the second operation unit 112 includes a second AND gate circuit 122 and a second buffer 132 connected in series, the second AND gate circuit 122 receives the initial control signal Control provided by the first transmission unit 105 and the second enable signal NEAR_EN provided by the signal processing unit 104, and the second AND gate circuit 122 generates a second control signal Control2 based on the initial control signal Control and the second enable signal NEAR_EN, and transmits the second control signal Control2 to the second buffer 132.

[0076] It is worth noting that the second buffer 132 buffers the second control signal Control2, which helps reduce the distortion rate of the second control signal Control2 and increase the driving capability of the second control signal Control2, for example, increasing the driving capability of the second control signal Control2 for the second decoder. In some embodiments, the second buffer 132 may also include M pairs of inverters connected in series, where M is a positive integer. A pair of inverters connected in series includes two inverters connected in series. The parts of the second buffer 132 that are identical or similar to the first buffer 131 are not further described here.

[0077] It should be noted that in Figure 3, the first AND gate circuit 121 and the second AND gate circuit 122 each include only one AND gate as an example. In actual applications, there is no restriction on the specific structure of the first AND gate circuit 121 and the second AND gate circuit 122. The circuit that can implement AND gate logic can be the first AND gate circuit 121 or the second AND gate circuit 122.

[0078] The first transmission unit 105 is described in detail below.

[0079] In some embodiments, referring to FIG4 , first transmission unit 105 includes a main circuit 115, a first branch circuit 125, and a second branch circuit 135. One end of main circuit 115 is electrically connected to signal processing unit 104, and the other end of main circuit 115 is electrically connected to first branch circuit 125 and second branch circuit 135, respectively. The other end of first branch circuit 125 is electrically connected to first computing unit 111, and the other end of second branch circuit 135 is electrically connected to second computing unit 112. Thus, first transmission unit 105 performs wave splitting and transmission on the received signal, thereby transmitting the initial control signal Control received by signal processing unit 104 to first computing unit 111 and second computing unit 112, respectively. It can be understood that when the signal is transmitted in the first transmission unit 105, the signal on the main path 115 is transmitted to the first branch 125 and the second branch 135 respectively. The ratio of the transmission path of the control signal on the first branch 125 and the transmission path on the second branch 135 is close to 1. There is no need to perform additional winding processing on the first branch 125 and the second branch 135. It can be ensured that the difference between the first delay of the initial control signal Control received by the first operation unit 111 and the second delay of the initial control signal Control received by the second operation unit 112 is less than the preset threshold.

[0080] It should be noted that Figure 4 is a combined functional block diagram of the signal processing unit, the first transmission unit, the first operation unit and the second operation unit in the wiring structure provided by an embodiment of the present disclosure. In order to illustrate the transmission path of the initial control signal Control in the signal processing unit 104, the first transmission unit 105, the first operation unit 111 and the second operation unit 112, the first transmission unit 105 illustrated in Figure 4 is only a simple functional block diagram, and Figure 4 does not limit the positional relationship between the signal processing unit 104, the first transmission unit 105, the first operation unit 111 and the second operation unit 112.

[0081] In some embodiments, the main path 115 and the first branch 125 together constitute a first transmission path, and the main path 115 and the second branch 135 together constitute a second transmission path; the first transmission path is used to transmit the initial control signal Control to the first operation unit 111, and the second transmission path is used to transmit the initial control signal Control to the second operation unit 112, and the ratio of the first length of the first transmission path to the second length of the second transmission path is 0.9 to 1.1.

[0082] It should be noted that the initial control signal Control transmitted by the first transmission path and the second transmission path is a signal processed by the signal processing unit 104. Based on the different internal circuit designs of the signal processing unit 104, the signals transmitted by the first transmission path and the second transmission path after being processed by the signal processing unit 104 will be different, but the signal finally transmitted to the first operation unit 111 and the second operation unit 112 via the first transmission unit 105 is the initial control signal Control after being jointly processed by the signal processing unit 104 and the first transmission unit 105.

[0083] It is worth noting that any of the main path 115, the first branch 125, and the second branch 135 may not be a transmission line extending along a fixed direction. Any of the main path 115, the first branch 125, and the second branch 135 may be a transmission line having a bending area or a transmission line spanning at least one metal layer. Based on this, the first transmission path formed by the main path 115 and the first branch 125 may not extend along a fixed direction, and the second transmission path formed by the main path 115 and the second branch 135 may not extend along a fixed direction. Therefore, designing the ratio of the first length of the first transmission path to the second length of the second transmission path to be 0.9 to 1.1 is beneficial to reducing the difference between the total length of the signal transmitted in the first transmission path and the total length transmitted in the second transmission path, thereby ensuring that the difference between the first delay of the initial control signal Control received by the first operation unit 111 and the second delay of the initial control signal Control received by the second operation unit 112 is less than a preset threshold.

[0084] It is understood that, in an optimal state, the ratio of the first length to the second length is controlled to be 1, that is, the total length of the signal transmitted in the first transmission path is consistent with the total length of the signal transmitted in the second transmission path, which helps to further reduce the difference between the first delay and the second delay, thereby improving the transmission performance of the first transmission unit 105. Taking into account the impact of the process of manufacturing the first transmission unit 105 in actual applications, the ratio of the first length of the first transmission path to the second length of the second transmission path is controlled to be 0.9 to 1.1, which helps to control the preset threshold to be no greater than 30 ps.

[0085] The specific structures of the signal processing unit 104 and the first transmission unit 105 include at least the following two situations:

[0086] In some embodiments, referring to FIG. 5 or FIG. 6 , the first transmission unit 105 may be located in the row decoding area 103 .

[0087] It is worth noting that the first transmission unit 105 being located in the row decoding area 103 means that the main wiring in the first transmission unit 105 is located in the row decoding area 103; in order to transmit the signal to the first operation unit 111, part of the wiring in the first transmission unit 105 needs to cross from the row decoding area 103 to the first column decoding area 101; in order to transmit the signal to the second operation unit 112, part of the wiring in the first transmission unit 105 needs to cross from the row decoding area 103 to the second column decoding area 102; in order to receive the initial control signal Control processed by the signal processing unit 104, part of the wiring in the first transmission unit 105 needs to cross from the signal processing unit 104 to the row decoding area 103.

[0088] In some embodiments, referring to Figure 5, Figure 6 or Figure 7, the signal processing unit 104 is configured to buffer the received initial control signal Control to obtain a first output signal Vout1, and output the first output signal Vout1; the first transmission unit 105 is configured to receive the first output signal Vout1 and transmit the first output signal Vout1 to the first operation unit 111 and the second operation unit 112 respectively.

[0089] Figure 5 is a schematic diagram of another top view of a wiring structure provided in one embodiment of the present disclosure; Figure 6 is a schematic diagram of yet another top view of a wiring structure provided in one embodiment of the present disclosure; and Figure 7 is a schematic diagram of yet another top view of a wiring structure provided in one embodiment of the present disclosure. Figures 5, 6, and 7 will be described in detail below.

[0090] In some embodiments, referring to FIG. 7 , the signal processing unit 104 includes a third buffer 114 , a fourth buffer 124 , and a fifth buffer 134 .

[0091] The third buffer 114 is configured to receive and buffer the initial control signal Control to generate a first output signal Vout1. It is worth noting that buffering the initial control signal Control by the third buffer 114 helps reduce the distortion rate of the initial control signal Control and increase the drive capability of the initial control signal Control. In some embodiments, the third buffer 114 may include M pairs of inverters connected in series, where M is a positive integer. A pair of inverters connected in series includes two inverters connected in series. The parts of the third buffer 114 that are identical or similar to the first buffer 131 are not further described here.

[0092] It should be noted that the waveform of the first output signal Vout1 is the same as the waveform of the initial control signal Control. The first output signal Vout1 is equivalent to the initial control signal Control.

[0093] The fourth buffer 124 is configured to receive the first enable signal FAR_EN and buffer it to reduce the distortion of the first enable signal FAR_EN output by the signal processing unit 104 and increase the drive capability of the first enable signal FAR_EN output by the signal processing unit 104. The fifth buffer 134 is configured to receive the second enable signal NEAR_EN and buffer it to reduce the distortion of the second enable signal NEAR_EN output by the signal processing unit 104 and increase the drive capability of the second enable signal NEAR_EN output by the signal processing unit 104. It should be noted that the parts of the fourth buffer 124 and the fifth buffer 134 that are identical or similar to the first buffer 131 are not further described here.

[0094] In some embodiments, referring to FIG. 5 , FIG. 6 or FIG. 7 , the first transmission unit 105 includes a main circuit 115 , a first branch circuit 125 and a second branch circuit 135 , and the main circuit 115 , the first branch circuit 125 and the second branch circuit 135 are located in the same metal layer.

[0095] It should be noted that Figures 5 and 6 illustrate two different arrangements of the main path 115, the first branch 125, and the second branch 135. In Figure 5, a portion of the second branch 135 bends when transitioning from the main path 115 to the first branch 125 and the second branch 135. In Figure 6, a portion of the main path 115 bends when transitioning from the main path 115 to the first branch 125 and the second branch 135. In practical applications, there is no restriction on the specific arrangement of the main path 115, the first branch 125, and the second branch 135. It is sufficient that the ratio of the first length of the first transmission path formed by the main path 115 and the first branch 125 to the second length of the second transmission path formed by the main path 115 and the second branch 135 is close to 1. For example, the ratio of the first length to the second length is 0.9 to 1.1. In addition, Figure 7 illustrates a specific structure of the signal processing unit 104 in Figure 5.

[0096] The wiring structure provided by an embodiment of the present disclosure is described in detail below using the first transmission unit 105 shown in FIG. 7 .

[0097] In some embodiments, with reference to Figures 7 and 8, Figure 8 is a schematic diagram of the top structure of the first transmission unit 105 in the wiring structure shown in Figure 7, the main path 115 and the first branch 125 constitute a first transmission line 165 that runs through the row decoding area 103, and the second branch 135 is a second transmission line 175 that is bent in a partial area.

[0098] It is noteworthy that the main line 115 and the first branch line 125 are on the same conductive layer in the wiring structure, serving as the first transmission line 165. The second branch line 135 itself serves as the second transmission line 175, which is in contact with the non-end region of the first transmission line 165. Thus, compared to existing wiring structures in which two non-contacting wiring lines are used, one of which is routed independently, the first transmission unit 105 occupies fewer lanes in the row decoding area 103, only two. This further reduces the lane resources occupied by the first transmission unit 105 in the row decoding area 103, thereby further reducing the layout space occupied by the entire wiring structure.

[0099] In some embodiments, referring to FIG. 8 , the unbent portion of the second transmission line 175 is parallel to and spaced from the first transmission line 165 , and the bent portion of the second transmission line 175 is electrically connected to the intersection of the main path 115 and the second transmission line 175 .

[0100] In some embodiments, referring to Figures 8 and 9a , the main path 115 and the first branch 125 together constitute a first transmission path 145. Referring to Figures 8 and 9b , the main path 115 and the second branch 135 together constitute a second transmission path 155. The initial control signal Control, i.e., the first output signal Vout1 (see Figure 7 ), processed by the signal processing unit 104 is transmitted to the first computing unit 111 (see Figure 7 ) via the first transmission path 145 and is then transmitted to the second computing unit 112 (see Figure 7 ) via the second transmission path 155.

[0101] Among them, Figure 9a is a top-down structural schematic diagram of the first transmission path 145 jointly constituted by the main path 115 and the first branch 125 in the first transmission unit 105 shown in Figure 8, and Figure 9b is a top-down structural schematic diagram of the second transmission path 155 jointly constituted by the main path 115 and the second branch 135 in the first transmission unit 105 shown in Figure 8.

[0102] In some embodiments, referring to Figure 10, the wiring structure may further include: a first shielding line 116, located on a side of the first transmission line 165 away from the second transmission line 175; a second shielding line 126, located between the first transmission line 165 and the second transmission line 175; and a third shielding line 136, located on a side of the second transmission line 175 away from the first transmission line 165.

[0103] 10 is a schematic top view of a wiring structure in which shielding wires are added to the structure shown in FIG. 7 . The shielding wires described here include a first shielding wire 116 , a second shielding wire 126 and a third shielding wire 136 .

[0104] It can be understood that the addition of the first shielding line 116 helps reduce electrical interference from other wiring located in the row decoding area 103 and on the same metal layer as the first transmission line 165 on the first transmission line 165. The addition of the second shielding line 126 helps reduce electrical interference from the first transmission line 165 and the second transmission line 175 on each other. The addition of the third shielding line 136 helps reduce electrical interference from other wiring located in the row decoding area 103 and on the same metal layer as the first transmission line 165 on the second transmission line 175. In this way, the provision of the first shielding line 116, the second shielding line 126, and the third shielding line 136 allows the first transmission line 165 and the second transmission line 175 to be surrounded by shielding lines, thereby reducing electrical interference from the first transmission line 165 and the second transmission line 175, thereby improving the transmission accuracy of the first transmission unit 105.

[0105] It is worth noting that the combination of the first shielded wire 116, the second shielded wire 126, and the third shielded wire 136 is beneficial for reducing the distortion rate of the first output signal Vout1 when transmitted in the first transmission line 165, and reducing the distortion rate of the first output signal Vout1 when transmitted in the second transmission line 175, thereby enabling the first transmission unit 105 to have a higher transmission accuracy. Furthermore, it is beneficial for improving the accuracy of the first output signal Vout1 received by the first operation unit 111, thereby improving the probability that the first control signal Control1 generated by the first operation unit 111 based on the first output signal Vout1 is accurately recognized by the first column decoder, and improving the accuracy of the first output signal Vout1 received by the second operation unit 112, thereby improving the probability that the second control signal Control2 generated by the second operation unit 112 based on the first output signal Vout1 is accurately recognized by the second column decoder.

[0106] Furthermore, since the first output signal Vout1 requiring shielding is transmitted only on the first transmission line 165 and the second transmission line 175, shielding wires need only be provided around the first and second transmission lines 165, 175, i.e., the two signal transmission lines, to meet this requirement. Therefore, only three shielding wires are required: the first shielding wire 116, the second shielding wire 126, and the third shielding wire 136, so that both the first operation unit 111 and the second operation unit 112 can receive the first output signal Vout1 with high accuracy. Compared to current wiring structures in which two non-contacting wiring lines are used and one of the wiring lines is individually routed, fewer shielding wires are required for the first and second transmission lines 165, 175, which intersect at a point. This helps further reduce the wiring resources occupied by the wiring structure in the row decoding area 103, thereby further reducing the layout space occupied by the entire wiring structure.

[0107] In some embodiments, the first shielding line 116 , the second shielding line 126 , and the third shielding line 136 are all grounded to achieve electromagnetic shielding, thereby isolating the electrical interference between the first transmission line 165 and the second transmission line 175 , and isolating the electrical interference of other wiring on the first transmission line 165 and the second transmission line 175 .

[0108] In some embodiments, referring to FIG10 , along the first direction X, the length of the first shielding line 116 may be equal to the length of the row decoding area 103, which helps ensure that the first transmission line 165 located in the row decoding area 103 as a whole is not subject to electrical interference from other external wiring. Along the first direction X, the length of the second shielding line 126 may be slightly less than the length of the second transmission line 175 located in the row decoding area 103, which helps ensure that most areas directly opposite the second transmission line 175 and the first transmission line 165 in the second direction Y are equipped with the second shielding line 126, so as to improve the shielding effect of the second shielding line 126 on the electrical interference between the first transmission line 165 and the second transmission line 175. Along the first direction X, the length of the third shielding line 136 may be slightly greater than the length of the second transmission line 175 located in the row decoding area 103, which helps ensure that the first transmission line 165 located in the row decoding area 103 as a whole is not subject to electrical interference from other external wiring, such as the second transmission unit 107.

[0109] It is worth noting that the first shielding line 116 , the second shielding line 126 , the third shielding line 136 , the first transmission line 165 , and the second transmission line 175 may be located in the same metal layer.

[0110] In practical applications, the lengths of the first shielding wire 116 , the second shielding wire 126 , and the third shielding wire 136 in the first direction X can be adjusted according to actual needs.

[0111] In some embodiments, referring to Figures 2, 3, 5 to 7 and 10, the wiring structure may further include: a second transmission unit 107, electrically connected to the signal processing unit 104 and the first operation unit 111, configured to transmit the first enable signal FAR_EN to the first operation unit 111; a third transmission unit 108, electrically connected to the signal processing unit 104 and the second operation unit 112, configured to transmit the second enable signal NEAR_EN to the second operation unit 112.

[0112] In some cases, because the signal processing unit 104 is located adjacent to the second column decoding region 102 and away from the first column decoding region 101, the first enable signal FAR_EN needs to be transmitted to the first column decoding region 101, which is farther away from the signal processing unit 104. As a result, the second transmission unit 107 for transmitting the first enable signal FAR_EN needs to pass through the row decoding region 103 along the first direction X. In contrast, the third transmission unit 108 can transmit the second enable signal NEAR_EN to the second column decoding region 102 without passing through the row decoding region 103.

[0113] In some embodiments, referring to Figure 11, Figure 11 is another top-view structural schematic diagram of the wiring structure provided by an embodiment of the present disclosure, the initial control signal Control includes N sub-control signals, the sub-control signals correspond one-to-one to the first transmission units 105, the N first transmission units 105 are arranged at intervals along the second direction Y, the second direction Y intersects with the first direction X, and the N first transmission units 105 correspond to the same second transmission unit 107 and the same third transmission unit 108, and N is a positive integer.

[0114] It is worth noting that different sub-control signals are not simultaneously active. Therefore, different sub-control signals can be processed by the signal processing unit 104 and the first transmission unit 105 and then transmitted to the same first operation unit 111 and second operation unit 112. Furthermore, different sub-control signals received by the first operation unit 111 can share the same first enable signal FAR_EN, and different sub-control signals received by the second operation unit 112 can share the same second enable signal NEAR_EN. Furthermore, in the signal processing unit 104, the sub-control signals correspond one-to-one to the third buffer 114.

[0115] It is understandable that the signal processing unit 104 performs only initial processing, i.e., buffering, on the received initial control signal Control. The logic operation between the initial control signal Control and the first enable signal FAR_EN is designed for the first operation unit 111 in the first column decoding area 101, and the logic operation between the initial control signal Control and the second enable signal NEAR_EN is designed for the second operation unit 112 in the second column decoding area 102. Therefore, when the wiring structure requires designing transmission paths for N sub-control signals, only N first transmission units 105 need to be designed, corresponding one-to-one to the N sub-control signals. The number of second transmission units 107 and third transmission units 108 remains constant at one. This way, a single first transmission unit 105 only occupies two lanes in the row decoding area 103, and N first transmission units 105 together only occupy 2N lanes in the row decoding area 103. Furthermore, only one lane in the row decoding area 103 is required for the second transmission unit 107. In other words, by reducing the number of lanes occupied by a single first transmission unit 105 in row decoding area 103 and reducing the number of second transmission units 107, the total number of wires in the wiring structure can be further reduced, thereby further reducing the lane resources occupied by the wiring structure in row decoding area 103, thereby further reducing the layout space occupied by the entire wiring structure. It should be noted that the wiring in the wiring structure includes first transmission lines 165, second transmission lines 175, and second transmission units 107.

[0116] It is worth noting that Figure 11 only illustrates two first transmission units 105 arranged at intervals along the second direction Y. In actual applications, the first transmission units 105 can be designed to be consistent with the number of sub-control signals based on the actual number of sub-control signals. For example, the number of first transmission units 105 arranged at intervals along the second direction Y can be designed to be 3, 4 or 5, etc.

[0117] In some embodiments, the N seed control signals included in the initial control signal Control may be a write enable signal WrEn, a read enable signal RdEn, or a read enable complementary signal RdEnN.

[0118] In some embodiments, referring to FIG. 11 , the first transmission units 105, the first shielding lines 116, and the second shielding lines 126 correspond one to one, with one first shielding line 116 located between two adjacent first transmission units 105 along the second direction Y. In other words, only two shielding lines, the first shielding line 116 and the second shielding line 126, need to be duplicated due to the different sub-control signals being transmitted. Two adjacent first transmission units 105 along the second direction Y can share one first shielding line 116, which helps reduce the number of first shielding lines 116 required, thereby further reducing the lane resources occupied by the overall wiring structure in the row decoding area 103.

[0119] In some embodiments, with continued reference to FIG. 11 , a third shielding line 136 is provided between a first transmission unit 105 closest to a second transmission unit 107 along the second direction Y and the second transmission unit 107. It will be appreciated that, regardless of the number of first transmission units 105 spaced apart along the second direction Y, they all share one second transmission unit 107, meaning that only one third shielding line 136 is required. This reduces the number of second transmission units 107, thereby further reducing the lane resources occupied by the overall wiring structure in the row decoding area 103.

[0120] It can be understood that in order to transmit N seed control signals and avoid distortion of the N seed control signals during transmission to the first operation unit 111 and the second operation unit 112, based on the design of the first transmission unit 105 in Figure 11, the design of the first operation unit 111 in the first column decoding area 101, and the design of the second operation unit 112 in the second column decoding area 102, it is beneficial to reduce the total number of wirings required to be designed in the row decoding area 103 to (4N+1+1) wirings, so as to further reduce the line resources occupied by the entire wiring structure in the row decoding area 103.

[0121] It is worth noting that in the (4N+1+1) wirings, “4” refers to the first transmission line 165 , the second transmission line 175 , the first shielding line 116 and the second shielding line 126 , one “1” refers to the third shielding line 136 , and another “1” refers to the second transmission unit 107 .

[0122] It should be noted that, to distinguish between the main circuit 115, the first branch 125, and the second branch 135, Figures 5 to 8, 10, and 11 all use a thicker solid line to indicate the main circuit 115, a dashed line to indicate the first branch 125, and a thinner solid line to indicate the second branch 135. Furthermore, to distinguish between the main circuit 115, the first branch 125, the second branch 135, and the shielded wires, Figures 10 and 11 all use dashed lines to indicate the shielded wires, which include the first shielded wire 116, the second shielded wire 126, and the third shielded wire 136. Furthermore, to distinguish between the first shielded wire 116, the second shielded wire 126, and the third shielded wire 136, Figures 10 and 11 use the dashed line with the longest length in the first direction X to indicate the first shielded wire 116, the dashed line with the shortest length in the first direction X to indicate the second shielded wire 126, and the dashed line with the intermediate length in the first direction X to indicate the third shielded wire 136.

[0123] The embodiments shown in Figures 5 to 11 above all take the first transmission unit 105 being located in the row decoding area 103 as an example. In other embodiments, only some wirings in the first transmission unit may be designed to be located in the row decoding area, and other wirings may be designed to be located in the storage array area.

[0124] The following describes in detail an embodiment in which the first transmission unit is partially located in the row decoding area and partially located in the storage array area in conjunction with the accompanying drawings. It should be noted that parts that are identical or corresponding to the previous embodiment are not repeated here.

[0125] In other embodiments, referring to Figure 12, Figure 12 is another top-view structural schematic diagram of the wiring structure provided by an embodiment of the present disclosure. On the basis that the wiring structure includes a first column decoding area 201, a second column decoding area 202, a row decoding area 203, a signal processing unit 204 and a first transmission unit 205, and the first column decoding area 201 has a first operation unit 211, the second column decoding area 202 has a second operation unit 212, and the first transmission unit 205 includes a main path 215, a first branch 225 and a second branch 235, the wiring structure may further include a storage array area 209, and the storage array area 209 and the row decoding area 203 are adjacent along the second direction Y, and are located between the first column decoding area 201 and the second column decoding area 202.

[0126] In some cases, with continued reference to FIG12 , the storage array area 209 may include a first storage array area 219 and a second storage array area 229, with the row decoding area 203 located between the first storage array area 219 and the second storage array area 229. It should be noted that FIG12 also uses a U piece to indicate the first storage array area 219, and a V piece to indicate the second storage array area 229.

[0127] Continuing with reference to FIG12 , the main path 215 may include a first main path 285 located in the storage array area 209 and a second main path 295 extending from the storage array area 209 to the row decoding area 203 . The first main path 285 is electrically connected to the signal processing unit 204 , and the second main path 295 is electrically connected to the first branch path 225 and the second branch path 235 , respectively.

[0128] It can be understood that the main part of the main path 215, namely the first main path 285, is not located in the row decoding area 203, so that the main path 215 does not occupy too many lines in the row decoding area 203, thereby helping to reduce the line resources occupied by the wiring structure in the row decoding area 203.

[0129] In some embodiments, referring to FIG. 13 , which is a top-down schematic diagram of another wiring structure provided in an embodiment of the present disclosure, the signal processing unit 204 includes a first inverter 244 configured to receive an initial control signal Control, invert the initial control signal Control to obtain a second output signal Vout2, and output the second output signal Vout2. It will be appreciated that, unlike the previous embodiment, the device in the signal processing unit 204 that receives and processes the initial control signal Control is not a third buffer, but an odd number of first inverters 244. Therefore, the waveform of the second output signal Vout2 is opposite to that of the initial control signal Control.

[0130] It should be noted that the signal processing unit 204 further includes a fourth buffer 224 and a fifth buffer 234. The fourth buffer 224 and the fifth buffer 234 are similar to the fourth buffer and the fifth buffer in the aforementioned embodiment and are not described in detail here. In addition, the first operation unit 211 and the second operation unit 212 are also similar to the first operation unit and the second operation unit in the aforementioned embodiment and are not described in detail here.

[0131] Continuing with reference to Figure 13, the first main path 285 is configured to receive and transmit the second output signal Vout2 to the second main path 295; the second main path 295 has a second inverter 254, which is configured to receive the second output signal Vout2 and invert the second output signal Vout2 to obtain a third output signal Vout3, and output the third output signal Vout3; the first branch 225 is configured to receive and transmit the third output signal Vout3 to the first operation unit 211; the second branch 235 is configured to receive and transmit the third output signal Vout3 to the second operation unit 212.

[0132] It is worth noting that the waveform of the third output signal Vout3 can be the same as the waveform of the initial control signal Control, then the third output signal Vout3 is equivalent to the initial control signal Control, which is conducive to ensuring that the first operation unit 211 and the second operation unit 212 receive the initial control signal Control.

[0133] Furthermore, since the first main path 285 is not located in the row decoding area 203 and needs to extend from the storage array area 209 to the row decoding area 203 via the second main path 295, the signal needs to be transferred from the storage array area 209 to the row decoding area 203 during transmission on the main path 215, resulting in a longer path for signal transmission on the main path 215. Based on this, a first inverter 244 is designed in the signal processing unit 204 to perform a first inversion on the initial control signal Control, and then a second inverter 254 is provided on the main path 215 to perform a second inversion on the initial control signal Control. This ensures that the interference effect on the second output signal Vout2 during transmission will not further affect the third output signal Vout3 after being inverted by the second inverter 254. In other words, the influences on the second output signal Vout2 and the third output signal Vout3 during transmission will not affect each other. In this way, during the transmission of the initial control signal Control from the signal processing unit 204 to the first operation unit 211 and the second operation unit 212, the interference caused to the signal on the main path 215 and the interference caused to the signal on the first branch 225 will not accumulate. The interference caused to the signal on the main path 215 and the interference caused to the signal on the second branch 235 will not accumulate. This is conducive to improving the accuracy of the initial control signal Control transmission by the signal processing unit 204 and the first transmission unit 205, that is, improving the transmission performance of the wiring structure.

[0134] In some cases, in combination with reference to Figures 13 and 14, Figure 14 is a schematic diagram of a combined top-down structure of the first transmission unit, the first storage array area, the row decoding area, and the second storage array area in the wiring structure shown in Figure 13. The first main path 285 is located in the metal layer M4. Due to the limited layout space in the row decoding area 203, the second inverter 254 is designed to be arranged in the metal layer M2 in the row decoding area 203, and the first branch 225 and the second branch 235 are located in the metal layer M4 in the row decoding area 203 to fully utilize the layout space in the row decoding area 203.

[0135] Based on this, the second main path 295 is designed to include a first part 295a, a second part 295b and a third part 295c, as well as a first conductive column (not shown in the figure) whose two ends respectively contact the first main path 285 and the first part 295a, a second conductive column (not shown in the figure) whose two ends respectively contact the first part 295a and the second inverter 254, a third conductive column (not shown in the figure) whose two ends respectively contact the second inverter 254 and the second part 295b, a fourth conductive column (not shown in the figure) whose two ends respectively contact the second part 295b and the third part 295c, and a fifth conductive column (not shown in the figure) whose two ends respectively contact the third part 295c and the first branch 225.

[0136] The first portion 295a is located in the metal layer M3. On the one hand, the second output signal Vout2 on the first main path 285 located in the metal layer M4 is transferred from the metal layer M4 to the metal layer M3 through the first conductive pillar. On the other hand, the second output signal Vout2 on the first portion 295a located in the metal layer M3 is transferred from the metal layer M3 to the metal layer M2 through the second conductive pillar to be transferred to the second inverter 254. The second portion 295b is located in the metal layer M2. On the one hand, the second output signal Vout2 on the second main path 285 located in the metal layer M4 is transferred from the metal layer M3 to the metal layer M2 through the third conductive pillar. 4 is transmitted to the second portion 295b. On the other hand, the third output signal Vout3 on the second portion 295b located in the metal layer M2 is transmitted from the metal layer M2 to the metal layer M3 via the fourth conductive pillar to be transmitted to the third portion 295c. The third portion 295c is located in the metal layer M3. The third output signal Vout3 on the third portion 295c located in the metal layer M3 is transmitted from the metal layer M3 to the metal layer M4 via the fifth conductive pillar to be transmitted to the first branch 225 and the second branch 235, respectively.

[0137] It is worth noting that, because other important electrical components are also disposed in the central region of the row decoding region 203 along the first direction X, the second inverter 254 is disposed in the metal layer M2 in the row decoding region 203, and the second inverter 254 is located in an area near the central region of the row decoding region 203. Based on this, to ensure that the ratio of the first length of the first transmission path to the second length of the second transmission path is close to 1, the third portion 295c is designed to be located in the central region of the row decoding region 203 along the first direction X, which further ensures that the transmission paths of the signals on the first branch 225 and the second branch 235 are consistent.

[0138] It should be noted that in order to clearly illustrate the positional relationship between the first main road 285, the second main road 295, the first branch road 225 and the second branch road 235, Figure 14 uses a perspective drawing method for the first main road 285, the first branch road 225 and the second branch road 235. Moreover, the same drawing method is used for the structures located in the same metal layer, and the metal layer where each structure is located is marked separately.

[0139] In some embodiments, referring to FIG15 , FIG15 is a schematic diagram of the top-down structure of the first transmission unit in the wiring structure shown in FIG12 , the first branch 225 and the second branch 235 are located on the same metal layer, and the first branch 225 and the second branch 235 constitute a third transmission line 239 that runs through the row decoding area 203 (refer to FIG12 ).

[0140] It is noteworthy that the first branch 225 and the second branch 235 are on the same conductive layer in the wiring structure, serving as the third transmission line 239. Thus, compared to conventional wiring structures in which two non-contacting wiring lines are used, one of which is routed independently, the design of a single third transmission line 239 in the first transmission unit 205 is located in the row decoding area 203, while the majority of the main line 215 is located in the memory array area 209. This further reduces the number of lanes occupied by the wiring structure in the row decoding area 203. Specifically, the single third transmission line 239 further reduces the number of lanes occupied by the first transmission unit 205 in the row decoding area 203, thereby further reducing the overall layout space occupied by the wiring structure.

[0141] In some embodiments, the first main path 285 in the main path 215 may be located in the same metal layer as the first branch path 225 and the second branch path 235 , but the first main path 285 is located in the memory array region 209 .

[0142] In some embodiments, referring to FIG. 15 , the first main path 285 and the third transmission line 239 are arranged in parallel and spaced apart.

[0143] In some embodiments, referring to FIG16 , FIG16 is a schematic top view of a wiring structure in which a shielding line is added to the structure shown in FIG13 . The wiring structure may further include: a fourth shielding line 216 and a fifth shielding line 226 , which are respectively located on opposite sides of the third transmission line 239 (refer to FIG15 ) along the second direction Y.

[0144] 16 is a schematic top view of a wiring structure in which shielding wires are added to the wiring structure shown in FIG. 13 . The shielding wires described here include a fourth shielding wire 216 and a fifth shielding wire 226 .

[0145] It can be understood that the addition of the fourth shielding line 216 and the fifth shielding line 226 is helpful in reducing the electrical interference of other wiring located in the row decoding area 203 and on the same metal layer as the third transmission line 239 to the third transmission line 239. In other words, by setting the fourth shielding line 216 and the fifth shielding line 226, most areas of the third transmission line 239 are surrounded by the shielding lines, so as to reduce the electrical interference to the third transmission line 239, thereby helping to improve the transmission accuracy of the first transmission unit 205.

[0146] It is worth noting that the combination of the fourth shielded line 216 and the fifth shielded line 226 helps reduce the distortion rate of the third output signal Vout3 when it is transmitted in the third transmission line 239, thereby ensuring that the first transmission unit 205 has a higher transmission accuracy. Furthermore, it helps improve the accuracy of the third output signal Vout3 received by the first operation unit 211, thereby improving the probability that the first control signal Control1 generated by the first operation unit 211 based on the third output signal Vout3 is accurately recognized by the first column decoder, and helps improve the accuracy of the third output signal Vout3 received by the second operation unit 212, thereby improving the probability that the second control signal Control2 generated by the second operation unit 212 based on the third output signal Vout3 is accurately recognized by the second column decoder.

[0147] Furthermore, since the third output signal Vout3 requiring shielding is only transmitted on the third transmission line 239, shielding wires need only be provided around the third transmission line 239, i.e., a single signal transmission line. Therefore, only two shielding wires, namely, the fourth shielding wire 216 and the fifth shielding wire 226, are required to enable both the first operation unit 111 and the second operation unit 212 to receive the third output signal Vout3 with high accuracy. Compared to current wiring structures that use two non-contacting wires and route one of the wires independently, fewer shielding wires are required for the third transmission line 239, further reducing the wiring resources occupied by the wiring structure in the row decoding area 203, thereby further reducing the overall layout space occupied by the wiring structure.

[0148] In some embodiments, the fourth shielding line 216 and the fifth shielding line 226 are both grounded to achieve electromagnetic shielding, thereby isolating the third transmission line 239 from electrical interference from other wiring.

[0149] In some embodiments, referring to Figure 16, along the first direction X, the length of the fourth shielding line 216 and the length of the fifth shielding line 226 can be equal to the length of the row decoding area 203, which is beneficial to ensure that the third transmission line 239 located in the row decoding area 203 as a whole will not be subject to electrical interference from other external wiring.

[0150] It is worth noting that the fourth shielding line 216 , the fifth shielding line 226 and the third transmission line 239 may be located in the same metal layer.

[0151] In practical applications, the lengths of the fourth shielding wire 216 and the fifth shielding wire 226 in the first direction X can be adjusted according to actual needs.

[0152] In some embodiments, referring to Figures 12, 13 and 16, the wiring structure may further include: a second transmission unit 207, electrically connected to the signal processing unit 204 and the first operation unit 211, configured to transmit the first enable signal FAR_EN to the first operation unit 211; a third transmission unit 208, electrically connected to the signal processing unit 204 and the second operation unit 212, configured to transmit the second enable signal NEAR_EN to the second operation unit 212.

[0153] It should be noted that the second transmission unit 207 and the third transmission unit 208 are similar to the second transmission unit and the third transmission unit in the aforementioned embodiment, and are not described in detail here.

[0154] In some embodiments, with reference to Figures 16 and 17, Figure 17 is another top-down structural schematic diagram of the first transmission unit in the wiring structure provided by an embodiment of the present disclosure, the initial control signal Control includes N sub-control signals, the sub-control signals correspond one-to-one to the first transmission units 205, the N third transmission lines 239 in the N first transmission units 205 are arranged at intervals along the second direction Y, and the N first transmission units 205 correspond to the same second transmission unit 207 and the same third transmission unit 208, where N is a positive integer.

[0155] It is worth noting that different sub-control signals are not simultaneously active. Therefore, different sub-control signals can be processed by the signal processing unit 204 and the first transmission unit 205 and then transmitted to the same first operation unit 211 and second operation unit 212. Furthermore, the different sub-control signals received by the first operation unit 211 can share the same first enable signal FAR_EN, and the different sub-control signals received by the second operation unit 212 can share the same second enable signal NEAR_EN. Furthermore, in the signal processing unit 204, the sub-control signals correspond one-to-one to the first inverters 244.

[0156] It can be understood that the signal processing unit 204 performs a first inversion on the received initial control signal Control, and the first transmission unit 205 performs a second inversion on the second output signal Vout2 output by the signal processing unit 204 to output a third output signal Vout3 having the same waveform as the initial control signal Control. The third output signal Vout3 is equivalent to the initial control signal Control. The logic operation processing of the initial control signal Control and the first enable signal FAR_EN is designed in the first operation unit 211 in the first column decoding area 201, and the logic operation processing of the initial control signal Control and the second enable signal NEAR_EN is designed in the second operation unit 212 in the second column decoding area 202. Based on this, when the wiring structure needs to design transmission paths for N seed control signals, only N first transmission units 205 need to be designed, corresponding one-to-one to the N seed control signals. The number of second transmission units 207 and third transmission units 208 is always one. In this way, on the one hand, a single first transmission unit 205 occupies only one lane in the row decoding area 103, and N first transmission units 205 occupy only N lanes in the row decoding area 203. On the other hand, only one lane needs to be designed in the row decoding area 203 for the second transmission unit 207. In other words, by reducing the number of lanes occupied by a single first transmission unit 205 in the row decoding area 203 and reducing the number of second transmission units 207, the total number of wiring lines in the wiring structure can be further reduced, further reducing the lane resources occupied by the wiring structure in the row decoding area 203, thereby further reducing the layout space occupied by the entire wiring structure. It should be noted that the wiring in the wiring structure includes the third transmission line 239 and the second transmission unit 207.

[0157] It is worth noting that Figure 17 only illustrates two first transmission units 205 arranged at intervals along the second direction Y. In actual applications, the first transmission units 205 can be designed to be consistent with the number of sub-control signals based on the actual number of sub-control signals. For example, the number of first transmission units 205 arranged at intervals along the second direction Y can be designed to be 3, 4 or 5, etc.

[0158] In some embodiments, with reference to FIG16 and FIG17 , the fourth shielding lines 216 correspond one-to-one with the third transmission lines 239, with one fourth shielding line 216 located between two adjacent third transmission lines 239 along the second direction Y. In other words, only one shielding line, namely the fourth shielding line 216, needs to be repeatedly provided due to different sub-control signals being transmitted. Two adjacent first transmission units 205 along the second direction Y can share one fourth shielding line 216, which helps reduce the number of fourth shielding lines 216 provided, thereby further reducing the line resources occupied by the overall wiring structure in the row decoding area 203.

[0159] In some embodiments, a fifth shielding line 226 is provided between a third transmission line 239 closest to the second transmission unit 207 along the second direction Y and the second transmission unit 207. It is understood that, regardless of the number of first transmission units 205 arranged at intervals along the second direction Y, they all share one second transmission unit 207, meaning that only one fifth shielding line 226 is required. This reduces the number of second transmission units 207, thereby further reducing the line resources occupied by the overall wiring structure in the row decoding area 203.

[0160] It can be understood that in order to transmit N seed control signals and avoid distortion of the N seed control signals during transmission to the first operation unit 211 and the second operation unit 212, based on the design of the first transmission unit 205 in Figure 16, the design of the first operation unit 211 in the first column decoding area 201, and the design of the second operation unit 212 in the second column decoding area 202, it is beneficial to reduce the total number of wirings required to be designed in the row decoding area 203 to (2N+1+1) wirings, so as to further reduce the line resources occupied by the entire wiring structure in the row decoding area 203.

[0161] It is worth noting that, among the (2N+1+1) wirings, “2” refers to the third transmission line 239 and the fourth shielding line 216 , one “1” refers to the fifth shielding line 226 , and another “1” refers to the second transmission unit 207 .

[0162] It should be noted that, in order to facilitate description and clearly illustrate the wiring structure, Figures 2 to 17 are all schematic diagrams of partial structures of the wiring structure.

[0163] In summary, taking the illustration in FIG. 2 as an example, the signal processing unit 104 and the first transmission unit 105 cooperate to transmit the initial control signal Control received by the signal processing unit 104 to the first operation unit 111 and the second operation unit 112, respectively. During this transmission process, a new first transmission unit 105 is designed. The first transmission unit 105 ensures that the difference between the first delay of the initial control signal Control received by the first operation unit 111 and the second delay of the initial control signal Control received by the second operation unit 112 is less than a preset threshold, thereby improving the transmission performance of the wiring structure. Furthermore, in the new wiring structure, the signal processing unit 104 is no longer solely responsible for processing the initial control signal Control to generate the control signal that prompts the first column decoding area 101 and the second column decoding area 102 to perform subsequent operations. Instead, the first control signal Control1 for prompting the first column decoding area 101 to perform subsequent operations is generated in the first column decoding area 101, and the second control signal Control2 for prompting the second column decoding area 102 to perform subsequent operations is generated in the second column decoding area 102. In this way, the first transmission unit 105 only needs to transmit one signal: the initial control signal Control received and processed by the signal processing unit 104, to the first operation unit 111 and the second operation unit 112. This helps reduce the layout space required by the first transmission unit 105, thereby reducing the layout space occupied by the wiring structure. Furthermore, it helps simplify the processing logic of the initial control signal Control by the signal processing unit 104, thereby reducing the complexity of the logic circuits in the signal processing unit 104, reducing the layout space required by the signal processing unit 104, and further reducing the layout space occupied by the wiring structure.

[0164] Figure 18 is a schematic diagram of the structure of a memory according to an embodiment of the present disclosure. Referring to Figure 18 , another embodiment of the present disclosure also provides a memory 1 comprising: a wiring structure 2 as provided in an embodiment of the present disclosure. This facilitates improving the transmission performance of the wiring structure, thereby enhancing the electrical performance of the memory.

[0165] In some embodiments, the memory may be a DDR memory, such as a DDR4 memory, a DDR5 memory, a DDR6 memory, a LPDDR4 memory, a LPDDR5 memory, or a LPDDR6 memory.

[0166] Those skilled in the art will appreciate that the above-described embodiments are specific examples for implementing the present disclosure, and in actual applications, various changes may be made to them in form and detail without departing from the spirit and scope of the embodiments of the present disclosure. Any person skilled in the art may make various changes and modifications without departing from the spirit and scope of the embodiments of the present disclosure. Therefore, the scope of protection of the embodiments of the present disclosure shall be based on the scope defined in the claims.

Claims

1. A wiring structure of a memory, characterized in that, Including: A first column decoding region (101) and a second column decoding region (102) arranged at intervals in a first direction (X). In the first column decoding region (101), there is a first operation unit (111), configured to receive an initial control signal (Control) and a first enable signal (FAR_EN) and generate a first control signal (Control1); in the second column decoding region (102), there is a second operation unit (112), configured to receive the initial control signal (Control) and a second enable signal (NEAR_EN) and generate a second control signal (Control2). A row decoding region (103) located between the first column decoding region (101) and the second column decoding region (102). A signal processing unit (104) located on a side adjacent to the second column decoding region (102) and far from the first column decoding region (101), configured to receive the initial control signal (Control), the first enable signal (FAR_EN), and the second enable signal (NEAR_EN), and process the initial control signal (Control), the first enable signal (FAR_EN), and the second enable signal (NEAR_EN) respectively. A first transmission unit (105), and the first transmission unit (105) and the signal processing unit (104) are jointly configured to transmit the initial control signal (Control) to the first operation unit (111) and the second operation unit (112) respectively, and make the difference between a first delay of the initial control signal (Control) received by the first operation unit (111) and a second delay of the initial control signal (Control) received by the second operation unit (112) less than a preset threshold.

2. The wiring structure according to claim 1, wherein The first transmission unit (105) includes a main path (115), a first branch (125), and a second branch (135). Wherein, one end of the main path (115) is electrically connected to the signal processing unit (104), the other end of the main path (115) is electrically connected to the first branch (125) and the second branch (135) respectively, the other end of the first branch (125) is electrically connected to the first operation unit (111), and the other end of the second branch (135) is electrically connected to the second operation unit (112).

3. The wiring structure according to claim 2, characterized in that, The main path (115) and the first branch (125) jointly form a first transmission path, and the main path (115) and the second branch (135) jointly form a second transmission path. The first transmission path is used to transmit the initial control signal (Control) to the first operation unit (111), the second transmission path is used to transmit the initial control signal (Control) to the second operation unit (112), and the ratio of a first length of the first transmission path to a second length of the second transmission path is 0.9 - 1.

1.

4. The wiring structure according to claim 2 or 3, characterized in that The first transmission unit (105) is located in the row decoding area (103).

5. The wiring structure according to claim 4, characterized in that, The signal processing unit (104) is configured to buffer the received initial control signal (Control) to obtain and output a first output signal (Vout1); The first transmission unit (105) is configured to receive the first output signal (Vout1) and transmit the first output signal (Vout1) to the first arithmetic unit (111) and the second arithmetic unit (112) respectively.

6. The wiring structure according to claim 4, wherein, The main path (115), the first branch path (125), and the second branch path (135) are located on the same metal layer, and the main path (115) and the first branch path (125) form a first transmission line (165) that penetrates the row decoding area (103), and the second branch path (135) is a second transmission line (175) with a bent partial area; The wiring structure further includes: A first shielding line (116), located on a side of the first transmission line (165) away from the second transmission line (175); A second shielding line (126), located between the first transmission line (165) and the second transmission line (175); A third shielding line (136), located on a side of the second transmission line (175) away from the first transmission line (165).

7. The wiring structure according to claim 6, characterized in that, It further includes: A second transmission unit (107), electrically connected to the signal processing unit (104) and the first arithmetic unit (111), and configured to transmit the first enable signal (FAR_EN) to the first arithmetic unit (111); A third transmission unit (108), electrically connected to the signal processing unit (104) and the second arithmetic unit (112), and configured to transmit the second enable signal (NEAR_EN) to the second arithmetic unit (112); The initial control signal (Control) includes N sub-control signals, the sub-control signals correspond to the first transmission units (105) one by one, the N first transmission units (105) are arranged at intervals along the second direction (Y), the second direction (Y) intersects with the first direction (X), and the N first transmission units (105) correspond to the same second transmission unit (107) and the same third transmission unit (108), and N is a positive integer.

8. The wiring structure according to claim 7, characterized in that, The first transmission unit (105), the first shielding line (116), and the second shielding line (126) correspond to each other one by one, and there is a first shielding line (116) between two adjacent first transmission units (105) along the second direction (Y).

9. The wiring structure according to claim 7, characterized in that, Along the second direction (Y), there is a third shielding line (136) between the first transmission unit (105) closest to the second transmission unit (107) and the second transmission unit (107).

10. The wiring structure according to claim 2 or 3, characterized in that, It further includes a storage array region (209). The storage array region (209) is adjacent to the row decoding region (203) along a second direction (Y) and is located between the first column decoding region (201) and the second column decoding region (202). The second direction (Y) intersects with the first direction (X). The main path (215) includes a first main path (285) located in the storage array region (209) and a second main path (295) extending from the storage array region (209) to the row decoding region (203). The first main path (285) is electrically connected to the signal processing unit (204), and the second main path (295) is electrically connected to the first branch (225) and the second branch (235) respectively.

11. The wiring structure according to claim 10, wherein The signal processing unit (204) includes a first inverter (244), which is configured to receive the initial control signal (Control) and invert the initial control signal (Control) to obtain and output a second output signal (Vout2). The first main path (285) is configured to receive and transmit the second output signal (Vout2) to the second main path (295). The second main path (295) has a second inverter (254), which is configured to receive the second output signal (Vout2) and invert the second output signal (Vout2) to obtain and output a third output signal (Vout3). The first branch (225) is configured to receive and transmit the third output signal (Vout3) to the first arithmetic unit (211). The second branch (235) is configured to receive and transmit the third output signal (Vout3) to the second arithmetic unit (212).

12. The wiring structure according to claim 10, wherein, The first branch (225) and the second branch (235) are located in the same metal layer, and the first branch (225) and the second branch (235) form a third transmission line (239) penetrating the row decoding region (203). The wiring structure further includes: A fourth shielding line (216) and a fifth shielding line (226), which are respectively located on opposite sides of the third transmission line (239) along the second direction (Y).

13. The wiring structure according to claim 12, characterized in that, It further includes: A second transmission unit (207), electrically connecting the signal processing unit (204) and the first arithmetic unit (211), which is configured to transmit the first enable signal (FAR_EN) to the first arithmetic unit (211). A third transmission unit (208), electrically connecting the signal processing unit (204) and the second arithmetic unit (212), which is configured to transmit the second enable signal (NEAR_EN) to the second arithmetic unit (212). The initial control signal (Control) includes N sub-control signals, and the sub-control signals correspond to the first transmission units (205) one by one. The N third transmission lines (239) in the N first transmission units (205) are arranged at intervals along the second direction (Y), and the N first transmission units (205) correspond to the same second transmission unit (207) and the same third transmission unit (208), where N is a positive integer.

14. The wiring structure according to claim 13, characterized in that, The fourth shield line (216) corresponds to the third transmission line (239) one by one, and there is one fourth shield line (216) between two adjacent third transmission lines (239) along the second direction (Y).

15. The wiring structure according to claim 13, wherein, Along the second direction (Y), there is one fifth shield line (226) between the second transmission unit (207) and one third transmission line (239) closest to the second transmission unit (207).

16. A memory (1), characterized in that, It includes the wiring structure (2) according to any one of claims 1 to 15.

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