Module and method for common mode voltage of clamping transceiver

Abstract

The present invention relates to a module for a common mode voltage of a clamping differential signal transceiver, said differential signal transceiver comprising a receiver for receiving and processing a differential signal from a bus, and the receiver comprising a first input end coupled to a first signal line of the bus and a second input end coupled to a second signal line of the bus. The module comprises: an acquisition circuit, which is configured to acquire a common mode voltage of the differential signal and, on the basis of the common mode voltage of the differential signal, generate a sensing voltage signal; and a feedback control circuit, an input of which is coupled with the acquisition circuit to receive the sensing voltage signal, the feedback control circuit receiving a reference voltage threshold, and an output of the feedback control circuit being coupled with the first input end and the second input end of the receiver. The feedback control circuit is further configured to, on the basis of the sensing voltage signal and the reference voltage threshold, control voltages at the first input end and the second input end, and clamp the sensing voltage signal to the reference voltage threshold.

Description

Module and method for clamping common mode voltage of transceiver

[0001] This invention claims priority to the Chinese patent application filed with the Patent Office of China on December 29, 2023, with application number 202311869454.8 and invention name “Module and method for clamping the common-mode voltage of a transceiver”. The entire contents of this application are incorporated herein by reference. Technical Field

[0002] The present invention relates to a module and method for clamping the common-mode voltage of a differential signal transceiver. More specifically, the module and method can be used to clamp the common-mode voltage between first and second input terminals of a receiver, respectively coupled to first and second signal lines of a bus. For example, the module and method can be used in a CAN receiver. Background Art

[0003] A bus system is a communication system used in various electronic devices to transmit data and control signals. It typically consists of a set of parallel or serial lines that connect various devices, enabling communication and coordination between them. Buses typically use differential transmission signaling technology because of its advantages, such as strong interference resistance, long transmission distance, and high transmission speed. Differential transmission refers to the transmission of signals on two signal lines, with the two signals having equal amplitude and opposite phase. The signals transmitted on these two signal lines are usually called differential signals. In differential signaling, one signal line carries a positive signal and the other carries a negative signal. The difference between these two signals constitutes the effective signal, known as the differential-mode voltage. The average of the voltages on these two signal lines is the common-mode voltage. Common-mode voltage is often caused by interference or signal line imbalance, and it can interfere with or damage signal transmission. Therefore, in differential signaling, common-mode voltage is often suppressed or shielded to ensure reliable and stable signal transmission.

[0004] Bus systems typically employ various communication protocols to transmit signals between nodes. For example, the Controller Area Network (CAN) bus is a common serial communication protocol bus for real-time applications. It is widely used in automotive, industrial control, and other fields to communicate data between various devices and sensors. CAN FD (CAN with Flexible Data Rate) is an abbreviation for CAN. These protocols are collectively referred to as CAN below, without distinguishing them.

[0005] To send and receive bus signals, various devices and sensors in a bus system typically require transceivers. For example, typical CAN transceiver chips must comply with ISO 11898-2:2016. A transceiver generally consists of a receiver (or receiving circuit) and a transmitter (or transmitting circuit). The transmitter receives high-speed serial digital signals from a microcontroller unit (MCU), converts these digital signals into differential signals, and outputs them to the bus. The receiver receives differential signals from the bus, converts them into digital signals, and outputs them to the MCU. For example, the main signal pins of a CAN transceiver include the CANH and CANL pins, which are coupled to the bus, respectively; the TXD pin for receiving digital signals; and the RXD pin for transmitting digital signals.

[0006] In a transceiver, the receiver receives the differential signal transmitted from the bus. This differential signal consists of a common-mode voltage (Vcm) and a differential-mode voltage (Vodiff). The receiver's primary functions include resisting interference caused by common-mode voltage fluctuations, identifying the differential-mode voltage, and correctly outputting it. If the common-mode voltage of the bus signal varies widely, the receiver must be able to handle differential signals with such a wide range. However, the receiver's design is significantly challenged by its need to maintain both high speed and high accuracy. Even in cases where the common-mode voltage of the bus signal is extremely high or low, the receiver may be unable to correctly process the differential signal, leading to communication errors. Summary of the Invention

[0007] One of the purposes of the present invention is to at least solve or alleviate the above technical problems.

[0008] The present invention proposes a module and method for clamping the common-mode voltage of a differential signal transceiver. The module and method can process the received bus signal and clamp the common-mode voltage of the transceiver within a certain voltage range, while the differential-mode voltage is not significantly affected. With the help of the present invention, the common-mode voltage of the signal transmitted to the receiver can be clamped within a set range, thereby reducing the design difficulty of the receiver and ensuring communication quality. The present invention also allows for clamping the common-mode voltage in a simple and cost-effective manner. At the same time, for the transceiver as a whole, it can process bus signals with common-mode voltages that vary over a wider range. With the help of the present invention, the common-mode voltage between the two signal lines of the bus is also not significantly affected.

[0009] According to a first aspect of the present invention, a module for clamping the common-mode voltage of a differential signal transceiver is provided. The differential signal transceiver includes a receiver for receiving and processing a differential signal from a bus, the receiver including a first input coupled to a first signal line of the bus and a second input coupled to a second signal line of the bus. The module according to the present invention includes: an acquisition circuit configured to acquire the common-mode voltage of the differential signal and generate a sensed voltage signal based on the common-mode voltage of the differential signal; and a feedback control circuit having an input coupled to the acquisition circuit to receive the sensed voltage signal, the feedback control circuit receiving a reference voltage threshold, and an output coupled to the first and second inputs of the receiver, respectively. The feedback control circuit is further configured to control the voltages at the first and second inputs based on the sensed voltage signal and the reference voltage threshold, thereby clamping the sensed voltage signal to the reference voltage threshold.

[0010] According to an exemplary aspect of the present disclosure, the differential signal transceiver includes a CAN transceiver, the bus includes a CAN bus, the first signal line includes a first CAN signal line, and the second signal line includes a second CAN signal line.

[0011] According to an exemplary aspect of the present disclosure, the reference voltage threshold includes a first reference voltage. When the sensing voltage signal is less than the first reference voltage, the feedback control circuit clamps the sensing voltage signal to the first reference voltage.

[0012] According to an exemplary aspect of the present disclosure, the reference voltage threshold includes a second reference voltage. When the sensing voltage signal is greater than the second reference voltage, the feedback control circuit clamps the sensing voltage signal to the second reference voltage.

[0013] According to an exemplary aspect of the present disclosure, the acquisition circuit is configured to acquire a common-mode voltage of a differential signal and attenuate a differential-mode voltage of the differential signal to generate a sensing voltage signal.

[0014] According to an exemplary aspect of the present disclosure, a transceiver includes a resistor array coupled to a first signal line and a second signal line, wherein the resistor array is coupled to a first input terminal and a second input terminal.

[0015] According to an exemplary aspect of the present disclosure, an acquisition circuit includes a set of resistors. The set of resistors includes a first resistor and a second resistor. A first end of the first resistor is coupled to a first input terminal, and a second end of the first resistor and a second end of the second resistor are coupled to an acquisition node. A first end of the second resistor is coupled to the second input terminal. The acquisition circuit acquires a common-mode voltage at the acquisition node and outputs a sensed voltage signal.

[0016] According to an exemplary aspect of the present disclosure, a resistor array includes a first voltage-dividing resistor, wherein a first end of the first voltage-dividing resistor is coupled to a first signal line. The resistor array includes a second voltage-dividing resistor, wherein a second end of the first voltage-dividing resistor and a first end of the second voltage-dividing resistor are coupled to a first input terminal. The resistor array includes a third voltage-dividing resistor, wherein a second end of the second voltage-dividing resistor and a first end of the third voltage-dividing resistor are coupled to a first end of the third voltage-dividing resistor. The resistor array includes a fourth voltage-dividing resistor, wherein a second end of the third voltage-dividing resistor and a first end of the fourth voltage-dividing resistor are coupled to a second input terminal. A second end of the fourth voltage-dividing resistor is coupled to a second signal line.

[0017] According to an exemplary aspect of the present disclosure, the resistance values ​​of the first voltage-dividing resistor and the fourth voltage-dividing resistor are equal. According to an exemplary aspect of the present disclosure, the resistance values ​​of the second voltage-dividing resistor and the third voltage-dividing resistor are equal;

[0018] According to an exemplary aspect of the present disclosure, the resistance value of the first resistor is equal to the resistance value of the second resistor. In some embodiments, the resistance values ​​of the first resistor and the second resistor are greater than the resistance value of the first voltage-dividing resistor. In some embodiments, the resistance values ​​of the first resistor and the second resistor are greater than the resistance value of the second voltage-dividing resistor.

[0019] In a preferred embodiment, the resistance value of the first resistor and the second resistor is much greater than the resistance value of the first voltage-dividing resistor. In some embodiments, the resistance value of the first resistor and the second resistor is much greater than the resistance value of the second voltage-dividing resistor. More preferably, the resistance value of the first resistor and the second resistor is at least 10 times the resistance value of the first voltage-dividing resistor. More preferably, the resistance value of the first resistor and the second resistor is at least 10 times the resistance value of the second voltage-dividing resistor.

[0020] According to an exemplary aspect of the present disclosure, the feedback control circuit includes a first operational amplifier that receives a sensing voltage signal and a first reference voltage as inputs and is configured to output a first voltage signal when the sensing voltage signal is less than the first reference voltage.

[0021] According to an exemplary aspect of the present disclosure, a feedback control circuit includes a first MOS transistor and a second MOS transistor. The control terminals of the first and second MOS transistors are both coupled to the output terminal of the first operational amplifier, and the first terminals of the first and second MOS transistors are both coupled to a power supply voltage. The second terminal of the first MOS transistor is coupled to the second input terminal of the receiver, and the second terminal of the second MOS transistor is coupled to the first input terminal of the receiver.

[0022] According to an exemplary aspect of the present disclosure, the feedback control circuit includes a second operational amplifier, which receives a sensing voltage signal and a second reference voltage as input, and the second operational amplifier is configured to output a second voltage signal when the sensing voltage signal is greater than the second reference voltage.

[0023] According to an exemplary aspect of the present disclosure, a feedback control circuit includes a third MOS transistor and a fourth MOS transistor. Control terminals of the third and fourth MOS transistors are coupled to the output terminal of the second operational amplifier. First terminals of the third and fourth MOS transistors are each coupled to a reference potential. A second terminal of the third MOS transistor is coupled to the second input terminal of a receiver. A second terminal of the fourth MOS transistor is coupled to the first input terminal of the receiver.

[0024] According to an exemplary aspect of the present disclosure, a feedback control circuit includes an analog-to-digital converter (ADC) and a current array. The ADC includes an n-bit ADC. The current array includes an n-bit current source and an n-bit switch. The n-bit ADC converts a captured sensed voltage signal into an n-bit digital value. The n-bit digital value controls the opening and closing of the n-bit switch in the current array and controls the current of the n-bit current source to control the voltage at the first input terminal and the second input terminal, thereby clamping the sensed voltage signal to a reference voltage threshold.

[0025] According to an exemplary aspect of the present disclosure, a feedback control circuit includes a first set of switches coupled to a first input terminal and a second input terminal, respectively. The feedback control circuit includes a first set of current sources coupled to the first set of switches, respectively. In some embodiments, the feedback control circuit further includes a first comparator. The first comparator is configured to compare a sensed voltage signal with a first reference voltage. When the sensed voltage signal is less than the first reference voltage, the first comparator closes the first set of switches, and the first set of current sources controls the voltages at the first input terminal and the second input terminal to clamp the sensed voltage signal to the first reference voltage.

[0026] According to an exemplary aspect of the present disclosure, a feedback control circuit includes a second set of switches coupled to a first input terminal and a second input terminal, respectively. The feedback control circuit includes a second set of current sources coupled to the second set of switches, respectively. In some embodiments, the feedback control circuit further includes a second comparator. The second comparator is configured to compare a sensed voltage signal with a second reference voltage. When the sensed voltage signal is greater than the second reference voltage, the second comparator closes the second set of switches, and the second set of current sources controls the voltages at the first input terminal and the second input terminal, thereby clamping the sensed voltage signal to the second reference voltage.

[0027] According to another aspect of the present invention, a method for clamping the common-mode voltage of a differential signal transceiver is provided. The differential signal transceiver includes a receiver for receiving and processing a differential signal from a bus, the receiver including a first input terminal coupled to a first signal line of the bus and a second input terminal coupled to a second signal line of the bus. The method includes: acquiring the common-mode voltage of the differential signal and attenuating the differential-mode voltage of the differential signal to generate a sensed voltage signal. The method according to the present invention also includes: controlling the voltage at the first input terminal and the second input terminal based on the sensed voltage signal and a reference voltage threshold. The method further includes clamping the sensed voltage signal to the reference voltage threshold. In some embodiments, the method is implemented using the module described above.

[0028] In some embodiments, the method according to the present invention can be used to clamp the common mode voltage received by a CAN receiver.

[0029] The method according to the present invention provides the same advantages as mentioned above with respect to the module for clamping the common mode voltage of a differential signal transceiver.

[0030] Other possible embodiments of the present invention also include combinations not explicitly mentioned of features or embodiments described above or below with respect to the embodiments. Here, those skilled in the art can also add individual aspects as improvements or supplements to the corresponding basic forms of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] For a better understanding of the present invention, some embodiments will now be described, by way of example only, with reference to the accompanying drawings, in which:

[0032] FIG1 schematically shows a simplified block diagram of a module for clamping a common mode voltage according to an example.

[0033] FIG2 schematically shows a simplified block diagram of a module for clamping a common mode voltage according to another example.

[0034] FIG3 schematically shows an example of a module for clamping a common mode voltage according to an embodiment of the present invention.

[0035] FIG. 4 schematically shows another example of a module for clamping a common mode voltage according to an embodiment of the present invention.

[0036] FIG5 schematically shows another example of a module for clamping a common mode voltage according to an embodiment of the present invention.

[0037] FIG. 6 schematically shows a comparison of signal transmission achieved with and without the module according to the present invention. DETAILED DESCRIPTION

[0038] The inventive concept will now be described more fully hereinafter with reference to the accompanying drawings, in which exemplary embodiments are shown. However, the inventive concept can be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; on the contrary, these embodiments are provided as examples so that this disclosure will be thorough and complete and will fully convey the scope of the inventive concept to those skilled in the art. Throughout this specification, like reference numerals refer to like parts. Moreover, in describing the preferred embodiments illustrated in the drawings, specific terms are employed for the sake of clarity. However, the disclosure of this patent application is not intended to be limited to the specific terms mentioned, and it should be understood that each specific element includes all technical equivalents that work in a similar manner.

[0039] The term "including" and its variations used in this document represent open inclusion, that is, "including but not limited to". Unless otherwise stated, the term "or" means "and / or". The term "based on" means "at least partially based on". The terms "an example embodiment" and "an embodiment" mean "at least one example embodiment". The term "another embodiment" means "at least one other embodiment". The terms "first", "second", etc. may refer to different or the same objects. The term "module" may refer to a unit that includes one or a combination of hardware, software, and firmware. For example, the term "module" may be used interchangeably with the terms "unit", "logic", "logic block", "component", or "circuit".

[0040] "Coupling" or "connection" herein includes both direct connection and indirect connection. Indirect connection is a connection through an intermediate medium, such as a connection through an electrically conductive medium such as a conductor, wherein the electrically conductive medium may contain parasitic inductance or parasitic capacitance, or a connection through an intermediate circuit or component as described in the embodiments in the specification; indirect connection may also include a connection through other active devices or passive devices on the basis of achieving the same or similar functions. The embodiments of the present disclosure relate to a bus system that transmits signals in a differential transmission manner, including but not limited to bus systems such as CAN and FlexRay. In the following, for the purpose of simplicity, the description is made by way of example with the aid of the CAN bus. However, as will be readily appreciated by those skilled in the art, the scope of the present application is not intended to be limited to the CAN bus, but may be applicable to any suitable bus system that transmits signals in a differential transmission manner.

[0041] A differential signal transceiver typically consists of two main parts: a transmitter and a receiver. The transmitter converts digital signals from a controller into physical signals on a bus (e.g., a CAN bus) and transmits them to other devices via the bus. The receiver receives the physical signals from the bus and converts them into digital signals readable by the controller. For example, a CAN receiver typically has two main ports: a CAN bus port and a controller port. The CAN bus port connects to the CAN bus, receives differential signals from the bus, and converts them into digital signals readable by the controller. The controller port connects to the controller and transmits the received digital signals to the controller for processing. Through these two ports, the CAN receiver facilitates communication between the controller and the CAN bus, ensuring reliable data transmission and processing. The CAN bus typically consists of a first signal line (usually labeled CANH) and a second signal line (usually labeled CANL).

[0042] 1 schematically shows a receiver 10 and a module 100 for clamping a common mode voltage of a differential signal transceiver. The receiver 10 comprises a first input terminal VP coupled to a first signal line CANH of a bus and a second input terminal VN coupled to a second signal line CANL of the bus.

[0043] The CAN transceiver (not fully shown) includes a resistor array 20 for coupling to a first signal line CANH and a second signal line CANL. The resistor array 20 is also coupled to a first input terminal VP and a second input terminal VN, respectively. In some embodiments, the resistor array may include first, second, third, and fourth voltage-dividing resistors 201, 202, 203, and 204. The first voltage-dividing resistor 201 has a first end coupled to the first signal line CANH of the bus, and a second end coupled to the first input terminal VP of the receiver 10. The second voltage-dividing resistor 202 also has a first end coupled to the first input terminal VP of the receiver 10, and a second end coupled to the first end of the third voltage-dividing resistor 203. The second end of the third voltage-dividing resistor 203 is coupled to the second input terminal VN of the receiver 10. The fourth voltage-dividing resistor 204 has a first end coupled to the second input terminal VN of the receiver 10, and a second end coupled to the second signal line CANL of the bus. 1 also shows a common mode voltage node SN1 inside the transceiver, which is located between the second voltage dividing resistor 203 and the fourth voltage dividing resistor 204. The common mode voltage node SN1 defines a reference common mode voltage Vref_cm inside the transceiver.

[0044] In a preferred embodiment, the first voltage-dividing resistor 201 and the fourth voltage-dividing resistor 204 have equal resistance values, as shown in FIG1 , and are both labeled R1. In a preferred embodiment, the second voltage-dividing resistor 202 and the third voltage-dividing resistor 203 have equal resistance values, as shown in FIG1 , and are both labeled R2.

[0045] As shown in Figure 1, module 100 for clamping the common-mode voltage of a differential signal transceiver includes an acquisition circuit 110 and a feedback control circuit 120 coupled to acquisition circuit 110. Acquisition circuit 110 is configured to acquire the common-mode voltage of a differential signal from a bus and generate a sense voltage signal Vsense based on the common-mode voltage of the differential signal. Acquisition circuit 110 is coupled to a first input terminal VP and a second input terminal VN of a receiver 10. As shown in Figure 1, acquisition circuit 110 may also be coupled between a first voltage-dividing resistor 201 and a second voltage-dividing resistor 202.

[0046] The input of the feedback control circuit 120 is coupled to the acquisition circuit 110 to receive the sense voltage signal Vsense from the acquisition circuit. The feedback control circuit also receives a reference voltage threshold for comparison with the sense voltage signal Vsense. As shown in FIG1 , the output of the feedback control circuit is coupled to a first input terminal VP and a second input terminal VN of the receiver 10, respectively. The feedback control circuit 120 is configured to control the voltages at the first input terminal VP and the second input terminal VN based on the sense voltage signal and the reference voltage threshold, thereby clamping the sense voltage signal Vsense to the reference voltage threshold.

[0047] FIG2 shows a simplified block diagram of another example of module 100, which differs from the one in FIG1 only in the feedback control circuit. The feedback control circuit may include first and second feedback control circuits 121 and 122. The first and second feedback control circuits 121 and 122 may be configured to have the structure and function of the feedback control circuit shown in FIG1 . The reference voltage threshold may include a first reference voltage and a second reference voltage. The first feedback control circuit 121 may receive a sense voltage signal Vsense and a first reference voltage and compare the sense voltage signal with the first reference voltage. When the value of the sense voltage signal is lower than the first reference voltage, the first feedback control circuit 121 controls the voltage at the first input terminal VP and the second input terminal VN to clamp the sense voltage signal Vsense to the first reference voltage. In some embodiments, the value of the first reference voltage is less than a reference common-mode voltage Vref_cm within the transceiver.

[0048] Similarly, the second feedback control circuit 122 can receive the sense voltage signal Vsense and a second reference voltage and compare the sense voltage signal with the second reference voltage. When the sense voltage signal is higher than the second reference voltage, the second feedback control circuit 122 controls the voltages at the first input terminal VP and the second input terminal VN to clamp the sense voltage signal Vsense to the second reference voltage. In some embodiments, the second reference voltage is greater than the reference common-mode voltage Vref_cm within the transceiver.

[0049] Figure 3 schematically illustrates an example embodiment of module 100. In such an embodiment, the acquisition circuit includes a set of resistors, including a first resistor 111 and a second resistor 112. The first end of first resistor 111 is coupled to a first input terminal VP, and the second end is coupled to the second end of second resistor 112. The first end of second resistor 112 is coupled to a second input terminal VN. The second end of first resistor 111 and the second end of second resistor 112 are coupled to an acquisition node SN2. The common-mode voltage of the differential signal between the first input terminal VP and the second output terminal VN is acquired at acquisition node SN2 and output as a sensed voltage signal Vsense. In some embodiments, the resistance values ​​of first resistor 111 and second resistor 112 are set to be equal, and are labeled R3 in Figure 3. In this configuration of acquisition circuit 110, since the voltage at acquisition node SN2 is divided only by R3 from VP and VN, the sensed voltage signal Vsense accurately reflects the common-mode voltage between VP and VN.

[0050] In a preferred embodiment, the resistance value R3 of the first resistor 111 and the second resistor 112 is set to be greater than the resistance value R1. In a preferred embodiment, the resistance value R3 of the first resistor 111 and the second resistor 112 is set to be greater than the resistance value R2. In a more preferred embodiment, the resistance value R3 of the first resistor 111 and the second resistor 112 is set to be much greater than the resistance value R1. In a more preferred embodiment, the resistance value R3 of the first resistor 111 and the second resistor 112 is set to be much greater than the resistance value R2. For example, R3 is at least 10 times greater than R1. For example, R3 is at least 10 times greater than R2.

[0051] It is advantageous to appropriately select the resistor value R3. Preferably, R3 is selected to be greater than R1 and R2. This allows the acquisition circuit 110 to acquire the common-mode voltage of the differential signal while attenuating the differential-mode voltage of the differential signal to generate the sense voltage signal Vsense. Preferably, R3 is selected to be much greater than R1 and R2. In this case, Vsense essentially only acquires the common-mode voltage between VP and VN, and almost no differential-mode voltage is acquired. This is explained in detail below with reference to the relationship. Assuming that module 100 is not provided between the receiver 10 and the resistor array 20, the differential-mode voltage between VP and VN is: ,

[0052] In the above relational expression (1), VVP and VVN represent the voltages at the first input terminal VP and the second input terminal VN, respectively; VCANH and VCANL represent the voltages at the first signal line and the second signal line CANH and CANL, respectively.

[0053] When the module 100 shown in FIG3 is provided between the receiver 10 and the resistor array 20, the differential mode voltage between VP and VN is: ,

[0054] It can be seen from the above relationship (2) that when the module 100 is set, the differential mode voltage between VP and VN will be attenuated due to the setting of the resistance value R3 of the first and second resistors 111 and 112 for voltage division.

[0055] Furthermore, from equations (1) and (2), it can be seen that when R3 is set to be significantly larger than R1 and R2, for example, when R3 is at least 10 times larger than R1 and R2, the effect of R3 on the differential-mode voltage between VP and VN can be negligible. In other words, by selecting an appropriate R3, module 100 can clamp only the common-mode voltage between VP and VN, while having little effect on the differential-mode voltage.

[0056] FIG3 also schematically illustrates an exemplary embodiment of a feedback control circuit. The feedback control circuit includes a first feedback control circuit 121. The first feedback control circuit 121 includes a first operational amplifier amp1, which receives a sense voltage signal Vsense and a first reference voltage Vref1 as inputs. As shown in FIG2 , the positive input terminal of the first operational amplifier receives the sense voltage signal Vsense, and the negative input terminal receives the first reference voltage Vref1. In some embodiments, the first reference voltage Vref1 may be from other modules of the transceiver. Specifically, the first reference voltage Vref1 may be less than the reference common-mode voltage Vref_cm. The first operational amplifier amp1 is configured to output a first voltage signal when the sense voltage signal Vsense is less than the first reference voltage Vref1.

[0057] The first feedback control circuit 121 further includes a first MOS transistor P1 and a second MOS transistor P2. The control terminals of the first and second MOS transistors P1 and P2 are both coupled to the output terminal of the first operational amplifier amp1, and the first terminals are both coupled to the power supply voltage of the transceiver. The second terminal of the first MOS transistor P1 is coupled to the second input terminal VN of the receiver. The second terminal of the second MOS transistor P2 is coupled to the first input terminal VP of the receiver. As shown in Figure 2, the positive input terminal of the first operational amplifier is coupled to the acquisition node SN2 to receive the sense voltage signal Vsense, and the negative input terminal receives the first reference voltage Vref1. In some embodiments, the first reference voltage Vref1 can be from other modules of the transceiver. Specifically, the first reference voltage Vref1 can be less than the reference common mode voltage Vref_cm.

[0058] Alternatively or additionally, the feedback control circuit may include a second feedback control circuit 122. In a similar manner as described above, the second feedback control circuit 122 includes a second operational amplifier amp2 that receives the sensed voltage signal Vsense and a second reference voltage as inputs. As shown in FIG. 2, the positive input terminal of the second operational amplifier amp2 is coupled to the acquisition node SN2 to receive the sensed voltage signal Vsense, and the negative input terminal receives the second reference voltage Vref2. In some embodiments, the second reference voltage Vref2 may be from other modules of the transceiver. Specifically, the second reference voltage Vref2 may be greater than the reference common-mode voltage Vref_cm. The second operational amplifier amp2 is configured to output a second voltage signal when the sensed voltage signal Vsense is greater than the second reference voltage.

[0059] The second feedback control circuit 122 further includes a third MOS transistor N1 and a fourth MOS transistor N2. The control terminals of the third and fourth MOS transistors N1, N2 are coupled to the output terminal of the second operational amplifier amp2. The first terminals of the third and fourth MOS transistors N1, N2 are both coupled to the reference potential. The second terminal of the third MOS transistor N1 is coupled to the second input terminal VN of the receiver. The second terminal of the fourth MOS transistor N2 is coupled to the first input terminal VP of the receiver.

[0060] The operation principle of the module 100 is depicted in conjunction with FIG. 3. The module 100 may have a first feedback control circuit 121 and / or a second feedback control circuit 122. For clarity of illustration, the following description includes the operation in the case of both, however, the present invention is not limited thereto. When the sensed voltage signal Vsense at the acquisition node SN2 is between the first reference voltage Vref1 and the second reference voltage Vref2, i.e., Vref1 < Vsense < Vref2, the first amplifier amp1 outputs a higher voltage, such that the on-resistances of the first and second MOS transistors P1, P2 are very large, and no current flows through this feedback control circuit to the first input terminals VP, VN. At this time, the module 100 does not affect the operation of the receiver. In other words, there is no feedback control on the common-mode voltage of VP and VN in this case.

[0061] When Vsense < Vref1, which may be caused by a very low common-mode voltage of the bus, the first amplifier amp1 outputs a first voltage signal. The first voltage signal may have a low voltage value. The first voltage signal reduces the on-resistances of the first and second MOS transistors P1, P2. At this time, the first amplifier amp1 and the first and second MOS transistors P1, P2 form a negative feedback control loop. The first and second MOS transistors P1, P2 pull up the voltages of VP and VN, and Vsense also rises until Vsense is clamped to Vref1.

[0062] Similarly, when Vsense > Vref2, a condition likely caused by a very high common-mode voltage on the bus, the second amplifier amp2 outputs a second voltage signal. This second voltage signal can have a high voltage value. This second voltage signal reduces the on-resistance of the third and fourth MOS transistors N1 and N2. At this point, the second amplifier amp2 forms a negative feedback control loop with the third and fourth MOS transistors N1 and N2. The third and fourth MOS transistors N1 and N2 pull down the voltages between VP and VN, causing Vsense to drop until it is clamped to Vref2.

[0063] Figure 4 schematically illustrates another example implementation of module 100. The module in Figure 4 is similar to that in Figure 3, differing only in the configuration of the feedback control circuit 120. For the sake of brevity, the components identical to those of module 100 in Figure 3 are not further described. The feedback control circuit includes an analog-to-digital converter (ADC) configured to receive a sense voltage signal Vsense and a current array configured to receive the output of the ADC. The ADC includes an n-bit ADC (Analog-to-Digital Converter). The current array includes an n-bit current source and an n-bit switch. The n-bit switch can be coupled to a first input terminal VP and a second input terminal VN of a receiver. The n-bit ADC converts the acquired sense voltage signal Vsense into an n-bit digital value, which controls the opening and closing of the n-bit switch in the current array. Furthermore, the n-bit digital value controls the current of the n-bit current source, thereby controlling the voltages at the first input terminal VP and the second input terminal VN, thereby clamping the sense voltage signal Vsense to a reference voltage threshold. Similar to the embodiment of FIG. 3 , the reference voltage threshold may include a first reference voltage Vref1 and / or a second reference voltage Vref2 , which will not be described in detail herein.

[0064] Figure 5 schematically illustrates another exemplary embodiment of module 100, which differs from Figure 3 in the configuration of the feedback control circuit. Parts identical to the embodiments in Figures 3 or 4 will not be reiterated here. The feedback control circuit may include a first feedback control circuit 121. The first feedback control circuit 121 may include a first set of switches S1 and S2. The first set of switches are coupled to a first input terminal VP and a second input terminal VN of the receiver 10, respectively. The first feedback control circuit 121 also includes a first set of current sources I1 and I2, respectively coupled to the first set of switches. Furthermore, the first feedback control circuit 121 includes a first comparator comp1 configured to compare the sense voltage signal Vsense with a first reference voltage Vref1. When the sense voltage signal Vsense is less than the first reference voltage Vref1, the first comparator comp1 closes the first set of switches S1 and S2, and the first set of current sources I1 and I2 control the voltages at the first input terminal VP and the second input terminal VN, clamping the sense voltage signal Vsense to the first reference voltage Vref1. The configuration of the first reference voltage Vref1 is also described above.

[0065] Alternatively or additionally, the feedback control circuit may include a second feedback control circuit 122. The second feedback control circuit 122 may include a second set of switches S3 and S4. The second set of switches is coupled to the first input terminal VP and the second input terminal VN of the receiver 10, respectively. The second feedback control circuit 122 also includes a second set of current sources I3 and I4, respectively coupled to the second set of switches. The second feedback control circuit 122 further includes a second comparator comp2 configured to compare the sense voltage signal Vsense with a second reference voltage Vref2. When the sense voltage signal Vsense is greater than the second reference voltage Vref2, the second comparator comp2 closes the second set of switches S3 and S4, and the second set of current sources I3 and I4 control the voltages at the first input terminal VP and the second input terminal VN, thereby clamping the sense voltage signal Vsense to the second reference voltage Vref2. The setting of the second reference voltage Vref2 is also described above.

[0066] The present invention also proposes a method for clamping the common-mode voltage of a differential signal transceiver. As described above, the differential signal transceiver includes a receiver for receiving and processing a differential signal from a bus. The receiver includes a first input terminal VP coupled to a first signal line of the bus and a second input terminal VN coupled to a second signal line of the bus. The method according to the present invention includes collecting the common-mode voltage of the differential signal and attenuating the differential-mode voltage of the differential signal to generate a sense voltage signal Vsense. The method includes controlling the voltage at the first input terminal VP and the second input terminal VN based on the sense voltage signal and a reference voltage threshold, thereby clamping the sense voltage signal Vsense to the reference voltage threshold. The module 100 described above can be used to implement this method. Any other suitable circuit or module can also be used.

[0067] Figure 6 schematically illustrates the clamping effect achieved by the clamping module according to the present invention. In Figure 6, (a) shows a schematic diagram of a differential signal received on two signal lines of a bus (e.g., CANH and CANL of a CAN bus), with the bus common-mode voltage being too high and too low being marked. (b) shows the signal received between the two input terminals VP and VN of a receiver without the clamping module. The common-mode voltage between VP and VN exhibits a similar effect to that of a high or low bus common-mode voltage, potentially causing the receiver to malfunction and thus affecting normal communication. (c) shows the signal received between the two input terminals VP and VN of a receiver with the clamping module according to the present invention. Even in the case of a high or low bus common-mode voltage, the common-mode voltage between VP and VN is clamped between Vref1 and Vref2, ensuring normal receiver operation and allowing normal communication. As can be seen, the clamping module according to the present invention can reduce the design complexity of a receiver and allow the transceiver to receive and process bus signals with a wider common-mode range.

[0068] The above description of the exemplary embodiments of the disclosed subject matter, including what is described in the Abstract, is not intended to be exhaustive or to limit the disclosed embodiments to the precise forms disclosed. Although specific embodiments and examples are described herein for illustrative purposes, various modifications are contemplated within the scope of such embodiments and examples, as those skilled in the relevant art will recognize.

[0069] In this regard, although the subject matter disclosed herein has been described in conjunction with various embodiments and corresponding drawings, it should be understood that other similar embodiments may be used or modifications and additions may be made to the described embodiments to perform the same, similar, alternative, or alternative functions of the disclosed subject matter without departing from the described embodiments. Accordingly, the disclosed subject matter should not be limited to any single embodiment described herein, but rather should be construed in accordance with the breadth and scope of the claims appended hereto.

[0070] In particular, with respect to the various functions performed by the aforementioned components (assemblies, devices, circuits, systems, etc.), unless otherwise specified, the terms used to describe such components (including references to "modules" or "devices") are intended to correspond to any component or structure that performs the designated functions of the components (e.g., functionally equivalent), even if not structurally equivalent to the disclosed structures that perform the functions in the exemplary embodiments of the present disclosure shown herein. In addition, while particular features have been disclosed with respect to only one of several embodiments, for any given or particular application, such features may be combined with one or more other features of other embodiments, which may be desirable and advantageous.

Claims

1. A module for clamping the common-mode voltage of a differential signal transceiver, the differential signal transceiver including a receiver for receiving and processing differential signals from a bus, the receiver including a first input terminal (VP) coupled to a first signal line of the bus and a second input terminal (VN) coupled to a second signal line of the bus, the module including: An acquisition circuit configured to acquire the common-mode voltage of the differential signals and generate a sense voltage signal (Vsense) based on the common-mode voltage of the differential signals; A feedback control circuit, an input of the feedback control circuit being coupled to the acquisition circuit to receive the sense voltage signal, the feedback control circuit receiving a reference voltage threshold, an output of the feedback control circuit being respectively coupled to the first input terminal and the second input terminal of the receiver, the feedback control circuit being configured to control the voltages at the first input terminal (VP) and the second input terminal (VN) based on the sense voltage signal and the reference voltage threshold to clamp the sense voltage signal (Vsense) to the reference voltage threshold.

2. The module according to claim 1, characterized in that: The differential signal transceiver includes a CAN transceiver, the bus includes a CAN bus, the first signal line includes a first CAN signal line (CANH), and the second signal line includes a second CAN signal line (CANL).

3. The module according to claim 1 or 2, wherein, The reference voltage threshold includes a first reference voltage (Vref1), and when the sense voltage signal is less than the first reference voltage, the feedback control circuit clamps the sense voltage signal to the first reference voltage; and / or The reference voltage threshold includes a second reference voltage (Vref2), and when the sense voltage signal is greater than the second reference voltage, the feedback control circuit clamps the sense voltage signal to the second reference voltage.

4. The module according to claim 1 or 2, wherein The acquisition circuit is configured to acquire the common-mode voltage of the differential signals and attenuate the differential-mode voltage of the differential signals to generate a sense voltage signal (Vsense).

5. The module according to claim 1 or 2, wherein The transceiver includes a resistor array for coupling to the first signal line and the second signal line, the resistor array being coupled to the first input terminal (VP) and the second input terminal (VN); wherein the acquisition circuit includes a group of resistors, the group of resistors including a first resistor and a second resistor, a first end of the first resistor being coupled to the first input terminal (VP), a second end of the first resistor and a second end of the second resistor being coupled at an acquisition node, a first end of the second resistor being coupled to the second input terminal (VN), and the common-mode voltage being acquired at the acquisition node and the sense voltage signal (Vsense) being output.

6. The module according to claim 5, wherein The resistor array includes: A first voltage-dividing resistor, a first end of the first voltage-dividing resistor being coupled to the first signal line, and a second end of the first voltage-dividing resistor and a first end of a second voltage-dividing resistor being coupled at the first input terminal (VP); A second end of the second voltage-dividing resistor is coupled to a first end of a third voltage-dividing resistor; The second end of the third voltage-dividing resistor is coupled to the first end of the fourth voltage-dividing resistor at the second input terminal (VN); The second end of the fourth voltage-dividing resistor is coupled to the second signal line; The resistance values of the first voltage-dividing resistor and the fourth voltage-dividing resistor are equal, and the resistance values of the second voltage-dividing resistor and the third voltage-dividing resistor are equal; The resistance value of the first resistor is equal to the resistance value of the second resistor, and the resistance values of the first resistor and the second resistor are greater than the resistance value of the first voltage-dividing resistor, and the resistance values of the first resistor and the second resistor are greater than the resistance value of the second voltage-dividing resistor.

7. The module according to claim 1 or 2, wherein The feedback control circuit includes: A first operational amplifier (amp1), which receives the sensed voltage signal and a first reference voltage as inputs, and is configured to output a first voltage signal when the sensed voltage signal is less than the first reference voltage; A first MOS transistor and a second MOS transistor, the control terminals of the first MOS transistor and the second MOS transistor are both coupled to the output terminal of the first operational amplifier, and the first ends are both coupled to the power supply voltage; the second end of the first MOS transistor is coupled to the second input terminal of the receiver, and the second end of the second MOS transistor is coupled to the first input terminal of the receiver; and / or The feedback control circuit includes: A second operational amplifier (amp2), which receives the sensed voltage signal and a second reference voltage as inputs, and is configured to output a second voltage signal when the sensed voltage signal is greater than the second reference voltage; A third MOS transistor and a fourth MOS transistor, the control terminals of the third MOS transistor and the fourth MOS transistor are coupled to the output terminal of the second operational amplifier, and the first ends of the third MOS transistor and the fourth MOS transistor are both coupled to the reference potential; the second end of the third MOS transistor is coupled to the second input terminal of the receiver, and the second end of the fourth MOS transistor is coupled to the first input terminal of the receiver.

8. The module according to claim 1 or 2, wherein The feedback control circuit includes an analog-to-digital converter and a current array; The analog-to-digital converter includes an n-bit ADC, the current array includes an n-bit current source and an n-bit switch, the n-bit ADC converts the acquired sensed voltage signal into an n-bit digital value, and the n-bit digital value controls the opening and closing of the n-bit switch in the current array and controls the current of the n-bit current source to control the voltages at the first input terminal (VP) and the second input terminal (VN), so as to clamp the sensed voltage signal (Vsense) to the reference voltage threshold.

9. The module according to claim 1 or 2, wherein The feedback control circuit includes: A first group of switches respectively coupled to the first input terminal and the second input terminal; A first group of current sources respectively coupled to the first group of switches; A first comparator configured to compare the sensed voltage signal and a first reference voltage, and when the sensed voltage signal is less than the first reference voltage, the first comparator closes the first set of switches, and the first set of current sources controls the voltages at the first input terminal (VP) and the second input terminal (VN) to clamp the sensed voltage signal (Vsense) to the first reference voltage; and / or The feedback control circuit includes: A second set of switches respectively coupled to the first input terminal and the second input terminal; A second set of current sources respectively coupled to the second set of switches; A second comparator configured to compare the sensed voltage signal and a second reference voltage, and when the sensed voltage signal is greater than the second reference voltage, the second comparator closes the second set of switches, and the second set of current sources controls the voltages at the first input terminal (VP) and the second input terminal (VN) such that the sensed voltage signal (Vsense) is clamped to the second reference voltage.

10. A method for clamping a common-mode voltage of a differential signal transceiver, the differential signal transceiver including a receiver for receiving and processing differential signals from a bus, the receiver including a first input terminal (VP) coupled to a first signal line of the bus and a second input terminal (VN) coupled to a second signal line of the bus, the method comprising: Acquiring the common-mode voltage of the differential signal and attenuating the differential-mode voltage of the differential signal to generate a sensed voltage signal (Vsense); Based on the sensed voltage signal and a reference voltage threshold, controlling the voltages at the first input terminal (VP) and the second input terminal (VN) to clamp the sensed voltage signal (Vsense) to the reference voltage threshold.

11. The method according to claim 10, wherein, Implementing the method using the module according to any one of claims 1-9.

12. The method according to claim 10, wherein, The method is used for clamping the common-mode voltage received by a CAN receiver.

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