Charge pump circuit

Abstract

Embodiments of the present invention relate to a charge pump circuit. Provided is a charge pump circuit, comprising: a detection feedback stage, a voltage input end and a voltage output end being connected to the detection feedback stage, and a feedback output end of the detection feedback stage generating a feedback voltage on the basis of an output voltage from the voltage output end and an input voltage from the voltage input end; an error amplification stage, having a feedback output end connected to a first input end of the error amplification stage, so as to input the feedback voltage to the error amplification stage, a second input end of the error amplification stage receiving a reference voltage signal, and the error amplification stage further comprising an amplification output end used for outputting a voltage signal; and a charge pump stage, the charge pump stage comprising charge pump units, the charge pump units being connected to the voltage input end and being used for converting the input voltage of the voltage input end and outputting the converted voltage from the voltage output end, and the charge pump stage being further connected to the amplification output end and used for adjusting the voltage conversion amplitude on the basis of the voltage signal outputted by the error amplification stage.

Description

Charge pump circuit

[0001] This invention claims priority to the Chinese patent application filed with the Patent Office of China on December 29, 2023, with application number 202311870614.0 and invention name “Charge Pump Circuit”. The entire contents of this application are incorporated herein by reference. Technical Field

[0002] Embodiments of the present disclosure relate to charge pump circuits. Background Art

[0003] A charge pump is a switching converter that uses capacitors to store energy. A switch is used to switch the capacitors between supply and discharge states, thereby increasing or decreasing the supply voltage.

[0004] Charge pumps have a wide range of applications in circuit design, including power supplies and storage devices. In power supply applications, the input voltage and load current of a charge pump typically vary widely, ranging from a few volts to tens of volts or even hundreds of volts, and the load current can range from tens of microamperes to several milliamperes or even tens of milliamperes. This poses significant challenges to the design of charge pump circuits in power supply products.

[0005] Prior art charge pump circuits are open-loop circuits with two input voltages. During operation, by opening and closing multiple switches, the charge pump can theoretically convert its output voltage to the sum of its two input voltages. However, in practice, the input voltage range is very wide. In this case, the higher the input voltage, the greater the parasitic capacitance generated at the charge pump nodes, resulting in greater efficiency losses. Consequently, the output voltage of such prior art open-loop charge pump circuits differs significantly from the theoretical value, and the power consumption of each node in the circuit is high.

[0006] Furthermore, this type of open-loop charge pump circuit in the prior art is not suitable for cascading because of the large parasitic capacitance generated at the relevant nodes in the second stage, which significantly degrades the efficiency of the charge pump. Although parasitic capacitance can be reduced by adding components such as MOSFETs, the driving voltage of the MOSFETs in an open-loop charge pump circuit significantly reduces the charge pump's boost capability, especially at low input voltages. Furthermore, when a higher boost voltage is required in the prior art charge pump circuit, high-voltage switches and capacitors are required, which significantly increases the area overhead.

[0007] Therefore, it is desired to provide a charge pump circuit that can have good boosting capability when the input voltage is low and has low power consumption and area overhead when the input voltage and load vary over a wide range. Summary of the Invention

[0008] This summary is provided to introduce a selection of concepts in a simplified form that are further described below in the detailed description. This summary is not intended to identify key features or essential features of the disclosure, nor is it intended to limit the scope of the disclosure.

[0009] According to an embodiment of the present disclosure, a charge pump circuit is provided, comprising: a detection feedback stage, wherein a voltage input terminal and a voltage output terminal are connected to the detection feedback stage, and the feedback output terminal of the detection feedback stage generates a feedback voltage based on the output voltage from the voltage output terminal and the input voltage of the voltage input terminal; an error amplifier stage, wherein the feedback output terminal is connected to the first input terminal of the error amplifier stage so as to input the feedback voltage to the error amplifier stage, the second input terminal of the error amplifier stage receives a reference voltage signal, and the error amplifier stage further includes an amplified output terminal for outputting a voltage signal; and a charge pump stage, wherein the charge pump stage includes a charge pump unit, the charge pump unit is connected to the voltage input terminal, converts the input voltage of the voltage input terminal and outputs it from the voltage output terminal, and the charge pump stage is further connected to the amplified output terminal for adjusting the voltage conversion amplitude according to the voltage signal output by the error amplifier stage. Through the above technical solution, the output signal of the charge pump circuit can be fed back to the input terminal in real time, so that in a closed-loop charge pump circuit, the voltage and current in the circuit can be adjusted in real time according to the feedback result through circuit design, thereby achieving the advantages of improving the performance and stability of the circuit.

[0010] According to an embodiment of the present disclosure, the detection feedback stage includes a voltage difference detection unit and a feedback network. The voltage difference detection unit obtains a voltage difference based on the output voltage and the input voltage and generates the feedback voltage through the feedback network.

[0011] According to an embodiment of the present disclosure, the charge pump stage includes a first power tube, the first pole or the second pole of the first power tube is connected to the charge pump unit, and the control end of the first power tube receives the voltage signal output by the amplified output end of the error amplification stage, wherein the current flowing through the first power tube changes with the change of the voltage signal output by the amplified output end.

[0012] According to an embodiment of the present disclosure, the charge pump circuit further includes a buffer stage between the error amplification stage and the charge pump stage, the amplification output end is connected to the buffer stage, and the buffer output end of the buffer stage is connected to the control end of the first power tube.

[0013] According to an embodiment of the present disclosure, the buffer stage includes a second power tube and a third power tube, the control end of the second power tube is connected to the control end of the first power tube of the charge pump stage, the first pole of the second power tube is connected to the first pole of the third power tube and to the control end of the second power tube, the second pole of the second power tube is connected to a reference potential, the control end of the third power tube is connected to the output end of the error amplification stage and receives a voltage signal from the error amplification stage, the first pole of the third power tube is connected to the first pole of the second power tube and to the control end of the second power tube, and the second pole of the third power tube is connected to the operating voltage.

[0014] According to an embodiment of the present disclosure, the detection feedback stage includes a fourth power tube, a fifth power tube, a first resistor, and a second resistor, the voltage input end is connected to the second pole of the fourth power tube, the control end of the fourth power tube is connected to the control end of the fifth power tube and to the first pole of the fourth power tube, the first pole of the fourth power tube is connected to one end of the first resistor and to a reference potential, the voltage output end is connected to one end of the second resistor, the other end of the second resistor is connected to the second pole of the fifth power tube, the control end of the fifth power tube is connected to the control end of the fourth power tube, and the first pole of the fifth power tube is connected to the other end of the first resistor and to the first input end of the error amplification stage.

[0015] According to an embodiment of the present disclosure, the charge pump stage includes a first power tube, a first capacitor, a first switch, a second switch, a third switch, and a fourth switch. The node at one end of the first capacitor is connected to the input voltage through the first switch and to the output voltage through the fourth switch, the node at the other end of the first capacitor is connected to the input voltage through the third switch and to the first pole of the first power tube through the second switch, and the second pole of the first power tube is connected to the reference potential.

[0016] According to an embodiment of the present disclosure, the charge pump stage includes N charge pump units, and the N charge pump units are connected to form an N-phase charge pump structure, where N is a positive integer.

[0017] According to an embodiment of the present disclosure, the charge pump stage includes a first power tube, a first capacitor, a second capacitor, a first switch, a second switch, a third switch, a fourth switch, a fifth switch, a sixth switch, a seventh switch, and an eighth switch. The node at one end of the first capacitor is connected to the input voltage through the first switch and to the output voltage through the fourth switch, the node at the other end of the first capacitor is connected to the input voltage through the third switch and to the first electrode of the first power tube through the second switch, the node at one end of the second capacitor is connected to the input voltage through the fifth switch and to the output voltage through the eighth switch, the node at the other end of the second capacitor is connected to the input voltage through the seventh switch and to the first electrode of the first power tube through the sixth switch, the second electrode of the first power tube is connected to the reference potential, and the control end of the first power tube is connected to the amplified output end.

[0018] According to an embodiment of the present disclosure, the charge pump stage includes a plurality of charge pump units, and the plurality of charge pump units are cascaded.

[0019] According to an embodiment of the present disclosure, the charge pump stage includes a first power tube, a first capacitor, a second capacitor, a first switch, a second switch, a third switch, a fourth switch, a fifth switch, a sixth switch, a seventh switch, and an eighth switch. The nodes at one end of the first capacitor are respectively connected to the input voltage through the first switch and to the next-stage charge pump unit through the fourth switch. The nodes at the other end of the first capacitor are respectively connected to the input voltage through the third switch and to the first electrode of the first power tube through the second switch. The nodes at one end of the second capacitor are respectively connected to the first stage through the fifth switch and to the output voltage through the eighth switch. The nodes at the other end of the second capacitor are respectively connected to the previous-stage charge pump unit through the seventh switch and to the first electrode of the first power tube through the sixth switch. The second electrode of the first power tube is connected to the reference potential.

[0020] According to an embodiment of the present disclosure, a charge pump circuit is provided, comprising: a detection feedback stage, a voltage output terminal being connected to the detection feedback stage, and a feedback output terminal of the detection feedback stage generating a feedback voltage based on an output voltage from the voltage output terminal and a reference potential; an error amplification stage, the feedback output terminal being connected to a first input terminal of the error amplification stage so as to input the feedback voltage into the error amplification stage, a second input terminal of the error amplification stage receiving a reference voltage signal, the error amplification stage further comprising an amplification output terminal for outputting a voltage signal; a buffer stage, the buffer stage being located between the error amplification stage and a charge pump stage, the amplification output terminal being connected to the buffer stage, the buffer output terminal of the buffer stage being connected to the charge pump stage; and a charge pump stage, the charge pump stage comprising a charge pump unit, the charge pump unit being connected to the voltage output terminal for causing a voltage to change and output from the voltage output terminal, the charge pump stage being further connected to the amplification output terminal via the buffer stage for adjusting a voltage conversion amplitude according to a voltage signal output by the error amplification stage. Through the above technical solution, the output signal of the charge pump circuit can be fed back to the input end in real time, so that in the closed-loop negative pressure charge pump circuit, the voltage and current in the circuit can be adjusted in real time according to the feedback results through circuit design, thereby achieving the advantages of improving the performance and stability of the circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The above and other objects, features and advantages of the embodiments of the present disclosure will become readily understood by reading the following detailed description with reference to the accompanying drawings, in which several embodiments of the present disclosure are shown by way of example and not limitation, in which:

[0022] FIG1 shows a charge pump circuit according to a preferred embodiment of the present disclosure.

[0023] FIG2 shows a charge pump circuit according to a preferred embodiment of the present disclosure.

[0024] FIG3 shows a charge pump circuit according to a preferred embodiment of the present disclosure.

[0025] FIG4 shows a charge pump circuit according to a preferred embodiment of the present disclosure.

[0026] FIG5 shows a charge pump circuit according to a preferred embodiment of the present disclosure.

[0027] FIG6 shows a charge pump circuit according to a preferred embodiment of the present disclosure.

[0028] FIG7 shows a charge pump circuit according to a preferred embodiment of the present disclosure.

[0029] FIG8 shows a negative voltage charge pump circuit according to a preferred embodiment of the present disclosure.

[0030] FIG9 shows a negative voltage charge pump circuit according to a preferred embodiment of the present disclosure. DETAILED DESCRIPTION

[0031] The preferred embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although preferred embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments set forth herein. Rather, these embodiments are provided to make the present disclosure more thorough and complete, and to fully convey the scope of the present disclosure to those skilled in the art.

[0032] The term "including" and its variations used in this document represent open inclusion, that is, "including but not limited to". Unless otherwise stated, the term "or" means "and / or". The term "based on" means "at least partially based on". The terms "an example embodiment" and "an embodiment" mean "at least one example embodiment". The term "another embodiment" means "at least one other embodiment". The terms "first", "second", etc. may refer to different or the same objects. In the description of this document, unless otherwise specified and limited, the terms "connected" and "connected" should be understood in a broad sense. For example, it can be a direct connection or an indirect connection through an intermediate medium. For ordinary technicians in this field, the specific meanings of the above terms can be understood according to specific circumstances.

[0033] The charge pump circuit in the prior art is open-loop and has two input voltages. During operation, by opening and closing multiple switches, the charge pump can theoretically convert the output voltage to the sum of the two input voltages. However, in actual operation, the input voltage range is very large. In this case, the higher the input voltage, the greater the parasitic capacitance generated in the charge pump nodes, resulting in greater efficiency loss. Therefore, the output voltage of this open-loop charge pump circuit in the prior art is significantly different from the theoretical value, and the power consumption of each node in the circuit is very high. Moreover, this open-loop charge pump circuit in the prior art is not suitable for cascading because large parasitic capacitance is generated at the relevant nodes of the second stage, which significantly deteriorates the efficiency of the charge pump. Moreover, when the charge pump circuit in the prior art requires a higher voltage boost, it is necessary to use high-voltage-resistant switches and capacitors, which greatly increases the area cost.

[0034] In order to solve the problems in the prior art, embodiments of the present disclosure provide an improved charge pump circuit.

[0035] FIG1 illustrates a charge pump circuit according to a preferred embodiment of the present disclosure. The charge pump circuit includes a detection feedback stage, an error amplifier stage, and a charge pump stage. The detection feedback stage includes a voltage differential detection unit and a feedback network. The input voltage VIN and the output voltage VCP are connected to the two input terminals of the voltage differential detection unit. The output terminal of the voltage differential detection unit is connected to one end of the feedback network and to the first input terminal of the error amplifier stage. FIG1 illustrates that the first input terminal of the error amplifier stage is negative, but this is merely exemplary and the present invention is not limited to this. The other end of the feedback network is connected to a reference potential. FIG1 illustrates that the reference potential is ground, but this is merely exemplary and the present invention is not limited to this. The detection feedback stage detects the voltage difference between the output voltage VCP of the charge pump and the input voltage VIN, generating a feedback voltage VFB. The feedback voltage VFB is input to the first input terminal of the error amplifier stage. In an exemplary embodiment, the first input terminal of the error amplifier stage is either an inverting input terminal or a non-inverting input terminal, and the second input terminal of the error amplifier stage is either a non-inverting input terminal or an inverting input terminal. Alternatively, the first input terminal of the error amplifying stage is a non-inverting input terminal or an inverting input terminal, and the second input terminal of the error amplifying stage is an inverting input terminal or a non-inverting input terminal.

[0036] Referring to Figure 1, the charge pump circuit of the preferred embodiment of the present disclosure is a closed-loop circuit. The output voltage VCP is connected to a detection feedback stage and compared with the input voltage VIN to generate a voltage difference. This voltage difference is input to the error amplifier stage as the feedback voltage VFB. The detection feedback stage of the charge pump circuit is used to generate a feedback voltage based on the input voltage and the output voltage. This design allows the output signal of the charge pump circuit to be fed back to the input terminal in real time. In this closed-loop charge pump circuit, the voltage and current in the circuit can be adjusted in real time based on the feedback results through circuit design, thereby achieving the advantages of improving the performance and stability of the circuit.

[0037] Continuing with Figure 1 , the output signal of the detection feedback stage is transmitted to the error amplifier stage. The error amplifier stage of the charge pump circuit includes a first input terminal (e.g., a negative terminal), a second input terminal (e.g., a positive terminal), and an amplifier output terminal. The first input terminal (e.g., a negative terminal) of the error amplifier stage receives the feedback voltage VFB, and the second input terminal (e.g., a positive terminal) of the error amplifier stage receives the reference voltage Vref. The reference voltage Vref is preset. The amplifier output terminal of the error amplifier stage can be connected to the control terminal (gate) of the first power transistor M1 of the charge pump stage. The error amplifier stage amplifies the voltage difference between VFB and Vref, and the amplifier output terminal of the error amplifier stage outputs the amplified first voltage VG1 to the control terminal of the first power transistor M1 of the charge pump stage. In the embodiment of Figure 1 , the first input terminal of the error amplifier stage can be a negative terminal, and the second input terminal can be a positive terminal, but the present invention is not limited to this.

[0038] The error amplifier stage can be used to amplify the slight difference in the input signal to a range that can be measured, thereby allowing it to be detected and measured. The error amplifier stage can accurately detect changes in voltage. As shown in Figure 1, the error amplifier stage is used to amplify the voltage difference between the feedback voltage and the reference voltage. In other words, the error amplifier stage is used to output a first voltage based on the feedback voltage and the reference voltage. The feedback voltage and the reference voltage are compared and amplified by the error amplifier stage, so that the first voltage output by the error amplifier stage can change with the change of the feedback voltage, thereby causing the output voltage of the charge pump stage to change, thereby achieving the purpose of automatically adjusting the voltage in the closed-loop circuit. At the same time, the error amplifier stage can also enhance stability by adding a compensation capacitor on the feedback path to prevent oscillation and shock. In an exemplary embodiment, the error amplifier stage is preferably an error amplifier.

[0039] Continuing with Figure 1 , the output signal of the error amplifier stage is transmitted to the charge pump stage. The charge pump stage includes a first power transistor M1, a first capacitor C1, a first switch S1, a second switch S2, a third switch S3, and a fourth switch S4. The charge pump stage has an input voltage VIN and an output voltage VCP. The nodes at one end of the first capacitor C1 are connected to the input voltage VIN through the first switch S1 and to the output voltage VCP through the fourth switch S4. The nodes at the other end of the first capacitor C1 are connected to the input voltage VIN through the third switch S3 and to the first electrode (e.g., the drain) of the first power transistor M1 through the second switch S2. The second electrode (e.g., the source) of the first power transistor M1 is connected to a reference potential. As described above, the input voltage VIN and the output voltage VCP are also connected to the voltage difference detection unit of the detection feedback stage. In the embodiment of Figure 1 , the first electrode of the first power transistor M1 can be a drain, the second electrode can be a source, and the reference potential is ground, but the present invention is not limited to this.

[0040] The charge pump stage shown in Figure 1 operates in two phases: In the first phase, the first and second switches S1, S2 are closed, and the third and fourth switches S3, S4 are open. The input voltage VIN is connected to the first electrode (e.g., drain) of the first power transistor M1 via the closed first switch S1, the first capacitor C1, and the closed second switch S2. During this first phase, the charge pump stage charges the first capacitor C1 via the first power transistor M1, with the charging current regulated by the loop based on the load. In the second phase, the first and second switches S1, S2 are open, and the third and fourth switches S3, S4 are closed. The input voltage VIN is connected to the output voltage VCP via the closed third switch S3, the first capacitor C1, and the closed fourth switch S4. During this second phase, the charge pump stage supplies power to the load at the output voltage VCP via the first capacitor C1. Thus, the preferred embodiment of the present disclosure achieves input voltage to output voltage conversion.

[0041] The charge pump stage is used to convert the input voltage into the output voltage. The first power tube M1 in the charge pump stage is used to form a current flowing therethrough, and the current in the first power tube M1 can change according to the change of the control terminal voltage, thereby changing the current in response to the change of the control terminal voltage and thus changing the output voltage, thereby achieving the function of automatically adjusting the voltage. In an exemplary embodiment, the control terminal voltage can be a voltage signal output from the amplified output terminal of the error amplifier stage. Specifically, the function of adjusting the voltage of the embodiment of the present disclosure is achieved in the following manner: (1) If the feedback voltage VFB increases, the reference voltage Vref is unchanged, and the feedback voltage is connected to the first input terminal (for example, the negative electrode) of the error amplifier stage, so the first voltage VG1 output from the error amplifier stage decreases as the feedback voltage increases. Since the voltage on the control terminal of the first power tube (the first voltage VG1) decreases, the current flowing through the first power tube becomes smaller. As the current flowing through the first power tube decreases, the charge charged to the first capacitor C1 decreases, thereby reducing the output voltage VCP. As the output voltage decreases, the feedback voltage output by the voltage difference detection unit decreases. The above cycle achieves the effect of lowering the feedback voltage when the feedback voltage is high. (2) On the contrary, if the feedback voltage VFB decreases, the reference voltage Vref remains unchanged, and the feedback voltage is connected to the first input terminal (for example, the negative electrode) of the error amplifier stage, so the first voltage VG1 output from the error amplifier stage increases as the feedback voltage decreases. Since the voltage on the control terminal of the first power tube (the first voltage VG1) increases, the current flowing through the first power tube becomes larger. As the current flowing through the first power tube increases, the charge charged to the first capacitor C1 increases, thereby increasing the output voltage VCP. As the output voltage increases, the feedback voltage output by the voltage difference detection unit increases. The above cycle achieves the effect of raising the feedback voltage when the feedback voltage is low. Therefore, the embodiment of the present disclosure can adjust the voltage conversion amplitude according to the voltage signal output by the error amplifier stage. It can be seen that through the design of the charge pump circuit and the characteristics of each component, automatic voltage adjustment is achieved.

[0042] Figure 2 shows a charge pump circuit according to a preferred embodiment of the present disclosure. The charge pump circuit includes a detection feedback stage, an error amplifier stage, and a charge pump stage. The charge pump stage comprises N charge pump units, which are connected to form an N-phase charge pump structure, where N is a positive integer. Figure 2 illustrates a dual-phase charge pump structure, but the present invention is not limited to this. The detection feedback stage includes a voltage difference detection unit and a feedback network. The input voltage VIN and the output voltage VCP are connected to the two input terminals of the voltage difference detection unit. The output terminal of the voltage difference detection unit is connected to one terminal of the feedback network and to the first input terminal of the error amplifier stage. Figure 2 shows the first input terminal of the error amplifier stage as negative, but this is for illustrative purposes only and the present invention is not limited to this. The other terminal of the feedback network is connected to a reference potential. Figure 2 shows the reference potential as ground, but this is for illustrative purposes only and the present invention is not limited to this. The detection feedback stage detects the voltage difference between the charge pump output voltage VCP and the input voltage VIN to generate a feedback voltage VFB. The feedback voltage VFB is input to the first input terminal of the error amplifier stage. In an exemplary embodiment, the first input terminal of the error amplifier stage is an inverting input terminal or a non-inverting input terminal, and the second input terminal of the error amplifier stage is a non-inverting input terminal or an inverting input terminal. Alternatively, the first input terminal of the error amplifier stage is a non-inverting input terminal or an inverting input terminal, and the second input terminal of the error amplifier stage is an inverting input terminal or a non-inverting input terminal.

[0043] The charge pump circuit shown in Figure 2 is a closed-loop circuit. The output voltage, VCP, is connected to a detection feedback stage, where it is compared with the input voltage, VIN, generating a voltage difference. This voltage difference, serving as feedback voltage, VFB, is input to the error amplifier stage. The detection feedback stage of the charge pump circuit generates a feedback voltage based on the input and output voltages. This design allows the output signal of the charge pump circuit to be fed back to the input in real time. In this closed-loop charge pump circuit, the circuit design allows for real-time adjustments to the voltage and current in the circuit based on the feedback results, thereby improving circuit performance and stability.

[0044] Continuing with Figure 2 , the output signal of the detection feedback stage is transmitted to the error amplifier stage. The error amplifier stage of the charge pump circuit includes a first input terminal (e.g., a negative terminal), a second input terminal (e.g., a positive terminal), and an amplifier output terminal. The first input terminal (e.g., a negative terminal) of the error amplifier stage receives the feedback voltage VFB, and the second input terminal (e.g., a positive terminal) of the error amplifier stage receives the reference voltage Vref. The reference voltage Vref is preset. The amplifier output terminal of the error amplifier stage is connected to the control terminal (gate) of the first power transistor M1 of the charge pump stage. The error amplifier stage amplifies the voltage difference between VFB and Vref, and the amplifier output terminal of the error amplifier stage outputs the amplified first voltage VG1 to the control terminal of the first power transistor M1 of the charge pump stage. In the embodiment of Figure 2 , the first input terminal of the error amplifier stage can be a negative terminal, and the second input terminal can be a positive terminal, but the present invention is not limited to this.

[0045] As shown in Figure 2, the error amplifier stage is used to amplify the voltage difference between the feedback voltage and the reference voltage. In other words, the error amplifier stage is used to output a first voltage based on the feedback voltage and the reference voltage. By comparing and amplifying the feedback voltage and the reference voltage through the error amplifier stage, the first voltage output by the error amplifier stage can change with changes in the feedback voltage, thereby causing the output voltage of the charge pump stage to change, thereby achieving the purpose of automatically adjusting the voltage in the closed-loop circuit. At the same time, the error amplifier stage can also enhance stability by adding a compensation capacitor in the feedback path to prevent oscillation and vibration. In an exemplary embodiment, the error amplifier stage is preferably an error amplifier.

[0046] Continuing with Figure 2, taking a dual-phase charge pump structure as an example, the output signal of the error amplifier stage is transmitted to the charge pump stage. The charge pump stage includes a first power transistor M1, a first capacitor C1, a second capacitor C2, a first switch S1, a second switch S2, a third switch S3, a fourth switch S4, a fifth switch S5, a sixth switch S6, a seventh switch S7, and an eighth switch S8. The charge pump stage has an input voltage VIN and an output voltage VCP. The nodes at one end of the first capacitor C1 are connected to the input voltage VIN through the first switch S1 and to the output voltage VCP through the fourth switch S4. The nodes at the other end of the first capacitor C1 are connected to the input voltage VIN through the third switch S3 and to the first electrode (e.g., the drain) of the first power transistor M1 through the second switch S2. The nodes at one end of the second capacitor C2 are connected to the input voltage VIN through the fifth switch S5 and to the output voltage VCP through the eighth switch S8. The nodes at the other end of the second capacitor C2 are connected to the input voltage VIN through the seventh switch S7 and to the first electrode (e.g., the drain) of the first power transistor M1 through the sixth switch S6. The second electrode (e.g., source) of the first power transistor M1 is connected to a reference potential. As described above, the input voltage VIN and the output voltage VCP are also connected to the voltage difference detection unit of the detection feedback stage. In the embodiment of Figure 2 , the first electrode of the first power transistor M1 can be a drain, the second electrode can be a source, and the reference potential is ground, but the present invention is not limited to this.

[0047] The charge pump stage circuit shown in Figure 2 operates in two phases: In the first phase, the first and second switches S1 and S2 are closed, while the third and fourth switches S3 and S4 are open. The input voltage VIN is connected to the first electrode (e.g., the drain) of the first power transistor M1 via the closed first switch S1, the first capacitor C1, and the closed second switch S2. During this first phase, the charge pump stage charges the first capacitor C1 via the first power transistor M1, with the charging current regulated by the loop based on the load. Simultaneously, the fifth and sixth switches S5 and S6 are open, while the seventh and eighth switches S7 and S8 are closed. The input voltage VIN is connected to the output voltage VCP via the closed seventh switch S7, the second capacitor C2, and the closed eighth switch S8. During this first phase, the charge pump stage supplies power to the load at the output voltage VCP via the second capacitor C2.

[0048] In the second phase, the first switch S1 and the second switch S2 are open, and the third switch S3 and the fourth switch S4 are closed. The input voltage VIN is connected to the output voltage VCP via the closed third switch S3, the first capacitor C1, and the closed fourth switch S4. During this second phase, the charge pump stage supplies power to the load at the output voltage VCP via the first capacitor C1. Simultaneously, the fifth switch S5 and the sixth switch S6 are closed, and the seventh switch S7 and the eighth switch S8 are open. The input voltage VIN is connected to the first electrode (e.g., the drain) of the first power transistor M1 via the closed fifth switch S5, the second capacitor C2, and the closed sixth switch S6. During this second phase, the charge pump stage charges the second capacitor C2 via the first power transistor M1, with the charging current being regulated by the loop based on the load. Thus, the preferred embodiment of the present disclosure achieves conversion from input voltage to output voltage.

[0049] A dual-phase charge pump stage can alternately charge and discharge two capacitors, thereby improving the efficiency of the charge pump. Similarly, a multi-phase charge pump stage can alternately charge and discharge multiple capacitors, thereby improving the efficiency of the charge pump.

[0050] Figure 3 shows a charge pump circuit according to a preferred embodiment of the present disclosure. The charge pump circuit includes a detection and feedback stage, an error amplifier stage, and a charge pump stage. The charge pump stage comprises N charge pump units connected in cascade (series), where N is a positive integer. Figure 3 illustrates a two-stage charge pump structure, but the present invention is not limited to this. The detection and feedback stage includes a voltage difference detection unit and a feedback network. The input voltage VIN and the output voltage VCP are connected to the two input terminals of the voltage difference detection unit. The output terminal of the voltage difference detection unit is connected to one terminal of the feedback network and to the first input terminal of the error amplifier stage. Figure 3 shows the first input terminal of the error amplifier stage as negative, but this is for illustrative purposes only and the present invention is not limited to this. The other terminal of the feedback network is connected to a reference potential. Figure 3 shows the reference potential as ground, but this is for illustrative purposes only and the present invention is not limited to this. The detection and feedback stage detects the voltage difference between the charge pump output voltage VCP and the input voltage VIN to generate a feedback voltage VFB. The feedback voltage VFB is input to the first input terminal of the error amplifier stage. In an exemplary embodiment, the first input terminal of the error amplifier stage is an inverting input terminal or a non-inverting input terminal, and the second input terminal of the error amplifier stage is a non-inverting input terminal or an inverting input terminal. Alternatively, the first input terminal of the error amplifier stage is a non-inverting input terminal or an inverting input terminal, and the second input terminal of the error amplifier stage is an inverting input terminal or a non-inverting input terminal.

[0051] The charge pump circuit shown in Figure 3 is a closed-loop circuit. The output voltage, VCP, is connected to a detection feedback stage, where it is compared with the input voltage, VIN, generating a voltage difference. This voltage difference, serving as feedback voltage, VFB, is input to the error amplifier stage. The detection feedback stage of the charge pump circuit generates a feedback voltage based on the input and output voltages. This design allows the output signal of the charge pump circuit to be fed back to the input in real time. In this closed-loop charge pump circuit, the circuit design allows for real-time adjustments to the voltage and current in the circuit based on the feedback results, thereby improving circuit performance and stability.

[0052] Continuing with Figure 3 , the output signal of the detection feedback stage is transmitted to the error amplifier stage. The error amplifier stage includes a first input terminal (e.g., a negative terminal), a second input terminal (e.g., a positive terminal), and an amplifier output terminal. The first input terminal (e.g., a negative terminal) of the error amplifier stage receives the feedback voltage VFB, and the second input terminal (e.g., a positive terminal) of the error amplifier stage receives the reference voltage Vref. The reference voltage Vref is preset. The amplifier output terminal of the error amplifier stage is connected to the control terminal (gate) of the first power transistor M1 of the charge pump stage. The error amplifier stage amplifies the voltage difference between VFB and Vref, and the amplifier output terminal of the error amplifier stage outputs the amplified first voltage VG1 to the control terminal of the first power transistor M1 of the charge pump stage. In the embodiment of Figure 3 , the first input terminal of the error amplifier stage can be a negative terminal, and the second input terminal can be a positive terminal, but the present invention is not limited to this.

[0053] As shown in Figure 3, the error amplifier stage is used to amplify the voltage difference between the feedback voltage and the reference voltage. In other words, the error amplifier stage is used to output a first voltage based on the feedback voltage and the reference voltage. By comparing and amplifying the feedback voltage and the reference voltage through the error amplifier stage, the first voltage output by the error amplifier stage can change with changes in the feedback voltage, thereby causing the output voltage of the charge pump stage to change, thereby achieving the purpose of automatically adjusting the voltage in the closed-loop circuit. At the same time, the error amplifier stage can also enhance stability by adding a compensation capacitor in the feedback path to prevent oscillation and vibration. In an exemplary embodiment, the error amplifier stage is preferably an error amplifier.

[0054] Continuing with Figure 3, taking a two-stage cascade charge pump structure as an example, the output signal of the error amplifier stage is transmitted to the charge pump stage. The charge pump stage includes a first power transistor M1, a first capacitor C1, a second capacitor C2, a first switch S1, a second switch S2, a third switch S3, a fourth switch S4, a fifth switch S5, a sixth switch S6, a seventh switch S7, and an eighth switch S8. The charge pump stage has an input voltage VIN and an output voltage VCP. The nodes at one end of the first capacitor C1 are connected to the input voltage VIN via the first switch S1 and to the next (second) stage charge pump unit via the fourth switch S4. The nodes at the other end of the first capacitor C1 are connected to the input voltage VIN via the third switch S3 and to the first electrode (e.g., drain) of the first power transistor M1 via the second switch S2. The nodes at one end of the second capacitor C2 are connected to the previous (first) stage charge pump unit via the fifth switch S5 and to the output voltage VCP via the eighth switch S8. The other end of the second capacitor C2 is connected to the previous (first-stage) charge pump unit via the seventh switch S7 and to the first electrode (e.g., drain) of the first power transistor M1 via the sixth switch S6. The second electrode (e.g., source) of the first power transistor M1 is connected to a reference potential. As described above, the input voltage VIN and the output voltage VCP are also connected to the voltage difference detection unit of the feedback stage. In the embodiment of Figure 3, the first electrode of the first power transistor M1 can be a drain, the second electrode can be a source, and the reference potential is ground, but the present invention is not limited to this.

[0055] The charge pump stage circuit shown in Figure 3 operates in two phases. In the first phase, the first and second switches S1 and S2 are closed, while the third and fourth switches S3 and S4 are open. The input voltage VIN is connected to the first electrode (e.g., drain) of the first power transistor M1 via the closed first switch S1, the first capacitor C1, and the closed second switch S2. During this first phase, the charge pump stage charges the first capacitor C1 via the first power transistor M1, with the charging current regulated by the loop based on the load. Simultaneously, the fifth and sixth switches S5 and S6 are open, while the seventh and eighth switches S7 and S8 are closed. The charge pump unit of the previous stage (the first stage) is connected to the output voltage VCP via the closed seventh switch S7, the second capacitor C2, and the closed eighth switch S8. During this first phase, the charge pump stage supplies power to the load at the output voltage VCP via the second capacitor C2.

[0056] In the second phase, the first and second switches S1 and S2 are open, while the third and fourth switches S3 and S4 are closed. The input voltage VIN is connected to the next (second) charge pump unit via the closed third switch S3, the first capacitor C1, and the closed fourth switch S4. During this second phase, the charge pump stage converts the voltage to a higher output voltage of the previous (first) stage via the first capacitor C1. Simultaneously, the fifth and sixth switches S5 and S6 are closed, while the seventh and eighth switches S7 and S8 are open. The previous (first) output voltage is connected to the first electrode (e.g., drain) of the first power transistor M1 via the closed fifth switch S5, the second capacitor C2, and the closed sixth switch S6. During this second phase, the charge pump stage charges the second capacitor C2 via the first power transistor M1, with the charging current regulated by the loop based on the load. Thus, preferred embodiments of the present disclosure achieve input voltage to output voltage conversion.

[0057] By cascading two charge pump stages, it is equivalent to connecting two capacitors in series, thereby converting the voltage to a higher level. Similarly, in the case of multi-stage cascade charge pump stages, it is equivalent to connecting multiple capacitors in series, thereby converting the voltage to a higher level.

[0058] Figure 4 shows a charge pump circuit according to a preferred embodiment of the present disclosure. The charge pump circuit includes a detection feedback stage, an error amplifier stage, a buffer stage, and a charge pump stage. The detection feedback stage includes a voltage difference detection unit and a feedback network. The input voltage VIN and the output voltage VCP are connected to the two inputs of the voltage difference detection unit. The output of the voltage difference detection unit is connected to one end of the feedback network and to the first input of the error amplifier stage. Figure 4 shows the first input of the error amplifier stage as positive, but this is for illustrative purposes only and the present invention is not limited to this. The other end of the feedback network is connected to a reference potential. Figure 4 shows the reference potential as ground, but this is for illustrative purposes only and the present invention is not limited to this. The other end of the feedback network is connected to a reference potential. Figure 4 shows the reference potential as ground, but this is for illustrative purposes only and the present invention is not limited to this. The detection feedback stage detects the voltage difference between the charge pump output voltage VCP and the input voltage VIN to generate a feedback voltage VFB. The feedback voltage VFB is input to the first input of the error amplifier stage. In an exemplary embodiment, the first input of the error amplifier stage is either the inverting input or the non-inverting input, and the second input of the error amplifier stage is either the non-inverting input or the inverting input. Alternatively, the first input terminal of the error amplifying stage is a non-inverting input terminal or an inverting input terminal, and the second input terminal of the error amplifying stage is an inverting input terminal or a non-inverting input terminal.

[0059] The charge pump circuit shown in Figure 4 is a closed-loop circuit. The output voltage, VCP, is connected to a detection feedback stage, where it is compared with the input voltage, VIN, generating a voltage difference. This voltage difference, serving as feedback voltage, VFB, is input to the error amplifier stage. The detection feedback stage of the charge pump circuit generates a feedback voltage based on the input and output voltages. This design allows the output signal of the charge pump circuit to be fed back to the input in real time. In this closed-loop charge pump circuit, the circuit design allows for real-time adjustment of the voltage and current based on the feedback, thereby improving circuit performance and stability.

[0060] Continuing with FIG4 , the output signal of the detection feedback stage is transmitted to the error amplifier stage. The error amplifier stage includes a first input terminal (e.g., a positive terminal), a second input terminal (e.g., a negative terminal), and an amplifier output terminal. The first input terminal (e.g., a positive terminal) of the error amplifier stage receives the feedback voltage VFB, and the second input terminal (e.g., a negative terminal) of the error amplifier stage receives the reference voltage Vref. The reference voltage Vref is preset. The amplifier output terminal of the error amplifier stage is connected to the control terminal (gate) of the third power transistor M3 of the buffer stage. The error amplifier stage amplifies the voltage difference between VFB and Vref, and the amplifier output terminal of the error amplifier stage outputs the amplified second voltage VG2 to the control terminal of the third power transistor M3 of the buffer stage. In the embodiment of FIG4 , the first input terminal of the error amplifier stage can be a positive terminal, and the second input terminal can be a negative terminal, but the present invention is not limited to this.

[0061] The buffer stage includes a second power transistor M2 and a third power transistor M3. The control terminal (gate) of the second power transistor M2 is connected to the control terminal (gate) of the first power transistor M1 of the charge pump stage. The first electrode (e.g., drain) of the second power transistor M2 is connected to the first electrode (e.g., drain) of the third power transistor M3 and to the control terminal of the second power transistor M2. The second electrode (e.g., source) of the second power transistor M2 is connected to a reference potential. The control terminal of the third power transistor M3 is connected to the amplified output terminal of the error amplifier stage and receives the second voltage VG2 from the error amplifier stage. The first electrode (e.g., drain) of the third power transistor M3 is connected to the first electrode (e.g., drain) of the second power transistor M2 and to the control terminal of the second power transistor M2. The second electrode (e.g., source) of the third power transistor M3 is connected to the operating voltage VDD. The buffer stage is used to regulate the current of the first power transistor M1 of the charge pump stage. The buffer stage provides isolation between circuits, preventing interference from the input and other circuits from affecting the output. Furthermore, the buffer ensures stable and accurate signal transmission.

[0062] Continuing with Figure 4 , the output signal of the buffer stage is transmitted to the charge pump stage. The charge pump stage includes a first power transistor M1, a first capacitor C1, a first switch S1, a second switch S2, a third switch S3, and a fourth switch S4. The charge pump stage circuit has an input voltage VIN and an output voltage VCP. The nodes at one end of the first capacitor C1 are connected to the input voltage VIN through the first switch S1 and to the output voltage VCP through the fourth switch S4. The nodes at the other end of the first capacitor C1 are connected to the input voltage VIN through the third switch S3 and to the first electrode (e.g., the drain) of the first power transistor M1 through the second switch S2. The second electrode (e.g., the source) of the first power transistor M1 is connected to a reference potential. As described above, the input voltage VIN and the output voltage VCP are also connected to the voltage difference detection unit of the detection feedback stage. In the embodiment of Figure 4 , the first electrode of the first power transistor M1 can be a drain and the second electrode can be a source; the first electrode of the second power transistor M2 can be a drain and the second electrode can be a source; the first electrode of the third power transistor M3 can be a drain and the second electrode can be a source. The reference potential is ground, but the present invention is not limited to this.

[0063] The operation process of the charge pump stage circuit shown in FIG4 is similar to that of the charge pump stage circuit shown in FIG1 , and will not be described in detail here.

[0064] The charge pump stage is used to convert the input voltage into the output voltage. Specifically, the voltage adjustment function of the embodiment of the present disclosure is achieved in the following manner: (1) If the feedback voltage VFB increases, the reference voltage Vref remains unchanged, and the feedback voltage is connected to the first input terminal (e.g., the positive electrode) of the error amplifier stage, so the second voltage VG2 output from the error amplifier stage increases as the feedback voltage increases. Since the voltage (second voltage VG2) on the control terminal of the third power tube M3 increases, the driving voltage Vgs of the third power tube M3 decreases, so the current flowing through the third power tube M3 decreases, and the current flowing through the second power tube M2 also decreases. As the current flowing through the second power tube M2 decreases, the first voltage VG1 on the control terminal of the second power tube M2 decreases, so the current flowing through the first power tube M1 decreases. As the current flowing through the first power tube M1 decreases, the charge charged to the first capacitor C1 decreases, thereby reducing the output voltage VCP. As the output voltage decreases, the feedback voltage output by the voltage difference detection unit decreases. The above cycle achieves the effect of lowering the feedback voltage when the feedback voltage is high. (2) On the contrary, if the feedback voltage VFB decreases, the reference voltage Vref remains unchanged, and the feedback voltage is connected to the first input terminal (for example, the positive electrode) of the error amplifier stage, so the second voltage VG2 output from the error amplifier stage decreases as the feedback voltage decreases. Since the voltage (second voltage VG2) on the control terminal of the third power tube M3 decreases, the driving voltage Vgs of the third power tube M3 increases, so the current flowing through the third power tube M3 increases, and the current flowing through the second power tube M2 also increases. As the current flowing through the second power tube M2 increases, the first voltage VG1 at the control terminal of the second power tube M2 increases, so the current flowing through the first power tube M1 increases. As the current flowing through the first power tube M1 increases, the charge charged to the first capacitor C1 increases, thereby increasing the output voltage VCP. As the output voltage increases, the feedback voltage output by the voltage difference detection unit increases. The above cycle achieves the effect of raising the feedback voltage when the feedback voltage is low. Therefore, the embodiments of the present disclosure can adjust the voltage conversion amplitude according to the voltage signal output by the error amplification stage.

[0065] Figure 5 illustrates a charge pump circuit according to a preferred embodiment of the present disclosure. The charge pump circuit includes a detection feedback stage, an error amplifier stage, a buffer stage, and a charge pump stage. The charge pump stage comprises N charge pump units, which are connected to form an N-phase charge pump structure, where N is a positive integer. Figure 5 illustrates a dual-phase charge pump structure, but the present invention is not limited to this. The detection feedback stage includes a voltage difference detection unit and a feedback network. The input voltage VIN and the output voltage VCP are connected to the two input terminals of the voltage difference detection unit. The output terminal of the voltage difference detection unit is connected to one terminal of the feedback network and to the first input terminal of the error amplifier stage. Figure 2 shows the first input terminal of the error amplifier stage as positive, but this is for illustrative purposes only and the present invention is not limited to this. The other terminal of the feedback network is connected to a reference potential. Figure 5 shows the reference potential as ground, but this is for illustrative purposes only and the present invention is not limited to this. The detection feedback stage detects the voltage difference between the charge pump output voltage VCP and the input voltage VIN to generate a feedback voltage VFB. The feedback voltage VFB is input to the first input terminal of the error amplifier stage. In an exemplary embodiment, the first input terminal of the error amplifier stage is an inverting input terminal or a non-inverting input terminal, and the second input terminal of the error amplifier stage is a non-inverting input terminal or an inverting input terminal. Alternatively, the first input terminal of the error amplifier stage is a non-inverting input terminal or an inverting input terminal, and the second input terminal of the error amplifier stage is an inverting input terminal or a non-inverting input terminal.

[0066] Continuing with Figure 5 , the output signal of the detection feedback stage is transmitted to the error amplifier stage. The error amplifier stage includes a first input terminal (e.g., a positive terminal), a second input terminal (e.g., a negative terminal), and an amplifier output terminal. The first input terminal (e.g., a positive terminal) of the error amplifier stage receives the feedback voltage VFB, and the second input terminal (e.g., a negative terminal) of the error amplifier stage receives the reference voltage Vref. The reference voltage Vref is preset. The amplifier output terminal of the error amplifier stage is connected to the control terminal (gate) of the first power transistor M1 of the charge pump stage. The error amplifier stage amplifies the voltage difference between VFB and Vref, and the amplifier output terminal of the error amplifier stage outputs the amplified second voltage VG2 to the control terminal of the third power transistor M3 of the buffer stage. In the embodiment of Figure 5 , the first input terminal of the error amplifier stage can be a positive terminal, and the second input terminal can be a negative terminal, but the present invention is not limited to this.

[0067] The buffer stage includes a second power transistor M2 and a third power transistor M3. The control terminal (gate) of the second power transistor M2 is connected to the control terminal (gate) of the first power transistor M1 of the charge pump stage. The first electrode (e.g., drain) of the second power transistor M2 is connected to the first electrode (e.g., drain) of the third power transistor M3 and to the control terminal of the second power transistor M2. The second electrode (e.g., source) of the second power transistor M2 is connected to a reference potential. The control terminal of the third power transistor M3 is connected to the amplified output terminal of the error amplifier stage and receives the second voltage VG2 from the error amplifier stage. The first electrode (e.g., drain) of the third power transistor M3 is connected to the first electrode (e.g., drain) of the second power transistor M2 and to the control terminal of the second power transistor M2. The second electrode (e.g., source) of the third power transistor M3 is connected to the operating voltage VDD. The buffer stage is used to regulate the current of the first power transistor M1 of the charge pump stage. The buffer stage provides isolation between circuits, preventing interference from the input and other circuits from affecting the output. Furthermore, the buffer ensures stable and accurate signal transmission.

[0068] Continuing with Figure 5 , the output signal of the buffer stage is transmitted to the charge pump stage. The charge pump stage includes a first power transistor M1, a first capacitor C1, a second capacitor C2, a first switch S1, a second switch S2, a third switch S3, a fourth switch S4, a fifth switch S5, a sixth switch S6, a seventh switch S7, and an eighth switch S8. The charge pump stage circuit has an input voltage VIN and an output voltage VCP. One end node of the first capacitor C1 is connected to the input voltage VIN via the first switch S1 and to the output voltage VCP via the fourth switch S4. The other end node of the first capacitor C1 is connected to the input voltage VIN via the third switch S3 and to the first electrode (e.g., the drain) of the first power transistor M1 via the second switch S2. One end node of the second capacitor C2 is connected to the input voltage VIN via the fifth switch S5 and to the output voltage VCP via the eighth switch S8. The other end node of the second capacitor C2 is connected to the input voltage VIN via the seventh switch S7 and to the first electrode (e.g., the drain) of the first power transistor M1 via the sixth switch S6. The second electrode (e.g., the source) of the first power transistor M1 is connected to a reference potential. As described above, the input voltage VIN and the output voltage VCP are also connected to the voltage difference detection unit of the detection feedback stage. In the embodiment of FIG5 , the first electrode of the first power transistor M1 can be a drain, and the second electrode can be a source; the first electrode of the second power transistor M2 can be a drain, and the second electrode can be a source; the first electrode of the third power transistor M3 can be a drain, and the second electrode can be a source. The reference potential is ground, but the present invention is not limited to this.

[0069] The operation process of the charge pump stage circuit shown in FIG5 is similar to that of the charge pump stage circuit shown in FIG2 , and will not be described in detail here.

[0070] The working principle of adjusting the voltage of the charge pump stage circuit shown in FIG5 is similar to the working principle of adjusting the voltage of the charge pump stage circuit shown in FIG4 , and will not be described in detail here.

[0071] Figure 6 illustrates a charge pump circuit according to a preferred embodiment of the present disclosure. The charge pump circuit includes a detection feedback stage, an error amplifier stage, and a charge pump stage. The charge pump stage comprises N charge pump units connected in cascade (series), where N is a positive integer. Figure 6 illustrates a two-stage charge pump structure, but the present invention is not limited to this. The detection feedback stage includes a voltage difference detection unit and a feedback network. The input voltage VIN and the output voltage VCP are connected to the two input terminals of the voltage difference detection unit. The output terminal of the voltage difference detection unit is connected to one terminal of the feedback network and to the first input terminal of the error amplifier stage. Figure 6 shows that the first input terminal of the error amplifier stage is positive, but this is merely an example and the present invention is not limited to this. The other terminal of the feedback network is connected to ground. The detection feedback stage detects the voltage difference between the charge pump output voltage VCP and the input voltage VIN to generate a feedback voltage VFB. The feedback voltage VFB is input to the first input terminal of the error amplifier stage. In an exemplary embodiment, the first input terminal of the error amplifier stage is either the inverting input terminal or the non-inverting input terminal, and the second input terminal of the error amplifier stage is either the non-inverting input terminal or the inverting input terminal. Alternatively, the first input terminal of the error amplifying stage is a non-inverting input terminal or an inverting input terminal, and the second input terminal of the error amplifying stage is an inverting input terminal or a non-inverting input terminal.

[0072] Continuing with Figure 6 , the output signal of the detection feedback stage is transmitted to the error amplifier stage. The error amplifier stage includes a first input terminal (e.g., a positive terminal), a second input terminal (e.g., a negative terminal), and an amplifier output terminal. The first input terminal (e.g., a positive terminal) of the error amplifier stage receives the feedback voltage VFB, and the second input terminal (e.g., a negative terminal) of the error amplifier stage receives the reference voltage Vref. The reference voltage Vref is preset. The amplifier output terminal of the error amplifier stage is connected to the control terminal (gate) of the first power transistor M1 of the charge pump stage. The error amplifier stage amplifies the voltage difference between VFB and Vref, and the amplifier output terminal of the error amplifier stage outputs the amplified second voltage VG2 to the control terminal of the third power transistor M3 of the buffer stage. In the embodiment of Figure 6 , the first input terminal of the error amplifier stage can be a positive terminal, and the second input terminal can be a negative terminal, but the present invention is not limited to this.

[0073] The buffer stage includes a second power transistor M2 and a third power transistor M3. The control terminal (gate) of the second power transistor M2 is connected to the control terminal (gate) of the first power transistor M1 of the charge pump stage. The first electrode (e.g., drain) of the second power transistor M2 is connected to the first electrode (e.g., drain) of the third power transistor M3 and to the control terminal of the second power transistor M2. The second electrode (e.g., source) of the second power transistor M2 is connected to a reference potential. The control terminal of the third power transistor M3 is connected to the amplifier output terminal of the error amplifier stage and receives the second voltage VG2 from the error amplifier stage. The first electrode (e.g., drain) of the third power transistor M3 is connected to the first electrode (e.g., drain) of the second power transistor M2 and to the control terminal of the second power transistor M2. The second electrode (e.g., source) of the third power transistor M3 is connected to the operating voltage VDD. The buffer stage is used to regulate the current of the first power transistor M1 of the charge pump stage.

[0074] Continuing with Figure 6, taking a two-stage cascade charge pump structure as an example, the output signal of the buffer stage is transmitted to the charge pump stage. The charge pump stage includes a first power transistor M1, a first capacitor C1, a second capacitor C2, a first switch S1, a second switch S2, a third switch S3, a fourth switch S4, a fifth switch S5, a sixth switch S6, a seventh switch S7, and an eighth switch S8. The charge pump stage has an input voltage VIN and an output voltage VCP. The nodes at one end of the first capacitor C1 are connected to the input voltage VIN via the first switch S1 and to the next (second) stage charge pump unit via the fourth switch S4. The nodes at the other end of the first capacitor C1 are connected to the input voltage VIN via the third switch S3 and to the first electrode (e.g., drain) of the first power transistor M1 via the second switch S2. The nodes at one end of the second capacitor C2 are connected to the previous (first) stage charge pump unit via the fifth switch S5 and to the output voltage VCP via the eighth switch S8. The node at the other end of the second capacitor C2 is connected to the previous (first) stage charge pump unit via the seventh switch S7 and to the first electrode (e.g., drain) of the first power transistor M1 via the sixth switch S6. The second electrode (e.g., source) of the first power transistor M1 is connected to a reference potential. As described above, the input voltage VIN and the output voltage VCP are also connected to the voltage difference detection unit of the detection feedback stage. In the embodiment of FIG6 , the first electrode of the first power transistor M1 can be a drain, and the second electrode can be a source; the first electrode of the second power transistor M2 can be a drain, and the second electrode can be a source; the first electrode of the third power transistor M3 can be a drain, and the second electrode can be a source; and the reference potential is ground, but the present invention is not limited to this.

[0075] The operation process of the charge pump stage circuit shown in FIG6 is similar to that of the charge pump stage circuit shown in FIG3 , and will not be described in detail here.

[0076] The working principle of adjusting the voltage of the charge pump stage circuit shown in FIG6 is similar to the working principle of adjusting the voltage of the charge pump stage circuit shown in FIG4 , and will not be described in detail here.

[0077] Figure 7 illustrates a charge pump circuit according to a preferred embodiment of the present disclosure, which shows a preferred embodiment of a detection feedback stage. The detection feedback stage includes a fourth power transistor M4, a fifth power transistor M5, a first resistor R1, and a second resistor R2. An input voltage VIN is connected to the second electrode (e.g., source) of the fourth power transistor M4. The control terminal of the fourth power transistor M4 is connected to the control terminal of the fifth power transistor M5 and to the first electrode (e.g., drain) of the fourth power transistor M4. The first electrode (e.g., drain) of the fourth power transistor M4 is connected to one end of the first resistor R1 and to a reference potential. An output voltage VCP is connected to one end of the second resistor R2, the other end of which is connected to the second electrode (e.g., source) of the fifth power transistor M5. The control terminal of the fifth power transistor M5 is connected to the control terminal of the fourth power transistor M4. The first electrode (e.g., drain) of the fifth power transistor M5 is connected to the other end of the first resistor R1 and to the first input terminal (e.g., positive electrode) of the error amplifier stage. In the embodiment of FIG. 7 , the first electrode of the fourth power transistor M4 may be a drain, and the second electrode may be a source; the first electrode of the fifth power transistor M5 may be a drain, and the second electrode may be a source, and the reference potential is grounded, but the present invention is not limited thereto.

[0078] Preferably, the operating parameters of the fourth power transistor M4 and the fifth power transistor M5 are identical, thus forming a circuit similar to a current mirror. Since the operating parameters of the fourth power transistor M4 and the fifth power transistor M5 are identical, the voltages across them are equal, which allows the voltage division across the second resistor R2 to be determined, thereby deriving the current flowing through it. Therefore, by detecting the voltage difference between the output voltage VCP and the input voltage VIN through the bias circuit Ib, M4, M5, and the second resistor R2, the current (VCP-VIN) / R2 can be obtained. Using the current (VCP-VIN) / R2 flowing through R1, the feedback voltage VFB = (VCP-VIN) × R1 / R2 can be obtained.

[0079] From the above formula, we can get VCP - VIN = VFB × R2 / R1. When the loop is working properly, the feedback voltage is equal to the reference voltage, that is, VFB = Vref. Therefore, the boost voltage of the charge pump can be expressed as VCP - VIN = Vref × R2 / R1. It can be seen that the boost voltage of the charge pump can be precisely controlled by controlling the ratio of the second resistor R2 to the first resistor R1. In addition, when the input VIN voltage is low (VIN < Vref × R2 / R1), the first capacitor C1 can be charged up to the voltage of VIN at most, and the output voltage VCP can be boosted up to 2VIN at most. Thus, the boost ability when the input VIN is low is greatly improved. When the input VIN voltage is high, the first capacitor C1 is charged up to the voltage of Vref × R2 / R1 at most. Since Vref × R2 / R1 is much smaller than VIN, the AC loss during the operation of the charge pump is greatly reduced. In addition, in the charge pump circuit shown in FIG. 7, by reasonably designing the magnitude of Vref × R2 / R1, when the charge pumps are connected in series in multiple stages, the first capacitor C1, the first switch S1, the third switch S3, and the fourth switch S4 in each stage can all be implemented using low-voltage MOS transistors. In the prior art, since the boost of the charge pump is not controlled by designing Vref × R2 / R1, high-voltage MOS is required as the switch during use, and MIM or MOS is used as the FLY capacitor. Compared with the existing circuit, the embodiment of the present disclosure has a great area advantage.

[0080] FIG. 7 shows a preferred embodiment of the detection feedback stage. The detection feedback stage according to the preferred embodiment of the present disclosure is not limited thereto. In addition, the detection feedback stage shown in FIG. 7 can be used in combination with various charge pump stages, including but not limited to, a single-stage charge pump stage, a cascaded charge pump stage, and a multiphase charge pump stage. In addition, the detection feedback stage shown in FIG. 7 can be used in combination with a buffer stage or can be used without a buffer stage.

[0081] Figure 8 shows a negative voltage charge pump circuit according to a preferred embodiment of the present disclosure. The charge pump circuit includes a detection feedback stage, an error amplifier stage, a buffer stage, and a charge pump stage. The detection feedback stage includes a voltage differential detection unit and a feedback network. The output voltage VCP is connected to one input of the voltage differential detection unit, and the other input of the voltage differential detection unit is connected to a reference potential (e.g., ground). The output of the voltage differential detection unit is connected to one end of the feedback network and to the first input (e.g., the positive terminal) of the error amplifier stage. The other end of the feedback network is connected to the second electrode (e.g., the source) of the second power transistor M2 of the buffer stage and to the second electrode (e.g., the source) of the first power transistor M1 of the charge pump stage. The voltage at this end is the operating voltage VDD, which can serve as a reference potential for the feedback network. The detection feedback stage detects the voltage difference between the charge pump output voltage VCP and the reference potential to generate a feedback voltage VFB. The feedback voltage VFB is input to the first input (e.g., the positive terminal) of the error amplifier stage.

[0082] The error amplifier stage includes a first input terminal (e.g., a positive terminal), a second input terminal (e.g., a negative terminal), and an amplifier output terminal. The first input terminal (e.g., a positive terminal) receives the feedback voltage VFB, and the second input terminal (e.g., a negative terminal) receives the reference voltage Vref. The reference voltage Vref is preset. The error amplifier stage amplifies the voltage difference between VFB and Vref, and the amplifier output terminal of the error amplifier stage outputs the amplified second voltage VG2 to the control terminal of the third power transistor M3 of the buffer stage.

[0083] The buffer stage includes a second power transistor M2 and a third power transistor M3. The control terminal of the second power transistor M2 is connected to the control terminal of the first power transistor M1 of the charge pump stage. The first electrode (e.g., drain) of the second power transistor M2 is connected to the first electrode (e.g., drain) of the third power transistor M3 and to the control terminal of the second power transistor M2. The second electrode (e.g., source) of the second power transistor M2 is connected to an operating voltage. The control terminal of the third power transistor M3 is connected to the amplifier output terminal of the error amplifier stage and receives a second voltage VG2 from the error amplifier stage. The first electrode (e.g., drain) of the third power transistor M3 is connected to the first electrode (e.g., drain) of the second power transistor M2 and to the control terminal of the second power transistor M2. The second electrode (e.g., source) of the third power transistor M3 is connected to a reference potential (e.g., ground). The buffer stage is used to regulate the current in the first power transistor M1 of the charge pump stage.

[0084] The charge pump stage includes a first power transistor M1, a first capacitor C1, a first switch S1, a second switch S2, a third switch S3, and a fourth switch S4. The charge pump stage circuit has an operating voltage VDD and an output voltage VCP. The nodes at one end of the first capacitor C1 are connected to a reference potential (e.g., ground) via the first switch S1 and to the output voltage VCP via the fourth switch S4. The nodes at the other ends of the first capacitor C1 are connected to a reference potential (e.g., ground) via the third switch S3 and to the first electrode (e.g., drain) of the first power transistor M1 via the second switch S2. The second electrode (e.g., source) of the first power transistor M1 is connected to the operating voltage VDD.

[0085] FIG9 illustrates a negative voltage charge pump circuit according to a preferred embodiment of the present disclosure. The charge pump circuit includes a detection feedback stage, an error amplifier stage, a buffer stage, and a charge pump stage. The detection feedback stage includes a voltage differential detection unit and a feedback network. The output voltage VCP is connected to one input of the voltage differential detection unit, the other input of which is connected to a reference potential (e.g., ground). The output of the voltage differential detection unit is connected to one end of the feedback network and to the first input of the error amplifier stage (e.g., the negative terminal). The other end of the feedback network is connected to the reference potential (e.g., ground). The detection feedback stage detects the voltage difference between the charge pump output voltage VCP and the reference potential to generate a feedback voltage VFB. The feedback voltage VFB is input to the first input of the error amplifier stage (e.g., the negative terminal).

[0086] The error amplifier stage includes a first input terminal (e.g., a negative terminal), a second input terminal (e.g., a positive terminal), and an amplifier output terminal. The second input terminal (e.g., a positive terminal) receives the feedback voltage VFB, and the first input terminal (e.g., a negative terminal) receives the reference voltage Vref. The reference voltage Vref is preset. The error amplifier stage amplifies the voltage difference between VFB and Vref, and the amplifier output terminal of the error amplifier stage outputs the amplified second voltage VG2 to the control terminal of the third power transistor M3 of the buffer stage.

[0087] The buffer stage includes a second power transistor M2 and a third power transistor M3. The control terminal of the second power transistor M2 is connected to the control terminal of the first power transistor M1 of the charge pump stage. The first electrode (e.g., drain) of the second power transistor M2 is connected to the first electrode (e.g., drain) of the third power transistor M3 and to the control terminal of the second power transistor M2. The second electrode (e.g., source) of the second power transistor M2 is connected to the operating voltage VDD. The control terminal of the third power transistor M3 is connected to the amplifier output terminal of the error amplifier stage and receives the second voltage VG2 from the error amplifier stage. The first electrode (e.g., drain) of the third power transistor M3 is connected to the first electrode (e.g., drain) of the second power transistor M2 and to the control terminal of the second power transistor M2. The second electrode (e.g., source) of the third power transistor M3 is connected to a reference potential (e.g., ground). The buffer stage is used to regulate the current of the first power transistor M1 of the charge pump stage.

[0088] The charge pump stage includes a first power transistor M1, a first capacitor C1, a first switch S1, a second switch S2, a third switch S3, and a fourth switch S4. The charge pump stage circuit has an operating voltage VDD and an output voltage VCP. The nodes at one end of the first capacitor C1 are connected to a reference potential (e.g., ground) via the first switch S1 and to the output voltage VCP via the fourth switch S4. The nodes at the other ends of the first capacitor C1 are connected to a reference potential (e.g., ground) via the third switch S3 and to the first electrode (e.g., drain) of the first power transistor M1 via the second switch S2. The second electrode (e.g., source) of the first power transistor M1 is connected to the operating voltage VDD.

[0089] The technical effects of the embodiments disclosed herein include: it can be applied to both positive and negative charge pumps; the amplitude of boost or buck (conversion amplitude) can be adjusted; the power consumption of the charge pump varies according to the load, and the power consumption is lower under light load; it still has a high boost capability when the input voltage is low; in the case of multi-stage boost, the FLY capacitor of each stage can use MOS capacitors, and most switches can use low-voltage MOS, which has a good area advantage.

[0090] While various embodiments of the present disclosure have been described above, the above descriptions are illustrative, non-exhaustive, and not intended to be limiting of the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is selected to best explain the principles of the embodiments, their practical applications, or technological improvements in the marketplace, or to enable other persons skilled in the art to understand the embodiments disclosed herein.

Claims

1. A charge pump circuit, comprising: A detection feedback stage, a voltage input terminal and a voltage output terminal are connected to the detection feedback stage, and a feedback output terminal of the detection feedback stage generates a feedback voltage based on an output voltage from the voltage output terminal and an input voltage of the voltage input terminal; An error amplification stage, the feedback output terminal is connected to a first input terminal of the error amplification stage, so as to input the feedback voltage into the error amplification stage, a second input terminal of the error amplification stage receives a reference voltage signal, and the error amplification stage further includes an amplified output terminal for outputting a voltage signal; And A charge pump stage, the charge pump stage includes a charge pump unit, the charge pump unit is connected to the voltage input terminal, converts the input voltage of the voltage input terminal and outputs from the voltage output terminal, and the charge pump stage is further connected to the amplified output terminal for adjusting a voltage conversion amplitude according to the voltage signal output by the error amplification stage.

2. The charge pump circuit according to claim 1, wherein, The detection feedback stage includes a differential pressure detection unit and a feedback network, and the differential pressure detection unit obtains a differential pressure based on the output voltage and the input voltage and generates the feedback voltage through the feedback network.

3. The charge pump circuit according to claim 1, wherein, The charge pump stage includes a first power transistor, a first pole or a second pole of the first power transistor is connected to the charge pump unit, a control terminal of the first power transistor receives the voltage signal output by the amplified output terminal of the error amplification stage, and a current flowing through the first power transistor changes with the change of the voltage signal output by the amplified output terminal.

4. The charge pump circuit according to claim 3, wherein The charge pump circuit further includes a buffer stage between the error amplification stage and the charge pump stage, the amplified output terminal is connected to the buffer stage, and a buffered output terminal of the buffer stage is connected to the control terminal of the first power transistor.

5. The charge pump circuit according to claim 4, wherein the buffer stage includes a second power transistor and a third power transistor, a control terminal of the second power transistor is connected to a control terminal of the first power transistor of the charge pump stage, a first pole of the second power transistor is connected to a first pole of the third power transistor and is connected to the control terminal of the second power transistor, a second pole of the second power transistor is connected to a reference potential, a control terminal of the third power transistor is connected to an output terminal of the error amplification stage and receives a voltage signal from the error amplification stage, a first pole of the third power transistor is connected to the first pole of the second power transistor and is connected to the control terminal of the second power transistor, and a second pole of the third power transistor is connected to an operating voltage.

6. The charge pump circuit according to claim 1, wherein, The detection feedback stage includes a fourth power transistor, a fifth power transistor, a first resistor, and a second resistor. The voltage input terminal is connected to the second pole of the fourth power transistor. The control terminal of the fourth power transistor is connected to the control terminal of the fifth power transistor and is connected to the first pole of the fourth power transistor. The first pole of the fourth power transistor is connected to one end of the first resistor and is connected to the reference potential. The voltage output terminal is connected to one end of the second resistor. The other end of the second resistor is connected to the second pole of the fifth power transistor. The control terminal of the fifth power transistor is connected to the control terminal of the fourth power transistor, and the first pole of the fifth power transistor is connected to the other end of the first resistor and is connected to the first input terminal of the error amplification stage.

7. The charge pump circuit according to claim 1, wherein, The charge pump stage includes a first power transistor, a first capacitor, a first switch, a second switch, a third switch, and a fourth switch. The node at one end of the first capacitor is respectively connected to the input voltage through the first switch and to the output voltage through the fourth switch. The node at the other end of the first capacitor is respectively connected to the input voltage through the third switch and to the first pole of the first power transistor through the second switch. The second pole of the first power transistor is connected to the reference potential.

8. The charge pump circuit according to claim 1, wherein, The charge pump stage includes N charge pump units, and the N charge pump units are connected to form an N-phase charge pump structure, where N is a positive integer.

9. The charge pump circuit according to claim 1, wherein, The charge pump stage includes a first power transistor, a first capacitor, a second capacitor, a first switch, a second switch, a third switch, a fourth switch, a fifth switch, a sixth switch, a seventh switch, and an eighth switch. The node at one end of the first capacitor is respectively connected to the input voltage through the first switch and to the output voltage through the fourth switch. The node at the other end of the first capacitor is respectively connected to the input voltage through the third switch and to the first pole of the first power transistor through the second switch. The node at one end of the second capacitor is respectively connected to the input voltage through the fifth switch and to the output voltage through the eighth switch. The node at the other end of the second capacitor is respectively connected to the input voltage through the seventh switch and to the first pole of the first power transistor through the sixth switch. The second pole of the first power transistor is connected to the reference potential, and the control terminal of the first power transistor is connected to the amplified output terminal.

10. The charge pump circuit according to claim 1, wherein, The charge pump stage includes a plurality of charge pump units, and the plurality of charge pump units are cascaded.

11. The charge pump circuit according to claim 1, wherein, The charge pump stage includes a first power transistor, a first capacitor, a second capacitor, a first switch, a second switch, a third switch, a fourth switch, a fifth switch, a sixth switch, a seventh switch, and an eighth switch. A node at one end of the first capacitor is respectively connected to the input voltage through the first switch and to the next-stage charge pump unit through the fourth switch. A node at the other end of the first capacitor is respectively connected to the input voltage through the third switch and to the first pole of the first power transistor through the second switch. A node at one end of the second capacitor is respectively connected to the first stage through the fifth switch and to the output voltage through the eighth switch. A node at the other end of the second capacitor is respectively connected to the previous-stage charge pump unit through the seventh switch and to the first pole of the first power transistor through the sixth switch. The second pole of the first power transistor is connected to the reference potential.

12. A charge pump circuit, comprising: A detection feedback stage, with a voltage output terminal connected to the detection feedback stage, and a feedback output terminal of the detection feedback stage generating a feedback voltage based on the output voltage from the voltage output terminal and the reference potential; An error amplification stage, with the feedback output terminal connected to a first input terminal of the error amplification stage, thereby inputting the feedback voltage to the error amplification stage. A second input terminal of the error amplification stage receives a reference voltage signal, and the error amplification stage further includes an amplified output terminal for outputting a voltage signal; A buffer stage, with the buffer stage located between the error amplification stage and the charge pump stage. The amplified output terminal is connected to the buffer stage, and a buffered output terminal of the buffer stage is connected to the charge pump stage; And A charge pump stage, with the charge pump stage including a charge pump unit. The charge pump unit is connected to the voltage output terminal for changing the voltage and outputting from the voltage output terminal. The charge pump stage is further connected to the amplified output terminal through the buffer stage for adjusting the voltage conversion amplitude according to the voltage signal output by the error amplification stage.

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