Memory

Abstract

The present disclosure provides a memory, comprising a logic chip and multiple layers of storage chips, which are stacked in a third direction, each storage chip comprising a plurality of storage structures arranged in a first direction and a second direction, wherein an ith bit line in a first storage structure is connected to an ith bit line in a fourth storage structure; an ith bit line in a third storage structure is connected to an ith bit line in a second storage structure; the first storage structure and the third storage structure are adjacent in the third direction; the fourth storage structure and the third storage structure are located on the same storage chip and are adjacent in the first direction; the second storage structure and the fourth storage structure are adjacent in the third direction; and the second storage structure and the first storage structure are located on the same storage chip and are adjacent in the first direction.

Description

A memory

[0001] Cross-references

[0002] This application claims priority to the Chinese patent application filed with the China Patent Office on December 27, 2023, with application number 202311841372.2 and application name “A Memory”, and claims priority to the Chinese patent application filed with the China Patent Office on August 16, 2024, with application number 202411133400.X and application name “A Memory”. The entire contents of the two Chinese patent applications are incorporated into this application by reference. Technical Field

[0003] The present disclosure relates to the field of semiconductor technology, and in particular to a memory. Background Art

[0004] Dynamic random access memory (DRAM) writes data to the memory by storing charge in the capacitors of the memory cells and reads data from the memory by reading the charge from the capacitors of the memory cells. In DRAM, multiple sense amplifiers are connected to the bit line BL and the reference bit line BLB. During the data read operation, the sense amplifiers are used to amplify the voltage difference between the bit line BL and the reference bit line BLB. However, the presence of large parasitic capacitance between the bit lines has a negative impact on memory performance.

[0005] Summary of the Invention

[0006] An embodiment of the present disclosure provides a memory device, comprising a logic chip and a multi-layer memory chip stacked along a third direction, wherein the memory chip comprises a plurality of memory structures arranged along a first direction and a second direction, the memory structures having a plurality of bit lines arranged along the second direction, and the logic chip comprises a plurality of sense amplifiers arranged along the second direction, wherein the first direction, the second direction, and the third direction intersect with each other.

[0007] The i-th bit line in the first storage structure is connected to the i-th bit line in the fourth storage structure and is connected to one end of the corresponding sense amplifier;

[0008] The i-th bit line in the third storage structure is connected to the i-th bit line in the second storage structure and is connected to the other end of the corresponding sense amplifier; i is an odd number or an even number;

[0009] Among them, the first storage structure is adjacent to the third storage structure in the third direction; the fourth storage structure is located in the same storage chip and is adjacent to the third storage structure in the first direction; the second storage structure is adjacent to the fourth storage structure in the third direction; the second storage structure is located in the same storage chip and is adjacent to the first direction.

[0010] In some embodiments, when i is an even number, the i+1th bit line in the first storage structure is connected to the i+1th bit line in the third storage structure; the i+1th bit line in the second storage structure is connected to the i+1th bit line in the fourth storage structure;

[0011] When i is an odd number, the i-1th bit line in the first storage structure is connected to the i-1th bit line in the third storage structure; the i-1th bit line in the second storage structure is connected to the i-1th bit line in the fourth storage structure.

[0012] In some embodiments, the memory further comprises a fifth storage structure and a sixth storage structure;

[0013] The i-th bit line in the third storage structure is also connected to the k-th bit line in the fifth storage structure;

[0014] The i-th bit line in the fourth storage structure is also connected to the k-th bit line in the sixth storage structure;

[0015] Among them, the fifth storage structure and the sixth storage structure are located in the same storage chip and are adjacent in the first direction, the fifth storage structure and the third storage structure are adjacent in the third direction, and the sixth storage structure and the fourth storage structure are adjacent in the third direction, and k is an odd number or an even number.

[0016] In some embodiments, the memory further comprises a seventh storage structure and an eighth storage structure;

[0017] The kth bit line in the fifth storage structure is also connected to the kth bit line in the eighth storage structure;

[0018] The kth bit line in the sixth storage structure is also connected to the kth bit line in the seventh storage structure;

[0019] Among them, the seventh storage structure and the eighth storage structure are located in the same storage chip and are adjacent to each other in the first direction, the seventh storage structure and the fifth storage structure are adjacent to each other in the third direction, and the eighth storage structure and the sixth storage structure are adjacent to each other in the third direction.

[0020] In some embodiments, both i and k are even numbers, or both i and k are odd numbers, or i is one of an odd number or an even number, and k is the other of an odd number or an even number.

[0021] In some embodiments, the memory further includes a ninth storage structure and a tenth storage structure; in the first direction, the ninth storage structure is located on a side of the fourth storage structure away from the third storage structure, and the tenth storage structure is located on a side of the sixth storage structure away from the fifth storage structure;

[0022] The mth bit line of the fourth storage structure is connected to the mth bit line of the tenth storage structure;

[0023] The mth bit line of the sixth memory structure is connected to the mth bit line of the ninth memory structure;

[0024] Here, the i is an odd number or an even number, and the m is the other of an odd number or an even number.

[0025] In some embodiments, the memory further includes an eleventh storage structure and a twelfth storage structure; in the first direction, the eleventh storage structure is located on a side of the second storage structure away from the first storage structure, and the twelfth storage structure is located on a side of the eighth storage structure away from the seventh storage structure;

[0026] The mth bit line of the second storage structure is connected to the mth bit line of the fourth storage structure;

[0027] The m-th bit line of the sixth memory structure is connected to the m-th bit line of the eighth memory structure.

[0028] In some embodiments, a bit line connection mode among the first storage structure, the second storage structure, the third storage structure, the fourth storage structure, the fifth storage structure, the sixth storage structure, the seventh storage structure, and the eighth storage structure is denoted as a first twisted mode; a bit line connection mode among the second storage structure, the fourth storage structure, the sixth storage structure, the eighth storage structure, the ninth storage structure, the tenth storage structure, the eleventh storage structure, and the twelfth storage structure is denoted as a second twisted mode;

[0029] In the first direction, the twisting modes between adjacent storage structures are alternately the first twisting mode and the second twisting mode.

[0030] In some embodiments, the memory is a dynamic random access memory, and the logic chip is located in the first wafer;

[0031] The multi-layer memory chips are all located in the second wafer, and the multi-layer memory chips are connected through silicon vias; or, the multi-layer memory chips are respectively located in different wafers, and the multi-layer memory chips are connected through hybrid bonding.

[0032] An embodiment of the present disclosure provides a memory, comprising a logic chip and a multi-layer memory chip stacked along a third direction, the memory chip comprising a plurality of memory structures arranged along a first direction and a second direction, the memory structure having a plurality of bit lines arranged along the second direction, the logic chip comprising a plurality of sense amplifiers arranged along the second direction, the first direction, the second direction, and the third direction intersecting in pairs; the i-th bit line in the first memory structure is connected to the i-th bit line in the fourth memory structure and to one end of the corresponding sense amplifier; the i-th bit line in the third memory structure is connected to the i-th bit line in the second memory structure and to the other end of the corresponding sense amplifier; i is an odd number or an even number; wherein the first memory structure is adjacent to the third memory structure in the third direction; the fourth memory structure and the third memory structure are located in the same memory chip and are adjacent in the first direction; the second memory structure and the fourth memory structure are adjacent in the third direction; and the second memory structure and the first memory structure are located in the same memory chip and are adjacent in the first direction. Based on this connection method, the parasitic capacitance between bit lines can be reduced, the system noise can be reduced, and the bit lines in the storage structure adjacent to a certain storage structure can offset the adverse effects between the bit lines in the storage structure, thereby ensuring the accuracy of data transmitted by the bit lines; at the same time, since the adverse effects are offset, the bit lines can be made closer, reducing the distance between the bit lines, which is also conducive to the high integration of the memory and improving the storage density. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] FIG1 is a schematic diagram of the structure of a DRAM provided by an embodiment of the present disclosure;

[0034] FIG2 is a schematic diagram of a first structure of a memory provided by an embodiment of the present disclosure;

[0035] FIG3 is a second schematic diagram of the composition structure of a memory provided by an embodiment of the present disclosure;

[0036] FIG4 is a third schematic diagram of the composition structure of a memory provided by an embodiment of the present disclosure;

[0037] FIG5 is a fourth schematic diagram of the composition structure of a memory provided by an embodiment of the present disclosure;

[0038] FIG6 is a fifth structural diagram of a memory provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0039] The following will be combined with the accompanying drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. It should be understood that the specific embodiments described herein are only used to illustrate the relevant disclosure and are not intended to limit the disclosure. It should also be noted that for ease of description, only the portions relevant to the relevant disclosure are shown in the drawings.

[0040] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art in the art of the present disclosure. The terms used herein are only for the purpose of describing the embodiments of the present disclosure and are not intended to limit the present disclosure.

[0041] In the following description, reference is made to “some embodiments”, which describes a subset of all possible embodiments, but it will be understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0042] It should be pointed out that the terms "first\second\third" involved in the embodiments of the present disclosure are only used to distinguish similar objects and do not represent a specific order for the objects. It can be understood that "first\second\third" can be interchanged with a specific order or sequence where permitted, so that the embodiments of the present disclosure described here can be implemented in an order other than that illustrated or described here.

[0043] Before further explaining the embodiments of the present disclosure in detail, the nouns and terms involved in the embodiments of the present disclosure are explained first. The nouns and terms involved in the embodiments of the present disclosure are subject to the following interpretations:

[0044] Dynamic Random Access Memory (DRAM);

[0045] Sense amplifier / sensitive amplifier (Sense Amplifier, SA);

[0046] Hybrid Bonding (HP);

[0047] Contact pad (PAD);

[0048] Sense Margin;

[0049] Bit Line (BL);

[0050] Storage structure (CELL MAT).

[0051] See Figure 1, which is a schematic diagram of the structure of a DRAM provided by an embodiment of the present disclosure. As shown in Figure 1, the DRAM includes a logic chip and a memory chip. The memory chip includes multiple storage structures (denoted as CELL MAT), which include multiple storage cells (not shown) for storing data and multiple bit lines, with one or more storage cells connected to a bit line. The logic chip includes multiple sense amplifiers SA, each of which is connected to a bit line BL from two storage structures and a reference bit line BLB.

[0052] Figure 1 shows two memory structures, CELL MAT1 and CELL MAT2, each with four bit lines BL. As shown in Figure 1, an even-numbered bit line in CELL MAT1 and an even-numbered bit line in CELL MAT2 serve as references to each other and are connected to the same sense amplifier SA. The reference bit line is referred to as reference bit line BLB. It should be understood that the bit lines and reference bit lines can interchange in different data readout processes; Figure 1 is merely an example.

[0053] As shown in FIG1 , the first even bit line BL in the memory structure CELL MAT2 <0> and the first even-numbered reference bit line BLB in the memory structure CELL MAT1 <0> Both connected to the sense amplifier BLSA <0> ; The second even bit line BL in the memory structure CELL MAT2 <2> and the second even-numbered reference bit line BLB in the memory structure CELL MAT1 <2> Both connected to the sense amplifier BLSA <2> The odd bit lines BL in the memory structure CELL MAT2 <1> and odd bit lines BL <3> Can be used as a reference to the bit lines in other storage structures; odd-numbered bit reference line BLB in storage structure CELL MAT1 <1> and odd bit reference bit lines BLB <3> It can be used as a reference with bit lines in other memory structures.

[0054] In the memory shown in Figure 1, there is very large inter-bit line noise, which affects the sensing margin and thus the increase in storage density. The overall parasitic capacitance of a bit line includes the parasitic capacitance between the bit lines and the parasitic capacitance between the bit line and the remaining conductive materials in the memory. Especially in the 4F2 structure, the problem becomes more serious because the proportion of the parasitic capacitance between the bit line and other bit lines in the overall parasitic capacitance of the bit line increases, which limits the integration of the memory.

[0055] Based on this, an embodiment of the present disclosure provides a memory in which the bit lines are connected by a twisted connection. Based on this twisted connection, the parasitic capacitance between the bit lines can be reduced, the system noise can be reduced, and the inductive margin can be increased, so that the bit lines in the storage structure adjacent to a certain storage structure can offset the adverse effects between the bit lines in the storage structure, thereby ensuring the accuracy of the data transmitted by the bit lines; at the same time, since the adverse effects are offset, the bit lines can be made closer, reducing the distance between the bit lines, which is also conducive to the high integration of the memory and improving the storage density.

[0056] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

[0057] In one embodiment of the present disclosure, referring to FIG2 , a schematic diagram illustrating the first structural structure of a memory device provided by an embodiment of the present disclosure is shown. As shown in FIG2 , the memory device includes a logic chip LC and a multi-layer memory chip AC stacked along a third direction. The memory chip AC includes a plurality of memory structures CELL MAT arranged along a first direction and a second direction. The memory structures CELL MAT have a plurality of bit lines BL arranged along the second direction. The logic chip LC includes a plurality of sense amplifiers SA arranged along the second direction. The first direction, the second direction, and the third direction intersect with each other.

[0058] The i-th bit line BLB in the first memory structure CELL MAT1 and the i-th bit line BL in the fourth memory structure CELL MAT4 connected to one end of the corresponding sense amplifier BLSA;

[0059] The i-th bit line BLB in the third memory structure CELL MAT3 and the i-th bit line BL in the second memory structure CELL MAT2 Connected to the other end of the corresponding sense amplifier BLSA; i is an odd number or an even number;

[0060] Among them, the first storage structure CELL MAT1 is adjacent to the third storage structure CELL MAT3 in the third direction; the fourth storage structure CELL MAT4 is located in the same storage chip AC-2 and is adjacent to the third storage structure CELL MAT3 in the first direction; the second storage structure CELL MAT2 is adjacent to the fourth storage structure CELL MAT4 in the third direction; the second storage structure CELL MAT2 is located in the same storage chip AC-1 and is adjacent to the first direction.

[0061] It should be noted that the embodiments of the present disclosure relate to semiconductor technology, such as DRAM circuits, which utilize multi-layer stacking and twisted bit lines to eliminate noise and are applied to various memories.

[0062] As shown in Figure 2, the extension direction of the bit line BL is recorded as the first direction, the arrangement direction of the bit line BL is recorded as the second direction, and the stacking direction of the memory chip AC and the logic chip LC is recorded as the third direction. In this embodiment, the first direction, the second direction and the third direction are perpendicular to each other as an example, and for the sake of convenience of description, the first direction is regarded as the left-right direction, the second direction is regarded as the front-back direction, and the third direction is regarded as the up-down direction.

[0063] It should also be noted that the bit lines in two adjacent memory structures CELL MAT along the first direction at least partially reference each other. The bit lines in the two adjacent memory structures CELL MAT are respectively denoted as bit line BL and reference bit line BLB. It is understood that the bit line BL and the reference bit line BLB can be interchangeable in different situations. In this embodiment, the reference bit line BLB is also directly referred to as bit line BLB.

[0064] In this embodiment, each memory structure includes multiple memory cells, and a bit line is connected to the multiple memory cells and to corresponding sense amplifiers. For example, if the memory structure has N bit lines and the bit lines are ordered starting from 0, i is an odd or even number greater than or equal to 0 and less than N.

[0065] In the embodiments of the present disclosure, various specific implementations are mainly described by taking i as an even number as an example. The case where i is an odd number is similar to the case where i is an even number, so the same description is omitted.

[0066] As shown in FIG2 , the bit line BLB in the first memory structure CELL MAT1 and the bit line BL in the second memory structure CELL MAT2 They are referenced to each other and are connected to the same sense amplifier SA; the bit line BLB in the third storage structure CELL MAT3 and the bit line BL in the fourth memory structure CELL MAT4 They are referenced to each other and are connected to the same sense amplifier SA, where i is an odd number or an even number. That is, two odd-numbered bit lines or even-numbered bit lines of the same order in adjacent storage structures are referenced to each other.

[0067] FIG2 shows two layers of memory chips AC, designated as a first memory chip AC-1 and a second memory chip AC-2. The first memory chip AC-1 includes a first memory structure CELL MAT1 and a second memory structure CELL MAT2, while the second memory chip AC-2 includes a third memory chip CELL MAT3 and a fourth memory structure CELL MAT4. The drawings of the disclosed embodiments illustrate only four bit lines in each memory structure as an example. In practice, each memory structure may include a greater number of bit lines, and each memory chip may also include a greater number of memory structures, and the memory may include more layers of memory chips. Specifically, the first memory structure CELL MAT1 is located directly above the third memory structure CELL MAT3, the second memory structure CELL MAT2 is located directly above the fourth memory structure CELL MAT4, the fourth memory structure CELL MAT4 is located to the lower right of the first memory structure CELL MAT1, and the third memory structure CELL MAT3 is located to the lower left of the second memory structure CELL MAT2.

[0068] The connection line from the bit line to the sense amplifier in each storage structure is called a bit line connection line. As shown in FIG2 , the bit line BLB in the first storage structure CELL MAT1 <0> The first bit line 101 is connected to the bit line BL in the fourth memory structure CELL MAT4. <0> connection, and connect to the sense amplifier BLSA <0> One end of the second memory structure CELL MAT2 bit line BL <0> The second bit line connection line 102 is connected to the bit line BLB in the third memory structure CELL MAT3 <0> connection, and connect to the sense amplifier BLSA <0> The other end of the bit line BLB in the first memory structure CELL MAT1 <2> The third bit line connection line 103 is connected to the bit line BL in the fourth memory structure CELL MAT4 <2> connection, and connect to the sense amplifier BLSA <2> One end of the second memory structure CELL MAT2 bit line BL <2> The fourth bit line connecting line 104 is connected to the bit line BLB in the third memory structure CELL MAT3 <2> connection, and connect to the sense amplifier BLSA <2> The C in the third storage structure CELL MAT3 roughly represents the parasitic capacitance between the bit lines here.

[0069] In this way, as shown in FIG2 , the even-numbered bit lines in the storage structure are not directly connected to the bit lines at the corresponding positions in the storage structure adjacent to it in the third direction, but are "twist" to the storage structure adjacent to it in the third direction and serving as a reference for the even-numbered bit lines. Based on this twisted connection method, the parasitic capacitance between the bit lines can be reduced, the coupling noise between the storage chips can be reduced, and the data transmitted by the bit lines can be ensured not to be affected by the adjacent bit lines and cause data transmission errors.

[0070] For example, when reading data from the second storage structure CELL MAT2, it is assumed that the bit line BL <0> , bit line BL <1> and bit line BL <2> The transmitted data are: 1 (logic high level), 0 (logic low level), 1, then the bit line BLB in the first storage structure CELL MAT1 <0> , bit line BLB <1> and bit line BLB <2> The data of can be relatively regarded as 0, 1, 0; the bit line BL in the second storage structure CELL MAT2 <0> and bit line BL <2> The data amplification will be on the bit line BL <1> adverse effects, such as the coupling of the bit line BL due to parasitic capacitance. <1> The potential of the bit line BL is pulled upward, which causes the bit line BL <1> Data may be misread or miswritten as 1. At this time, based on this "twisted" structure, the bit line BL in the fourth storage structure CELL MAT4 <0> The bit line BLB in the first memory structure CELL MAT1 <0> is connected, so it also shows 0. Similarly, the bit line BL in the fourth storage structure CELL MAT4 <2> It can also be regarded as 0, the bit line BL in the fourth storage structure CELL MAT4 <0> and bit line BL <2> Also the bit line BL in the second memory structure CELL MAT2 <1> The bit line BL in the fourth memory structure CELL MAT4 is affected. <0> and bit line BL <2> The data of the bit line BL in the second memory structure CELL MAT2 is 0. <0> and bit line BL <2> bit line BL <1> The effect is opposite, which is beneficial to at least partially offset the bit line BL in the second storage structure CELL MAT2 <0> and bit line BL <2> The influence of the second storage structure CELL MAT2 midline BL <1> The data is read and written correctly. The same is true for other reading situations, which will not be described here.

[0071] In this way, the disclosed embodiment uses twisted data line interconnection to effectively eliminate noise (coupling noise between different bit lines in the same storage structure and bit line coupling noise between adjacent storage structures in the third direction), improves the inductive margin, and is conducive to achieving higher DRAM integration.

[0072] It should be noted that the drawings are not drawn to scale to clearly illustrate the memory structure. In practice, the distance between the memory chips in the third direction is not as far as shown in the drawings, so the bit lines in the memory structures adjacent in the third direction can affect each other.

[0073] It should also be noted that, in the example of Figure 2 , the even-numbered bit lines in the memory structure are twisted to compensate for coupling noise. This means that the bit lines originally connected to the bit line directly below them are now connected to the bit line directly below the bit line that serves as a reference, thus "swapping" the connection. Furthermore, if the even-numbered bit lines in the memory structure are twisted to bit lines in a memory chip on one side in a third direction, the odd-numbered bit lines in the memory structure can be set to not be twisted to bit lines in the memory chip on the same side, i.e., "not swapped."

[0074] Based on FIG. 2 , as shown in FIG. 3 , in some embodiments, when i is an even number, the i+1th bit line BLB in the first storage structure CELL MAT1<i+1> and the i+1th bit line BLB in the third storage structure CELL MAT3<i+1> Connection; the i+1th bit line BL in the second storage structure CELL MAT2<i+1> and the i+1th bit line BL in the fourth memory structure CELL MAT4<i+1> connect.

[0075] As shown in FIG3 , in this example, the bit line BLB in the first memory structure CELL MAT1 <1> and the bit line BLB in the third memory structure CELL MAT3 <1> connected to the corresponding sense amplifier (not shown); the bit line BLB in the first storage structure CELL MAT1 <3> and the bit line BLB in the third memory structure CELL MAT3 <3> connected to the corresponding sense amplifier (not shown); the bit line BL in the second storage structure CELL MAT2 <1> and the bit line BL in the fourth memory structure CELL MAT4 <1> connected to the corresponding sense amplifier (not shown); the bit line BL in the second storage structure CELL MAT2 <3> and the bit line BL in the fourth memory structure CELL MAT4 <3> connected to the corresponding sense amplifier (not shown).

[0076] As shown in FIG4 , in some other embodiments, when i is an odd number, the i-1th bit line BLB in the first storage structure CELL MAT1 <i-1>and the i-1th bit line BLB in the third memory structure CELL MAT3 <i-1>Connection; the i-1th bit line BL in the second storage structure CELL MAT2 <i-1>and the i-1th bit line BL in the fourth memory structure CELL MAT4 <i-1>connect.

[0077] As shown in FIG4 , in this example, the first bit line BLB in the first memory structure CELL MAT1 <1> The bit lines of the corresponding order in the storage structure (not shown) are twisted and connected to the corresponding sense amplifier (not shown in the figure), in the same way as the twisting of the even-numbered bit lines in FIG3 . The third bit line BLB <3> Similarly, the first bit line BLB in the third storage structure CELL MAT3 <1> The third bit line BLB is connected to the corresponding bit lines in the memory structure (not shown) in the upper left corner and connected to the corresponding sense amplifier (not shown). <3> Similarly, the first bit line BLB in the second storage structure CELL MAT2 <1> The third bit line BLB is connected to the corresponding bit lines in the memory structure (not shown) in the lower right corner and connected to the corresponding sense amplifier (not shown). <3> Similarly, the first bit line BLB in the fourth storage structure CELL MAT4 <1> The third bit line BLB is connected to the corresponding bit lines in the memory structure (not shown) in the upper right corner and connected to the corresponding sense amplifier (not shown). <3> Similarly, the even bit lines BLB in the first memory structure CELL MAT1 <0> Directly connected to the even bit line BL in the third memory structure CELL MAT3 located below it <0> Connection, even bit line BLB <2> Similarly, the even bit lines BLB in the second storage structure CELL MAT2 <0> Directly connected to the even bit line BL in the fourth memory structure CELL MAT4 located below it <2> Connection, even bit line BLB <2> Same thing.

[0078] Based on FIG2 , as shown in FIG5 , the memory further includes a fifth storage structure CELL MAT5 and a sixth storage structure CELL MAT6;

[0079] The i-th bit line BLB in the third memory structure CELL MAT3 Also connected to the kth bit line BLB in the fifth storage structure CELL MAT5 <k>connect;

[0080] The i-th bit line BL in the fourth memory structure CELL MAT4 Also connected to the kth bit line BL in the sixth storage structure CELL MAT6 <k>connect;

[0081] Among them, the fifth storage structure CELL MAT5 and the sixth storage structure CELL MAT6 are located in the same memory chip AC-3 and are adjacent to each other in the first direction, the fifth storage structure CELL MAT5 and the third storage structure CELL MAT3 are adjacent to each other in the third direction, and the sixth storage structure CELL MAT6 and the fourth storage structure CELL MAT4 are adjacent to each other in the third direction, and k is an odd number or an even number.

[0082] Here, i and k are both even numbers, or i and k are both odd numbers, or i is one of an odd number or an even number, and k is the other of an odd number or an even number.

[0083] It should be noted that when i and k are both odd or even, i can be equal to k; when one of i and k is odd and the other is even, the difference between i and k can be 1. In FIG5 , the case where both i and k are even and i is equal to k is used as an example. The principles of the other implementations are similar and are not further described in the figures in this embodiment.

[0084] As shown in Figure 5, the memory also includes a third memory chip AC-3, which includes a fifth memory structure CELL MAT5 and a sixth memory structure CELL MAT6. The fifth memory structure CELL MAT5 is located below the third memory structure CELL MAT3, and the sixth memory structure CELL MAT6 is located below the fourth memory structure CELL MAT4.

[0085] In this example, the even-numbered bit lines in the second memory chip AC-2 are twisted with the even-numbered bit lines in the first memory chip AC-1 located above, and are not twisted with the bit lines in the third memory chip AC-3 located below. As shown in FIG5 , the bit lines BLB in the third memory chip CELL MAT3 are twisted with the even-numbered bit lines in the first memory chip AC-1 located above. <0> and the bit line BLB in the fifth memory chip CELL MAT5 <0> Connection: bit line BLB in the third memory chip CELL MAT3 <2> and the bit line BLB in the fifth memory chip CELL MAT5 <2> Connection: bit line BL in the fourth memory chip CELL MAT4 <0> and the bit line BL in the sixth memory chip CELL MAT6 <0> Connection: bit line BL in the fourth memory chip CELL MAT4 <2> and the bit line BLB in the sixth memory chip CELL MAT6 <2> connect.

[0086] It can be seen that in the connection in the third direction, the i-th bit line can be "twisted" on one side and "not twisted" on the other side.

[0087] Furthermore, as shown in FIG5 , in some embodiments, the memory further includes a seventh storage structure CELL MAT7 and an eighth storage structure CELL MAT8;

[0088] The k-th bit line BLB in the fifth memory structure CELL MAT5 <k>Also connected to the kth bit line BL in the eighth storage structure CELL MAT8 <k>connect;

[0089] The k-th bit line BLB of CELL MAT6 in the sixth storage structure <k>Also connected to the kth bit line BLB in the seventh storage structure CELL MAT7 <k>connect;

[0090] Among them, the seventh storage structure CELL MAT7 and the eighth storage structure CELL MAT8 are located in the same memory chip and are adjacent in the first direction, the seventh storage structure CELL MAT7 and the fifth storage structure CELL MAT5 are adjacent in the third direction, and the eighth storage structure CELL MAT8 and the sixth storage structure CELL MAT6 are adjacent in the third direction.

[0091] It should be noted that, as shown in Figure 5, the memory also includes a fourth memory chip AC-4 located below the third memory chip AC-3, and the fourth memory chip AC-4 includes a seventh storage structure CELL MAT7 and an eighth storage structure CELL MAT8, wherein the seventh storage structure CELL MAT is located below the fifth storage structure CELL MAT5, and the eighth storage structure CELL MAT8 is located below the sixth storage structure CELL MAT6.

[0092] The even bit lines in the fifth storage structure CELL MAT5 are twisted to connect with the even bit lines in the eighth storage structure CELL MAT8, and the even bit lines in the sixth storage structure CELL MAT6 are twisted to connect with the even bit lines in the seventh storage structure CELL MAT7. As shown in FIG5 , the bit lines BLB in the fifth storage structure CELL MAT5 are twisted to connect with the even bit lines in the eighth storage structure CELL MAT8. <0> and the bit line BL in the eighth memory structure CELL MAT8 <0> Connection; bit line BLB in the fifth storage structure CELL MAT5 <2> and the bit line BL in the eighth memory structure CELL MAT8 <2> Connection; bit line BL in the sixth storage structure CELL MAT6 <0> and the bit line BLB in the seventh memory structure CELL MAT7 <0> Connection; bit line BL in the sixth storage structure CELL MAT6 <2> and the bit line BLB in the seventh memory structure CELL MAT7 <2> connect.

[0093] In addition, as shown in FIG5 , the odd bit lines BLB in the third storage structure CELL MAT3 <1> and odd bit lines BLB <3> The bit lines in the first memory chip AC-1 above it are not twisted, but are connected to the bit lines in the unillustrated memory structure located to its lower left and lower left in a twisted manner. The odd-numbered bit lines in the fifth memory structure CELL MAT5 are connected to the bit lines in the unillustrated memory structure located to its upper left and upper left in a twisted manner, but are not twisted with the odd-numbered bit lines in the seventh memory structure CELL MAT7 located below it. The same applies to the second, fourth, sixth, and eighth memory structures, and will not be further described here.

[0094] Based on Figure 5 , as shown in Figure 6 , the memory further includes a ninth storage structure CELL MAT9 and a tenth storage structure CELL MAT10. The ninth storage structure CELL MAT9 belongs to the second memory chip AC-2, and the tenth storage structure CELL MAT10 belongs to the third memory chip AC-3. In the first direction, the ninth storage structure CELL MAT9 is located on a side of the fourth storage structure CELL MAT4 away from the third storage structure CELL MAT3, and the tenth storage structure CELL MAT10 is located on a side of the sixth storage structure CELL MAT6 away from the fifth storage structure CELL MAT5.

[0095] The m-th bit line BL of the fourth memory structure CELL MAT4 <m>and the m-th bit line BLB of the tenth memory structure CELL MAT10 <m>connect;

[0096] The m-th bit line BL of the sixth memory structure CELL MAT <m>and the m-th bit line BLB of the ninth memory structure CELL MAT9 <m>connect;

[0097] Here, i is an odd number or an even number, and m is the other of an odd number or an even number.

[0098] In this embodiment, two sides along the first direction may include multiple storage structures arranged in the same manner. Similarly, multiple storage chips may be stacked in the same manner in the second direction.

[0099] In FIG6 , the even-numbered bit lines BL / BLB are twisted to compensate for coupling noise between the first memory chip AC-1 and the second memory chip AC-2, and to compensate for coupling noise between the third memory chip AC-3 and the fourth memory chip AC-4. The odd-numbered bit lines BL / BLB are also twisted between the second memory chip AC-2 and the third memory chip AC-3.

[0100] In the example of FIG6 , i is an even number and m is an odd number. Taking the fourth storage structure CELL MAT4 as an example, the even bit lines BL and the even bit line BLB in the first memory structure CELL MAT1 located on the upper left thereof Twisted connection, where the odd bit lines BL <m>and the odd bit lines BLB in the tenth memory structure CELL MAT10 located at the lower right thereof. <m>Twist connection.

[0101] It can be seen that in the embodiment of the present disclosure, the bit line may have a twisted connection with the bit line in one of the memory chips above and below, but not with the bit line in the other memory chip; thus, a twisted connection exists for each bit line (the top chip and the bottom chip are special cases, and there may be odd-numbered bit lines or even-numbered bit lines without a twisted connection), thereby reducing the parasitic capacitance between the bit lines, reducing coupling noise, and ensuring the accuracy of data transmitted by the bit lines.

[0102] In the disclosed embodiment, the odd-numbered bit lines and even-numbered bit lines in any memory structure may not simultaneously have twisted connections with bit lines in the same memory chip. Instead, if the even-numbered bit lines have twisted connections with bit lines in the memory chip above, then the odd-numbered bit line has twisted connections with bit lines in the memory chip below, such as the third memory chip CELL MAT3 in FIG6 . If the even-numbered bit lines have twisted connections with bit lines in the memory chip below, then the odd-numbered bit line has twisted connections with bit lines in the memory chip above, such as the sixth memory chip CELL MAT6 in FIG6 . This avoids problems such as parasitic capacitance and parasitic resistance caused by excessively long wiring.

[0103] In some embodiments, as shown in FIG6 , the memory further includes an eleventh storage structure CELL MAT11 and a twelfth storage structure CELL MAT12, wherein the eleventh storage structure CELL MAT11 belongs to the first memory chip AC-1, and the twelfth storage chip CELL MAT12 belongs to the fourth memory chip AC-1. In a first direction, the eleventh storage structure CELL MAT11 is located on a side of the second storage structure CELL MAT2 away from the first storage structure CELL MAT1, and the twelfth storage structure CELL MAT12 is located on a side of the eighth storage structure CELL MAT8 away from the seventh storage structure CELL MAT7.

[0104] The m-th bit line BL of the second memory structure CELL MAT2 <m>The m-th bit line BL of the fourth memory structure CELL MAT4 <m>connect;

[0105] The m-th bit line BL of the sixth memory structure CELL MAT6 <m>and the m-th bit line BL of the eighth memory structure CELL MAT8 <m>connect;

[0106] The m-th bit line BLB of the eleventh memory structure CELL MAT11 <m>and the m-th bit line BLB of the ninth memory structure CELL MAT9 <m>connect;

[0107] The m-th bit line BLB of the tenth memory structure CELL MAT10 <m>and the m-th bit line BLB of the twelfth memory structure CELL MAT12 <m>connect.

[0108] Based on the aforementioned Figures 2 to 6, each storage structure can contain multiple bit lines. Based on this stacking structure, the storage density can be increased, such as a 4-layer storage chip. In addition, due to the reduction of parasitic capacitance, the bit lines can be made closer in the storage structure, further improving the storage density.

[0109] In the disclosed embodiment, as shown in FIG6 , the bit line connections between the first storage structure CELL MAT1, the second storage structure CELL MAT2, the third storage structure CELL MAT3, the fourth storage structure CELL MAT4, the fifth storage structure CELL MAT5, the sixth storage structure CELL MAT6, the seventh storage structure CELL MAT7, and the eighth storage structure CELL MAT8 are described as a first twisted configuration, while the bit line connections between the second storage structure CELL MAT2, the fourth storage structure CELL MAT4, the sixth storage structure CELL MAT6, the eighth storage structure CELL MAT8, the ninth storage structure CELL MAT9, the tenth storage structure CELL MAT10, the eleventh storage structure CELL MAT11, and the twelfth storage structure CELL MAT12 are described as a second twisted configuration. As can be seen, in the first direction, the twists between adjacent storage structures CELL MAT alternate between the first twisted configuration and the second twisted configuration. This reduces parasitic capacitance per bit line and reduces system noise.

[0110] In some embodiments, the logic chip LC is located within the first wafer. Regarding the memory chips, in a first implementation, the multiple layers of memory chips AC are all located within the second wafer, and the multiple layers of memory chips AC are electrically connected via through-silicon vias or other fixed methods. Alternatively, in a second implementation, the multiple layers of memory chips AC are located within different wafers, and the multiple layers of memory chips are connected via hybrid bonding.

[0111] Taking Figure 5 as an example, the four-layer memory chip can be four array chips respectively, or can be created together on one chip (silicon wafer).

[0112] It should be noted that, based on different architectures, the embodiments of the present disclosure may use through silicon vias (TSVs) or HBs to connect the memory chips, and the logic chip LC and its nearest memory chip AC may be connected via HBs. The memory may be a DRAM.

[0113] In summary, the current existing DRAM architecture has the following problems: very large noise, which affects the inductive margin and thus affects the increase in storage density; especially in the 4F2 structure, the problem becomes more serious due to the increase in the proportion of the parasitic capacitance between the bit lines and the overall parasitic capacitance of the bit lines. Therefore, the embodiment of the present disclosure eliminates noise by designing a new architecture while providing high integration of DRAM (i.e., high storage density). Specifically, the embodiment of the present disclosure utilizes hybrid bonding technology to realize that the logic chip of the peripheral circuit is made on one wafer (first wafer); DRAM (multiple memory chips) is made on another wafer (second wafer) or multiple wafers to realize WoW architecture. In the interconnection implementation process, through effective optimization and twisting of bit lines, for example, twisting the bit lines / reference bit lines of even or odd bits, the noise of the system is reduced, so that higher DRAM integration can be achieved, such as double or quadruple, or even higher.

[0114] The above description is only a preferred embodiment of the present disclosure and is not intended to limit the scope of protection of the present disclosure.

[0115] It should be noted that, in this disclosure, the terms "comprise," "include," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not preclude the presence of other identical elements in the process, method, article, or apparatus comprising the element.

[0116] The serial numbers of the above-mentioned embodiments of the present disclosure are for description only and do not represent the advantages or disadvantages of the embodiments.

[0117] The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0118] The features disclosed in the several product embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new product embodiments.

[0119] The features disclosed in several method or device embodiments provided in this disclosure may be arbitrarily combined without conflict to obtain new method embodiments or device embodiments.

[0120] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.< / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / k> < / k> < / k> < / k> < / k> < / k>

Claims

1. A memory device includes a logic chip (LC) and a multi-layer memory chip (AC) stacked along a third direction. The memory chip (AC) includes a plurality of memory structures (CELL MAT) arranged along a first direction and a second direction. The memory structure (CELL MAT) has a plurality of bit lines (BL) arranged along the second direction. The logic chip (LC) includes a plurality of sense amplifiers (SA) arranged along the second direction. The first direction, the second direction, and the third direction intersect pairwise. The i-th bit line in the first memory structure (CELL MAT1) is connected to the i-th bit line in the fourth memory structure (CELL MAT4) and is connected to one end of the corresponding sense amplifier (SA). The i-th bit line in the third memory structure (CELL MAT3) is connected to the i-th bit line in the second memory structure (CELL MAT2) and is connected to the other end of the corresponding sense amplifier (SA). Here, i is either odd or even. Among them, the first memory structure (CELL MAT1) and the third memory structure (CELL MAT3) are adjacent in the third direction; the fourth memory structure (CELL MAT4) and the third memory structure (CELL MAT3) are located in the same memory chip (AC) and are adjacent in the first direction; the second memory structure (CELL MAT2) and the fourth memory structure (CELL MAT4) are adjacent in the third direction; the second memory structure (CELL MAT2) and the first memory structure (CELL MAT1) are located in the same memory chip (AC) and are adjacent in the first direction.

2. The memory according to claim 1, wherein, When i is even, the (i + 1)-th bit line in the first memory structure (CELL MAT1) is connected to the (i + 1)-th bit line in the third memory structure (CELL MAT3). The (i + 1)-th bit line in the second memory structure (CELL MAT2) is connected to the (i + 1)-th bit line in the fourth memory structure (CELL MAT4). When i is odd, the (i - 1)-th bit line in the first memory structure (CELL MAT1) is connected to the (i - 1)-th bit line in the third memory structure (CELL MAT3); the (i - 1)-th bit line in the second memory structure (CELL MAT2) is connected to the (i - 1)-th bit line in the fourth memory structure (CELL MAT4).

3. The memory device according to claim 1, further comprising a fifth memory structure (CELL MAT5) and a sixth memory structure (CELL MAT6). The i-th bit line in the third memory structure (CELL MAT3) is further connected to the k-th bit line in the fifth memory structure (CELL MAT5). The i-th bit line in the fourth memory structure (CELL MAT4) is further connected to the k-th bit line in the sixth memory structure (CELL MAT6). Among them, The fifth storage structure (CELL MAT5) and the sixth storage structure (CELL MAT6) are located in the same storage chip (AC) and are adjacent in the first direction. The fifth storage structure (CELL MAT5) is adjacent to the third storage structure (CELL MAT3) in the third direction. The sixth storage structure (CELL MAT6) is adjacent to the fourth storage structure (CELL MAT4) in the third direction. k is odd or even.

4. The memory according to claim 3, wherein the memory further comprises a seventh storage structure (CELL MAT7) and an eighth storage structure (CELL MAT8); The k-th bit line in the fifth storage structure (CELL MAT5) is further connected to the k-th bit line in the eighth storage structure (CELL MAT8); The k-th bit line in the sixth storage structure (CELL MAT6) is further connected to the k-th bit line in the seventh storage structure (CELL MAT7); Among them, The seventh storage structure (CELL MAT7) and the eighth storage structure (CELL MAT8) are located in the same storage chip (AC) and are adjacent in the first direction. The seventh storage structure (CELL MAT7) is adjacent to the fifth storage structure (CELL MAT5) in the third direction. The eighth storage structure (CELL MAT8) is adjacent to the sixth storage structure (CELL MAT6) in the third direction.

5. The memory according to claim 3, wherein, Both i and k are even, or both i and k are odd, or one of i is odd or even and the other of k is odd or even.

6. The memory according to claim 4, wherein the memory further comprises a ninth storage structure (CELL MAT9) and a tenth storage structure (CELL MAT10); in the first direction, the ninth storage structure (CELL MAT9) is located on a side of the fourth storage structure (CELL MAT4) away from the third storage structure (CELL MAT3), and the tenth storage structure (CELL MAT10) is located on a side of the sixth storage structure (CELL MAT6) away from the fifth storage structure (CELL MAT5); The m-th bit line of the fourth storage structure (CELL MAT4) is connected to the m-th bit line of the tenth storage structure (CELL MAT10); The m-th bit line of the sixth storage structure (CELL MAT6) is connected to the m-th bit line of the ninth storage structure (CELL MAT9); Wherein, one of i is odd or even and the other of m is odd or even.

7. The memory according to claim 6, wherein the memory further comprises an eleventh memory structure (CELL MAT11) and a twelfth memory structure (CELL MAT12); in the first direction, the eleventh memory structure (CELL MAT11) is located on a side of the second memory structure (CELL MAT2) away from the first memory structure (CELL MAT1), and the twelfth memory structure (CELL MAT12) is located on a side of the eighth memory structure (CELL MAT8) away from the seventh memory structure (CELL MAT7); The m-th bit line of the second memory structure (CELL MAT2) is connected to the m-th bit line of the fourth memory structure (CELL MAT4); The m-th bit line of the sixth memory structure (CELL MAT6) is connected to the m-th bit line of the eighth memory structure (CELL MAT8).

8. The memory according to claim 7, wherein Denote the bit line connection manner among the first memory structure (CELL MAT1), the second memory structure (CELL MAT2), the third memory structure (CELL MAT3), the fourth memory structure (CELL MAT4), the fifth memory structure (CELL MAT5), the sixth memory structure (CELL MAT6), the seventh memory structure (CELL MAT7), and the eighth memory structure (CELL MAT8) as the first twisting manner; Denote the bit line connection manner among the second memory structure (CELL MAT2), the fourth memory structure (CELL MAT4), the sixth memory structure (CELL MAT6), the eighth memory structure (CELL MAT8), the ninth memory structure (CELL MAT9), the tenth memory structure (CELL MAT10), the eleventh memory structure (CELL MAT11), and the twelfth memory structure (CELL MAT12) as the second twisting manner; In the first direction, the twisting manners between adjacent memory structures (CELL MAT1) alternate between the first twisting manner and the second twisting manner.

9. The memory according to any one of claims 1 to 8, wherein the memory is a dynamic random access memory, and the logic chip (LC) is located in the first wafer; All of the multi-layer memory chips (AC) are located in the second wafer, and the multi-layer memory chips (AC) are connected through through-silicon vias; or, the multi-layer memory chips (AC) are respectively located in different wafers, and the multi-layer memory chips (AC) are connected through hybrid bonding.

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