Instruction sampling circuit and memory

Abstract

The present disclosure provides an instruction sampling circuit and a memory. The instruction sampling circuit comprises a sampling circuit and a delay circuit. The sampling circuit receives a memory instruction and a sampling clock, and samples the memory instruction in response to a first sampling edge and a second sampling edge of the sampling clock, respectively, to output a first period instruction and a second period instruction; the sampling circuit has a first output end and a second output end; the delay circuit delays an instruction output by the first output end of the sampling circuit and then outputs the instruction; an instruction decoding circuit receives an output clock, decodes the instruction output by the sampling circuit, and in response to an output edge of the output clock, outputs a current decoding result as decoding information of the memory instruction; and an address output circuit receives the output clock, and in response to the output edge, outputs an instruction currently output by the second output end of the sampling circuit as address information of the memory instruction. The present solution can improve the efficiency of instruction sampling.

Description

Instruction sampling circuit and memory

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on December 29, 2023, with application number 202311872682.0 and application name “Instruction Sampling Circuit and Memory”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present disclosure relates to memory technology, and more particularly to an instruction sampling circuit and a memory. Background Art

[0003] Dynamic Random Access Memory (DRAM) is a semiconductor memory that can write and read data randomly at high speed and is widely used in data storage devices or apparatuses.

[0004] In practical applications, the information of memory instructions may need to be sampled separately over multiple cycles and finally output to subsequent circuits. Therefore, it is necessary to provide an instruction sampling circuit to achieve the above purpose.

[0005] Summary of the Invention

[0006] Embodiments of the present disclosure provide an instruction sampling circuit and a memory.

[0007] According to some embodiments, the present disclosure provides an instruction sampling circuit in a first aspect, comprising: a sampling circuit and a delay circuit; the sampling circuit receives a memory instruction and a sampling clock, and is used to sample the memory instruction in response to a first sampling edge and a second sampling edge of the sampling clock, respectively, and output a first cycle instruction and a second cycle instruction; the sampling circuit has a first output end and a second output end; the input end of the delay circuit is connected to the first output end of the sampling circuit, and the output end of the delay circuit is connected to the instruction decoding circuit, and the delay circuit is used to delay and output the instruction output from the first output end of the sampling circuit; the instruction decoding circuit is coupled to the instruction sampling circuit, receives the output clock, is used to decode the instruction output from the sampling circuit, and outputs the current decoding result as decoding information of the memory instruction in response to the output edge of the output clock; the second output end of the sampling circuit is connected to the address output circuit; the address output circuit receives the output clock, and is used to output the instruction currently output from the second output end of the sampling circuit as address information of the memory instruction in response to the output edge.

[0008] In some examples, the delay circuit includes an even number of inverters.

[0009] In some examples, the output edge of the output clock is located at the second sampling edge, or is located after the second sampling edge and has a preset delay with the second sampling edge, and the delay meets the timing requirements required for sampling at the output edge.

[0010] In some examples, the sampling circuit and the instruction decoding circuit both include flip-flops; and the delay amount includes a setup time of the flip-flop in the instruction decoding circuit and a hold time of the flip-flop in the sampling circuit.

[0011] In some examples, the delay amount is no greater than a difference between a time elapsed between the first sampling edge and the second sampling edge and a setup time of a flip-flop in the instruction decoding circuit.

[0012] In some examples, the sampling clock includes an odd clock and an even clock; the sampling circuit includes: a first sub-sampling circuit and a second sub-sampling circuit, the first sub-sampling circuit has a first even output terminal and a second even output terminal, and the second sub-sampling circuit has a first odd output terminal and a second odd output terminal; the input terminal of the first sub-sampling circuit is connected to the input terminal of the second sub-sampling circuit for receiving memory instructions; the clock terminal of the first sub-sampling circuit receives the even clock, and the clock terminal of the second sub-sampling circuit receives the odd clock; the delay circuit includes: a first sub-delay circuit and a second sub-delay circuit, the first even output terminal is connected to the input terminal of the first sub-delay circuit, and the first odd output terminal is connected to the input terminal of the second sub-delay circuit; the output terminals of the first sub-delay circuit and the second sub-delay circuit and the second even output terminal and the second odd output terminal are all connected to the instruction decoding circuit; the second even output terminal and the second odd output terminal are connected to the address output circuit.

[0013] In some examples, the instruction decoding circuit includes a decoding circuit and a decoding output circuit; the input end of the decoding circuit is connected to the output end of the first sub-delay circuit, the output end of the second sub-delay circuit, the second even output end, and the second odd output end, and the output end of the decoding circuit is connected to the decoding output circuit, and the decoding circuit is used to perform decoding processing; the decoding output circuit receives an output clock and is used to respond to the output edge and output the decoding result currently output by the decoding circuit as the decoding information of the memory instruction.

[0014] In some examples, the decoding circuit includes: a first decoding circuit corresponding to the 1N mode and a second decoding circuit corresponding to the 2N mode; the input end of the first decoding circuit is connected to the second even output end and the second odd output end, the output end of the first decoding circuit is connected to the decoding output circuit, and the first decoding circuit is used to decode the received instruction and output the corresponding decoding result; the input end of the second decoding circuit is connected to the output ends of the first sub-delay circuit and the second sub-delay circuit, the output end of the second decoding circuit is connected to the decoding output circuit, and the second decoding circuit is used to decode the received instruction and output the corresponding decoding result; the decoding output circuit receives an output clock and is used to output the decoding result currently output by the first decoding circuit or the second decoding circuit as decoding information of the memory instruction in response to the output edge.

[0015] In some examples, the input terminal of the address output circuit is connected to the second even output terminal and the second odd output terminal, the clock terminal of the address output circuit receives the output clock, and the address output circuit is used to output the current output of the second even output terminal or the second odd output terminal as the address information of the memory instruction in response to the output edge.

[0016] In some examples, the address output circuit includes: a first output circuit, a second output circuit, and an integration circuit; the input end of the first output circuit is connected to the second even output end, and the clock end of the first output circuit receives an output clock, and is used to output the current output of the second even output end in response to an output edge; the input end of the second output circuit is connected to the second odd output end, and the clock end of the second output circuit receives an output clock, and is used to output the current output of the second odd output end in response to an output edge; the integration circuit is coupled to the first output circuit and the second output circuit, and is used to integrate the outputs of the first output circuit and the second output circuit and output them as address information of the memory instruction.

[0017] In some examples, the instruction sampling circuit further includes: a clock generation circuit; the clock generation circuit receives a sampling clock, is coupled to the instruction decoding circuit and the address output circuit, and is configured to generate an output clock based on the sampling clock.

[0018] According to some embodiments, a second aspect of the present disclosure provides a memory, comprising: the above-mentioned instruction sampling circuit, instruction decoding circuit, and address output circuit.

[0019] In the instruction sampling circuit and memory provided by the embodiment of the present disclosure, the sampling circuit samples the memory instruction in response to the first sampling edge and the second sampling edge of the sampling clock, and outputs the first cycle instruction and the second cycle instruction; the sampling circuit has a first output terminal and a second output terminal, and the delay circuit delays the instruction output from the first output terminal of the sampling circuit and outputs it; the instruction decoding circuit receives the output clock, decodes the instruction output from the sampling circuit, and outputs the current decoding result as the decoding information of the memory instruction in response to the output edge of the output clock; the address output circuit receives the output clock, and outputs the instruction currently output from the second output terminal of the sampling circuit as the address information of the memory instruction in response to the output edge. In this solution, the first cycle instruction output from the first output terminal of the sampling circuit is delayed by the delay circuit, the instruction decoding circuit decodes the delayed first cycle instruction to obtain decoding information, and in response to the output edge of the output clock, the decoding information and address information of the memory instruction are simultaneously output through the instruction decoding circuit and the address output circuit, thereby shortening the transmission delay of the decoding information and the address information and improving the efficiency of instruction sampling. Furthermore, the output logic for distinguishing between the 1N mode and the 2N mode is reduced in the address output circuit, thereby simplifying the circuit and improving the performance of the DRAM.

[0020] The configuration of the present disclosure and other inventive objects and advantageous effects thereof will become more apparent through the description of preferred embodiments with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0022] FIG1 is a diagram illustrating an exemplary memory architecture;

[0023] FIG2 is a structural diagram of an exemplary storage unit;

[0024] FIG3 is a schematic diagram of the structure of an exemplary instruction sampling circuit;

[0025] FIG4 is a timing diagram of instruction sampling and outputting various signals in an exemplary 1N mode and 2N mode;

[0026] FIG5 is a schematic diagram of the structure of an exemplary instruction sampling circuit;

[0027] FIG6 is a timing diagram of instruction sampling and outputting various signals in an exemplary 1N mode and 2N mode;

[0028] FIG7 is a schematic diagram of the structure of an exemplary instruction sampling circuit;

[0029] FIG8 is a timing diagram of an output clock PCSCLK according to an example;

[0030] FIG9 is a schematic diagram of the structure of an exemplary instruction sampling circuit;

[0031] FIG10 is a schematic structural diagram of the connection between the decoding circuit and the decoding output circuit;

[0032] FIG11 is a schematic structural diagram of an address output circuit;

[0033] FIG. 12 is a diagram showing an exemplary structure of a memory.

[0034] The above drawings illustrate specific embodiments of the present disclosure, which will be described in more detail below. These drawings and textual descriptions are not intended to limit the scope of the present disclosure in any way, but rather to illustrate the concepts of the present disclosure to those skilled in the art by reference to specific embodiments. DETAILED DESCRIPTION

[0035] Exemplary embodiments are described in detail herein, with examples illustrated in the accompanying drawings. When the following description refers to the drawings, identical numerals in different figures represent identical or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments are not intended to represent all possible embodiments consistent with the present disclosure. Rather, they are merely examples of apparatuses and methods consistent with certain aspects of the present disclosure.

[0036] The terms "including" and "having" in this disclosure are intended to convey an open-ended sense of inclusion and indicate that additional elements / components / etc. may exist in addition to the listed elements / components / etc. The logical symbol " / " is used to represent the logical meaning of "or." The terms "first" and "second" are used solely for identification or distinction and do not limit the order or quantity of their objects. Furthermore, the various elements and regions in the drawings are schematically illustrated and are not limited to the sizes or distances shown in the drawings. "Connected" in this disclosure may refer to either direct or indirect connections.

[0037] The technical solution is described in detail below with specific embodiments. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments. The embodiments of the present disclosure will be described below with reference to the accompanying drawings.

[0038] Figure 1 shows an example memory architecture. Taking DRAM as an example, Figure 1 shows a memory array comprising a data input / output buffer, a row decoder, a column decoder, a sense amplifier, and a memory array. The data input / output buffer belongs to the peripheral circuit area, while the sense amplifier, row decoder, column decoder, and memory array belong to the array circuit area. The memory array primarily consists of word lines, bit lines, and memory cells. Word lines in the memory array extend in the row direction, while bit lines in the memory array extend in the column direction. The intersection of word lines and bit lines represents the memory cells of the memory array.

[0039] Each memory cell is used to store one bit of data. Figure 2 shows an example of a memory cell structure. The memory cell primarily consists of a transistor switch M and a capacitor C. The capacitor is used to store data, and the transistor switch is used to turn off or on depending on the selected state.

[0040] A memory cell can be activated by controlling the word line and the bit line to achieve access to the memory cell. Take the read scenario as an example: when it is necessary to read the data in the memory cell, the word line of the row where the memory cell is located can be selected through the row decoder. Correspondingly, the transistor M in the diagram is turned on, and the state of the capacitor C at this time can be sensed by sensing and amplifying the bit line signal. For example, if the bit data stored in the memory cell is 1, then after the transistor M is turned on, 1 will be read from the bit line of the memory cell, and vice versa. In addition, take the write scenario as an example: when it is necessary to write bit data to a memory cell, such as writing 1. The word line of the row where the memory cell is located can be selected through the row decoder. The transistor M in the diagram is turned on accordingly, and by setting the logic level of the bit line to 1, the capacitor C is charged, that is, 1 is written to the memory cell. Conversely, if 0 is to be written, the logic level of the bit line is set to 0, so that the capacitor C is discharged, that is, 0 is written to the memory cell.

[0041] In conjunction with the aforementioned operating principle of the memory, in practical applications, the memory receives a command signal, which can be a read command, a write command, or other instructions such as activation. Taking the read command as an example, Figure 3 is a schematic diagram of the structure of an exemplary command sampling circuit. The read command is divided into two cycles to sample command information and address information, and the decoded information of the command information and the address information need to be output simultaneously. The circuit illustrated in Figure 3 includes two paths, each of which is equipped with multiple stages of flip-flops, namely, first-stage flip-flops and second-stage flip-flops. For example, in 1N mode, the first-stage flip-flops in the even-clock path respond to the first rising edge of the even clock to sample the first-cycle instruction and send it to the instruction decoding circuit to obtain the decoded information. After 1T (external clock period), the first-stage flip-flops in the odd-clock path respond to the first rising edge of the odd clock to sample the second-cycle instruction and send it to the address output circuit to obtain the address information. Upon the output edge of the output clock, the decoded information and address information are simultaneously transmitted. In 2N mode, sampling can be performed using only the even clock or the odd clock. Taking sampling using the even clock as an example, at the first rising edge of the even clock, the first-stage trigger in the even clock path samples the first-cycle instruction. After 2T (external clock cycles), at the second rising edge of the even clock, the first-stage trigger in the even clock path samples the second-cycle instruction and sends it to the address output circuit to obtain address information. At this time, the second-stage trigger in the even clock path samples the first-cycle instruction output before the first-stage trigger updates the output, and transmits it to the instruction decoding circuit to obtain decoding information. In other words, in order to ensure that the decoding information and address information are output simultaneously, the first-cycle instruction is not sent to the decoding circuit after the first rising edge of the even clock. Instead, the first-cycle instruction is transmitted to the instruction decoding circuit only when the second rising edge of the even clock arrives. Then, when the output edge of the output clock in the 2N mode arrives, the decoding information and address information are transmitted simultaneously. As an example, Figure 4 is a timing diagram of the instruction sampling output signals in 1N mode and 2N mode. The sampling process for the second-cycle instruction is not shown in the timing diagram. The timing diagram mainly illustrates the sampling and transmission process of the first-cycle instruction (arrows in the diagram indicate sampling or sample output). In 2N mode, the first-cycle instruction with a length of 2T (external clock cycle) is the instruction output by the first-stage flip-flop when the first rising edge arrives. The second-cycle instruction with a length of 2T (external clock cycle) is the instruction output by the second-stage flip-flop when the second rising edge arrives. This instruction is transmitted to the instruction decoding circuit.It can be understood that since the first cycle instruction is transmitted to the instruction decoding circuit only after the second rising edge arrives, the output edge of the output clock in this example needs to be delayed by a certain time compared to the second rising edge (such as the delay a between the two dotted lines in Figure 4) in order to correctly sample the decoding information output by the instruction decoding circuit. This delay needs to take into account the setup and hold time of each level of triggers and the time required for the instruction decoding circuit to perform decoding processing, etc.

[0042] This presents some problems. For example, in practical applications, to simplify circuits and save space, the output clocks in both 1N and 2N modes are typically generated by the same clock generation circuit. This results in a delay a also being applied to the output clock in 1N mode, reducing sampling efficiency. Furthermore, at high frequencies, this delay a may exceed a single external clock cycle, 1T. This can cause the output clock edge in 1N mode to miss the data window for decoding information, leading to sampling failure in 1N mode.

[0043] Some aspects of the embodiments of the present disclosure relate to the above considerations. The following describes the solutions with reference to some embodiments.

[0044] Example 1

[0045] FIG5 is a schematic diagram of the structure of an example instruction sampling circuit. As shown in FIG5 , the instruction sampling circuit includes: a sampling circuit 11 and a delay circuit 12; the sampling circuit 11 receives a memory instruction CA and a sampling clock PCLK, and is used to sample the memory instruction CA in response to the first sampling edge and the second sampling edge of the sampling clock PCLK, and output a first cycle instruction first cycle CA and a second cycle instruction second cycle CA. CA; the sampling circuit 11 has a first output terminal OUT1 and a second output terminal OUT2; the input terminal of the delay circuit 12 is connected to the first output terminal OUT1 of the sampling circuit 11, and the output terminal of the delay circuit 12 is connected to the instruction decoding circuit 13, and the delay circuit 12 is used to delay the instruction output from the first output terminal OUT1 of the sampling circuit 11 and then output it; the instruction decoding circuit 13 is coupled to the instruction sampling circuit, receives the output clock PCSCLK, is used to decode the instruction output by the sampling circuit 11, and outputs the current decoding result as the decoding information of the memory instruction CA in response to the output edge of the output clock PCSCLK; the second output terminal OUT2 of the sampling circuit 11 is connected to the address output circuit 14; the address output circuit 14 receives the output clock PCSCLK, and is used to output the instruction currently outputted from the second output terminal OUT2 of the sampling circuit 11 as the address information of the memory instruction CA in response to the output edge.

[0046] In practical applications, the circuit provided in this embodiment can be applied to various memories. For example, it can be applied to, but not limited to, dynamic random access memory (DRAM). The sampling circuit 11 receives a memory instruction CA and a sampling clock PCLK, and samples the memory instruction CA in response to the first sampling edge and the second sampling edge of the sampling clock PCLK, respectively. The sampling circuit 11 has a first output terminal OUT1 and a second output terminal OUT2. PCLK is a divided clock of the external clock CK, including an odd clock PCLK-O and an even clock PCLK-E. Both clock cycles are twice that of CK, with a phase difference of 180°. The first cycle of the memory instruction CA includes command-related instructions and address-related instructions, and the second cycle includes address-related instructions.

[0047] There are two modes for sampling and outputting memory instructions CA: 1N mode and 2N mode. Figure 6 shows an example timing diagram of instruction sampling and output signals in the 1N and 2N modes, with the instruction sampled first at the even clock PCLK-E. In the 1N mode, upon the arrival of the first sampling edge of the sampling clock PCLK (using PCLK-E as an example in Figure 6), the memory instruction CA is sampled and the first cycle instruction CA is output at the second output terminal. Upon the arrival of the second sampling edge of the sampling clock PCLK (using PCLK-O as an example in Figure 6), the memory instruction CA is sampled and the second cycle instruction CA is output at the second output terminal. In 2N mode, the memory instruction CA is sampled at the first sampling edge of the sampling clock PCLK (Figure 6 uses PCLK-E as an example), that is, the first rising edge of the sampling clock PCLK-E, and the first cycle instruction CA is output at the first output terminal. The memory instruction CA is sampled at the second sampling edge of the sampling clock PCLK-E, that is, the second rising edge after the first rising edge of PCLK-E, and the second cycle instruction CA is output at the second output terminal. It should be noted that in 1N mode, the phase difference between the first sampling edge and the second sampling edge is one external clock cycle; in 2N mode, the phase difference between the first sampling edge and the second sampling edge is two external clock cycles.

[0048] For example, the command address pin end of the memory is used to receive instruction information CA of the specific command and address instructing the memory to operate. Taking the read instruction of DDR5 DRAM as an example, the instruction CA information received by some pin ends is shown in Table 1.

[0049] Table 1

[0050] In the table above, the first row indicates the specific pin that received the instruction, the second row indicates the first cycle CA instruction received by the corresponding pin in the first cycle, and the third row indicates the second cycle CA instruction received by the corresponding pin in the second cycle. As can be seen from the table above, the first cycle CA instruction contains the instruction information required to decode the specific command and the address information for the command operation, while the second cycle CA instruction contains the address information for the command operation.

[0051] Specifically, the input of the delay circuit 12 is connected to the first output terminal OUT1 of the sampling circuit 11, and the output of the delay circuit 12 is connected to the instruction decoding circuit 13. The delay circuit 12 delays the first-cycle instruction (first cycle CA) output from the first output terminal of the sampling circuit 11 and outputs it to the instruction decoding circuit 13. The instruction decoding circuit 13 is coupled to the instruction sampling circuit and receives the first-cycle instruction (first cycle CA) output from the second output terminal OUT2 of the sampling circuit 11 or the delayed first-cycle instruction (first cycle CA) output from the output terminal of the delay circuit 12. The instruction decoding circuit 13 decodes the received first-cycle instruction (first cycle CA) to obtain decoding information corresponding to the first-cycle instruction (first cycle CA). The sampling clock PCLK is delayed to obtain the output clock PCSCLK. The instruction decoding circuit 13 receives the output clock PCSCLK and, in response to the output edge of the output clock PCSCLK, outputs the current decoding result as the decoding information of the memory CA command upon the arrival of the output edge. The second output terminal OUT2 of the sampling circuit 11 is connected to the address output circuit 14, receives the same output clock PCSCLK, and responds to the output edge of the output clock PCSCLK. When the output edge arrives, the second cycle CA currently output by the second output terminal OUT2 of the sampling circuit 11 is output as the address information of the memory instruction CA and the command decoding information at the same time.

[0052] 6 , in 1N mode, when the first sampling edge of the sampling clock PCLK arrives, the command portion of the first-cycle instruction (first cycle CA) in Table 1 is output at the second output terminal and transmitted to the instruction decoding circuit 13 for decoding. When the second sampling edge of the sampling clock PCLK arrives, the second-cycle instruction (second cycle CA) in Table 1 is output at the second output terminal and transmitted to the address output circuit 14. Correspondingly, in 2N mode, when the first sampling edge of the sampling clock PCLK arrives, the first-cycle instruction (first cycle CA) in Table 1 is output at the first output terminal and transmitted to the instruction decoding circuit 13 for decoding. When the second sampling edge of the sampling clock PCLK arrives, the second-cycle instruction (second cycle CA) in Table 1 is output at the second output terminal and transmitted to the address output circuit 14. At this time, the instruction decoding circuit 13 receives the first-cycle instruction (first cycle CA) for decoding. Since the output edge has not yet arrived at this time, the decoded information obtained during the decoding process is temporarily stored. When the output edge of the output clock PCSCLK arrives, the currently obtained command decoded information is valid and output as the decoded information of the memory instruction CA. Similarly, the address output circuit 14 receives the second cycle instruction second cycle CA and performs corresponding processing. When the output edge of the output clock PCSCLK arrives, the currently obtained address information is valid and is output as the address information of the memory instruction CA.

[0053] Compared with the example technology, this solution does not need to set up multiple stages of triggers to control the output of the first cycle instruction first cycle CA. Instead, the delay circuit 12 is used to perform sampling delay on the first cycle instruction first cycle CA. The setting time interval and sampling margin for the output edge are larger than those in the example technology. The circuit of this solution can prepare the command decoding information earlier and increase the sampling margin of the output clock. Furthermore, the output edge of the output clock can arrive earlier, thereby outputting the decoding information and address information in advance, thereby improving the efficiency and quality of instruction sampling.

[0054] Based on the above example, in one example, the delay circuit 12 includes an even number of inverters. Figure 7 is a schematic diagram of the structure of an exemplary instruction sampling circuit. It should be noted that this is merely an example. The delay circuit 12 can include an even number of cascaded inverters, or alternatively, an even number of cascaded inverters, or a delay circuit formed by CMOS capacitors similar to inverters, as long as it provides a delay function. The number of inverters is not specifically limited here and can be set based on the desired delay time, such as 2, 4, 6, 8, etc., as long as the number is an even number. As shown in Figure 7, the delay circuit 12 includes four cascaded inverters. In the above example, by providing an even number of inverters in the delay circuit 12, the signal levels before and after the delay remain consistent, and the first cycle instruction CA output from the first output terminal of the sampling circuit 11 can be delayed, so that the decoded information and address information of the memory instruction CA are output simultaneously. The delay amount of the delay circuit 12 can be Dly as shown in Figure 6.

[0055] In one example, the output edge of the output clock PCSCLK is located at the second sampling edge (as shown in the example of Figure 6), or is located after the second sampling edge and has a preset delay amount delay with the second sampling edge, and the delay amount delay meets the timing requirements required for sampling at the output edge.

[0056] Specifically, when outputting the decoded information and address information, the instruction decode circuit 13 and the address output circuit 14 must respond to the output edge of the output clock PCSCLK. Upon the output edge of the output clock PCSCLK, the decoded information and address information are simultaneously output. The output clock PCSCLK is generated based on the sampling clock PCLK. The output edge of the output clock PCSCLK can occur at the second sampling edge of the sampling clock PCLK, or it can occur after the second sampling edge of the sampling clock PCLK with a preset delay. The delay only needs to meet the timing requirements for sampling at the output edge. In other words, the output edge obtained after the second sampling edge is delayed to simultaneously output the decoded information and address information.

[0057] In conjunction with the foregoing example, the output clock PCSCLK includes a first output clock corresponding to the 1N mode and a second output clock corresponding to the 2N mode. The output edge of the first output clock corresponds to the second sampling edge in the 1N mode or the position of the second sampling edge in the 1N mode after being delayed by the delay amount delay; the output edge of the second output clock corresponds to the second sampling edge in the 2N mode or the position of the second sampling edge in the 2N mode after being delayed by the delay amount delay.

[0058] Through the solution of this example, the output clock PCSCLK is generated according to the sampling clock PCLK. The output edge of the output clock PCSCLK can be the second sampling edge, or it can be after the second sampling edge and there is a preset delay amount delay with the second sampling edge. When the output edge of the output clock PCSCLK arrives, the decoding information and address information of the instruction are output at the same time, thereby shortening the transmission delay of the decoding information and address information and improving the performance of the DRAM.

[0059] Based on the above example, the sampling circuit 11 and the instruction decoding circuit 13 both include a trigger; the delay amount delay includes the setup time of the trigger in the instruction decoding circuit 13 and the hold time of the trigger in the sampling circuit 11 .

[0060] Specifically, the sampling circuit 11 and the instruction decoding circuit 13 both include a trigger. When the output edge of the output clock PCSCLK is located after the second sampling edge and there is a preset delay amount delay with the second sampling edge, the delay amount delay includes the setup time of the trigger in the decoding circuit 13 and the hold time of the trigger in the sampling circuit 11. The setup time of the trigger refers to the time during which the data input to the data terminal must remain unchanged before the sampling edge of the trigger's sampling clock arrives. The hold time of the trigger refers to the time during which the data input to the data terminal must remain unchanged after the sampling edge of the trigger's sampling clock arrives. Specifically, in the disclosed embodiment, the hold time of the trigger in the sampling circuit 11 refers to the time during which the first cycle instruction (first cycle CA) must remain unchanged after the sampling edge of the sampling clock PCLK arrives. The setup time of the trigger in the instruction decoding circuit 13 refers to the time during which the first cycle instruction (first cycle CA) must remain unchanged before the output edge of the output clock PCSCLK arrives.

[0061] Based on this, to ensure that the decoded information corresponding to the first-cycle instruction (first cycle CA) can be output when the output edge arrives, in one example, the delay amount (delay) is no greater than the difference between the time elapsed between the first and second sampling edges and the setup time of the flip-flop in the instruction decoding circuit 13. Figure 8 shows an example timing diagram of the output clock PCSCLK. As shown in Figure 8, in 2N mode, the time between dashed lines 1 and 3 represents the time elapsed between the first and second sampling edges, that is, two external clock cycles, and the time between dashed lines 2 and 3 represents the setup time of the flip-flop in the instruction decoding circuit 13. Therefore, it can be concluded that the time difference between dashed lines 1 and 2 is the time elapsed between the first and second sampling edges minus the setup time of the flip-flop in the instruction decoding circuit 13. The maximum delay amount (delay) of the first-cycle instruction (first cycle CA) cannot exceed the difference between the time elapsed between the first and second sampling edges and the setup time of the flip-flop in the instruction decoding circuit 13, that is, the difference between two external clock cycles and the setup time of the flip-flop in the instruction decoding circuit 13.

[0062] In the above example, the delay value of the output clock PCSCLK is set to ensure that the decoded information and address information of the memory instruction CA are output simultaneously when the output edge of the output clock PCSCLK arrives. At the same time, the timing of outputting the decoded information and address information can be adjusted based on the required sampling margin and output time requirements.

[0063] In one example, FIG9 is a schematic diagram of the structure of an example instruction sampling circuit. As shown in FIG9 , the sampling clock PCLK includes an odd clock PCLK-O and an even clock PCLK-E; the sampling circuit 11 includes: a first sub-sampling circuit 111 and a second sub-sampling circuit 112, the first sub-sampling circuit 111 having a first even output terminal and a second even output terminal EVEN-1T, and the second sub-sampling circuit 112 having a first odd output terminal and a second odd output terminal ODD-1T; the input terminal of the first sub-sampling circuit 111 is connected to the input terminal of the second sub-sampling circuit 112 for receiving the memory instruction CA; the clock terminal of the first sub-sampling circuit 111 receives the even clock PCLK- E, the clock end of the second sub-sampling circuit 112 receives the odd clock PCLK-O; the delay circuit 12 includes: a first sub-delay circuit 121 and a second sub-delay circuit 122, the first even output end is connected to the input end of the first sub-delay circuit 121, and the first odd output end is connected to the input end of the second sub-delay circuit 122; the output end EVEN-0T of the first sub-delay circuit 121, the output end ODD-0T of the second sub-delay circuit 122, and the second even output end EVEN-1T and the second odd output end ODD-1T are all connected to the instruction decoding circuit 13; the second even output end EVEN-1T and the second odd output end ODD-1T are connected to the address output circuit 14.

[0064] Specifically, sampling circuit 11 includes a first sub-sampling circuit 111 and a second sub-sampling circuit 112. First sub-sampling circuit 111 and second sub-sampling circuit 112 receive memory instruction CA. A first even output terminal of first sub-sampling circuit 111 is connected to first sub-delay circuit 121, and a first odd output terminal of second sub-sampling circuit 112 is connected to second sub-delay circuit 122.

[0065] In the 1N mode, the first sub-sampling circuit 111 and the second sub-sampling circuit 112 receive a memory instruction CA. The clock terminal of the first sub-sampling circuit 111 receives the even clock PCLK-E. If the first cycle command arrives at the first rising edge of the even clock PCLK-E, it will be sampled by the first sub-sampling circuit. In response to the first sampling edge, that is, the first rising edge of the even clock PCLK-E, the first cycle instruction first cycle CA is output to the instruction decoding circuit 13 at the second even output terminal EVEN-1T of the first sub-sampling circuit 111. The clock terminal of the second sub-sampling circuit 112 receives the odd clock PCLK-O. In response to the second sampling edge, that is, the rising edge of the odd clock PCLK-O immediately following the first rising edge of the even clock PCLK-E, the second odd output terminal ODD-1T of the second sub-sampling circuit 112 samples and outputs the second cycle instruction second cycle CA to the address output circuit 14. Similarly, if the first cycle command arrives at the first rising edge of the odd clock PCLK-O, it will be sampled by the second sub-sampling circuit. In response to the first sampling edge, that is, the first rising edge of the odd clock PCLK-O, the second odd output terminal ODD-1T of the second sub-sampling circuit 112 outputs the first cycle instruction (first cycle CA) to the instruction decoding circuit 13. The clock terminal of the first sub-sampling circuit 111 receives the even clock PCLK-E. In response to the second sampling edge, that is, the rising edge of the even clock PCLK-E immediately following the first rising edge of the odd clock PCLK-O, the second even output terminal EVEN-1T of the first sub-sampling circuit 111 samples and outputs the second cycle instruction (second cycle CA) to the address output circuit 14.

[0066] In the 2N mode, the first sub-sampling circuit 111 and the second sub-sampling circuit 112 receive a memory instruction CA. If a first-cycle instruction arrives at the first rising edge of the even clock PCLK-E, it will be sampled by the first sub-sampling circuit 111. The clock terminal of the first sub-sampling circuit 111 receives the even clock PCLK-E. In response to the first sampling edge, that is, the first rising edge of the even clock PCLK-E, the first-cycle instruction CA is output at the first even output terminal of the first sub-sampling circuit 111 to the first sub-delay circuit 121. After a delay, the first-cycle instruction CA is output at the output terminal EVEN-0T of the first sub-delay circuit 121 to the instruction decoding circuit 13. In response to the second sampling edge of the even clock PCLK-E, that is, the second rising edge after the first rising edge of the even clock PCLK-E, the second-cycle instruction CA is output at the second even output terminal EVEN-1T of the first sub-sampling circuit 111 to the address output circuit 14. If the first cycle command arrives at the first rising edge of the odd clock PCLK-O, it will be collected by the second sub-sampling circuit 112. The clock end of the second sub-sampling circuit 112 receives the odd clock PCLK-O. In response to the first sampling edge, that is, the first rising edge of the odd clock PCLK-O, the first cycle command "first cycle CA" is output to the second sub-delay circuit 122 at the first odd output end of the second sub-sampling circuit 112. After a delay, the first cycle command "first cycle CA" is output to the instruction decoding circuit 13 at the output end ODD-0T of the second sub-delay circuit 122. In response to the second sampling edge of the odd clock PCLK-O, that is, the second rising edge after the first rising edge of the odd clock PCLK-O, the second cycle command "second cycle CA" is output to the address output circuit 14 at the second odd output end ODD-1T of the second sub-sampling circuit 112.

[0067] Through the solution of this example, the sampling clock PCLK includes an odd clock PCLK-O and an even clock PCLK-E, the sampling circuit 11 includes a first sub-sampling circuit 111 and a second sub-sampling circuit 112, and the delay circuit 12 includes a first sub-delay circuit 121 and a second sub-delay circuit 122. For the 1N mode and the 2N mode, the first cycle instruction first cycle CA is output to the instruction decoding circuit 13 and the second cycle instruction second cycle CA is output to the address output circuit 14 at different output terminals, thereby ensuring the timing of instruction transmission.

[0068] In one example, the instruction decoding circuit 13 includes a decoding circuit 131 and a decoding output circuit 132; the input end of the decoding circuit 131 is connected to the output end EVEN-0T of the first sub-delay circuit 121, the output end ODD-0T of the second sub-delay circuit 122, the second even output end EVEN-1T and the second odd output end ODD-1T, and the output end of the decoding circuit 131 is connected to the decoding output circuit 132, and the decoding circuit 131 is used to perform decoding processing; the decoding output circuit 132 receives the output clock PCSCLK, and is used to respond to the output edge and output the decoding result currently output by the decoding circuit 131 as the decoding information of the memory instruction CA.

[0069] Figure 10 is a schematic diagram of the connection between decoding circuit 131 and decoding output circuit 132. Decoding circuit 131 is used to decode received instructions. In practical applications, this can be implemented using logic gates, such as NAND gates and NOR gates. The input of decoding circuit 131 is connected to the output EVEN-0T of the first sub-delay circuit 121, the output ODD-0T of the second sub-delay circuit 122, the second even output EVEN-1T, and the second odd output ODD-1T. Decoding circuit 131 receives the command-related portion of the first cycle instruction (first cycle CA) and decodes it. For example, based on Cs_n and CA0-CA4 of the first cycle in Table 1, it decodes a read command. The output end of decoding circuit 131 is connected to decoding output circuit 132. Decoding output circuit 132 includes a flip-flop. First cycle instruction CA, output from output end EVEN-0T of first sub-delay circuit 121, output end ODD-0T of second sub-delay circuit 122, second even output end EVEN-1T, and second odd output end ODD-1T, is decoded by decoding circuit 131 to obtain decoding information, which is then transmitted to a flip-flop in decoding output circuit 132. The flip-flop in decoding output circuit 132 receives the output clock signal PCSCLK and, in response to an output edge, outputs the decoding result currently output by decoding circuit 131 as command decoding information for memory instruction CA.

[0070] In the above example, the first cycle instruction first cycle CA outputted from any of the output terminals EVEN-0T of the first sub-delay circuit 121, the output terminal ODD-0T of the second sub-delay circuit 122, and the second even output terminal EVEN-1T and the second odd output terminal ODD-1T is decoded by the decoding circuit 131. In response to the output edge of the output clock PCSCLK, the decoding result currently outputted by the decoding circuit 131 is outputted as the decoding information of the memory instruction CA, thereby ensuring the accuracy of the output of the decoding information.

[0071] In combination with the above examples, in the 1N mode and the 2N mode, the decoding circuit 131 includes: a first decoding circuit corresponding to the 1N mode and a second decoding circuit corresponding to the 2N mode; the input end of the first decoding circuit is connected to the second even output end EVEN-1T and the second odd output end ODD-1T, and the output end of the first decoding circuit is connected to the decoding output circuit 132. The first decoding circuit is used to decode the received instruction and output the corresponding decoding result; the input end of the second decoding circuit is connected to the output end EVEN-0T of the first sub-delay circuit 121 and the output end ODD-0T of the second sub-delay circuit 122, and the output end of the second decoding circuit is connected to the decoding output circuit 132. The second decoding circuit is used to decode the received instruction and output the corresponding decoding result; the decoding output circuit 132 receives the output clock PCSCLK and is used to output the decoding result currently output by the first decoding circuit or the second decoding circuit as decoding information of the memory instruction CA in response to the output edge.

[0072] In actual applications, because the correspondence between the sampling clock and the output clock differs between the 1N and 2N modes, a first decoding circuit corresponding to the 1N mode and a second decoding circuit corresponding to the 2N mode are provided. Furthermore, considering that the sampling clock for sampling the first cycle instruction CA may be either an even or odd clock, to ensure sampling reliability, the first decoding circuit in the 1N mode includes a first decoding circuit corresponding to the even clock and a first decoding circuit corresponding to the odd clock; while the second decoding circuit in the 2N mode includes a second decoding circuit corresponding to the even clock and a second decoding circuit corresponding to the odd clock. Similarly, considering sampling reliability, the output clock PCSCLK includes an even output clock PCSCLK-E and an odd output clock PCSCLK-O. The decoded output circuit 132 includes two flip-flops: the first flip-flop receives the even output clock PCSCLK-E, and the second flip-flop receives the odd output clock PCSCLK-O.

[0073] Specifically, as an example, in 1N mode, the input of the first decoding circuit corresponding to the even clock is connected to the second even output terminal EVEN-1T, and the input of the first decoding circuit corresponding to the odd clock is connected to the second odd output terminal ODD-1T. The output of the first decoding circuit corresponding to the even clock is connected to the second flip-flop in the decoding output circuit 132 and responds to the odd output clock PCSCLK-O. The output of the first decoding circuit corresponding to the odd clock is connected to the first flip-flop in the decoding output circuit 132 and responds to the even output clock PCSCLK-E. The first decoding circuit corresponding to the even clock receives the first cycle instruction CA output from the second even output terminal EVEN-1T. After decoding by the first decoding circuit corresponding to the even clock, decoding information is obtained. When the output edge of the odd output clock PCSCLK-O arrives, the current decoding result is output as the decoding information of the memory instruction CA. The input end of the first decoding circuit corresponding to the odd clock receives the first cycle instruction first cycle CA output by the second odd output end ODD-1T. After being decoded by the first decoding circuit corresponding to the odd clock, decoding information is obtained. When the output edge of the even output clock PCSCLK-E arrives, the current decoding result is output as the decoding information output of the memory instruction CA.

[0074] Accordingly, in 2N mode, the input of the second decoding circuit corresponding to the even clock is connected to the output EVEN-0T of the first sub-delay circuit 121, and the input of the second decoding circuit corresponding to the odd clock is connected to the output ODD-0T of the second sub-delay circuit 122. The output of the second decoding circuit corresponding to the even clock is connected to the first flip-flop in the decoding output circuit 132 and responds to the even output clock PCSCLK-E. The output of the second decoding circuit corresponding to the odd clock is connected to the second flip-flop in the decoding output circuit 132 and responds to the odd output clock PCSCLK-O. The input of the second decoding circuit corresponding to the even clock receives the first cycle instruction CA outputted from the output EVEN-0T of the first sub-delay circuit 121. After decoding by the second decoding circuit corresponding to the even clock, decoding information is obtained. When the output edge of the even output clock PCSCLK-E arrives, the current decoding result is outputted as the decoding information of the memory instruction CA. The input end of the second decoding circuit corresponding to the odd clock receives the first cycle instruction CA output by the output end ODD-0T of the second sub-delay circuit 122. After being decoded by the second decoding circuit corresponding to the odd clock, decoding information is obtained. When the output edge of the odd output clock PCSCLK-0 arrives, the current decoding result is output as the decoding information of the memory instruction CA.

[0075] In the above example, the decoding circuit 131 includes a first decoding circuit in the 1N mode and a second decoding circuit in the 2N mode, which enriches the decoding methods of the memory instruction CA in different scenarios and outputs decoding information.

[0076] In one example, the input end of the address output circuit 14 is connected to the second even output end EVEN-1T and the second odd output end ODD-1T, the clock end of the address output circuit 14 receives the output clock PCSCLK, and the address output circuit 14 is used to output the current output of the second even output end EVEN-1T or the second odd output end ODD-1T as the address information of the memory instruction CA in response to the output edge.

[0077] Specifically, the second even output terminal EVEN-1T and the second odd output terminal ODD-1T of the sampling circuit 11 are connected to the address output circuit 14. In the 1N mode and the 2N mode, the even clock signal PCLK-E of the sampling clock samples the second cycle CA of the memory instruction CA at the second sampling edge and outputs it at the second even output terminal EVEN-1T. The odd clock signal PCLK-O of the sampling clock samples the second cycle CA of the memory instruction CA at the second sampling edge and outputs it at the second odd output terminal ODD-1T. The input terminal of the address output circuit 14 is connected to the second even output terminal EVEN-1T and the second odd output terminal ODD-1T. The address output circuit 14 receives the second cycle CA output from the second even output terminal EVEN-1T and the second odd output terminal ODD-1T, and outputs the current output of the second even output terminal EVEN-1T or the second odd output terminal ODD-1T as the address information of the memory instruction CA in response to the output edge of the output clock signal PCSCLK. With the solution of this example, for the second cycle instruction, since the address information in both the 1N and 2N modes is output through the second even output terminal EVEN-1T or the second odd output terminal ODD-1T, the second cycle instruction CA directly reaches the address output circuit 14 for output. Therefore, the 1N and 2N distinction logic of the second cycle address output circuit can be eliminated, saving circuit area, and allowing the address information to arrive earlier, thereby improving the setup time margin.

[0078] FIG11 is a schematic diagram of the structure of the address output circuit 14. As shown in FIG11 , based on the above example, the address output circuit 14 includes: a first output circuit 141, a second output circuit 142, and an integration circuit 143. The input terminal of the first output circuit 141 is connected to the second even output terminal EVEN-1T. The clock terminal of the first output circuit 141 receives the output clock signal PCSCLK and is configured to output the current output of the second even output terminal EVEN-1T in response to an output edge. The input terminal of the second output circuit 142 is connected to the second odd output terminal ODD-1T. The clock terminal of the second output circuit 142 receives the output clock signal PCSCLK and is configured to output the current output of the second odd output terminal ODD-1T in response to an output edge. The integration circuit 143 is coupled to the first output circuit 141 and the second output circuit 142 and is configured to integrate the outputs of the first output circuit 141 and the second output circuit 142 and output the result as the address information of the memory instruction CA.

[0079] Considering that in actual applications, the clock used to sample the first cycle data may be either an even clock or an odd clock, to ensure reliable sampling, as an example, the address output circuit 14 includes a first output circuit 141, a second output circuit 142, and an integration circuit 143. In both the 1N mode and the 2N mode, the input terminal of the first output circuit 141 receives the second cycle instruction second cycle CA output by the second even output terminal EVEN-1T, and outputs the current output of the second even output terminal EVEN-1T in response to the output edge of the even output clock PCSCLK-E. The input terminal of the second output circuit 142 receives the second cycle instruction second cycle CA output by the second odd output terminal ODD-1T, and outputs the current output of the second odd output terminal ODD-1T in response to the output edge of the odd output clock PCSCLK-O. Similarly, in response to the output edge of the odd output clock PCSCLK-O or the output edge of the even output clock PCSCLK-E, the integration circuit 143 integrates the current output of the second even output terminal EVEN-1T with the current output of the second odd output terminal ODD-1T, and outputs the integrated result as the address information of the memory instruction CA. In the above example, for the second cycle instruction CA, since the address information is output through the second even output terminal EVEN-1T or the second odd output terminal ODD-1T in both the 1N and 2N modes, the second cycle instruction CA directly reaches the address output circuit 14 for output. Therefore, the 1N and 2N differentiation logic of the second cycle address output circuit can be eliminated, saving circuit area, allowing the address information to arrive earlier, and improving the setup time margin.

[0080] Exemplarily, the first output circuit 141 and the second output circuit 142 may be flip-flops or latches. For example, the first output circuit 141 may be a flip-flop or latch that outputs sampled address information during the even output clock PCSCLK-E, and the second output circuit 142 may be a flip-flop or latch that outputs sampled address information during the odd output clock PCSCLK-O. The integration circuit may also be a circuit composed of flip-flops or latches, or may be two gated inverters, whose transition clocks or control terminals of the gated inverters receive the output clock signals PCSCLK-E and PCSCLK-O, respectively, thereby integrating the address information output during the odd output clock and the address information output during the even output clock into a single path.

[0081] Based on any of the above examples, the instruction sampling circuit further includes: a clock generation circuit; the clock generation circuit receives the sampling clock PCLK, is coupled to the instruction decoding circuit 13 and the address output circuit 14, and is used to generate the output clock PCSCLK according to the sampling clock PCLK.

[0082] Specifically, the instruction sampling circuit also includes a clock generation circuit that receives a sampling clock PCLK and generates an output clock PCSCLK based on the sampling clock PCLK. According to the aforementioned embodiment, the clock generation circuit can directly generate the output clock PCSCLK without performing any processing on the sampling clock PCLK. That is, the output clock PCSCLK and the sampling clock PCLK have the same source and frequency and can be considered a single clock. The clock generation circuit can also directly generate the output clock PCSCLK by delaying the sampling clock PCLK. The specific design considerations for the delay amount are described above and are not further elaborated here. In the above example, the output clock PCSCLK is generated based on the sampling clock PCLK, thereby ensuring the output timing of the decoded information and address information of the memory instruction CA.

[0083] In the instruction sampling circuit provided by the embodiment of the present disclosure, the sampling circuit samples the memory instruction in response to the first sampling edge and the second sampling edge of the sampling clock, and outputs the first cycle instruction and the second cycle instruction; the sampling circuit has a first output terminal and a second output terminal, and the delay circuit delays the instruction output from the first output terminal of the sampling circuit and outputs it; the instruction decoding circuit receives the output clock, decodes the instruction output from the sampling circuit, and outputs the current decoding result as the decoding information of the memory instruction in response to the output edge of the output clock; the address output circuit receives the output clock, and outputs the instruction currently output from the second output terminal of the sampling circuit as the address information of the memory instruction in response to the output edge. In this solution, the first cycle instruction output from the first output terminal of the sampling circuit is delayed by the delay circuit, the instruction decoding circuit decodes the delayed first cycle instruction to obtain decoding information, and in response to the output edge of the output clock, the decoding information and address information of the memory instruction are simultaneously output through the instruction decoding circuit and the address output circuit, thereby shortening the transmission delay of the decoding information and the address information and improving the efficiency of instruction sampling. Furthermore, the output logic for distinguishing between the 1N mode and the 2N mode is reduced in the address output circuit, thereby simplifying the circuit and improving the performance of the DRAM.

[0084] Example 2

[0085] FIG12 is a structural diagram of an exemplary memory. As shown in FIG12 , the memory includes: an instruction sampling circuit, an instruction decoding circuit 13 and an address output circuit 14 as in any of the previous examples.

[0086] Specifically, in combination with the above solution, the sampling circuit 11 receives the memory instruction CA and the sampling clock PCLK, and samples the memory instruction CA in response to the first sampling edge and the second sampling edge of the sampling clock PCLK. The sampling circuit 11 has a first output terminal and a second output terminal.

[0087] There are two modes for sampling and outputting memory instructions CA: 1N mode and 2N mode. In 1N mode, the memory instruction CA is sampled at the first sampling edge of the sampling clock PCLK, and the first-cycle instruction CA is output at the second output terminal. At the second sampling edge of the sampling clock PCLK, the memory instruction CA is sampled and the second-cycle instruction CA is output at the second output terminal. In 2N mode, the memory instruction CA is sampled at the first sampling edge of the sampling clock PCLK, that is, the first rising edge of the sampling clock PCLK-E, and the first-cycle instruction CA is output at the first output terminal. At the second sampling edge of the sampling clock PCLK-E, that is, the second rising edge after the first rising edge of PCLK-E, the memory instruction CA is sampled and the second-cycle instruction CA is output at the second output terminal. It should be noted that in 1N mode, the phase difference between the first sampling edge and the second sampling edge is one external clock cycle; in 2N mode, the phase difference between the first sampling edge and the second sampling edge is two external clock cycles.

[0088] More specifically, the input of delay circuit 12 is connected to the first output of sampling circuit 11, and the output of delay circuit 12 is connected to instruction decoding circuit 13. Delay circuit 12 delays the first-cycle instruction (first cycle CA) output from the first output of sampling circuit 11 and outputs it to instruction decoding circuit 13. Instruction decoding circuit 13 is coupled to the instruction sampling circuit and receives the first-cycle instruction (first cycle CA) output from the second output of sampling circuit 11 or the delayed first-cycle instruction (first cycle CA) output from the output of delay circuit 12. Instruction decoding circuit 13 decodes the received first-cycle instruction (first cycle CA) to obtain decoding information corresponding to the first-cycle instruction (first cycle CA). The sampling clock PCLK is delayed to obtain the output clock PCSCLK. Instruction decoding circuit 13 receives the output clock PCSCLK and, in response to an output edge of the output clock PCSCLK, outputs the current decoding result as decoding information for the memory instruction CA command. The second output terminal of the sampling circuit 11 is connected to the address output circuit 14, receives the same output clock PCSCLK, and responds to the output edge of the output clock PCSCLK. When the output edge arrives, the second cycle instruction second cycle CA currently output by the second output terminal of the sampling circuit 11 is output as the address information of the memory instruction CA and the command decoding information at the same time.

[0089] In 1N mode, when the first sampling edge of the sampling clock PCLK arrives, the command portion of the first-cycle instruction (first cycle CA) is output at the second output terminal and transmitted to the instruction decoding circuit 13 for decoding. When the second sampling edge of the sampling clock PCLK arrives, the second-cycle instruction (second cycle CA) is output at the second output terminal and transmitted to the address output circuit 14. Correspondingly, in 2N mode, when the first sampling edge of the sampling clock PCLK arrives, the first-cycle instruction (first cycle CA) is output at the first output terminal and transmitted to the instruction decoding circuit 13 for decoding. When the second sampling edge of the sampling clock PCLK arrives, the second-cycle instruction (second cycle CA) is output at the second output terminal and transmitted to the address output circuit 14. At this time, the instruction decoding circuit 13 receives the first-cycle instruction (first cycle CA) for decoding. Because the output edge has not yet arrived at this time, the decoded information obtained during the decoding process is temporarily stored. When the output edge of the output clock PCSCLK arrives, the currently obtained command decoded information becomes valid and is output as the decoded information of the memory instruction CA. Similarly, the address output circuit 14 receives the second cycle instruction second cycle CA and performs corresponding processing. When the output edge of the output clock PCSCLK arrives, the currently obtained address information is valid and is output as the address information of the memory instruction CA.

[0090] In the memory provided by the embodiment of the present disclosure, the sampling circuit samples the memory instruction in response to the first sampling edge and the second sampling edge of the sampling clock, and outputs the first cycle instruction and the second cycle instruction; the sampling circuit has a first output terminal and a second output terminal, and the delay circuit delays the instruction outputted from the first output terminal of the sampling circuit and outputs it; the instruction decoding circuit receives the output clock, decodes the instruction outputted from the sampling circuit, and outputs the current decoding result as the decoding information of the memory instruction in response to the output edge of the output clock; the address output circuit receives the output clock, and outputs the instruction currently outputted from the second output terminal of the sampling circuit as the address information of the memory instruction in response to the output edge. In this solution, the first cycle instruction outputted from the first output terminal of the sampling circuit is delayed by the delay circuit, the instruction decoding circuit decodes the delayed first cycle instruction to obtain decoding information, and outputs the decoding information and address information of the memory instruction simultaneously through the instruction decoding circuit and the address output circuit in response to the output edge of the output clock, thereby shortening the transmission delay of the decoding information and the address information and improving the efficiency of instruction sampling. Furthermore, the output logic for distinguishing between the 1N mode and the 2N mode is reduced in the address output circuit, thereby simplifying the circuit and improving the performance of the DRAM.

[0091] Other embodiments of the present disclosure will readily occur to those skilled in the art after considering the specification and practicing the invention disclosed herein. This disclosure is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art not disclosed herein. The description and examples are to be considered as exemplary only.

[0092] It will be understood that the present disclosure is not limited to the exact construction that has been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof.

Claims

1. An instruction sampling circuit, characterized in that, Comprising: A sampling circuit (11) and a delay circuit (12); The sampling circuit (11) receives a memory instruction (CA) and a sampling clock (PCLK), and is used to sample the memory instruction respectively in response to a first sampling edge and a second sampling edge of the sampling clock, and output a first-cycle instruction (first cycle CA) and a second-cycle instruction (second cycle CA); the sampling circuit (11) has a first output terminal (OUT1) and a second output terminal (OUT2); The input terminal of the delay circuit is connected to the first output terminal of the sampling circuit, and the output terminal of the delay circuit is connected to an instruction decoding circuit (13), and the delay circuit is used to delay the instruction output from the first output terminal (OUT1) of the sampling circuit and then output it; The instruction decoding circuit is coupled to the instruction sampling circuit and receives an output clock (PCSCLK), and is used to decode the instruction output by the sampling circuit, and in response to an output edge of the output clock, output the current decoding result as decoding information of the memory instruction; The second output terminal (OUT2) of the sampling circuit (11) is connected to an address output circuit (14); the address output circuit (14) receives the output clock and is used to, in response to the output edge, output the instruction currently output by the second output terminal of the sampling circuit as address information of the memory instruction.

2. The instruction sampling circuit according to claim 1, wherein The delay circuit (12) includes an even number of inverters.

3. The instruction sampling circuit according to claim 1 or 2, characterized in that, The output edge of the output clock (PCSCLK) is located at the second sampling edge, or is located after the second sampling edge and has a preset delay amount from the second sampling edge, and the delay amount satisfies the timing requirements for sampling at the output edge.

4. The instruction sampling circuit according to claim 3, wherein Both the sampling circuit (11) and the instruction decoding circuit (13) include flip-flops; the delay amount includes the setup time of the flip-flop in the instruction decoding circuit and the hold time of the flip-flop in the sampling circuit.

5. The instruction sampling circuit according to claim 3 or 4, wherein The delay amount is not greater than the difference between the time elapsed between the first sampling edge and the second sampling edge and the setup time of the flip-flop in the instruction decoding circuit.

6. The instruction sampling circuit according to any one of claims 1-5, characterized in that The sampling clock (PCLK) includes an odd clock (PCLK-O) and an even clock (PCLK-E); The sampling circuit (11) includes: a first sub-sampling circuit (111) and a second sub-sampling circuit (112), the first sub-sampling circuit (111) has a first even output terminal and a second even output terminal (EVEN-1T), and the second sub-sampling circuit has a first odd output terminal and a second odd output terminal (ODD-1T); the input terminals of the first sub-sampling circuit and the second sub-sampling circuit are connected to receive the memory instruction (CA); the clock terminal of the first sub-sampling circuit receives the even clock (PCLK-E), and the clock terminal of the second sub-sampling circuit receives the odd clock (PCLK-O); The delay circuit (12) includes: a first sub-delay circuit (121) and a second sub-delay circuit (122). The first even output terminal is connected to the input terminal of the first sub-delay circuit, and the first odd output terminal is connected to the input terminal of the second sub-delay circuit; The output terminals (EVEN-0T, ODD-0T) of the first sub-delay circuit and the second sub-delay circuit, as well as the second even output terminal (EVEN-1T) and the second odd output terminal (ODD-1T) are all connected to the instruction decoding circuit (13); the second even output terminal and the second odd output terminal are connected to the address output circuit (14).

7. The instruction sampling circuit according to claim 6, wherein The instruction decoding circuit (13) includes a decoding circuit (131) and a decoding output circuit (132); The input terminal of the decoding circuit is connected to the output terminals of the first sub-delay circuit, the second sub-delay circuit, as well as the second even output terminal and the second odd output terminal. The output terminal of the decoding circuit is connected to the decoding output circuit. The decoding circuit is used to perform decoding processing; The decoding output circuit receives the output clock and is used to output the decoding result currently output by the decoding circuit as the decoding information of the memory instruction in response to the output edge.

8. The instruction sampling circuit according to claim 7, wherein The decoding circuit includes: a first decoding circuit corresponding to the 1N mode and a second decoding circuit corresponding to the 2N mode; The input terminal of the first decoding circuit is connected to the second even output terminal (EVEN-1T) and the second odd output terminal (ODD-1T). The output terminal of the first decoding circuit is connected to the decoding output circuit (132). The first decoding circuit is used to decode the received instruction and output the corresponding decoding result; The input terminal of the second decoding circuit is connected to the output terminals (EVEN-0T, ODD-0T) of the first sub-delay circuit and the second sub-delay circuit. The output terminal of the second decoding circuit is connected to the decoding output circuit. The second decoding circuit is used to decode the received instruction and output the corresponding decoding result; The decoding output circuit (132) receives the output clock (PCSCLK) and is used to output the decoding result currently output by the first decoding circuit or the second decoding circuit as the decoding information of the memory instruction in response to the output edge.

9. The instruction sampling circuit according to claim 6, wherein The input terminal of the address output circuit is connected to the second even output terminal and the second odd output terminal. The clock terminal of the address output circuit receives the output clock. The address output circuit is used to output the current output of the second even output terminal or the second odd output terminal as the address information of the memory instruction in response to the output edge.

10. The instruction sampling circuit according to claim 9, characterized in that, The address output circuit (14) includes: a first output circuit (141), a second output circuit (142), and an integration circuit (143); The input terminal of the first output circuit is connected to the second even output terminal. The clock terminal of the first output circuit receives the output clock and is used to output the current output of the second even output terminal in response to the output edge; The input end of the second output circuit is connected to the second odd output end, and the clock end of the second output circuit receives the output clock, and is used to output the current output of the second odd output end in response to the output edge. The integration circuit is coupled to the first output circuit and the second output circuit, and is used to integrate the outputs of the first output circuit and the second output circuit and then output them as the address information of the memory instruction.

11. The instruction sampling circuit according to any one of claims 1-10, characterized in that, The instruction sampling circuit further includes: a clock generation circuit; The clock generation circuit receives the sampling clock and is coupled to the instruction decoding circuit and the address output circuit, and is used to generate the output clock according to the sampling clock.

12. A memory, characterized in that, Including: The instruction sampling circuit, the instruction decoding circuit and the address output circuit according to any one of claims 1-11.

Images