Memory and control method therefor, and electronic device

Abstract

Provided in the present disclosure are a memory and a control method therefor, and an electronic device. In a first chip of the memory, each local bit line is coupled to a common bit line on one side by means of a bit line selector of the local bit line, and each local bit line is coupled to a common bit line on the other side by means of a pre-charging switch of the local bit line; and a bit line selector is used for receiving a sub-word-line driving signal and selectively connecting, on the basis of the sub-word-line driving signal, the local bit line connected thereto to the common bit line connected thereto; and a pre-charging switch is used for receiving a sub-word-line driving complementary signal and selectively connecting, on the basis of the sub-word-line driving complementary signal, the local bit line connected thereto to the common bit line connected thereto.

Description

Memory and control method thereof, and electronic device

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on December 29, 2023, with application number 202311869141.2 and application name “A memory and its control method, electronic device”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present disclosure relates to the field of semiconductors, and in particular to a memory, a control method thereof, and an electronic device. Background Art

[0003] With the development of semiconductor technology, semiconductor memory has been widely used in electronic devices. Dynamic Random Access Memory (DRAM) is a type of volatile memory. Due to its fast access speed, DRAM is often used as cache memory.

[0004] Dynamic random access memory (DRAM) mainly consists of two parts: the peripheral circuit (Periphery) and the memory array (Core). To further improve storage density, three-dimensional DRAM (3D DRAM) places the peripheral circuit (Periphery) and the memory array (Core) in two separate chips, which are then connected by bonding. At the same time, the three-dimensional structure of the memory array is more complex, requiring additional control logic.

[0005] Summary of the Invention

[0006] Embodiments of the present disclosure provide a memory, a control method thereof, and an electronic device.

[0007] The technical solution of the present disclosure is achieved as follows:

[0008] In a first aspect, the present disclosure provides a memory, comprising a first chip, the first chip comprising a plurality of memory array chips, each of the memory array chips comprising a plurality of local bit lines and a plurality of common bit lines, the local bit lines extending along a first direction, the common bit lines extending along a second direction, and a common bit line being present on each side of the local bit lines along the first direction; the first direction intersecting the second direction;

[0009] Each of the local bit lines is coupled to the common bit line on one side via a respective bit line selector, and each of the local bit lines is coupled to the common bit line on the other side via a respective precharge switch;

[0010] The bit line selector is configured to receive and selectively connect the connected local bit line and the connected common bit line based on the sub-word line driving signal;

[0011] The precharge switch is configured to receive and selectively connect the connected local bit line and the connected common bit line based on a sub-word line drive complementary signal; wherein the sub-word line drive signal and the sub-word line drive complementary signal are both generated by decoding a row address signal in a command address signal received by the memory.

[0012] In some embodiments, each of the memory array chips includes a plurality of sub-array chips arranged in sequence along the second direction, each of the sub-array chips includes a plurality of memory regions stacked in sequence along the third direction, and each of the memory regions includes two memory layer groups arranged in the first direction; a plurality of local bit lines are provided in each of the memory layer groups, a first common bit line is provided on the outer side of each of the memory layer groups away from another of the memory layer groups in the same memory region, and a second common bit line is provided on the inner side of each of the memory layer groups close to another of the memory layer groups in the same memory region;

[0013] For each of the storage layer groups, each of the local bit lines is coupled to the second common bit line via the respective bit line selectors, and each of the local bit lines is coupled to the first common bit line via the respective precharge switches.

[0014] In some embodiments, each of the memory array chips includes a plurality of sub-array chips arranged in sequence along the second direction, each of the sub-array chips includes a plurality of memory regions stacked in sequence along the third direction, and each of the memory regions includes two memory layer groups arranged in the first direction; a plurality of local bit lines are provided in each of the memory layer groups, a first common bit line is provided on the outer side of each of the memory layer groups away from another of the memory layer groups in the same memory region, and a second common bit line is provided on the inner side of each of the memory layer groups close to another of the memory layer groups in the same memory region;

[0015] For the same sub-array slice, numbering the storage areas along the third direction;

[0016] For the odd-numbered storage regions, each of the local bit lines is coupled to the first common bit line via the respective bit line selectors, and each of the local bit lines is coupled to the second common bit line via the respective precharge switches;

[0017] For the even-numbered storage regions, each of the local bit lines is coupled to the second common bit line via the respective bit line selectors, and each of the local bit lines is coupled to the first common bit line via the respective precharge switches.

[0018] In some embodiments, the memory array chip further includes a plurality of local word lines, and each of the local word lines penetrates the plurality of stacked memory layer groups along a third direction; the third direction is perpendicular to the first direction and perpendicular to the second direction;

[0019] A plurality of local word lines passing through the same storage layer group and aligned along the first direction form a sub-word line group;

[0020] One of the local bit lines corresponds to one of the sub-word line groups, and a memory cell is formed at the intersection of the local bit line and each of the corresponding local word lines;

[0021] All local word lines in the same sub-word line group share the same sub-word line drive signal and the same sub-word line drive complementary signal, the bit line selector of the local bit line receives the sub-word line drive signal of the corresponding sub-word line group, and the pre-charge switch of the local bit line receives the sub-word line drive complementary signal of the corresponding sub-word line group.

[0022] In some embodiments, each of the memory array slices further includes a plurality of common word lines extending along the second direction;

[0023] The local word lines in each sub-array slice are numbered independently in sequence. Local word lines with the same number in different sub-array slices are electrically connected to the same common word line and share the same sub-word line driving signal and the same sub-word line driving complementary signal.

[0024] In some embodiments, in the memory array slice, the common word lines are numbered sequentially along a first direction, and N consecutively numbered common word lines form a main word line group;

[0025] The memory includes a decoding unit and a plurality of sub-word line driving units, where N is a positive integer;

[0026] The decoding unit is configured to decode the row address signal to generate a main word line driving signal, the sub word line driving signal and a sub word line driving complementary signal for each of the common word lines;

[0027] The sub-word line driving unit is coupled to one of the common word lines and configured to receive and turn on or off the coupled common word line based on a corresponding main word line driving signal, a corresponding sub-word line driving signal and a corresponding sub-word line driving complementary signal;

[0028] Among them, the two storage layer groups in each storage area are successively called the first storage layer group and the second storage layer group along the first direction, the main word line drive signal is used to select a main word line group in each of the first storage layer group and the second storage layer group, and the sub-word line drive signal and the sub-word line drive complementary signal are used to select one of the common word lines from the main word line group selected in the first storage layer group, or to select one of the common word lines from the main word line group selected in the second storage layer group.

[0029] In some embodiments, the sub-word line driving unit includes a first switch tube, a second switch tube and a third switch tube;

[0030] The control ends of the first switch tube and the second switch tube both receive the main word line drive signal, the first end of the first switch tube receives the sub-word line drive signal, the second end of the first switch tube, the first end of the second switch tube, and the first end of the third switch tube are all connected to the common word line, the second end of the second switch tube and the second end of the third switch tube are both connected to the power supply end, and the control end of the third switch tube receives the sub-word line drive complementary signal.

[0031] In some embodiments, the memory further includes a second chip, the first chip and the second chip are stacked along a third direction, and the first chip is bonded to the second chip;

[0032] The second chip includes a sensing amplification region;

[0033] In the first chip, a step contact structure is provided between two adjacent storage layer groups along a first direction, and the common bit line directly connected to the bit line selector is coupled to the sensing amplification region through the step contact structure.

[0034] In a second aspect, an embodiment of the present disclosure provides a method for controlling a memory, wherein a first chip in the memory includes a plurality of memory array chips, each of the memory array chips includes a plurality of local bit lines and a plurality of common bit lines, each of the local bit lines is coupled to a common bit line on one side via a bit line selector, and each of the local bit lines is coupled to a common bit line on the other side via a respective precharge switch;

[0035] The method comprises:

[0036] receiving a command address signal, decoding a row address signal in the command address signal, and generating a plurality of main word line drive signals, a plurality of sub-word line drive signals, and a plurality of sub-word line drive complementary signals;

[0037] Based on each of the sub-word line driving signals, controlling the corresponding bit line selector to connect the connected local bit line and the connected common bit line;

[0038] Based on each of the sub-word line driving complementary signals, the corresponding precharge switch is controlled to connect the connected local bit line and the connected common bit line.

[0039] In some embodiments, each of the memory array chips includes a plurality of sub-array chips arranged in sequence along the second direction, each of the sub-array chips includes a plurality of storage areas stacked in sequence along the third direction, and each of the storage areas includes two storage layer groups arranged along the first direction; a plurality of local bit lines are provided in each of the storage layer groups, and a common bit line is provided on each side of each of the storage layer groups along the first direction;

[0040] The memory array chip further includes a plurality of local word lines, and each of the local word lines penetrates a plurality of stacked memory layer groups along a third direction; a plurality of the local word lines that pass through the same memory layer group and are aligned along the first direction form a sub-word line group, and all local word lines in the same sub-word line group share the same sub-word line drive signal and the same sub-word line drive complementary signal; a local bit line corresponds to a sub-word line group, and a memory cell is formed at the intersection of the local bit line and each corresponding local word line;

[0041] Each of the sub-word line groups has a sub-word line driving signal and a sub-word line driving complementary signal; the method further includes:

[0042] transmitting a sub-word line driving signal of the sub-word line group to a bit line selector of the local bit line corresponding thereto;

[0043] The sub-word line driving complementary signal of the sub-word line group is transmitted to the precharge switch of the local bit line corresponding thereto.

[0044] In some embodiments, the local word lines are numbered independently and sequentially in each sub-array slice, and the local word lines with the same number in different sub-array slices are electrically connected to the same common word line and share the same sub-word line drive signal and the same sub-word line drive complementary signal; in the memory array slice, the common word lines are numbered along a first direction, and N consecutively numbered common word lines form a main word line group;

[0045] The two storage layer groups in each storage area are sequentially referred to as the first storage layer group and the second storage layer group along the first direction; the method further includes:

[0046] Based on the main word line driving signal, one main word line group is selected in each of the first storage layer group and the second storage layer group.

[0047] Selecting one of the common word lines from the main word line group selected from the first storage layer group or the main word line group selected from the second storage layer group based on the sub-word line driving signal and the sub-word line driving complementary signal;

[0048] The selected common word line is turned on, and the operation indicated by the command address signal is performed.

[0049] In a third aspect, an embodiment of the present disclosure provides an electronic device, comprising the memory as described in the first aspect.

[0050] The embodiments of the present disclosure provide a memory, a control method thereof, and an electronic device, which utilize sub-word line drive signals and sub-word line drive complementary signals generated by decoding row address signals to control the working states of the pre-charge switches and bit line selectors of local bit lines. Thus, although the stereoscopic memory additionally introduces pre-charge switches and bit line selectors, it does not require the additional introduction of control information and redundant decoding logic, thereby improving control efficiency and reducing redundant devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] Figure 1A / 1B is a schematic diagram of the structure of the memory array chip in the first chip;

[0052] FIG2 is a schematic diagram of a cross-sectional structure of a memory array chip;

[0053] FIG3 is a schematic diagram of the cross-sectional structure of another memory array chip;

[0054] FIG4 is a first structural diagram of a sub-array sheet provided in an embodiment of the present disclosure;

[0055] FIG5 is a schematic diagram of a stacking structure of a memory provided by an embodiment of the present disclosure;

[0056] FIG6 is a second structural diagram of a sub-array sheet provided in an embodiment of the present disclosure;

[0057] FIG7 is a schematic structural diagram of another memory array chip provided by an embodiment of the present disclosure;

[0058] 8A / 8B are schematic cross-sectional views of a memory array chip according to an embodiment of the present disclosure;

[0059] FIG9 is a schematic diagram of the circuit structure of a first chip provided in an embodiment of the present disclosure;

[0060] FIG10 is a schematic structural diagram of a sub-word line driving unit provided in an embodiment of the present disclosure;

[0061] FIG11 is a flow chart of a control method provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0062] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the technical solutions of the present disclosure are further elaborated in detail below with reference to the accompanying drawings and embodiments. The described embodiments should not be regarded as limiting the present disclosure. All other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present disclosure.

[0063] In the following description, reference is made to “some embodiments”, which describes a subset of all possible embodiments, but it will be understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0064] If similar descriptions of "first / second" appear in the application documents, the following explanation is added. In the following description, the terms "first / second / third" are merely used to distinguish similar objects and do not represent a specific order for the objects. It is understandable that "first / second / third" can be interchanged with a specific order or sequence where permitted, so that the embodiments of the present disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0065] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art in the art of the present disclosure. The terms used herein are only for the purpose of describing the embodiments of the present disclosure and are not intended to limit the present disclosure.

[0066] Glossary:

[0067] WL (WordLine): word line;

[0068] BL (BitLine): bit line;

[0069] CMOS (Complementary Metal Oxide Semiconductor): complementary metal oxide semiconductor;

[0070] TSV (Through-Silicon-Via): through silicon via;

[0071] Mat (Memory Array Tile): storage array tile.

[0072] Before introducing the embodiments of the present disclosure, three directions that may be used to describe a three-dimensional structure in a plane involved in the following embodiments are defined. Taking a Cartesian coordinate system as an example, the three directions may include a first direction, a second direction, and a third direction.

[0073] The semiconductor chip may include a top surface on the front side and a bottom surface on the back side opposite to the front side; while ignoring the flatness of the top surface and the bottom surface, a direction intersecting (for example, perpendicular) with the top surface and the bottom surface of the semiconductor chip is defined as a third direction; at the same time, an extension direction of a local bit line in the semiconductor chip is defined as a first direction, and an extension direction of a local word line in the semiconductor chip is defined as a second direction, and the first direction and the second direction intersect.

[0074] 3D DRAM consists of a first chip and a second chip stacked along a third dimension, with the memory array (Core) located in the first chip and the peripheral control area (Periphery), sensing and amplifier area, etc. located in the second chip. The memory array (Core) of the first chip includes a large number of memory cells, which are further divided into multiple memory array slices (Mats) for better control and management.

[0075] Please refer to Figure 1A, which shows a schematic diagram of the structure of the memory array chip 11 in the first chip. As shown in Figure 1A, each memory array chip 11 includes a plurality of sub-array chips Sub Mat0, Sub Mat1, Sub Mat2, etc. arranged in sequence along the second direction. Each sub-array chip includes a plurality of storage areas stacked in sequence along the third direction. Each storage area includes two storage layer groups arranged in the first direction, respectively referred to as the first storage layer group and the second storage layer group. A step contact structure (Staircase) 14 is provided between the first storage layer group and the second storage layer group. Please refer to Figure 1B, which shows the positions of the local bit line Local BL, the common bit line Common BL, the local word line Local WL, and the common word line Common WL. As shown in Figure 1B, the local word line runs through multiple storage layer groups along the third direction. In each sub-array chip, the local word lines are numbered along the second direction, and local word lines with the same number in different sub-array chips are coupled to the same common word line, and the common word line extends along the second direction; at the same time, each storage layer group includes multiple local bit lines extending along the first direction, and a common bit line is respectively provided on the left and right sides of each storage layer group.

[0076] Please refer to Figures 2 and 3, both of which are schematic cross-sectional views of the memory array slice along the third direction, and both of which are based on the memory array slice including 20 sub-array slices (Sub Mat0, Sub Mat1...Sub Mat19). As shown in Figure 2, a first common bit line is provided on the outside of each memory layer group (referring to the side away from another memory layer group in the same memory area), and a second common bit line is provided on the inside of each memory layer group (close to another memory layer group in the same memory area). Please refer to Figure 3, all local bit lines in the memory layer group are connected to the first common bit line through the precharge switch Eq, and all local bit lines in the memory layer group are connected to the second common bit line through the bit line selector Se. At the same time, a step contact structure is provided between the first memory layer group and the second memory layer group, and each second common bit line is coupled to the sense amplifier in the sense amplifier area through the step contact structure.

[0077] Taking data reading as an example, multiple groups of target memory cells are enabled by turning on a common word line, with each group of target memory cells aligned along a third direction. At the same time, the bit line selectors Se of the local bit lines connected to each group of target memory cells are turned on. At this point, each target memory cell is connected to its corresponding second common bit line. As a result, the group of second common bit lines aligned along the third direction share charge with their respective target memory cells and undergo sense amplification. After sense amplification, the charge is at a high or low potential (depending on the data stored in the target memory cells). The bit line selectors Se of the unselected local bit lines are turned off, and the precharge switches Eq are turned on. Simultaneously, all first common bit lines are charged to a precharge potential, so that all unselected local bit lines are at the precharge potential. Here, the precharge potential can be an intermediate potential, which can be half the memory array power supply voltage (Vblh), i.e., intermediate potential = 1 / 2Vblh.

[0078] Simply put, for 3D DRAM, the local bit lines of the same storage layer group share a first common bit line and the same second common bit line. The bit line selector Se is used to select whether to access the second common bit line, and the pre-charge switch Eq is used to select whether to access the first common bit line. Therefore, the control logic of the bit line selector Se / pre-charge switch Eq needs to be additionally designed.

[0079] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

[0080] In one embodiment of the present disclosure, a memory is provided, comprising a first chip, wherein the first chip comprises a plurality of memory array chips 11. Referring to FIG4 , a partial structural schematic diagram of a memory array chip 11 provided in an embodiment of the present disclosure is shown, specifically a schematic diagram of the remaining portion of a sub-array chip (e.g., Sub Mat0, Sub Mat1, etc.) after omitting the step contact structure. As shown in FIG4 , each memory array chip comprises a plurality of local bit lines and a plurality of common bit lines (e.g., the first common bit line 12 and the second common bit line 13 in FIG4 ), wherein the local bit lines extend along a first direction, and the common bit lines extend along a second direction, and a common bit line exists on each side of the local bit lines along the first direction; the first direction intersects the second direction;

[0081] Each local bit line is coupled to a common bit line on one side via a respective bit line selector Se, and each local bit line is coupled to a common bit line on the other side via a respective precharge switch Eq;

[0082] The bit line selector Se is configured to receive and drive the bit line based on the sub-word line driving signal Phdec. (i is a positive integer), selectively connecting the connected local bit line and the connected common bit line;

[0083] A precharge switch Eq is configured to receive and drive a complementary signal PhdecN based on a sub-word line. (i is a positive integer), selectively connecting the connected local bit line and the connected common bit line.

[0084] Here, the sub-word line driving signal Phdec And the sub-word line drive complementary signal PhdecN They are generated by decoding the row address signal in the command address signal received by the memory. Generally speaking, the sub-word line drives the complementary signal PhdecN The sub-word line can be driven by the signal Phdec Meanwhile, in some embodiments, the sub-word line driving complementary signal PhdecN The sub-word line can be driven by the signal Phdec After inversion and delay processing, the sub-word line drive signal Phdec is obtained. And the sub-word line drive complementary signal PhdecN It is not a completely strict anti-phase state.

[0085] It should be understood that the row address signal is used to indicate the word line information selected (i.e., enabled) for this operation. In other words, the disclosed embodiment reuses word line information to control the operating state of the local bit line precharge switch Eq and the bit line selector Se. The specific principle is described below. Therefore, for stereo memory, although the precharge switch Eq and bit line selector Se are additionally introduced, no additional control information or redundant decoding logic is required, thereby improving control efficiency and reducing redundant components.

[0086] It should be noted that FIG4 illustrates that each storage layer group includes four local bit lines, but this does not constitute a relevant limitation.

[0087] Referring to Figures 1A and 1B , each memory array chip includes a plurality of sub-array chips (Sub Mat0, Sub Mat1, Sub Mat2, etc.) sequentially arranged along the second direction. Each sub-array chip includes a plurality of storage areas stacked sequentially along the third direction. Figures 1A and 1B illustrate an example in which each sub-array chip includes five storage areas, but the number of storage areas may be greater. Each storage area includes a first storage layer group and a second storage layer group arranged along the first direction.

[0088] In some embodiments, as shown in Figure 4, multiple local bit lines are set in each storage layer group, a first common bit line 12 is set on the outside of each storage layer group away from another storage layer group in the same storage area, and a second common bit line 13 is set on the inside of each storage layer group close to another storage layer group in the same storage area.

[0089] For each memory layer group, each local bit line is coupled to the second common bit line 13 via a respective bit line selector Se, and each local bit line is coupled to the first common bit line 12 via a respective precharge switch Eq.

[0090] In some embodiments, the memory further includes a second chip, the first chip and the second chip are stacked along a third direction, and the first chip is bonded to the second chip; the second chip includes a sensing amplification region;

[0091] In the first chip, a step contact structure is provided between two adjacent memory layer groups along the first direction, and a common bit line directly connected to the bit line selector Se is coupled to the sensing amplification region through the step contact structure.

[0092] It should be noted that the first chip and the second chip are connected by bonding. Bonding means that the two chips are electrically connected through a hybrid bonding structure (also known as a bonding column). Hybrid bonding is the process of creating a permanent bond between heterogeneous or homogeneous chips. "Hybrid" means forming a dielectric-dielectric and metal-metal bond between two surfaces, which has the following advantages: (1) Shorter interconnection distance: Not only does it not require wires to connect to each other, but it also does not require TSVs to pass through the entire CMOS layer. Interconnection can be achieved simply by connecting copper contacts in the back-end; (2) Higher interconnection density: The area of ​​the copper contacts is very small. Compared with solder balls and TSVs with a diameter of 100 microns, the spacing size of the copper contacts in the hybrid bonding process is even less than 10 microns, which can undoubtedly achieve a higher interconnection density; (3) Lower cost: It is undeniable that interconnecting each chip individually requires more time. Through wafer bonding, large-area high-density interconnection can be achieved, which makes a significant contribution to the improvement of production capacity. Naturally, production costs can also be reduced.

[0093] It should be noted that the sensing amplification area includes multiple sensing amplifiers (SA), also known as sensitive amplifiers, which sense and amplify the electrical signal of the common bit line connected to the selected memory cell, and finally the potential of the common bit line reaches a low potential or a high potential, thereby achieving the purpose of reading or writing data from the selected memory cell.

[0094] Here, since 3D DRAM mostly uses a vertical stacking of multiple layers of memory cells (i.e., multiple memory layer groups) to form a storage structure, in order to ensure that the sense amplifier can be smoothly connected to the common bit line in each memory layer group, it is necessary to form a 3D step contact structure (Staircase). The different steps of the step contact structure are electrically isolated, and one step is correspondingly connected to a common bit line (connected to the bit line connector Se), so that the common bit line is connected to the sense amplifier SA in the sense amplification area to realize the sense amplification processing.

[0095] In this way, the local bit lines in each storage layer group are coupled to the second common bit line 13 set in the middle part of the storage area to which they belong through the bit line selector Se, and a step contact structure is also set in the middle part of the storage area, that is, the second common bit line 13 of each storage layer group can be externally connected to the sensing amplifier in the sensing amplification area through the step contact structure set in the middle part of the storage area.

[0096] In some other embodiments, referring to FIG6 , for the same sub-array slice, the storage areas are numbered along the third direction: storage area 0, storage area 1, storage area 2, storage area 3, storage area 4;

[0097] For odd-numbered storage areas 1 and 3, each local bit line is coupled to the first common bit line 12 via its own bit line selector Se, and each local bit line is coupled to the second common bit line 13 via its own pre-charge switch Eq; for even-numbered storage areas 0, 2, and 4, each local bit line is coupled to the second common bit line 13 via its own bit line selector Se, and each local bit line is coupled to the first common bit line 12 via its own pre-charge switch Eq.

[0098] That is to say, the first common bit lines 12 of two adjacent storage layer groups are adjacent in the third direction, and the second common bit lines 13 of two adjacent storage layer groups are adjacent in the third direction, but any first common bit line 12 and any second common bit line 13 are not adjacent in the third direction; at the same time, for odd-numbered storage areas 1 and 3, the local bit lines are connected to the first common bit line 12 through the bit line selector Se, and are connected to the second common bit line 13 through the pre-charge switch Eq; for even-numbered storage areas 0, 2, and 4, the local bit lines are connected to the second common bit line 13 through the bit line selector Se, and are connected to the first common bit line 12 through the pre-charge switch Eq. Therefore, during the sensing and amplification process, for the selected multiple storage layer groups, for two adjacent first common bit lines 12, one first common bit line 12 must be in the sensing and amplification state (at a high or low potential after the sensing and amplification state ends, depending on the specific data value), and the other first common bit line 12 must be in the precharge potential. For two adjacent second common bit lines 13, one second common bit line 13 must be in the sensing and amplification state (at a high or low potential after the sensing and amplification state ends, depending on the specific data value), and the other second common bit line must be in the precharge potential, with the low potential < precharge potential < high potential. However, two adjacent common bit lines along the third direction will not undergo sensing and amplification processing at the same time, and thus the two adjacent common bit lines along the third direction will not be in the sensing and amplification state at the same time. Therefore, the coupling between the two adjacent common bit lines is significantly reduced, thereby improving the sensing and amplification margin.

[0099] Of course, no matter how the positions of the precharge switch Eq and the bit line selector Se change, the control signal received by them remains unchanged, and the sub-word line drive complementary signal PhdecN generated by the row address signal is still multiplexed. and sub-word line drive signal Phdec Just control it.

[0100] In addition, please refer to Figure 7. At this time, the step contact structure will be located in the middle of each storage area and on the outside of each storage area, so that for the even-numbered storage areas 0, 2, and 4, the local bit line is connected to the inner second common bit line 13, and then coupled to the sense amplifier through the internal step contact structure; for the odd-numbered storage areas 1 and 3, the local bit line is connected to the outer first common bit line 12, and then coupled to the sense amplifier through the external step contact structure.

[0101] In some embodiments, as shown in FIG1B , the memory array further includes multiple local word lines, each of which extends along a third direction through the stacked memory layer groups. A memory cell is formed at the intersection of a local bit line and each corresponding local word line. Note that the local bit lines and local word lines are not directly connected. Exemplarily, the memory cell has a 1T1C structure, comprising a transistor and a capacitor. The transistor's gate is connected to the local word line, and the transistor's source and drain are connected to the local bit line and capacitor, respectively. The third direction is perpendicular to both the first direction and the second direction.

[0102] Please refer to Figure 8A , which illustrates the control logic for local word lines and local bit lines, using a cross-section of sub-array wafer Sub Mat0 along the third direction as an example. As shown in Figure 8A , multiple local word lines that pass through the same storage layer group and are aligned along the first direction form a sub-word line group. All local word lines in the same sub-word line group share the same sub-word line drive signal and the same sub-word line drive complement signal.

[0103] For example, for the first memory layer group, the local word line WL <0> 、WL <4> ...WL <1592> 、WL <1596> Form a sub-wordline group, and the sub-wordline group shares Phdec <0> and PhdecN <0> Local word line WL <1> 、WL <5> ...WL <1593> 、WL <1597> Form a sub-wordline group, and the sub-wordline group shares Phdec <1> and PhdecN <1> Local word line WL <2> 、WL <6> ...WL <1594> 、WL <1598> Form a sub-wordline group, and the sub-wordline group shares Phdec <2> and PhdecN <2> Local word line WL <3> 、WL <7> ...WL <1595> 、WL <1599> Form a sub-wordline group, and the sub-wordline group shares Phdec <3> and PhdecN <3> ;

[0104] For the second storage layer group, the local word line WL <1600> 、WL <1604> ...WL <3192> 、WL <3196> Form a sub-wordline group, and the sub-wordline group shares Phdec <4> and PhdecN <4> Local word line WL <1601> 、WL <1605> ...WL <3193> 、WL <3197> Form a sub-wordline group, and the sub-wordline group shares Phdec <5> and PhdecN <5> Local word line WL <1602> 、WL <1606> ...WL <3194> 、WL <3198> Form a sub-wordline group, and the sub-wordline group shares Phdec <6> and PhdecN <6> Local word line WL <1603> 、WL <1607> ...WL <3195> 、WL <3199> Form a sub-wordline group, and the sub-wordline group shares Phdec <7> and PhdecN <7> .

[0105] A local bit line corresponds to a sub-word line group, and the intersection of the local bit line and each corresponding local word line forms a memory cell; for example, the local bit line BL0 and the local word line WL <0> 、WL <4> ...WL <1592> 、WL <1596> Correspondingly, the local bit line BL0 and the local word line WL <0> There is a memory cell at the intersection of the local bit line BL0 and WL <4> There is a memory cell at the intersection of the local bit lines BL0 and WL <1596> There is a storage unit at the intersection of .

[0106] The bit line selector Se of the local bit line receives the sub-word line drive signal of the corresponding sub-word line group, and the precharge switch Eq of the local bit line receives the sub-word line drive complementary signal of the corresponding sub-word line group. For example, the control signal Sel of the bit line selector Se of the local bit line BL0 is <0> =Phdec <0> , the control signal Eq of the precharge switch Eq of the local bit line BL0 <0> =PhdecN <0> .

[0107] In some embodiments, as shown in FIG8B , each memory array chip further includes a plurality of common word lines Common WL extending along the second direction; the local word lines are independently numbered in sequence in each sub-array chip, and local word lines with the same number in different sub-array chips are electrically connected to the same common word line and share the same sub-word line drive signal and the same sub-word line drive complementary signal.

[0108] That is, the local word lines WL in each sub-array tile Sub Mat0, Sub Mat1...Sub Mat19 <0> 、WL <4> ...WL <1596> Both share the sub-word line drive signal Phdec <0> And the sub-word line drive complementary signal PhdecN <0> .

[0109] Specifically, the local word lines WL in each sub-array tile Sub Mat0, Sub Mat1...Sub Mat19 <0> Connected to the common bit line Common WL0, each sub-array piece Sub Mat0, Sub Mat1...Sub Mat19 local word line WL <4> Connected to the common bit line Common WL4... local word line WL in each sub-array tile Sub Mat0, Sub Mat1...Sub Mat19 <1596> Connected to the common bit line Common WL1596, but the common bit lines Common WL0, Common WL4..., Common WL1596 share the sub-word line drive signal Phdec <0> And the sub-word line drive complementary signal PhdecN <0> ;

[0110] At the same time, the bit line selector Se of the first local bit line BL0 in each storage area in each sub-array receives the sub-word line drive signal Phdec <0> The precharge switch Eq of the local bit line BL0 in each storage area in each sub-array receives the sub-word line drive signal PhdecN <0> .

[0111] In some embodiments, as shown in FIG8B , in a memory array, common word lines are sequentially numbered along a first direction, and N consecutively numbered common word lines form a main word line group. FIG8B takes N=4 as an example, i.e., WL <0> ~WL <3> is a main word line group, WL <4> ~WL <7> For a main word line group...

[0112] 9 , the memory includes a decoding unit 21 and a plurality of sub-word line driving units 22 , where N is a positive integer;

[0113] The decoding unit 21 is configured to decode the row address signal to generate a main word line driving signal GrDec<399:0>, a sub word line driving signal Phdec<7:0> and a sub word line driving complementary signal PhdecN<7:0> for each common word line.

[0114] The sub-word line driving unit 22 is coupled to a common word line and configured to receive and turn on or off the coupled common word line based on a corresponding main word line driving signal, a corresponding sub-word line driving signal and a corresponding sub-word line driving complementary signal;

[0115] Among them, the main word line drive signal is used to select a main word line group in the first storage layer group and the second storage layer group, and the sub-word line drive signal and the sub-word line drive complementary signal are used to select a common word line from the main word line group selected in the first storage layer group, or to select a common word line from the main word line group selected in the second storage layer group.

[0116] For example, assuming that the main word line driving signal GrDec <0> =0, GrDec <1> ~GrDec <399> =1 (when the main word line drive signal is low, it indicates selection; when the main word line drive signal is high, it indicates non-selection), sub-word line drive signal Phdec <0> =1, Phdec <1> ~Phdec <7> =0, sub-word line driving complementary signal PhdecN <0> =0, PhdecN <1> ~PhdecN <7> =1, then the common bit line Common WL <0> Selected, that is, WL in each sub-array piece Sub Mat0, Sub Mat1...Sub Mat19 <0> will be selected (turned on); at the same time, for each storage area of ​​each sub-array chip Sub Mat0, Sub Mat1 ... Sub Mat19 (as FIG. 8B is a cross-sectional view, it is only a schematic view of one storage area of ​​each sub-array chip Sub Mat0, Sub Mat1 ... Sub Mat19), the bit line selector Se of the local bit line BL0 is turned on (its control signal Sel <0> =Phdec <0> =1), and the precharge switch Eq is turned off (its control signal Eq <0> =PhdecN <0> =0), and the bit line selectors Se of the local bit lines BL1 to BL4 are turned off, and the precharge switch Eq is turned on. <0> When BL0 is turned on, it is connected to the adjacent common bit line through the bit line selector Se, and the common bit line is coupled to the sense amplifier via the step contact structure. <0> The memory cell formed at the intersection of WL and BL0 will share the charge with the corresponding common bit line (through BL0 and bit line selector Se), and the potential of the common bit line is amplified by the sense amplifier; at the same time, WL <1> ~WL <4> It is not turned on. For BL1~BL4, they are connected to the adjacent common bit line through the precharge switch Eq, and the common bit line is controlled at the precharge potential, which can be the intermediate potential 1 / 2Vblh, and Vblh is the power supply potential of the storage array (or sense amplifier).

[0117] In some embodiments, referring to FIG. 10 , the sub-word line driving unit 22 includes a first switch tube 301 , a second switch tube 302 , and a third switch tube 303 ;

[0118] The control ends of the first switch tube 301 and the second switch tube 302 both receive the main word line drive signal Grdec. The first end of the first switch tube 301 receives the sub-word line drive signal Phdec. The second end of the first switch tube 301, the first end of the second switch tube 302, and the first end of the third switch tube 303 are all connected to the common word line Common WL. The second end of the second switch tube 302 and the second end of the third switch tube 303 are both connected to the power supply end. The control end of the third switch tube 303 receives the sub-word line drive complementary signal PhdecN.

[0119] It should be noted that the power supply terminal may be a ground terminal, the first switch tube 301 is P-type doped, and the second switch tube 302 and the third switch tube 303 are both N-type doped.

[0120] In this way, in one case, if Grdec=0, it means that the main word line group where the common word line is located is selected, and the first switch tube 301 is turned on. If Phdec=1, it means that the common word line is selected. At this time, the common word line Common WL is at a high level (that is, selected / turned on), and the transistor in the connected memory cell is turned on; in another case, if Grdec=0, Phdec=0, it means that although the main word line group where the common word line is located is selected, the common word line is not selected, the common word line Common WL is at a low level, and the transistor in the connected memory cell will not be turned on; in yet another case, if Grdec=1, it means that the main word line group where the common word line is located is not selected as a whole, the first switch tube 301 is not turned on, the common word line Common WL is at a low level, and the transistor in the connected memory cell will not be turned on.

[0121] In addition, the third switch tube 303 is used to quickly turn off the corresponding common word line after the common word line is selected and the corresponding operation is performed.

[0122] In summary, the disclosed embodiments provide a three-dimensional memory, comprising a first chip and a second chip, which are stacked along a third direction and connected by hybrid bonding. The first chip is primarily used to fabricate a memory array (Core), which is further divided into multiple memory array chips (Mat) for better control and management; the second chip is primarily used to fabricate a peripheral control region (Periphery) and a sensing amplification region, among others. In the first chip, each memory array chip comprises multiple sub-array chips arranged in sequence along the second direction, each sub-array chip comprises multiple storage regions stacked in sequence along the third direction, and each storage region comprises two storage layer groups arranged along the first direction; each storage layer group comprises multiple local bit lines, and each storage layer group has a common bit line disposed on both sides along the first direction; each local bit line is coupled to the common bit line on one side via its own bit line selector, and each local bit line is coupled to the common bit line on the other side via its own precharge switch, and the bit line selector operates based on a sub-word line drive signal, and the precharge switch operates based on a sub-word line drive complementary signal. In this way, the embodiment of the present disclosure reuses word line information to control the working status of the pre-charge switch Eq and the bit line selector Se of the local bit line. Therefore, although the three-dimensional memory additionally introduces the pre-charge switch Eq and the bit line selector Se, it does not need to additionally introduce control information and redundant decoding logic, thereby improving control efficiency and reducing redundant devices.

[0123] In another embodiment of the present disclosure, see Figure 11, which shows a flow chart of a control method for a memory provided by an embodiment of the present disclosure. The control method is applied to the aforementioned memory, please refer to Figure 1A, the memory includes a first chip and a second chip stacked along a first direction, the first chip includes a plurality of memory array chips, each memory array chip includes a plurality of sub-array chips arranged in sequence along a second direction, each sub-array chip includes a plurality of storage areas stacked in sequence along a third direction, each storage area includes two storage layer groups arranged along the first direction; each storage layer group includes a plurality of local bit lines, and each storage layer group is provided with a common bit line on both sides along the first direction, each local bit line is coupled to the common bit line on one side via its own bit line selector, and each local bit line is coupled to the common bit line on the other side via its own precharge switch.

[0124] As shown in FIG11 , the method includes:

[0125] S501: Receive a command address signal, decode a row address signal in the command address signal, and generate a plurality of main word line drive signals, a plurality of sub-word line drive signals, and a plurality of sub-word line drive complementary signals.

[0126] S502 : Based on each sub-word line driving signal, control the corresponding bit line selector to connect the connected local bit line and the connected common bit line.

[0127] S503 : Based on each sub-word line driving complementary signal, controlling the corresponding precharge switch to connect the connected local bit line and the connected common bit line.

[0128] In some embodiments, referring to FIG. 8B , the memory array chip further includes a plurality of local word lines, each of which penetrates through a plurality of stacked memory layer groups along a third direction. Multiple local word lines that pass through the same memory layer group and are aligned along the first direction form a sub-word line group. All local word lines in the same sub-word line group share the same sub-word line drive signal and the same sub-word line drive complementary signal. A local bit line corresponds to a sub-word line group, and a memory cell is formed at the intersection of a local bit line and each corresponding local word line.

[0129] Each sub-word line group has a sub-word line driving signal and a sub-word line driving complementary signal; the method further comprises:

[0130] a bit line selector for transmitting a sub-word line driving signal of the sub-word line group to a local bit line corresponding thereto;

[0131] The sub-word line driving complementary signal of the sub-word line group is transmitted to the precharge switch of the local bit line corresponding thereto.

[0132] In some embodiments, local word lines are numbered independently and sequentially in each sub-array slice, and local word lines with the same number in different sub-array slices are electrically connected to the same common word line and share the same sub-word line drive signal and the same sub-word line drive complementary signal; in the memory array slice, the common word lines are numbered along a first direction, and N consecutively numbered common word lines form a main word line group;

[0133] The two storage layer groups in each storage area are sequentially referred to as the first storage layer group and the second storage layer group along the first direction; the method further includes:

[0134] Based on the main word line driving signal, a main word line group is selected in each of the first storage layer group and the second storage layer group.

[0135] Selecting a common word line from the main word line group selected in the first storage layer group or the main word line group selected in the second storage layer group based on the sub-word line driving signal and the sub-word line driving complementary signal;

[0136] The selected common word line is turned on and the operation indicated by the command address signal is performed.

[0137] In this way, the embodiment of the present disclosure reuses word line information to control the working status of the pre-charge switch Eq and the bit line selector Se of the local bit line. Therefore, although the three-dimensional memory additionally introduces the pre-charge switch Eq and the bit line selector Se, it does not need to additionally introduce control information and redundant decoding logic, thereby improving control efficiency and reducing redundant devices.

[0138] In another embodiment of the present disclosure, an electronic device is provided. The electronic device includes a memory as shown in FIG4 . The memory includes a first chip and a second chip stacked along a third direction. The first chip and the second chip are bonded together.

[0139] Referring to Figure 1A , in a first chip, each memory array chip includes multiple sub-array chips arranged in sequence along a second direction. Each sub-array chip includes multiple memory regions stacked in sequence along a third direction. Each memory region includes two memory layer groups arranged along the first direction. Each memory layer group includes multiple local bit lines, and a common bit line is provided on both sides of each memory layer group along the first direction. Each local bit line is coupled to the common bit line on one side via its own bit line selector, and each local bit line is coupled to the common bit line on the other side via its own pre-charge switch. Referring to Figure 4 , the bit line selector operates based on a sub-word line drive signal, and the pre-charge switch operates based on a complementary sub-word line drive signal. Thus, the disclosed embodiment reuses word line information to control the operating states of the local bit line pre-charge switch Eq and the bit line selector Se. Thus, although the stereoscopic memory additionally introduces the pre-charge switch Eq and the bit line selector Se, no additional control information or redundant decoding logic is required, thereby improving control efficiency and reducing redundant components.

[0140] It should be noted that, in this document, the terms "comprise," "include," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus comprising a list of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a..." does not preclude the presence of other identical elements in the process, method, article, or apparatus comprising the element.

[0141] The serial numbers of the embodiments of the present disclosure are for descriptive purposes only and do not represent the merits of the embodiments. The methods disclosed in the several method embodiments provided in the present disclosure can be arbitrarily combined to obtain new method embodiments when there is no conflict. The features disclosed in the several product embodiments provided in the present disclosure can be arbitrarily combined to obtain new product embodiments when there is no conflict. The features disclosed in the several method or device embodiments provided in the present disclosure can be arbitrarily combined to obtain new method embodiments or device embodiments when there is no conflict.

[0142] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A memory, characterized in that, The memory includes a first chip, the first chip includes a plurality of memory array slices, each of the memory array slices includes a plurality of local bit lines and a plurality of common bit lines, the local bit lines extend along a first direction, the common bit lines extend along a second direction, and there is one of the common bit lines on each side of the local bit line along the first direction; The first direction intersects with the second direction; Each of the local bit lines is coupled to the common bit line on one side via its respective bit line selector (Se), and each of the local bit lines is coupled to the common bit line on the other side via its respective precharge switch (Eq); The bit line selector (Se) is configured to receive and, based on a sub-word line driving signal, selectively connect the connected local bit line to the connected common bit line; The precharge switch (Eq) is configured to receive and, based on a complementary sub-word line driving signal, selectively connect the connected local bit line to the connected common bit line; wherein, both the sub-word line driving signal and the complementary sub-word line driving signal are generated by decoding a row address signal in the command address signal received by the memory.

2. The memory according to claim 1, characterized in that, Each of the memory array slices includes a plurality of sub-array slices arranged in sequence along the second direction, each of the sub-array slices includes a plurality of memory regions stacked in sequence along the third direction, each of the memory regions includes 2 memory layer groups arranged along the first direction; a plurality of the local bit lines are provided in each of the memory layer groups, a first common bit line is provided outside the other memory layer group of the same memory region away from each memory layer group, and a second common bit line is provided inside the other memory layer group of the same memory region close to each memory layer group; For each of the memory layer groups, each of the local bit lines is coupled to the second common bit line via its respective bit line selector, and each of the local bit lines is coupled to the first common bit line via its respective precharge switch.

3. The memory according to claim 1, wherein Each of the memory array slices includes a plurality of sub-array slices arranged in sequence along the second direction, each of the sub-array slices includes a plurality of memory regions stacked in sequence along the third direction, each of the memory regions includes 2 memory layer groups arranged along the first direction; a plurality of the local bit lines are provided in each of the memory layer groups, a first common bit line is provided outside the other memory layer group of the same memory region away from each memory layer group, and a second common bit line is provided inside the other memory layer group of the same memory region close to each memory layer group; For the same sub-array slice, the memory regions are numbered along the third direction; For the memory regions with odd numbers, each of the local bit lines is coupled to the first common bit line via its respective bit line selector, and each of the local bit lines is coupled to the second common bit line via its respective precharge switch; For the memory regions with even numbers, each of the local bit lines is coupled to the second common bit line via its respective bit line selector, and each of the local bit lines is coupled to the first common bit line via its respective precharge switch.

4. The memory according to claim 2 or 3, characterized in that, The storage array slice further includes a plurality of local word lines, and each of the local word lines penetrates through the stacked plurality of storage layer groups in a third direction; the third direction is perpendicular to the first direction and perpendicular to the second direction; A plurality of the local word lines passing through the same storage layer group and aligned in the first direction form a sub-word line group; A local bit line has a corresponding relationship with a sub-word line group, and a storage unit is formed at the intersection of the local bit line and each corresponding local word line; All the local word lines in the same sub-word line group share the same sub-word line drive signal and the same sub-word line drive complementary signal. The bit line selector of the local bit line receives the sub-word line drive signal of the corresponding sub-word line group, and the precharge switch of the local bit line receives the sub-word line drive complementary signal of the corresponding sub-word line group.

5. The memory according to claim 4, wherein Each storage array slice further includes a plurality of common word lines extending in the second direction; In each sub-array slice, the local word lines are sequentially and independently numbered, and the local word lines with the same number in different sub-array slices are electrically connected to the same common word line and share the same sub-word line drive signal and the same sub-word line drive complementary signal.

6. The memory according to claim 5, wherein, In the storage array slice, the common word lines are sequentially numbered in the first direction, and N continuously numbered common word lines form a main word line group; The memory includes a decoding unit (21) and a plurality of sub-word line driving units (22), and N is a positive integer; The decoding unit (21) is configured to decode the row address signal to generate a main word line drive signal, the sub-word line drive signal, and the sub-word line drive complementary signal for each common word line; The sub-word line driving unit (22) is coupled to a common word line and is configured to receive and, based on the corresponding main word line drive signal, the corresponding sub-word line drive signal, and the corresponding sub-word line drive complementary signal, turn on or off the coupled common word line; Wherein, the two storage layer groups of each storage area are sequentially referred to as the first storage layer group and the second storage layer group in the first direction. The main word line drive signal is used to select a main word line group in both the first storage layer group and the second storage layer group, and the sub-word line drive signal and the sub-word line drive complementary signal are used to select a common word line from the main word line group selected in the first storage layer group, or select a common word line from the main word line group selected in the second storage layer group.

7. The memory according to claim 6, characterized in that, The sub-word line driving unit (22) includes a first switching transistor (301), a second switching transistor (302), and a third switching transistor (303); The control terminals of the first switching transistor and the second switching transistor both receive the main word line driving signal. The first end of the first switching transistor receives the sub word line driving signal. The second end of the first switching transistor, the first end of the second switching transistor, and the first end of the third switching transistor are all connected to the common word line. The second end of the second switching transistor and the second end of the third switching transistor are both connected to the power supply terminal. The control terminal of the third switching transistor receives the complementary sub word line driving signal.

8. The memory according to claim 7, wherein The memory further includes a second chip. The first chip and the second chip are stacked along a third direction, and the first chip is bonded to the second chip. The second chip includes a sense amplifier region. In the first chip, a step contact structure is provided between two adjacent memory layer groups along a first direction. The common bit line directly connected to the bit line selector is coupled to the sense amplifier region through the step contact structure.

9. A control method for a memory, characterized in that, The first chip in the memory includes a plurality of memory array slices. Each memory array slice includes a plurality of local bit lines and a plurality of common bit lines. Each local bit line is coupled to a common bit line on one side via a bit line selector, and each local bit line is coupled to a common bit line on the other side via a respective precharge switch. The method includes: Receiving a command address signal, decoding the row address signal in the command address signal to generate a plurality of main word line driving signals, a plurality of sub word line driving signals, and a plurality of complementary sub word line driving signals. Based on each sub word line driving signal, controlling whether the corresponding bit line selector connects the connected local bit line to the connected common bit line. Based on each complementary sub word line driving signal, controlling whether the corresponding precharge switch connects the connected local bit line to the connected common bit line.

10. The control method according to claim 9, wherein Each memory array slice includes a plurality of sub-array slices arranged in sequence along a second direction. Each sub-array slice includes a plurality of memory regions stacked in sequence along a third direction. Each memory region includes two memory layer groups arranged in sequence along a first direction. A plurality of local bit lines are provided in each memory layer group, and a common bit line is provided on each side of each memory layer group along the first direction. The memory array slice further includes a plurality of local word lines, and each local word line penetrates through a plurality of stacked memory layer groups along the third direction. A plurality of local word lines passing through the same memory layer group and aligned along the first direction form a sub word line group. All local word lines in the same sub word line group share the same sub word line driving signal and the same complementary sub word line driving signal. A local bit line has a corresponding relationship with a sub word line group, and a memory cell is formed at the intersection of the local bit line and each corresponding local word line. Each sub word line group has a sub word line driving signal and a complementary sub word line driving signal. The method Further includes: Transmitting the sub word line driving signal of the sub word line group to the bit line selector of the local bit line corresponding to it. Transmitting the complementary sub word line driving signal of the sub word line group to the precharge switch of the local bit line corresponding to it.

11. The control method according to claim 10, characterized in that, In each of the sub-array slices, the local word lines are numbered independently in sequence. The local word lines with the same number in different sub-array slices are electrically connected to the same common word line, and share the same sub-word line driving signal and the same complementary sub-word line driving signal; in the memory array slice, the common word lines are numbered in a first direction, and N consecutively numbered common word lines form a main word line group; The two memory layer groups in each memory area are sequentially called the first memory layer group and the second memory layer group in the first direction; the method further includes: Based on the main word line driving signal, one main word line group is selected in both the first memory layer group and the second memory layer group, Based on the sub-word line driving signal and the complementary sub-word line driving signal, one common word line is selected from the main word line group selected in the first memory layer group or from the main word line group selected in the second memory layer group; The selected common word line is turned on, and the operation indicated by the command address signal is executed.

12. An electronic device, characterized in that, The electronic device includes the memory according to any one of claims 1-8.

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