Memory and manufacturing method therefor, and electronic device

Abstract

The present disclosure relates to a memory and a manufacturing method therefor, and an electronic device. The memory comprises: a common bit line, bit lines, and a cell array. The common bit line extends in a first direction parallel to a substrate. The bit lines are located on a first side of the common bit line and extend in a second direction parallel to the substrate. The cell array comprises a plurality of cells corresponding to the bit lines; the plurality of cells are located on the same sides of the bit lines and are sequentially arranged in the second direction; and the plurality of cells include: at least one connecting cell, at least one gating cell located on the side of the at least one connecting cell away from the common bit line, and a plurality of storage cells located on the side of the at least one gating cell away from the common bit line. The storage cells and the gating cells each comprise transistors coupled to the bit lines. The transistor comprised in each gating cell is a gating transistor, and the gating transistor is coupled to the common bit line by means of the corresponding connecting cell.

Description

Memory and preparation method thereof, and electronic device

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on December 25, 2023, with application number 202311810441.3 and application name “Memory and its preparation method, electronic device”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present disclosure relates to the field of storage technology, and in particular to a memory, a preparation method thereof, and an electronic device. Background Art

[0003] With the development of semiconductor technology, in order to further pursue the miniaturization of device structures within memories, the process has been transformed from planar to three-dimensional, that is, the three-dimensional spatial arrangement of each storage unit and related signal lines within the memory has become the main development direction of current memory structure research.

[0004] Currently, in three-dimensional memories, bit lines and common bit lines can extend in different directions parallel to the substrate, and the bit lines can be coupled to the common bit lines via a gate transistor. However, the gate transistor is typically placed between the bit lines and the common bit line, which can easily affect production yield due to etch loading effects, leading to memory failure.

[0005] Summary of the Invention

[0006] Based on this, the embodiments of the present disclosure provide a memory and a method for manufacturing the same, and an electronic device, which are beneficial to improving the production yield of the selection transistor, thereby improving the production yield and performance of the memory and electronic device.

[0007] In order to achieve the above-mentioned purpose, on the one hand, some embodiments of the present disclosure provide a memory, comprising: a common bit line, a bit line and a cell array. The common bit line extends along a first direction parallel to the substrate. The bit line is located on a first side of the common bit line and extends along a second direction parallel to the substrate. The second direction intersects with the first direction. The cell array includes a plurality of cells corresponding to the bit line, and the plurality of cells are located on the same side of the bit line and are arranged sequentially in the second direction; wherein the plurality of cells include: at least one connection unit, at least one gating unit located on a side of the at least one connection unit away from the common bit line, and a plurality of storage cells located on a side of the at least one gating unit away from the common bit line. Both the storage cell and the gating unit include a transistor coupled to the bit line. The transistor included in the gating unit is a gating transistor, and the gating transistor is coupled to the common bit line through the connection unit.

[0008] In some embodiments of the present disclosure, the transistor included in the memory cell is an access transistor. The memory cell also includes a capacitor, which includes a first electrode coupled to the access transistor, a second electrode arranged opposite to the first electrode, and a dielectric layer located between the first electrode and the second electrode. The gating unit and the connecting unit both include a first electrode dummy structure. The first electrode dummy structures in the gating unit and the connecting unit corresponding to the bit line are interconnected. The gating transistor in the gating unit is coupled to its first electrode dummy structure. The first electrode dummy structure in the connecting unit close to the common bit line is coupled to the common bit line.

[0009] In some embodiments of the present disclosure, the unit includes: a first hole with an axis perpendicular to the substrate, and a first receiving groove extending in a direction parallel to the substrate and located on the side wall of the first hole. The first electrode and the first electrode dummy structure are both conformally covered on the inner side wall of the corresponding first receiving groove. The dielectric layer conformally covers the first electrode and the side wall of the first hole. The second electrode covers the dielectric layer and fills the first receiving groove and the first hole. The selection unit and the connection unit also include: a supporting electrode covering the first electrode dummy structure and filling the first receiving groove, and a first filling layer filling the first hole.

[0010] In some embodiments of the present disclosure, the unit further includes: a second hole located between the bit line and the first hole and having its axis perpendicular to the substrate. In which, both the storage unit and the selection unit further include: a second accommodating groove extending in a direction parallel to the substrate and located on the side wall of the second hole. The second accommodating groove exposes the side wall of the bit line and the side wall of the corresponding first electrode or the corresponding first electrode dummy structure on two opposite sides in the first direction. The transistor includes: a semiconductor layer conformally covering the inner side wall of the corresponding second accommodating groove, and a gate insulating layer conformally covering the semiconductor layer and the side wall of the second hole. The memory further includes: a word line covering the gate insulating layer and filling the second hole in the storage unit, and a selection line covering the gate insulating layer and filling the second hole in the selection unit. The connection unit further includes: a second filling layer filled in the second hole.

[0011] In some embodiments of the present disclosure, the unit further includes: a second hole located between the bit line and the first hole and having an axis perpendicular to the substrate; wherein the second hole exposes the sidewalls of the bit line and the corresponding first electrode or the sidewalls of the corresponding first electrode dummy structure on two opposite sides in the first direction. The access transistor and the selection transistor both further include a semiconductor layer and a gate insulation layer formed on the inner sidewalls of the second hole, and the semiconductor layers between adjacent access transistors in the direction perpendicular to the substrate are insulated, and the semiconductor layers between adjacent selection transistors in the direction perpendicular to the substrate are insulated. The memory further includes: a word line covering the gate insulation layer and filling the second hole in the memory cell, and a selection line covering the gate insulation layer and filling the second hole in the selection unit. The connection unit further includes: a second filling layer filled in the second hole.

[0012] In some embodiments of the present disclosure, a bit line includes a first portion opposite a memory cell and a gating unit, and a second portion opposite a connection unit. The second portion is integral with the common bit line. The memory also includes an isolation structure between the first portion and the second portion.

[0013] In some embodiments of the present disclosure, the same bit line corresponds to at least two connection units, wherein the isolation structure includes: a first isolation portion located between the first portion and the second portion, and a second isolation portion that is at least part of the second filling layer and is at least connected to the first isolation portion.

[0014] In some embodiments of the present disclosure, there are multiple bit lines, and the multiple bit lines are arranged in an insulated manner parallel to the substrate and insulated and stacked in a direction perpendicular to the substrate; wherein, each two adjacent bit lines in the direction parallel to the substrate constitute a bit line group; and each unit corresponding to any bit line in the bit line group is located on the same side of the bit line away from another bit line.

[0015] In some embodiments of the present disclosure, there are multiple common bit lines, and the multiple common bit lines are insulated and stacked in a direction perpendicular to the substrate. The memory further includes: a stepped structure located on a side of the common bit lines facing away from the bit lines. The stepped structure includes multiple conductive steps correspondingly coupled to each common bit line.

[0016] On the other hand, some embodiments of the present disclosure further provide a method for preparing a memory, which is used to prepare the memory described in some of the above embodiments. The method comprises the following steps.

[0017] A plurality of first dielectric layers and a plurality of second dielectric layers are alternately stacked on the substrate.

[0018] The plurality of first dielectric layers and the plurality of second dielectric layers are etched in a direction perpendicular to the substrate to form a first etched groove extending in a first direction parallel to the substrate and at least one second etched groove located on one side of the first etched groove and extending in a second direction parallel to the substrate, where the second direction intersects the first direction.

[0019] Based on the first etching groove, each second dielectric layer is etched along a direction parallel to the substrate to form a plurality of common bit line accommodating grooves, and common bit lines are formed in the common bit line accommodating grooves.

[0020] The second dielectric layers are etched along a direction parallel to the substrate based on the second etching grooves to form a plurality of bit line accommodating grooves, and bit lines are formed in the bit line accommodating grooves.

[0021] The plurality of first dielectric layers and the plurality of second dielectric layers are etched in a direction perpendicular to the substrate to form an etched hole array. The etched hole array includes a plurality of etched hole groups corresponding to the same side of the bit lines and arranged sequentially in the second direction. The plurality of etched hole groups include: a plurality of first etched hole groups spaced apart in the second direction, at least one second etched hole group located on a side of the plurality of first etched hole groups close to a common bit line, and at least one third etched hole group located on a side of the at least one second etched hole group close to the common bit line.

[0022] A memory cell is formed based on the first etch hole group; the memory cell includes an access transistor coupled to a corresponding bit line.

[0023] A gating unit is formed based on the second etch hole group; the gating unit includes a gating transistor coupled to a corresponding bit line.

[0024] A connection unit is formed based on the third etching hole group; and the gate transistor corresponding to the same bit line is also coupled to the common bit line through the corresponding connection unit.

[0025] In some embodiments of the present disclosure, the etch hole array is formed before forming the common bit line etch groove and the bit line etch groove; the first etch hole group, the second etch hole group and the third etch hole group all include first holes whose axis lines are perpendicular to the substrate.

[0026] Accordingly, the method for preparing the memory further includes the following steps.

[0027] A third dielectric layer is filled in each etched hole of the etched hole array.

[0028] After forming the common bit line, the third dielectric layer in each first hole is removed.

[0029] The second dielectric layer is etched along a direction parallel to the substrate based on the first hole to form a first containing groove.

[0030] Accordingly, a storage unit is formed based on the first etched hole group, including: forming a first electrode that conformally covers the inner side wall of the corresponding first receiving groove, forming a dielectric layer that conformally covers the first electrode and the side wall of the first hole, and forming a second electrode that covers the dielectric layer and fills the first receiving groove and the first hole.

[0031] Forming a gating unit based on the second etched hole group and forming a connecting unit based on the third etched hole group both include: forming a first electrode dummy structure conformally covering the inner sidewall of the corresponding first containing groove.

[0032] As described above, the first electrode dummy structures in the gating unit and the connecting unit corresponding to the same bit line are interconnected. The gating transistors in the same gating unit are coupled to their first electrode dummy structures. The first electrode dummy structures in the connecting unit close to the common bit line are coupled to the common bit line.

[0033] In some embodiments of the present disclosure, forming a selection unit based on the second etched hole group and forming a connection unit based on the third etched hole group both further include: forming a supporting electrode covering the first electrode dummy structure and filling the first receiving groove; and forming a first filling layer filling the first hole.

[0034] In some embodiments of the present disclosure, the first etch hole group, the second etch hole group, and the third etch hole group each further include: a second hole located between the bit line and the first hole and with its axis perpendicular to the substrate.

[0035] Correspondingly, forming a storage unit based on the first etching hole group and forming a gating unit based on the second etching hole group both include the following steps.

[0036] The third dielectric layer in the second hole is removed.

[0037] The second dielectric layer is etched along a direction parallel to the substrate based on the second hole to form a second receiving groove. The second receiving groove exposes sidewalls of the bit line and sidewalls of the corresponding first electrode or the corresponding first electrode dummy structure on two opposite sides in the first direction.

[0038] A semiconductor layer is formed to conformally cover the inner sidewall of the corresponding second receiving groove.

[0039] A gate insulating layer is formed to conformally cover the semiconductor layer and the sidewall of the second hole.

[0040] Accordingly, the method for preparing the memory further includes: forming a word line covering the gate insulating layer and filling the second hole in the memory cell, and a gate line covering the gate insulating layer and filling the second hole in the gate cell.

[0041] In some other embodiments of the present disclosure, the method for preparing a memory further includes: before forming the storage unit, the selection unit, and the connection unit, filling the first etching groove and the second etching groove with a first isolation layer.

[0042] Furthermore, the first, second, and third etch hole groups each further include a second hole located between the bit line and the first hole, with its axis perpendicular to the substrate. The second hole exposes the sidewalls of the bit line and the corresponding first electrode or the corresponding first electrode dummy structure on opposite sides of the second hole in the first direction. Accordingly, forming a memory cell based on the first etch hole group and forming a gate cell based on the second etch hole group both include the following steps.

[0043] The third dielectric layer in the second hole is removed.

[0044] An initial semiconductor layer and a gate insulating layer are sequentially formed on the inner sidewall of the second hole.

[0045] A word line covering the gate insulating layer and filling the second hole in the memory cell, and a gate line covering the gate insulating layer and filling the second hole in the gate cell are formed.

[0046] The first isolation layer in the second etching groove is removed.

[0047] Each first dielectric layer is etched along a first direction until a sidewall of the initial semiconductor layer facing away from the gate insulating layer is exposed.

[0048] The initial semiconductor layer between any adjacent second dielectric layers is removed by etching to form a plurality of semiconductor layers spaced apart in a direction perpendicular to the substrate.

[0049] A second isolation layer is formed to fill the spaces between adjacent semiconductor layers, the first dielectric layer removed region and the second etched groove.

[0050] In some embodiments of the present disclosure, a single bit line corresponds to at least two connection units. The first, second, and third etched hole groups each further include a second hole located between the bit line and the first hole, with its axis perpendicular to the substrate. Forming the bit line within the bit line receiving groove includes the following steps.

[0051] An initial bit line is formed in the bit line receiving groove.

[0052] After forming the memory cell, the gating cell, and the connecting cell, the third dielectric layer in the second hole in any third etched hole group is removed, and the initial bit line is cut off by etching along a direction parallel to the substrate based on the second hole to form a bit line; wherein the bit line includes a first portion opposite to the memory cell and the gating cell, and a second portion opposite to the connecting cell.

[0053] An isolation structure is formed in the cut-off region of the initial bit line and in the connected second hole.

[0054] In some embodiments of the present disclosure, the end of the bit line accommodating groove adjacent to the common bit line accommodating groove is connected to the common bit line accommodating groove. The common bit line and the initial bit line are formed simultaneously. The second portion of the bit line is an integral structure with the common bit line.

[0055] In some embodiments of the present disclosure, after forming the common bit line and the initial bit line and before forming the storage unit, the gating unit and the connecting unit, the method for preparing the memory further includes the following steps.

[0056] The plurality of first dielectric layers and the plurality of second dielectric layers are etched in a direction perpendicular to the substrate to form a third etching groove on a side of the common bit line away from the initial bit line.

[0057] Each first dielectric layer is etched based on the third etching groove to form a plurality of insulating steps.

[0058] Each second dielectric layer is etched based on the third etching groove to form a plurality of conductive step accommodating grooves; the conductive step accommodating grooves expose side walls corresponding to the common bit lines.

[0059] A conductive step coupled to the common bit line is formed in the conductive step receiving groove. Each conductive step and each insulating step together form a step structure.

[0060] A covering layer is formed covering the stepped structure.

[0061] On the other hand, some embodiments of the present disclosure further provide a memory comprising: a common bit line, a bit line, a dummy line, a gate line, a word line, an access transistor, a capacitor, and a gate transistor. The common bit line extends along a first direction parallel to the substrate. The bit line is located on a first side of the common bit line and extends along a second direction parallel to the substrate. The second direction intersects the first direction. The dummy line, the gate line, and the word line are all located on a first side of the common bit line, are all located on the same side of the bit line, and extend along a third direction perpendicular to the substrate, wherein the dummy line, the gate line, and the word line are arranged in sequence along the second direction and away from the common bit line in sequence. The access transistor is coupled to the word line and the bit line. The capacitor is located on a side of the access transistor away from the bit line and is coupled to the access transistor. The gate transistor is coupled to the gate line, the bit line, and the common bit line.

[0062] In some embodiments of the present disclosure, the memory further includes a connecting electrode located between the capacitor and the common bit line, wherein the gate transistor is coupled to the common bit line via the connecting electrode.

[0063] On the other hand, some embodiments of the present disclosure further provide an electronic device, comprising: a memory as described in some of the above embodiments, and a processor coupled to the memory.

[0064] The embodiments of the present disclosure may or may have at least the following advantages:

[0065] In the embodiment of the present disclosure, a plurality of cells (i.e., a cell array) arranged sequentially in the second direction are provided on the same side of the bit line extending in the second direction. These plurality of cells can be used as a plurality of storage cells, at least one gating cell, and at least one connecting cell arranged sequentially in a direction close to a common bit line, respectively. The gating transistors of the gating cells are coupled to the common bit line via the connecting cells. In this way, the embodiment of the present disclosure can effectively reduce or eliminate the etching load effect during the preparation of the cell array based on the distribution of the cells in the cell array, thereby effectively improving the production yield of the gating transistors, thereby improving the production yield and performance of the memory and electronic devices.

[0066] The details of one or more embodiments of the present disclosure are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the present disclosure will become apparent from the description, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0067] In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the traditional technology, the following briefly introduces the drawings required for use in the embodiments or the description of the traditional technology. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0068] FIG1 is a schematic diagram of a partial structure of a memory provided in some embodiments;

[0069] FIG2 is a schematic diagram of the position distribution of a bit line, a common bit line, and a cell array on a substrate provided in some embodiments;

[0070] FIG3 is a schematic cross-sectional view of a memory device shown in FIG1 taken along the BB direction and perpendicular to the substrate;

[0071] FIG4 is another schematic cross-sectional view of the memory device shown in FIG1 taken along the BB direction perpendicular to the substrate;

[0072] FIG5 is a schematic flow chart of a method for preparing a memory provided in some embodiments;

[0073] FIG6 is a schematic diagram of a structure obtained after forming a plurality of first dielectric layers and a plurality of second dielectric layers, provided in some embodiments;

[0074] FIG7 is a schematic diagram of a structure obtained after forming a plurality of etching hole groups provided in some embodiments;

[0075] FIG8 is a schematic diagram of a structure obtained after filling a third dielectric layer, provided in some embodiments;

[0076] FIG9 is a schematic diagram of a structure obtained after forming a common bit line and an initial bit line, provided in some embodiments;

[0077] FIG10 is a schematic diagram of a structure obtained after forming a stepped structure provided in some embodiments;

[0078] FIG11 is a schematic diagram of a structure obtained after forming a connecting unit provided in some embodiments;

[0079] FIG12 is a schematic diagram of a structure obtained after forming a semiconductor layer, a gate insulating layer, a word line, and a gate line, provided in some embodiments;

[0080] FIG13 is a schematic diagram of a structure obtained after forming a capacitor provided in some embodiments;

[0081] FIG14 is a schematic diagram of a structure obtained after forming a bit line and an isolation structure according to some embodiments;

[0082] FIG15 is a schematic diagram of another structure obtained after forming an initial semiconductor layer, a gate insulating layer, a word line, and a gate line, provided in some embodiments;

[0083] FIG16 is a schematic diagram of another structure obtained after forming a semiconductor layer and a capacitor according to some embodiments;

[0084] FIG. 17 is a schematic diagram of another structure obtained after forming bit lines and isolation structures provided in some embodiments.

[0085] Description of reference numerals:

[0086] CBL-common bit line, BL-bit line, BLA-initial bit line, BLa-first part, BLb-second part, N-cell array, U1-memory cell, U2-selection unit, U3-connection unit, T1-access transistor, T2-selection transistor, M1-first etching hole group, M2-second etching hole group, M3-third etching hole group, C-capacitor, H1-first hole, H2-second hole, WL-word line, SL-selection line, DL-dummy line, S-staircase structure, S1-insulating step, S2-conductive step, L1-first dielectric layer, L2-second dielectric layer, L3-third dielectric layer;

[0087] 1-substrate, 21-first electrode, 22-dielectric layer, 23-second electrode, 31-first electrode dummy structure, 32-support electrode, 33-first filling layer, 34-second filling layer, 41-semiconductor layer, 41A-initial semiconductor layer, 42-gate insulating layer, 5-isolation structure, 61-first isolation layer, 611-silicon nitride layer, 612-aluminum oxide layer, 62-second isolation layer, 71-titanium nitride layer, 72-tungsten metal layer, 81-isolation retaining wall, 82-covering layer, 821-first sublayer, 822-second sublayer, 9-connecting electrode. DETAILED DESCRIPTION

[0088] To facilitate understanding of the present disclosure, a more comprehensive description of the present disclosure will be provided below with reference to the accompanying drawings. The drawings illustrate preferred embodiments of the present disclosure. However, the present disclosure can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and comprehensive understanding of the present disclosure.

[0089] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art in the art of the present disclosure. The terms used herein in the specification of the present disclosure are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure.

[0090] It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Therefore, a first element, component, region, layer, or part discussed below may be referred to as a second element, component, region, layer, or part without departing from the teachings of the present invention.

[0091] It should be understood that when an element is considered to be "coupled" to another element, it can be directly connected to the other element or connected to the other element through an intervening element. In addition, the term "coupling" in the following embodiments should be understood as "electrical connection", "communication connection", etc., if there is transmission of electrical signals or data between the connected objects.

[0092] It should be understood that the singular forms "a", "an", and "the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, integers, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof.

[0093] Referring to Figures 1 and 2, some embodiments of the present disclosure provide a memory including: a common bit line CBL, a bit line BL, and a cell array N. The common bit line CBL extends along a first direction (e.g., the Y direction) parallel to the substrate 1. The bit line BL is located on a first side of the common bit line CBL and extends along a second direction (e.g., the X direction) parallel to the substrate 1. The second direction (e.g., the X direction) intersects with the first direction (e.g., the Y direction). The cell array N includes a plurality of cells corresponding to the bit line BL, and the plurality of cells are located on the same side of the bit line BL and are arranged sequentially in the second direction (e.g., the X direction); wherein the plurality of cells include: at least one connection unit U3, at least one gating unit U2 located on a side of the at least one connection unit U3 away from the common bit line CBL, and a plurality of memory cells U1 located on a side of the at least one gating unit U2 away from the common bit line CBL. The memory cell U1 and the gating unit U2 both include a transistor coupled to the bit line BL. The transistor included in the memory cell U1 is an access transistor T1. The transistor included in the gating unit U2 is a gating transistor T2 , and the gating transistor T2 is coupled to the common bit line CBL through the connecting unit U3 .

[0094] For example, the common bit line CBL and the bit line BL include substantially the same material composition. In the embodiment of the present disclosure, “substantially the same” means at least 85% or more the same.

[0095] For example, the cell array N may be arranged in a layer; or, the cell array N may be stacked in multiple layers along a third direction (eg, Z direction) perpendicular to the substrate 1 to form a three-dimensional memory.

[0096] In the embodiment of the present disclosure, a plurality of cells (i.e., a cell array N) arranged sequentially in a second direction (e.g., the X direction) and disposed on the same side of a bit line BL extending along the second direction (e.g., the X direction) can be utilized as a plurality of memory cells U1, at least one gating unit U2, and at least one connecting unit U3 arranged sequentially in a direction close to a common bit line CBL, and the gating transistor T2 of the gating unit U2 is coupled to the common bit line CBL via the connecting unit U3. In this way, the embodiment of the present disclosure can effectively reduce or eliminate the etching load effect during the fabrication process of the cell array N based on the distribution of the cells in the cell array N, thereby effectively improving the production yield of the gating transistor T2, thereby improving the production yield and performance of the memory and electronic devices.

[0097] In some embodiments of the present disclosure, please continue to refer to Figures 1 and 2. The storage unit U1 also includes a capacitor C. The capacitor C includes a first electrode 21 coupled to the access transistor T1, a second electrode 23 arranged opposite to the first electrode 21, and a dielectric layer 22 located between the first electrode 21 and the second electrode 23. The selection unit U2 and the connection unit U3 both include a first electrode dummy structure 31. Among them, the first electrode dummy structures 31 in the selection unit U2 and the connection unit U3 corresponding to the bit line BL are interconnected to form a connection electrode 9. The selection transistor T2 in the selection unit U2 is coupled to its first electrode dummy structure 31. The first electrode dummy structure 31 in the connection unit U3 close to the common bit line CBL is coupled to the common bit line CBL.

[0098] FIG1 and FIG2 illustrate two gating units U2 and two connecting units U3, respectively, but are not limited thereto. For example, the number of gating units U2 corresponding to the same bit line BL can be one, three, or more. Each gating transistor T2 in multiple gating units U2 can operate as a parallel transistor to improve the performance of the gating transistor T2 corresponding to any bit line BL. Furthermore, FIG2 merely illustrates the relative positional relationship between the bit line BL, the common bit line CBL, the memory cell U1, the gating unit U2, and the connecting unit U3, and does not define the specific locations, outline shapes, and connection relationships of the bit line BL, the common bit line CBL, the memory cell U1, the gating unit U2, and the connecting unit U3. In addition, FIG2 shows the direction of current between the common bit line CBL and the bit line BL with a black arrow; that is, the current can start from the common bit line CBL, sequentially pass through the connecting unit U3 and the gating unit U2 to the bit line BL, and then be transmitted from the bit line BL to each memory cell U1.

[0099] In some embodiments of the present disclosure, as shown in Figure 1 , each cell in the cell array N includes: a first hole with its axis perpendicular to the substrate 1, and a first receiving groove extending parallel to the substrate 1 and located on the sidewalls of the first hole. The first electrode 21 and the first electrode dummy structure 31 conformally cover the inner sidewalls of the corresponding first receiving groove. The dielectric layer 22 conformally covers the first electrode 21 and the sidewalls of the first hole. The second electrode 23 covers the dielectric layer 22 and fills the first receiving groove and the first hole.

[0100] In some examples, as shown in FIG. 1 , the gating unit U2 and the connecting unit U3 each further include a supporting electrode 32 covering the first electrode dummy structure 31 and filling the first receiving groove, and a first filling layer 33 filling the first hole.

[0101] For example, the connection electrode 9 may further include: supporting electrodes 32 that are in contact with and connected to the first electrode dummy structures 31 in the gating unit U2 and the connection unit U3 .

[0102] In other examples, the first electrode dummy structures 31 in the gating unit U2 and the connecting unit U3 may optionally fill the first receiving groove, and the gating unit U2 and the connecting unit U3 may also include a first filling layer 33 filling the first hole. Accordingly, the connecting electrode 9 may be formed by connecting only the first electrode dummy structures 31 in the gating unit U2 and the connecting unit U3.

[0103] For example, the first hole includes but is not limited to a circular hole, an elliptical hole or a rectangular hole, etc. The first receiving groove surrounds the circumference of the first hole and is an annular groove.

[0104] For example, the first electrode 21 and the first electrode dummy structure 31 include, but are not limited to, a titanium nitride layer or a stacked structure of a titanium nitride layer and a tungsten layer.

[0105] Illustratively, the first electrode 21 and the first electrode dummy structure 31 include substantially the same material composition.

[0106] Illustratively, the first electrode 21 and the first electrode dummy structure 31 are formed simultaneously.

[0107] Illustratively, the support electrode 32 includes, but is not limited to, a polysilicon layer.

[0108] For example, the first filling layer 33 may be a single-layer structure or a stacked-layer structure, for example a stacked-layer structure of a silicon nitride layer and a silicon oxide layer.

[0109] For example, the dielectric layer 22 is a high-K dielectric layer, including but not limited to a hafnium oxide layer, etc. K is a dielectric constant, and high-K means that the K value is greater than 3.9.

[0110] By way of example, the second electrode 23 includes but is not limited to a polysilicon layer or a stacked structure of a titanium nitride layer and a polysilicon layer.

[0111] In some embodiments of the present disclosure, please refer to Figures 1 and 3 to understand that each cell in the cell array N further includes: a second hole located between the bit line BL and the first hole and with its axis perpendicular to the substrate 1. Among them, the memory cell U1 and the selection unit U2 both further include: a second accommodating groove extending in a direction parallel to the substrate 1 and located on the side wall of the second hole. The second accommodating groove exposes the side wall of the bit line BL and the side wall of the corresponding first electrode 21 or the corresponding first electrode dummy structure 31 on opposite sides in the first direction (for example, the Y direction). That is, the second accommodating groove of the memory cell U1 will expose the side wall of the corresponding first electrode 21, and the second accommodating groove of the selection unit U2 will expose the side wall of the corresponding first electrode dummy structure 31.

[0112] Furthermore, the access transistor T1 of memory cell U1 and the gate transistor T2 of gate unit U2 both include a semiconductor layer 41 conformally covering the inner sidewalls of the corresponding second receiving groove, and a gate insulation layer 42 conformally covering the semiconductor layer 41 and the sidewalls of the second hole. Accordingly, the memory also includes a word line WL covering the gate insulation layer 42 and filling the second hole in memory cell U1, and a gate line SL covering the gate insulation layer 42 and filling the second hole in gate unit U2. The connection unit U3 also includes a second filling layer 34 filling the second hole.

[0113] Here, the second filling layer 34 filled in the second hole can also be regarded as a dummy line DL. That is, the dummy line DL, the gate line SL and the word line WL can be sequentially arranged along the second direction (eg, the X direction) and sequentially away from the common bit line CBL.

[0114] For example, the material of the word line WL and the gate line SL includes but is not limited to indium-tin-oxide (ITO).

[0115] Illustratively, the word lines WL and the gate lines SL include substantially the same material composition.

[0116] For example, the second filling layer 34 is an insulating material layer, such as an aluminum oxide layer, but is not limited thereto.

[0117] For example, the diameters of the first hole H1 and the second hole H2 may be the same or different.

[0118] It should be noted that, in conjunction with Figures 1 and 4 , in some other embodiments of the present disclosure, the second hole of each cell in the cell array N exposes the sidewalls of the bit line BL and the sidewalls of the corresponding first electrode 21 or the corresponding first electrode dummy structure 31 on opposite sides in the first direction (e.g., the Y direction). Thus, both the access transistor T1 and the gate transistor T2 further include a semiconductor layer 41 and a gate insulation layer 42 formed on the inner sidewalls of the second hole. The semiconductor layer 41 between adjacent access transistors T1 in a direction perpendicular to the substrate 1 (e.g., the Z direction) is insulated, and the semiconductor layer 41 between adjacent gate transistors T2 in a direction perpendicular to the substrate 1 (e.g., the Z direction) is insulated. Accordingly, the memory further includes: a word line WL covering the gate insulation layer 42 and filling the second hole in the memory cell U1, and a gate line SL covering the gate insulation layer 42 and filling the second hole in the gate cell U2. The connection unit U3 further includes: a second filling layer 34 (i.e., a dummy line DL) filling the second hole.

[0119] For example, please refer to Figures 1 and 4 to understand that there are multiple bit lines BL, and the multiple bit lines BL are arranged in an insulated manner along a direction parallel to the substrate 1 and insulated and stacked along a direction perpendicular to the substrate 1; wherein, every two adjacent bit lines BL along the direction parallel to the substrate 1 constitute a bit line group; and each unit corresponding to any bit line BL in the bit line group is located on the same side of the bit line BL away from another bit line BL.

[0120] For example, two bit lines BL in the same bit line group can be composed of two side lines separated by a ring-shaped conductive layer. Accordingly, the memory further includes: a first isolation layer 61 (for example, as shown in FIG3 ) or a second isolation layer 62 (for example, as shown in FIG4 ) disposed between two adjacent bit lines BL in the bit line group. Referring to FIG4 , in the example where the second isolation layer 62 is disposed between two adjacent bit lines BL, the semiconductor layer 41 between adjacent access transistors T1 in a direction perpendicular to the substrate 1 (for example, the Z direction) and the semiconductor layer 41 between adjacent selection transistors T2 in a direction perpendicular to the substrate 1 (for example, the Z direction) can be insulated by the second isolation layer 62 extending along a direction parallel to the substrate 1.

[0121] For example, referring to FIG1 , the common bit line CBL can be a ring-shaped conductive layer. Accordingly, the memory further includes a first isolation layer 61 disposed within the ring region of the common bit line CBL.

[0122] By way of example, the first isolation layer 61 includes, but is not limited to, a stacked structure of a silicon nitride layer 611 and an aluminum oxide layer 612 .

[0123] By way of example, the second isolation layer 62 includes, but is not limited to, a stacked structure of a silicon nitride layer and a silicon oxide layer.

[0124] By way of example, the common bit line CBL and the bit line BL include, but are not limited to, a stacked structure of a titanium nitride layer and a tungsten metal layer.

[0125] In some embodiments of the present disclosure, referring again to FIG. 1 , the bit line BL includes a first portion BLa opposite the memory cell U1 and the gate unit U2, and a second portion BLb opposite the connection unit U3. The second portion BLb and the common bit line CBL may be integral or spaced apart. The memory also includes an isolation structure 5 between the first portion BLa and the second portion BLa.

[0126] In some embodiments of the present disclosure, please refer to Figure 1 to understand that the same bit line BL corresponds to at least two connection units U1. The isolation structure 5 includes a first isolation portion located between the first portion BLa and the second portion BLb, and a second isolation portion that is at least a portion of the second filler layer 34 (i.e., the dummy line DL) and is connected to at least the first isolation portion. For example, the second isolation portion may also extend to the sidewall of the first electrode dummy structure 31 in the connection unit U3. Figure 1 only illustrates the isolation structure 5 as a whole, without distinguishing the first isolation portion from the second isolation portion.

[0127] In some embodiments of the present disclosure, as shown in FIG1 , there are multiple common bit lines CBL, and the multiple common bit lines CBL are insulated and stacked in a direction perpendicular to the substrate 1 (e.g., the Z direction). The memory device further includes a stepped structure S located on a side of the common bit lines CBL facing away from the bit lines BL. The stepped structure S includes multiple conductive steps correspondingly coupled to each common bit line CBL.

[0128] Illustratively, the stepped structure S further includes a plurality of insulating steps alternately stacked with the plurality of conductive steps.

[0129] Here, it is understood that the staircase structure S can be a single-sided staircase or a double-sided staircase. Furthermore, in the example of a double-sided staircase, the number of conductive steps in each of the two staircases can be the same or different. For example, in the example of a double-sided staircase, the conductive steps of one staircase are coupled to the common bit lines CBL of the odd-numbered layers, and the conductive steps of the other staircase are coupled to the common bit lines CBL of the even-numbered layers.

[0130] For example, the memory further includes an isolation barrier 81 located on the side of the common bit line CBL away from the bit line BL. The area enclosed by the isolation barrier 81 and the common bit line CBL is the area where the step structure S is provided. The isolation barrier 81 may be, for example, a silicon oxide barrier.

[0131] For example, the memory further includes a covering layer 82 covering each step in the stepped structure S. The covering layer 82 may be, for example, a stacked structure of a first sublayer 821 and a second sublayer 822, wherein the first sublayer 821 includes but is not limited to an aluminum oxide layer, and the second sublayer 822 includes but is not limited to a silicon oxide layer.

[0132] It is worth noting that, in conjunction with Figure 1 , in some embodiments of the present disclosure, multiple first dielectric layers L1 and multiple second dielectric layers L2 may be alternately stacked on a substrate 1. The first dielectric layers L1 include, but are not limited to, silicon oxide layers, and the second dielectric layers L2 include, but are not limited to, silicon nitride layers. Accordingly, the various components of the memory device can be formed by first etching each of the first dielectric layers L1 and each of the second dielectric layers L2 to form holes or grooves, and then forming the corresponding holes or grooves.

[0133] Some embodiments of the present disclosure further provide a method for preparing a memory, which is used to prepare the memory described in some of the above embodiments. This method also possesses the technical advantages of the above memories.

[0134] Please refer to FIG5 , the preparation method includes the following steps.

[0135] S100 , alternately stacking a plurality of first dielectric layers and a plurality of second dielectric layers on a substrate.

[0136] S200, etching the plurality of first dielectric layers and the plurality of second dielectric layers in a direction perpendicular to the substrate to form a first etched groove extending in a first direction parallel to the substrate, and at least one second etched groove located on one side of the first etched groove and extending in a second direction parallel to the substrate, wherein the second direction intersects the first direction.

[0137] S300: etching each second dielectric layer along a direction parallel to the substrate based on the first etching groove to form a plurality of common bit line accommodating grooves, and forming common bit lines in the common bit line accommodating grooves.

[0138] S400: etching each second dielectric layer along a direction parallel to the substrate based on the second etching groove to form a plurality of bit line accommodating grooves, and forming bit lines in the bit line accommodating grooves.

[0139] S500: Etching the plurality of first dielectric layers and the plurality of second dielectric layers in a direction perpendicular to the substrate to form an etched hole array. The etched hole array includes a plurality of etched hole groups arranged sequentially in a second direction on the same side of the corresponding bit lines; the plurality of etched hole groups include: a plurality of first etched hole groups spaced apart in the second direction, at least one second etched hole group located on a side of the plurality of first etched hole groups close to a common bit line, and at least one third etched hole group located on a side of the at least one second etched hole group close to the common bit line.

[0140] S600 , forming a memory cell based on the first etching hole group; the memory cell includes an access transistor coupled to a corresponding bit line.

[0141] S700 , forming a gating unit based on the second etching hole group; the gating unit includes a gating transistor coupled to a corresponding bit line.

[0142] S800 , forming a connection unit based on the third etching hole group; the gate transistor corresponding to the same bit line is further coupled to the common bit line through the corresponding connection unit.

[0143] In some embodiments of the present disclosure, the etch hole array in step S500 can be formed before forming the common bit line etch groove and the bit line etch groove. In addition, the first etch hole group, the second etch hole group, and the third etch hole group all include first holes with axis lines perpendicular to the substrate.

[0144] Accordingly, the method for preparing the memory further includes the following steps.

[0145] S510 , filling each etched hole of the etched hole array with a third dielectric layer.

[0146] S520 , after forming the common bit line, removing the third dielectric layer in each first hole.

[0147] S530 , etching the second dielectric layer along a direction parallel to the substrate based on the first hole to form a first receiving groove.

[0148] Accordingly, in step S600, a storage unit is formed based on the first etched hole group, including: forming a first electrode conformally covering the inner side wall of the corresponding first receiving groove, forming a dielectric layer conformally covering the first electrode and the side wall of the first hole, and forming a second electrode covering the dielectric layer and filling the first receiving groove and the first hole.

[0149] The step S700 of forming a gating unit based on the second etched hole group and the step S800 of forming a connecting unit based on the third etched hole group both include: S710.

[0150] S710 , forming a first electrode dummy structure that conformally covers the inner sidewall of the corresponding first receiving groove.

[0151] As described above, the first electrode dummy structures in the gating unit and the connecting unit corresponding to the same bit line are interconnected. The gating transistors in the same gating unit are coupled to their first electrode dummy structures. The first electrode dummy structures in the connecting unit close to the common bit line are coupled to the common bit line.

[0152] In some embodiments of the present disclosure, step S700 of forming a gating unit based on the second etched hole group and step S800 of forming a connecting unit based on the third etched hole group both further include: S720 and S730.

[0153] S720 , forming a supporting electrode covering the first electrode dummy structure and filling the first receiving groove.

[0154] S730 , forming a first filling layer to fill the first hole.

[0155] In some embodiments of the present disclosure, the first etch hole group, the second etch hole group, and the third etch hole group each further include: a second hole located between the bit line and the first hole and with its axis perpendicular to the substrate.

[0156] Accordingly, step S600 of forming a storage unit based on the first etching hole group and step S700 of forming a gating unit based on the second etching hole group both include the following steps S610 to S640.

[0157] S610 , removing the third dielectric layer in the second hole.

[0158] S620: Etching the second dielectric layer in a direction parallel to the substrate based on the second hole to form a second receiving groove. The second receiving groove exposes sidewalls of the bit line and sidewalls of the corresponding first electrode or the corresponding first electrode dummy structure on two opposite sides in the first direction.

[0159] S630 , forming a semiconductor layer that conformally covers the inner sidewall of the corresponding second receiving groove.

[0160] S640 , forming a gate insulating layer conformally covering the semiconductor layer and the sidewalls of the second hole.

[0161] Correspondingly, the method for preparing the memory further includes: S650.

[0162] S650 , forming a word line covering the gate insulating layer and filling the second hole in the memory cell, and a gate line covering the gate insulating layer and filling the second hole in the gate cell.

[0163] In some other embodiments of the present disclosure, the method for preparing a memory further includes: before forming the storage unit, the selection unit, and the connection unit, filling the first etching groove and the second etching groove with a first isolation layer.

[0164] Furthermore, the first, second, and third etch hole groups each further include a second hole located between the bit line and the first hole, with its axis perpendicular to the substrate. The second hole exposes the sidewalls of the bit line and the corresponding first electrode or the corresponding first electrode dummy structure on two opposing sides in the first direction. Accordingly, step S600 of forming a memory cell based on the first etch hole group and step S700 of forming a gate cell based on the second etch hole group both include the following steps S610' to S670'.

[0165] S610 ′, removing the third dielectric layer in the second hole.

[0166] S620 ′, forming an initial semiconductor layer and a gate insulating layer in sequence on the inner sidewall of the second hole.

[0167] S630 ′, forming a word line covering the gate insulating layer and filling the second hole in the memory cell, and a gate line covering the gate insulating layer and filling the second hole in the gate cell.

[0168] S640 ′, removing the first isolation layer in the second etching groove.

[0169] S650 ′, etching each first dielectric layer along the first direction until the sidewalls of the initial semiconductor layer facing away from the gate insulating layer are exposed.

[0170] S660 ′, etching and removing the initial semiconductor layer between any adjacent second dielectric layers to form a plurality of semiconductor layers spaced apart in a direction perpendicular to the substrate.

[0171] S670 ′, forming a second isolation layer that fills the spaces between adjacent semiconductor layers, the first dielectric layer removed areas, and the second etched grooves.

[0172] In some embodiments of the present disclosure, a same bit line corresponds to at least two connection units. Step S400 forms a bit line in a bit line receiving groove, including the following steps S410 to S430.

[0173] S410 , forming an initial bit line in a bit line receiving groove.

[0174] S420, after forming the memory cell, the gating unit, and the connecting unit, removing the third dielectric layer in the second hole in any third etch hole group, and etching and cutting the initial bit line along a direction parallel to the substrate based on the second hole to form a bit line; wherein the bit line includes a first portion opposite to the memory cell and the gating unit, and a second portion opposite to the connecting unit.

[0175] S430 , forming an isolation structure in the cut-off region of the initial bit line and in the connected second hole.

[0176] In some embodiments of the present disclosure, the end of the bit line accommodating groove near the common bit line accommodating groove is connected to the common bit line accommodating groove. The common bit line and the initial bit line are formed simultaneously. The second portion of the bit line and the common bit line can be an integral structure.

[0177] In some embodiments of the present disclosure, after forming the common bit line and the initial bit line and before forming the storage unit, the gating unit and the connecting unit, the method for preparing the memory further includes the following steps S401 to S405 .

[0178] S401 , etching the plurality of first dielectric layers and the plurality of second dielectric layers in a direction perpendicular to the substrate to form a third etched groove on a side of the common bit line away from the initial bit line.

[0179] S402 , etching each first dielectric layer based on the third etching groove to form a plurality of insulating steps.

[0180] S403 , etching each second dielectric layer based on the third etching groove to form a plurality of conductive step receiving grooves; the conductive step receiving grooves expose sidewalls corresponding to the common bit lines.

[0181] S404: forming a conductive step coupled to the common bit line in the conductive step receiving groove. The conductive steps and the insulating steps together form a staircase structure.

[0182] S405 , forming a covering layer covering the stepped structure.

[0183] In the above embodiments of the present disclosure, unless otherwise specified herein, there is no strict order restriction for the execution of the steps in the above methods. These steps may not necessarily be executed in the order described, but may be executed in other ways. Moreover, at least a portion of any of the steps may include multiple sub-steps or multiple stages, and these sub-steps or stages are not necessarily executed at the same time, but may be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but may be executed in turn or alternately with other steps or at least a portion of the sub-steps or stages of other steps.

[0184] In order to more clearly illustrate the manufacturing methods of the memories described in some of the above embodiments, the following embodiments describe in detail the manufacturing methods of some memories with reference to FIG. 6 to FIG. 17 .

[0185] In step S100 , referring to FIG. 6 , a plurality of first dielectric layers L1 and a plurality of second dielectric layers L2 are alternately stacked on a substrate 1 .

[0186] For example, the first dielectric layer L1 includes but is not limited to a silicon oxide layer, and the second dielectric layer L2 includes but is not limited to a silicon nitride layer.

[0187] For example, the substrate 1 can be made of a semiconductor material, an insulating material, a conductive material, or any combination thereof. The substrate 1 can be a single-layer structure or a multi-layer structure. For example, the substrate 1 can be a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III / V semiconductor substrates or II / VI semiconductor substrates. Alternatively, for example, the substrate 1 can be a layered substrate including Si / SiGe, Si / SiC, silicon on insulator (SOI), or silicon germanium on insulator.

[0188] For example, the number of stacked layers of the first dielectric layer L1 and the second dielectric layer L2 can be set as needed. Furthermore, the alternating stacking of the first dielectric layer L1 and the second dielectric layer L2 can begin and end with the first dielectric layer L1. The following embodiments of the present disclosure are described in detail using this example, but are not limited to this. For example, starting with the second dielectric layer L2 and ending with the first dielectric layer L1 is also permitted.

[0189] For example, the formation process of the first dielectric layer L1 and the second dielectric layer L2 includes, but is not limited to, a chemical vapor deposition process.

[0190] In step S500, referring to FIG. 7 , each first dielectric layer L1 and each second dielectric layer L2 are etched along a direction perpendicular to the substrate (e.g., the Z direction) to form an etched hole array. The etched hole array includes a plurality of etched hole groups arranged sequentially in a second direction (e.g., the X direction) on the same side of the corresponding bit lines BL. The plurality of etched hole groups include: a plurality of first etched hole groups M1 spaced apart in the second direction (e.g., the X direction), at least one second etched hole group M2 located on a side of the plurality of first etched hole groups M1 close to the common bit line CBL, and at least one third etched hole group M3 located on a side of the at least one second etched hole group M2 close to the common bit line CBL.

[0191] Here, the first etching hole group M1 may be used to prepare a memory cell, the second etching hole group M2 may be used to prepare a gate cell, and the third etching hole group M3 may be used to prepare a connection cell.

[0192] It can be understood that when the etch hole array is formed, the bit lines BL and the common bit lines CBL have not yet been formed. FIG. 7 shows the areas where the bit lines BL and the common bit lines CBL are to be formed, so as to clearly illustrate the distribution positions of the etch holes.

[0193] For example, the first etching hole group M1, the second etching hole group M2 and the third etching hole group M3 are located on the same side of the corresponding bit line BL extending along the second direction (eg, X direction) and are sequentially distributed along the direction close to the common bit line CBL in the second direction (eg, X direction).

[0194] For example, the first etching hole group M1 , the second etching hole group M2 and the third etching hole group M3 each include: a first hole H1 with an axis perpendicular to the substrate, and a second hole H2 located between the bit line BL and the first hole H1 and with an axis perpendicular to the substrate 1 .

[0195] For example, the diameters of the first hole H1 and the second hole H2 may be the same or different.

[0196] For example, adjacent third etched hole groups M3 and adjacent second etched hole groups M2 along the second direction (e.g., X direction) may be arranged with no spacing or with only a small spacing. For example, the spacing between adjacent third etched hole groups M3 along the second direction (e.g., X direction) and the spacing between adjacent second etched hole groups M2 along the second direction (e.g., X direction) are smaller than the spacing between adjacent first etched hole groups M1 along the second direction (e.g., X direction).

[0197] In step S510 , referring to FIG. 8 , each etched hole in the etched hole array is filled with a third dielectric layer L3 .

[0198] For example, the third dielectric layer L3 is made of a different material from the first dielectric layer L1 and the second dielectric layer L2. For example, the third dielectric layer L3 includes but is not limited to an aluminum oxide layer.

[0199] In step S200, as will be understood in conjunction with FIG. 9 , each first dielectric layer L1 and each second dielectric layer L2 are etched along a direction perpendicular to the substrate 1 (e.g., the Z direction), forming a first etched groove extending along a first direction parallel to the substrate 1 (e.g., the Y direction), and at least one second etched groove located to one side of the first etched groove and extending along a second direction parallel to the substrate 1 (e.g., the X direction). The second direction (e.g., the X direction) and the first direction (e.g., the Y direction) intersect, for example, are orthogonal.

[0200] It is understood that although the first and second etched grooves are not labeled in FIG9 , the first etched groove is the region within the ring of the subsequently formed common bit line CBL, and the second etched groove is the spacer region between each adjacent bit line BL. Furthermore, the first and second etched grooves can penetrate each first dielectric layer L1 and each second dielectric layer L2 to expose the surface of the substrate 1.

[0201] In steps S300 and S400, please refer to Figure 9 to understand that based on the first etching groove, each second dielectric layer L2 is etched along a direction parallel to the substrate 1, a plurality of common bit line accommodating grooves can be formed to form common bit lines CBL in the common bit line accommodating grooves; based on the second etching groove, each second dielectric layer L2 is etched along a direction parallel to the substrate 1, a plurality of bit line accommodating grooves can be formed to form bit lines BL in the bit line accommodating grooves.

[0202] Here, it can be understood that to match the coupling relationship between the initial bit line BLA and the common bit line CBL, the end of the bit line accommodating groove close to the common bit line accommodating groove can be connected to or spaced apart from the common bit line accommodating groove.

[0203] In some embodiments, the end of the bit line accommodating groove adjacent to the common bit line accommodating groove is connected to the common bit line accommodating groove. The bit line BL can be obtained by first forming an initial bit line BLA in the bit line accommodating groove (for example, as shown in FIG9 ) and then cutting the initial bit line BLA (for example, as shown in FIG14 ).

[0204] For example, the first etching groove and the second etching groove may be formed by a dry etching process, and the bit line accommodating groove and the common bit line accommodating groove may be formed by a wet etching process.

[0205] For example, the common bit line accommodating groove is in a ring shape, and the bit line accommodating grooves corresponding to every two adjacent initial bit lines BLA can be connected to form a ring shape.

[0206] For example, the initial bit line BLA and the common bit line CBL can be formed simultaneously and use a single conductive layer or a stacked conductive layer. For example, the initial bit line BLA and the common bit line CBL are both stacked structures of a titanium nitride layer 71 and a tungsten metal layer 72.

[0207] For example, referring to FIG. 9 , before forming the memory unit U1 , the gate unit U2 , and the connection unit U3 , the first isolation layer 61 is filled in the first etching groove and the second etching groove.

[0208] For example, the first isolation layer 61 may be a single-layer insulation layer or a stacked insulation layer. For example, the first isolation layer 61 includes but is not limited to a stacked layer of a silicon nitride layer 611 and an aluminum oxide layer 612 .

[0209] In some embodiments of the present disclosure, referring to FIG. 9 , the memory fabrication method further includes forming an isolation barrier 81 on a side of the common bit line CBL facing away from the bit line BL, thereby forming a stepped structure S in the area enclosed by the isolation barrier 81 and the common bit line CBL. The isolation barrier 81 may be, for example, a silicon oxide barrier.

[0210] For example, referring to FIG. 10 , after forming the common bit line CBL and the initial bit line BLA and before forming the memory unit U1 , the gate unit U2 and the connection unit U3 , the memory manufacturing method further includes the following steps S401 - S405 .

[0211] In step S401 , each first dielectric layer L1 and each second dielectric layer L2 is etched along a direction perpendicular to the substrate 1 (eg, Z direction) to form a third etched groove on a side of the common bit line CBL away from the initial bit line BLA.

[0212] For example, the third etched groove may be formed by a dry etching process.

[0213] In step S402 , each first dielectric layer L1 is etched based on the third etching groove to form a plurality of insulating steps S1 .

[0214] In step S403 , each second dielectric layer L2 is etched based on the third etching groove to form a plurality of conductive step receiving grooves; the conductive step receiving grooves expose sidewalls corresponding to the common bit lines CBL.

[0215] For example, the conductive step receiving groove may be formed by a wet etching process.

[0216] In step S404, a conductive step S2 coupled to the common bit line CBL is formed in the conductive step receiving groove. Each conductive step S2 and each insulating step S1 together form a stepped structure S.

[0217] By way of example, the conductive step S2 includes but is not limited to a tungsten metal layer.

[0218] In step S405 , a cover layer 82 covering the stepped structure S is formed.

[0219] For example, the cover layer 82 may be a stacked structure of a first sub-layer 821 and a second sub-layer 822 , wherein the first sub-layer 821 includes but is not limited to an aluminum oxide layer, and the second sub-layer 822 includes but is not limited to a silicon oxide layer.

[0220] The above embodiment exemplarily provides a method for forming a stepped structure S, but the method for forming the stepped structure S is not limited thereto, and any other method that can be used to prepare a stepped structure is also applicable to the present disclosure.

[0221] In step S520 , please refer to FIG. 11 to understand that after forming the common bit line CBL, the third dielectric layer L3 in each first hole H1 is removed.

[0222] For example, the third dielectric layer L3 in the first hole H1 may be removed by using a dry etching process.

[0223] In step S530 , please refer to FIG. 11 for understanding, based on the first hole H1 , the second dielectric layer L2 is etched in a direction parallel to the substrate 1 to form a first receiving groove.

[0224] For example, the first receiving groove may be formed by a wet etching process.

[0225] In steps S600 , S700 and S800 , please refer to FIG. 11 to FIG. 14 to understand that the storage unit U1 is formed based on the first etching hole group M1 , the selection unit U2 is formed based on the second etching hole group M2 , and the connection unit U3 is formed based on the third etching hole group M3 .

[0226] Here, the structures of the memory cell U1, the gating unit U2, and the connecting unit U3 can be found in the related descriptions of some of the aforementioned embodiments and will not be described in detail. Furthermore, the fabrication processes of the memory cell U1, the gating unit U2, and the connecting unit U3 may interact with each other. For example, the access transistor T1 of the memory cell U1 and the gating transistor T2 of the gating unit U2 may be fabricated simultaneously.

[0227] For example, as shown in FIG11 , in step S710, after forming the first receiving grooves, the first electrodes 21 can be conformally covered on the inner sidewalls of the first receiving grooves corresponding to the first etched hole group M1, and the first electrode dummy structures 31 can be conformally covered on the inner sidewalls of the first receiving grooves corresponding to the second etched hole group M2 and the third etched hole group M3. The first electrode dummy structures 31 in the gating unit U2 and the connection unit U3 corresponding to the same bit line BL are interconnected to form a connection electrode 9. Furthermore, the first electrode dummy structures 31 in the connection unit U3 near the common bit line CBL are coupled to the common bit line CBL.

[0228] For example, the first electrode 21 and the first electrode dummy structure 31 may be made of the same material and formed using an atomic layer deposition process.

[0229] In step S720, a supporting electrode 32 is formed to cover the first electrode dummy structure 31 and fill the first receiving grooves corresponding to the second etched hole group M2 and the third etched hole group M3. Furthermore, a supporting electrode 32 is formed to cover the first electrode 21 and fill the first receiving grooves corresponding to the first etched hole group M1.

[0230] Illustratively, the support electrode 32 includes, but is not limited to, a polysilicon layer.

[0231] In step S730 , a first filling layer 33 is formed to fill each first hole H1 .

[0232] For example, the first filling layer 33 is a stacked structure of a silicon nitride layer and a silicon oxide layer.

[0233] It is understood that in other embodiments, the first electrode dummy structures 31 formed in the gating unit U2 and the connecting unit U3 can completely fill the first receiving groove. Accordingly, forming the gating unit U2 and the connecting unit U3 also includes forming a first filling layer 33 that fills the first hole. The connecting electrode 9 can be formed solely by connecting the first electrode dummy structures 31 in the gating unit U2 and the connecting unit U3.

[0234] It should be noted that there are many possible implementations for matching the aperture size of the second hole H2 in the etching hole group, the access transistor T1 of the memory unit U1 and the gate transistor T2 of the gate unit U2.

[0235] In some possible implementations, please refer to FIG. 3 and FIG. 12 and FIG. 13 to understand that step S600 forms the storage unit U1 based on the first etching hole group M1 and step S700 forms the selection unit U2 based on the second etching hole group M2, both of which include the following steps S610 to S640.

[0236] In step S610 , the third dielectric layer L3 in the second holes H2 in each first etching hole group M1 and each second etching hole group M2 is removed, for example, by using a dry or wet etching process.

[0237] At this time, the third dielectric layer L3 in the second hole H2 in the third etched hole group M3 constitutes the second filling layer 34 in the second hole H2 in the connecting unit U3, and can also be regarded as the dummy line DL.

[0238] In step S620, based on the second holes H2 in each of the first etch hole groups M1 and each of the second etch hole groups M2, the second dielectric layer L2 is etched in a direction parallel to the substrate 1 to form second receiving grooves. The second receiving grooves corresponding to the first etch hole groups M1 expose the sidewalls of the bit line BL and the sidewalls of the corresponding first electrode 21 on opposite sides in the first direction (e.g., the Y direction). The second receiving grooves corresponding to the second etch hole groups M2 expose the sidewalls of the bit line BL and the sidewalls of the corresponding first electrode dummy structure 31 on opposite sides in the first direction (e.g., the Y direction).

[0239] For example, the second receiving groove may be formed by a wet etching process.

[0240] In step S630, a semiconductor layer 41 is formed conformally covering the inner sidewalls of the corresponding second receiving grooves. The semiconductor layer 41 of the access transistor T1 in the same memory cell U1 is in contact with the first electrode 21 thereof. The semiconductor layer 41 of the gate transistor T2 in the same gate cell U2 is in contact with the first electrode dummy structure 31 thereof.

[0241] For example, the semiconductor layer 41 includes but is not limited to a metal oxide layer, such as an indium gallium zinc oxide (IGZO) layer.

[0242] For example, the semiconductor layer 41 may be formed by an atomic layer deposition process.

[0243] In step S640 , a gate insulating layer 42 is formed to conformally cover the semiconductor layer 41 and the sidewalls of the second hole H2 .

[0244] In step S650 , a word line WL covering the gate insulating layer 42 and filling the second hole H2 in the memory unit U1 and a gate line SL covering the gate insulating layer 42 and filling the second hole H2 in the gate unit U2 are formed.

[0245] For example, the word lines WL and the gate lines SL are simultaneously formed using the same material, such as ITO.

[0246] For example, referring to FIG13 , after forming the word lines WL and the gate lines SL, the first filling layer 33 within the first holes H1 in the first etched hole group M1 and the support electrode 32 within the corresponding first receiving groove can be removed to expose the first electrode 21. Then, a dielectric layer 22 is formed to conformally cover the first electrode 21 and the sidewalls of the first holes H1, and a second electrode 23 is formed to cover the dielectric layer 22 and fill the first receiving groove and the first holes H1, thereby fabricating a capacitor C.

[0247] 14 , the same bit line BL corresponds to at least two connection units U3 . Step S400 forms the bit line BL in the bit line receiving groove, including the following steps S410 - S430 .

[0248] In step S410 , as shown in FIG. 9 to FIG. 13 , an initial bit line BLA is formed in a bit line receiving groove.

[0249] In step S420, as shown in FIG14 , after forming the memory cell U1, the gating unit U2, and the connecting unit U3, the third dielectric layer L3 (i.e., the second filling layer 34) in the second hole H2 in any third etch hole group M3 is removed, and the initial bit line BLA is etched and cut off along a direction parallel to the substrate 1 based on the second hole H2 to form a bit line BL; wherein the bit line BL includes a first portion BLa opposite to the memory cell U1 and the gating unit U2, and a second portion BLb opposite to the connecting unit U3.

[0250] Illustratively, the second portion BLb of the bit line BL is an integral structure with the common bit line CBL.

[0251] In step S430 , as shown in FIG. 14 , an isolation structure 5 is formed in the cut-off region of the initial bit line BLA and in the connected second hole H2 .

[0252] Illustratively, the isolation structure 5 is formed of insulating materials, including but not limited to a silicon oxide layer.

[0253] In other possible embodiments, please refer to Figures 4, 15, and 16 to understand that the second hole H2 exposes the sidewalls of the bit line BL and the sidewalls of the corresponding first electrode 21 or the corresponding first electrode dummy structure 31 on two opposite sides in the first direction (e.g., the Y direction). Accordingly, step S600 of forming the memory cell U1 based on the first etch hole group M1 and step S700 of forming the gating cell U2 based on the second etch hole group M2 can both include the following steps S610' to S670'.

[0254] In step S610 ′, the third dielectric layer L3 in the second holes H2 in each first etching hole group M1 and each second etching hole group M2 may be removed by, for example, a dry or wet etching process.

[0255] In step S620 ′, an initial semiconductor layer 41A and a gate insulating layer 42 are sequentially formed on the inner sidewalls of the second holes H2 in each of the first etch hole groups M1 and each of the second etch hole groups M2 .

[0256] In step S630 ′, a word line WL covering the gate insulating layer 42 and filling the second hole H2 in the memory unit U1 and a gate line SL covering the gate insulating layer 42 and filling the second hole H2 in the gate unit U2 are formed.

[0257] In step S640 ′, the first isolation layer 61 in the second etching groove is removed.

[0258] In step S650 ′, each first dielectric layer L1 is etched along a first direction (eg, the Y direction) until the sidewalls of the initial semiconductor layer 41A facing away from the gate insulating layer 42 are exposed.

[0259] In step S660 ′, the initial semiconductor layer 41A between any adjacent second dielectric layers L2 is removed by etching to form a plurality of semiconductor layers 41 spaced apart in a direction perpendicular to the substrate 1 (eg, the Z direction).

[0260] In step S670 ′, a second isolation layer 62 is formed to fill the spaces between adjacent semiconductor layers 41 , the removed areas of the first dielectric layer L1 , and the second etched grooves.

[0261] By way of example, the second isolation layer 62 includes, but is not limited to, a stacked structure of a silicon nitride layer and a silicon oxide layer.

[0262] As described above, the semiconductor layer 41 of the access transistor T1 in the same memory cell U1 is in contact with and connected to its first electrode 21, and the semiconductor layers 41 of adjacent access transistors T1 in a direction perpendicular to the substrate 1 (e.g., the Z direction) are insulated from each other by the portion of the second isolation layer 62 extending parallel to the substrate 1. The semiconductor layer 41 of the gate transistor T2 in the same gate unit U2 is in contact with and connected to its first electrode dummy structure 31, and the semiconductor layers 41 of adjacent gate transistors T2 in a direction perpendicular to the substrate 1 (e.g., the Z direction) are insulated from each other by the portion of the second isolation layer 62 extending parallel to the substrate 1.

[0263] For example, referring to FIG16 , after forming the word lines WL and the gate lines SL, the first filling layer 33 within the first holes H1 in the first etched hole group M1 and the support electrode 32 within the corresponding first receiving groove can be removed to expose the first electrode 21. Then, a dielectric layer 22 is formed to conformally cover the first electrode 21 and the sidewalls of the first holes H1, and a second electrode 23 is formed to cover the dielectric layer 22 and fill the first receiving groove and the first holes H1, thereby fabricating a capacitor C.

[0264] 17 , the same bit line BL corresponds to at least two connection units U3 . Step S400 forms the bit line BL in the bit line receiving groove, including the following steps S410 - S430 .

[0265] In step S410 , as shown in FIG. 9 to FIG. 13 , an initial bit line BLA is formed in a bit line receiving groove.

[0266] In step S420, as shown in FIG17 , after forming the memory cell U1, the gating unit U2, and the connecting unit U3, the third dielectric layer L3 (i.e., the second filling layer 34) in the second hole H2 in any third etching hole group M3 is removed, and the initial bit line BLA is etched and cut off along a direction parallel to the substrate 1 based on the second hole H2 to form a bit line BL; wherein the bit line BL includes a first portion BLa opposite to the memory cell U1 and the gating unit U2, and a second portion BLb opposite to the connecting unit U3.

[0267] Illustratively, the second portion BLb of the bit line BL is an integral structure with the common bit line CBL.

[0268] In step S430 , as shown in FIG. 17 , an isolation structure 5 is formed in the cut-off region of the initial bit line BLA and in the connected second hole H2 .

[0269] Referring to Figures 14 and 17 , some embodiments of the present disclosure further provide a memory device including: a common bit line CBL, a bit line BL, a dummy line DL, a gate line SL, a word line WL, an access transistor T1, a capacitor C, and a gate transistor T2. The common bit line CBL extends along a first direction (e.g., the Y direction) parallel to a substrate 1. The bit line BL is located on a first side of the common bit line CBL and extends along a second direction (e.g., the X direction) parallel to the substrate 1. The second direction (e.g., the X direction) and the first direction (e.g., the Y direction) intersect, for example, are orthogonal to each other.

[0270] Continuing with Figures 14 and 17 , the dummy line DL, gate line SL, and word line WL are all located on a first side of the common bit line CBL, on the same side of the bit line BL, and extend along a third direction (e.g., the Z direction) perpendicular to the substrate 1. The dummy line DL, gate line SL, and word line WL are sequentially arranged along a second direction (e.g., the X direction) and sequentially away from the common bit line CBL. Access transistor T1 is coupled to word line WL and bit line BL. Capacitor C is located on a side of access transistor T1 away from bit line BL and is coupled to access transistor T1. Gate transistor T2 is coupled to gate line SL, bit line BL, and common bit line CBL.

[0271] For example, the access transistor T1 is disposed around the word line WL, and the gate transistor T2 is disposed around the gate line SL.

[0272] For example, the word lines WL and the gate lines SL are conductive lines, such as those formed of ITO, and the dummy lines DL are insulating lines, such as those formed of a high-K dielectric material, such as aluminum oxide.

[0273] For example, the orthographic projection shapes of the word lines WL, gate lines SL, and dummy lines DL on the substrate 1 are the same or similar. Furthermore, at least one dummy line DL, at least one gate line SL, and multiple word lines WL are arranged in a second direction (e.g., X direction) away from the common bit line CBL.

[0274] In addition, the structures of the access transistor T1, the selection transistor T2, the capacitor C, the bit line BL, the common bit line CBL and other film layers in the memory can all be referred to the relevant descriptions in some of the previous embodiments and will not be described in detail here. The technical advantages of the above-mentioned memories are also possessed by this memory.

[0275] In some embodiments of the present disclosure, referring to FIG. 14 and FIG. 17 , the memory further includes a connecting electrode 9 . The connecting electrode 9 is located between the capacitor C and the common bit line CBL. The gate transistor T2 is coupled to the common bit line CBL via the connecting electrode 9 .

[0276] For example, the connecting electrode 9 includes at least two first electrode dummy structures 31 coupled to each other, wherein at least one first electrode dummy structure 31 is located on the side of the selection transistor T2 away from the bit line BL and is in contact with the semiconductor layer 41 of the selection transistor T2; at least one first electrode dummy structure 31 is located on the side of the dummy line DL away from the bit line BL.

[0277] For example, the first electrode dummy structure 31 and the first electrode 21 of the capacitor C are formed simultaneously using the same material.

[0278] For example, the connecting electrode 9 may further include: a supporting electrode 32 in contact with and connected to the first electrode dummy structure 31 .

[0279] Some embodiments of the present disclosure also provide an electronic device, such as a data storage device, a copier, a network device, a household appliance, an instrument, a mobile phone, a computer, or other device with a data storage function. The electronic device may include a memory as described in some of the above embodiments and a processor coupled to the memory. The structure of the memory can refer to the relevant description in some of the above embodiments. The processor can control the read and write operations of the memory. The electronic device may also include other necessary elements or components, which are not limited by the embodiments of the present disclosure.

[0280] For example, the electronic device may include a housing and a circuit board disposed in the housing; the memory and the processor may be integrated on the circuit board.

[0281] The technical features of the above-mentioned embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features of the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0282] The above-described embodiments merely represent several implementation methods of the present disclosure. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that a person of ordinary skill in the art may make various modifications and improvements without departing from the spirit of the present disclosure, all of which fall within the scope of protection of the present disclosure. Therefore, the scope of protection of the patent disclosed herein shall be determined by the appended claims.

Claims

1. A memory, comprising: A common bit line (CBL) extending along a first direction (Y) parallel to a substrate (1); A bit line (BL) located on a first side of the common bit line and extending along a second direction (X) parallel to the substrate, the second direction intersecting the first direction; A cell array (N) including a plurality of cells (U1, U2, U3) corresponding to the bit line, the plurality of cells being located on the same side of the bit line and arranged in sequence in the second direction; Wherein, the plurality of cells include: at least one connection cell (U3), at least one selection cell (U2) located on a side of the at least one connection cell away from the common bit line, and a plurality of storage cells (U1) located on a side of the at least one selection cell away from the common bit line; both the storage cell and the selection cell include a transistor coupled to the bit line; the transistor included in the selection cell is a selection transistor (T2), and the selection transistor is further coupled to the common bit line through the connection cell.

2. The memory according to claim 1, wherein, The transistor included in the storage cell is an access transistor (T1); the storage cell further includes a capacitor (C), the capacitor including a first electrode (21) coupled to the access transistor, a second electrode (23) disposed opposite to the first electrode, and a dielectric layer (22) located between the first electrode and the second electrode; Both the selection cell and the connection cell include a first electrode dummy structure (31); Wherein, each of the first electrode dummy structures in the selection cell and the connection cell corresponding to the bit line are interconnected; the selection transistor in the selection cell is coupled to its first electrode dummy structure; the first electrode dummy structure in the connection cell close to the common bit line is coupled to the common bit line.

3. The memory according to claim 2, wherein, The cell includes: a first hole (H1) with an axis perpendicular to the substrate, and a first accommodation groove extending along a direction parallel to the substrate and located on a sidewall of the first hole; Wherein, both the first electrode and the first electrode dummy structure conformally cover an inner sidewall of the corresponding first accommodation groove; the dielectric layer conformally covers the first electrode and a sidewall of the first hole; the second electrode covers the dielectric layer and fills the first accommodation groove and the first hole; Both the selection cell and the connection cell further include: a support electrode (32) covering the first electrode dummy structure and filling the first accommodation groove, and a first filling layer (33) filling the first hole; 4. The memory according to claim 3, wherein, The cell further includes: a second hole (H2) located between the bit line and the first hole and having an axis perpendicular to the substrate; Wherein, the storage unit and the selection unit further each include: a second accommodation groove extending along a direction parallel to the substrate and located on the sidewall of the second hole; the two opposite sides of the second accommodation groove in the first direction respectively expose the sidewall of the bit line and the sidewall corresponding to the first electrode or the dummy structure of the first electrode; the transistor includes: a semiconductor layer (41) conformally covering the inner sidewall of the corresponding second accommodation groove, and a gate insulating layer (42) conformally covering the semiconductor layer and the sidewall of the second hole; the memory further includes: a word line (WL) covering the gate insulating layer and filling the second hole in the storage unit, and a selection line (SL) covering the gate insulating layer and filling the second hole in the selection unit; The connection unit further includes: a second filling layer (34) filled in the second hole.

5. The memory according to claim 3, wherein, The unit further includes: a second hole (H2) located between the bit line and the first hole and having an axis perpendicular to the substrate; Wherein, the two opposite sides of the second hole in the first direction respectively expose the sidewall of the bit line and the sidewall corresponding to the first electrode or the dummy structure of the first electrode; both the access transistor and the selection transistor further include a semiconductor layer (51) and a gate insulating layer (42) formed on the inner sidewall of the second hole, and the semiconductor layers between adjacent access transistors are insulated from each other in the direction perpendicular to the substrate, and the semiconductor layers between adjacent selection transistors are insulated from each other in the direction perpendicular to the substrate; the memory further includes: a word line (WL) covering the gate insulating layer and filling the second hole in the storage unit, and a selection line (SL) covering the gate insulating layer and filling the second hole in the selection unit; The connection unit further includes: a second filling layer (34) filled in the second hole.

6. The memory according to any one of claims 1 to 5, wherein, The bit line includes: a first part (BLa) opposite to the storage unit and the selection unit, and a second part (BLb) opposite to the connection unit; Wherein, the second part and the common bit line are of an integral structure; The memory further includes an isolation structure (5) located between the first part and the second part.

7. The memory according to claim 6, wherein, The same bit line corresponds to at least two of the connection units; Wherein, the isolation structure includes: a first isolation part located between the first part and the second part, and a second isolation part including at least part of the second filling layer and at least connected to the first isolation part.

8. The memory according to claim 6, wherein, The number of the bit lines is multiple, and the multiple bit lines are insulated and arranged along a direction parallel to the substrate and insulated and stacked along a direction perpendicular to the substrate; Wherein, every two adjacent bit lines along the direction parallel to the substrate form a bit line group; each of the units corresponding to any one of the bit lines in the bit line group is located on the same side of the bit line away from the other bit line.

9. The memory according to claim 6, wherein The number of the common bit lines is multiple, and the multiple common bit lines are insulated and stacked along a direction perpendicular to the substrate; The memory further includes: a stepped structure (S) located on a side of the common bit line away from the bit line; the stepped structure includes a plurality of conductive steps (S2) correspondingly coupled to the respective common bit lines.

10. A method for manufacturing a memory, comprising: alternately stacking a plurality of first dielectric layers (L1) and a plurality of second dielectric layers (L2) on a substrate (1); etching the plurality of first dielectric layers and the plurality of second dielectric layers in a direction perpendicular to the substrate to form a first etching groove extending in a first direction (Y) parallel to the substrate, and at least one second etching groove located on one side of the first etching groove and extending in a second direction (X) parallel to the substrate; the second direction intersects the first direction; etching each of the second dielectric layers along a direction parallel to the substrate based on the first etching groove to form a plurality of common bit line accommodating grooves; forming a common bit line (CBL) in the common bit line accommodating grooves; etching each of the second dielectric layers along a direction parallel to the substrate based on the second etching groove to form a plurality of bit line accommodating grooves; forming a bit line (BL) in the bit line accommodating grooves; etching the plurality of first dielectric layers and the plurality of second dielectric layers in a direction perpendicular to the substrate to form an etching hole array; the etching hole array includes a plurality of etching hole groups located on the same side of the corresponding bit line and arranged in sequence in the second direction; the plurality of etching hole groups include: a plurality of first etching hole groups (M1) spaced apart in the second direction, at least one second etching hole group (M2) located on a side of the plurality of first etching hole groups close to the common bit line, and at least one third etching hole group (M3) located on a side of the at least one second etching hole group close to the common bit line; forming a memory cell (U1) based on the first etching hole group; the memory cell includes an access transistor (T1) coupled to the corresponding bit line; forming a selection unit (U2) based on the second etching hole group; the selection unit includes a selection transistor (T2) coupled to the corresponding bit line; forming a connection unit (U3) based on the third etching hole group; wherein, the selection transistors corresponding to the same bit line are further coupled to the common bit line through the corresponding connection units.

11. The method for manufacturing a memory according to claim 10, wherein, The etching hole array is formed before forming the common bit line etching groove and the bit line etching groove; the first etching hole group, the second etching hole group, and the third etching hole group each include a first hole (H1) with an axis perpendicular to the substrate; The method for manufacturing the memory further includes: filling a third dielectric layer (L3) into each etching hole of the etching hole array; after forming the common bit line, removing the third dielectric layer in each of the first holes; etching the second dielectric layer along a direction parallel to the substrate based on the first hole to form a first accommodating groove; wherein, forming the memory cell based on the first etching hole group includes: forming a first electrode (21) conformally covering the inner sidewall of the corresponding first accommodating groove, forming a dielectric layer (22) conformally covering the first electrode and the sidewall of the first hole, and forming a second electrode (23) covering the dielectric layer and filling the first accommodating groove and the first hole; Forming the selection unit based on the second etch hole group and forming the connection unit based on the third etch hole group both include: forming a first electrode dummy structure (31) that conformally covers the inner sidewall of the corresponding first accommodation groove; Among them, the first electrode dummy structures in the selection unit and the connection unit corresponding to the same bit line are interconnected; the selection transistor in the same selection unit is coupled to its first electrode dummy structure; the first electrode dummy structure in the connection unit close to the common bit line is coupled to the common bit line.

12. The method for manufacturing a memory according to claim 11, wherein, Forming the selection unit based on the second etch hole group and forming the connection unit based on the third etch hole group both further include: Forming a support electrode (32) that covers the first electrode dummy structure and fills the first accommodation groove; Forming a first filling layer (33) that fills the first hole.

13. The method for manufacturing a memory according to claim 11, wherein, The first etch hole group, the second etch hole group, and the third etch hole group all further include: a second hole (H2) located between the bit line and the first hole and having an axis perpendicular to the substrate; Among them, forming the memory cell based on the first etch hole group and forming the selection unit based on the second etch hole group both include: Removing the third dielectric layer in the second hole; Etching the second dielectric layer along a direction parallel to the substrate based on the second hole to form a second accommodation groove; the two opposite sides of the second accommodation groove in the first direction respectively expose the sidewalls of the bit line and the sidewalls corresponding to the first electrode or the first electrode dummy structure; Forming a semiconductor layer (41) that conformally covers the inner sidewall of the corresponding second accommodation groove; Forming a gate insulating layer (42) that conformally covers the semiconductor layer and the sidewall of the second hole; Among them, the method for manufacturing the memory further includes: Forming a word line (WL) that covers the gate insulating layer and fills the second hole in the memory cell, and a selection line (SL) that covers the gate insulating layer and fills the second hole in the selection unit.

14. The method for manufacturing the memory according to claim 11, wherein, The method for manufacturing the memory further includes: before forming the memory cell, the selection unit, and the connection unit, filling a first isolation layer (61) in the first etch groove and the second etch groove; Among them, the first etch hole group, the second etch hole group, and the third etch hole group all further include: a second hole (H2) located between the bit line and the first hole and having an axis perpendicular to the substrate; the two opposite sides of the second hole in the first direction respectively expose the sidewalls of the bit line and the sidewalls corresponding to the first electrode or the first electrode dummy structure; forming the memory cell based on the first etch hole group and forming the selection unit based on the second etch hole group both include: Removing the third dielectric layer in the second hole; Sequentially forming an initial semiconductor layer (41A) and a gate insulating layer (42) on the inner sidewall of the second hole; Form a word line (WL) covering the gate insulating layer and filling the second holes in the memory cell, and a select line (SL) covering the gate insulating layer and filling the second holes in the select unit; Remove the first isolation layer in the second etching groove; Etch each of the first dielectric layers in the first direction until the side wall of the initial semiconductor layer facing away from the gate insulating layer is exposed; Etch and remove the initial semiconductor layer between any adjacent second dielectric layers to form a plurality of semiconductor layers (41) spaced apart in the direction perpendicular to the substrate; Form a second isolation layer (62) filling the space between adjacent semiconductor layers, the removed area of the first dielectric layer, and the second etching groove; 15. The method for manufacturing a memory according to claim 11, wherein, The same bit line corresponds to at least two of the connection units; the first etching hole group, the second etching hole group, and the third etching hole group each further include: a second hole (H2) located between the bit line and the first hole and having an axis perpendicular to the substrate; forming a bit line in the bit line accommodation groove includes: Form an initial bit line (BLA) in the bit line accommodation groove; After forming the memory cell, the select unit, and the connection unit, remove the third dielectric layer in the second hole in any one of the third etching hole groups, and etch and cut the initial bit line along a direction parallel to the substrate based on the second hole to form the bit line (BL); wherein, the bit line includes a first portion (BLa) opposite to the memory cell and the select unit, and a second portion (BLb) opposite to the connection unit; Form an isolation structure (5) in the cut-off area of the initial bit line and the second hole communicating therewith; 16. The method for manufacturing a memory according to claim 15, wherein, The end of the bit line accommodation groove close to the common bit line accommodation groove communicates with the common bit line accommodation groove; the common bit line and the initial bit line are formed synchronously; Wherein, the second portion of the bit line and the common bit line are of an integral structure; 17. The method for manufacturing a memory according to claim 15, wherein, After forming the common bit line and the initial bit line and before forming the memory cell, the select unit, and the connection unit, the method for manufacturing the memory further includes: Etch the plurality of first dielectric layers and the plurality of second dielectric layers in a direction perpendicular to the substrate to form a third etching groove on a side of the common bit line facing away from the initial bit line; Etch each of the first dielectric layers based on the third etching groove to form a plurality of insulating steps (S1); Etch each of the second dielectric layers based on the third etching groove to form a plurality of conductive step accommodation grooves; the conductive step accommodation grooves expose the side walls corresponding to the common bit line; Form a conductive step (S2) coupled to the common bit line in the conductive step accommodation groove; each of the conductive steps and each of the insulating steps together form a stepped structure (S); Form a covering layer (82) covering the stepped structure; 18. A memory, comprising: A common bit line (CBL) extending in a first direction (Y) parallel to the substrate (1); A bit line (BL) located on a first side of the common bit line and extending in a second direction (X) parallel to the substrate, the second direction intersecting the first direction; Dummy lines (DL), strobe lines (SL), and word lines (WL) are all located on a first side of the common bit line, all on the same side of the bit line, and all extend along a third direction (Z) perpendicular to the substrate, wherein the dummy lines, the strobe lines, and the word lines are arranged in sequence along the second direction and are sequentially away from the common bit line; Access transistors (T1) are coupled to the word lines and the bit lines; Capacitors (C) are located on a side of the access transistors away from the bit lines and are coupled to the access transistors; Strobe transistors (T2) are coupled to the strobe lines, the bit lines, and the common bit line.

19. The memory according to claim 18, further comprising: Connection electrodes (9) are located between the capacitors and the common bit line; wherein the strobe transistors are coupled to the common bit line through the connection electrodes.

20. An electronic device includes the memory according to any one of claims 1-9 or claims 18-19, and a processor coupled to the memory.

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