Memory, bit line control method, and electronic device

Abstract

Provided in the present disclosure are a memory, a bit line control method, and an electronic device. In a first chip of the memory, each core sheet comprises a plurality of storage layer groups, which are sequentially stacked in a third direction, wherein in odd-numbered storage layer groups, each local bit line is coupled to a first common bit line thereof via a bit line selector thereof, and each local bit line is coupled to a second common bit line thereof via a pre-charge switch thereof; and in even-numbered storage layer groups, each local bit line is coupled to the first common bit line thereof via the pre-charge switch thereof, and each local bit line is coupled to the second common bit line thereof via the bit line selector thereof.

Description

Memory, bit line control method and electronic device

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on December 26, 2023, with application number 202311829091.5 and application name “A memory, bit line control method and electronic device”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present disclosure relates to the field of semiconductors, and in particular to a memory, a bit line control method, and an electronic device. Background Art

[0003] With the development of semiconductor technology, semiconductor memory has been widely used in electronic devices. Dynamic Random Access Memory (DRAM) is a type of volatile memory. Due to its fast access speed, DRAM is often used as cache memory.

[0004] Dynamic random access memory (DRAM) primarily consists of two components: the periphery and the core. To further increase storage density, three-dimensional DRAM (3D DRAM) places the periphery and core in two separate chips, which are then connected via bonding. However, current 3D DRAM suffers from a serious problem of BL-to-BL coupling, which results in a loss of sensing margin.

[0005] Summary of the Invention

[0006] Embodiments of the present disclosure provide a memory, a bit line control method, and an electronic device.

[0007] The technical solution of the present disclosure is achieved as follows:

[0008] In a first aspect, the present disclosure provides a memory, which includes a first chip, the first chip includes multiple memory array chips, and each memory array chip includes multiple memory layer groups stacked in sequence along a third direction; each memory layer group has multiple local bit lines extending along the first direction, and the multiple local bit lines are arranged in sequence along the second direction; the first side of each memory layer group has a first common bit line, and the second side of each memory layer group has a second common bit line, the first side and the second side are opposite to each other along the first direction, the first direction and the second direction intersect, and the third direction is perpendicular to the first direction and perpendicular to the second direction; each memory layer group also includes multiple bit line selectors and multiple pre-charge switches; the multiple memory layer groups are numbered along the third direction: in odd-numbered memory layer groups, each local bit line is coupled to its respective first common bit line via its respective bit line selector, and each local bit line is coupled to its respective second common bit line via its respective pre-charge switch; in even-numbered memory layer groups, each local bit line is coupled to its respective first common bit line via its respective pre-charge switch, and each local bit line is coupled to its respective second common bit line via its respective bit line selector.

[0009] In some embodiments, a first step contact structure is further provided on the first side of the first common bit line, and a second step contact structure is further provided on the second side of the second common bit line, and both the first step contact structure and the second step contact structure are connected to the sensing amplification region; the first common bit line of the odd-numbered storage layer group is connected to the first step contact structure, and the second common bit line of the even-numbered storage layer group is connected to the second step contact structure.

[0010] In some embodiments, the first step contact structure and the second step contact structure both include multiple steps, and each first common bit line of the odd-numbered storage layer group is coupled to a sensing amplifier in the sensing amplification area via a step of the first step contact structure; each second common bit line of the even-numbered storage layer group is coupled to a sensing amplifier in the sensing amplification area via a step of the second step contact structure.

[0011] In some embodiments, for the first step contact structure, several consecutive steps form a step group, and multiple step groups are arranged at intervals along the second direction; for the second step contact structure, several consecutive steps form a step group, and multiple step groups are arranged at intervals along the second direction.

[0012] In some embodiments, the memory further includes a second chip, the first chip and the second chip are stacked along a third direction, and the first chip and the second chip are bonded together; and the sensing amplification region is located in the second chip.

[0013] In some embodiments, each memory array slice further includes a plurality of local word lines, and each local word line penetrates the plurality of memory layer groups along a third direction.

[0014] In some embodiments, the memory further includes a plurality of common word lines extending along the second direction, and a plurality of local word lines aligned along the second direction are coupled to the same common word line.

[0015] In some embodiments, the memory layer group further includes a plurality of memory cells, and each memory cell is respectively connected to a local bit line and a local word line;

[0016] A memory is configured such that, during a read operation or a write operation, for a selected memory cell, a bit line selector controlling a local bit line connected thereto is in an on state, and a pre-charge switch controlling a local bit line connected thereto is in an off state; and for an unselected memory cell, a bit line selector controlling a local bit line connected thereto is in an off state, and a pre-charge switch controlling a local bit line connected thereto is in an on state.

[0017] In some embodiments, in odd-numbered memory layer groups, each precharge switch is located on a third side of a corresponding local bit line, and each bit line selector is located on a fourth side of a corresponding local bit line; the third side and the fourth side are opposite to each other along the second direction;

[0018] In even-numbered memory layer groups, each precharge switch is located on the fourth side of the corresponding local bit line, and each bit line selector is located on the third side of the corresponding local bit line.

[0019] In some embodiments, the bit line selector and the precharge switch are both CMOS switches.

[0020] In a second aspect, an embodiment of the present disclosure provides a bit line control method, which is applied to the memory according to the first aspect. The method includes:

[0021] Based on the address signal, a plurality of local bit lines aligned along a third direction are selected in the target memory array slice;

[0022] In odd-numbered storage layer groups, the selected local bit line is controlled to be electrically connected to the first common bit line of the storage layer group to which it belongs, and the unselected local bit line is controlled to be electrically connected to the second common bit line of the storage layer group to which it belongs; and, in even-numbered storage layer groups, the selected local bit line is controlled to be electrically connected to the second common bit line of the storage layer group to which it belongs, and the unselected local bit line is controlled to be electrically connected to the first common bit line of the storage layer group to which it belongs.

[0023] In some embodiments, the method further comprises:

[0024] Controlling the bit line selector of the selected local bit line to be in an on state and the precharge switch of the selected local bit line to be in an off state, so that the selected local bit line in the odd-numbered storage layer is electrically connected to the first common bit line, and the selected local bit line in the even-numbered storage layer is electrically connected to the second common bit line;

[0025] The bit line selector that controls the unselected local bit lines is in the off state, and the pre-charge switch of the unselected local bit lines is in the on state, so that the unselected local bit lines in the odd-numbered storage layer are electrically connected to the second common bit line, and the unselected local bit lines in the even-numbered storage layer are electrically connected to the first common bit line.

[0026] In some embodiments, the method further includes: for odd-numbered storage layer groups, controlling the potential of the second common bit line to be a precharge potential; and, through charge sharing and sensing amplification processing, making the potential of the first common bit line a low potential or a high potential; for even-numbered storage layer groups, controlling the potential of the first common bit line to be a precharge potential; and, through charge sharing and sensing amplification processing, making the potential of the second common bit line a low potential or a high potential; wherein, the low potential < precharge potential < high level.

[0027] In a third aspect, an embodiment of the present disclosure provides an electronic device, comprising the memory as described in the first aspect.

[0028] The embodiments of the present disclosure provide a memory, a bit line control method, and an electronic device. For odd-numbered storage layer groups, the local bit line is connected to the first common bit line through a bit line selector and to the second common bit line through a pre-charge switch; for even-numbered storage layer groups, the local bit line is connected to the second common bit line through a bit line selector and to the first common bit line through a pre-charge switch. At the same time, all the first common bit lines are arranged in sequence in a direction perpendicular to the storage layer group, and all the second common bit lines are arranged in a direction perpendicular to the storage layer group. In this way, during the sensing and amplification process, for two first common bit lines adjacent in the third direction, one of the first common bit lines must be in a sensing and amplification state (high potential or low potential) and the other first common bit line must be in a pre-charge potential; for two second common bit lines adjacent in the third direction, one of the second common bit lines must be in a sensing and amplification state (high potential or low potential) and the other second common bit line must be in a pre-charge potential. The coupling of adjacent common bit lines is significantly weakened, thereby improving the sensing and amplification margin. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] FIG1A is a schematic diagram of the structure of a memory array chip in a first chip;

[0030] FIG1B is a schematic diagram of a partial structure of a memory array chip;

[0031] FIG2 is a schematic diagram of a specific structure of a storage array chip;

[0032] FIG3 is a schematic diagram of the bit line-bit line coupling effect in a memory array chip;

[0033] FIG4 is a schematic structural diagram of a memory array chip in a first chip provided by an embodiment of the present disclosure;

[0034] FIG5A is a schematic top view of a storage layer group;

[0035] FIG5B is a schematic top view of a storage layer group provided by an embodiment of the present disclosure;

[0036] FIG6 is a schematic structural diagram of a memory array chip in another first chip provided by an embodiment of the present disclosure;

[0037] FIG7 is a schematic diagram of a partial structure of a memory provided by an embodiment of the present disclosure;

[0038] FIG8 is a schematic structural diagram of a memory array chip in another first chip provided by an embodiment of the present disclosure;

[0039] FIG9 is a schematic diagram of a stacking structure of a memory provided by an embodiment of the present disclosure;

[0040] FIG10 is a schematic structural diagram of a memory array chip in a first chip provided by an embodiment of the present disclosure;

[0041] FIG11 is a schematic diagram of the working state of a storage array chip provided by an embodiment of the present disclosure;

[0042] FIG12 is a schematic diagram of a bit line-to-bit line coupling effect in a memory array chip according to an embodiment of the present disclosure;

[0043] FIG13 is a flow chart of a bit line control method provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0044] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the technical solutions of the present disclosure are further elaborated in detail below with reference to the accompanying drawings and embodiments. The described embodiments should not be regarded as limiting the present disclosure. All other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present disclosure.

[0045] In the following description, reference is made to “some embodiments”, which describes a subset of all possible embodiments, but it will be understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0046] If similar descriptions of "first / second" appear in the application documents, the following explanation is added. In the following description, the terms "first / second / third" are merely used to distinguish similar objects and do not represent a specific order for the objects. It is understandable that "first / second / third" can be interchanged with a specific order or sequence where permitted, so that the embodiments of the present disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0047] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art in the art of the present disclosure. The terms used herein are only for the purpose of describing the embodiments of the present disclosure and are not intended to limit the present disclosure.

[0048] Glossary:

[0049] WL (WordLine): word line;

[0050] BL (BitLine): bit line;

[0051] CMOS (Complementary Metal Oxide Semiconductor): complementary metal oxide semiconductor;

[0052] TSV (Through-Silicon-Via): through silicon via;

[0053] Mat (Memory Array Tile): storage array tile.

[0054] Before introducing the embodiments of the present disclosure, three directions that may be used to describe a three-dimensional structure in the plane involved in the following embodiments are defined. Taking the Cartesian coordinate system as an example, the three directions may include a first direction, a second direction, and a third direction.

[0055] The semiconductor chip may include a top surface on the front side and a bottom surface on the back side opposite to the front side; while ignoring the flatness of the top surface and the bottom surface, a direction intersecting (for example, perpendicular) with the top surface and the bottom surface of the semiconductor chip is defined as a third direction; at the same time, an extension direction of a local bit line in the semiconductor chip is defined as a first direction, and an extension direction of a local word line in the semiconductor chip is defined as a second direction, and the first direction and the second direction intersect.

[0056] For 3D DRAM, it includes a first chip and a second chip stacked along a third direction, and the memory array (Core) is distributed in the first chip, and the peripheral control area (Periphery), sensing and amplification area, etc. are distributed in the second chip. For the first chip, the memory array (Core) includes a large number of memory cells, which are divided into multiple memory array slices (Mat) for better control and management. Please refer to Figure 1A, which shows a schematic structural diagram of the memory array slice 11 in the first chip. As shown in Figure 1A, each memory array slice 11 includes multiple sub-array slices arranged in sequence along the second direction, each sub-array slice includes multiple storage areas stacked in sequence along the third direction, and each storage area includes two storage layer groups arranged along the first direction, and a step contact structure (Staircase) 14 is provided between the first storage layer group and the second storage layer group. Please refer to Figure 1B, which is an enlarged schematic diagram of the local structure in Figure 1A. As shown in FIG1B , each storage layer group includes a plurality of local bit lines Local BL extending along a first direction, and a local word line Local WL running through the plurality of storage layer groups along a third direction. A storage cell is formed at the intersection of the local word line and the local bit line (represented by a five-pointed star in FIG1B ). Please refer to FIG2 , which shows a schematic diagram of the specific structure of each storage layer group in the memory array chip 11. As shown in FIG2 , a first common bit line (Common BL) 12 and a second common bit line 13 are provided on the left and right sides of each storage layer group, respectively. The left ends of all local bit lines in the storage layer group are connected to the first common bit line 12 on the left through a precharge switch Eq, and the right ends of all local bit lines in the storage layer group are connected to the second common bit line 13 on the right through a bit line selector Se. At the same time, each second common bit line is coupled to a sense amplifier SA in the sense amplification area through a step contact structure 14.

[0057] Taking data reading as an example, a group of target memory cells aligned along the third direction are enabled by turning on the target word line, and the bit line selectors Se of the local bit lines connected to this group of target memory cells are turned on. At this time, each target memory cell is connected to its corresponding second common bit line 13, so that the group of second common bit lines 13 aligned along the third direction share charge with their respective target memory cells and undergo sense amplification, thereby being at a high or low potential (depending on the data stored in the target memory cells); the bit line selectors Se of the unselected local bit lines are turned off and the precharge switches Eq are turned on, and all first common bit lines 12 are charged to the precharge potential, so that all unselected local bit lines are at the precharge potential. Here, the precharge potential can be an intermediate potential, which can be half of the memory array power supply voltage (Vblh), that is, the intermediate potential = 1 / 2Vblh. That is to say, in the above scenario, the first common bit line 12 is at a precharge potential, and the second common bit line 13 is at a high potential or a low potential. Due to the parasitic capacitance between the two adjacent common bit lines along the third direction, a serious BL-to-BL coupling occurs between the bit lines. For example, in FIG3 , the coupling capacitance between adjacent second common bit lines is recorded as C_BL2BL. Assuming that a second common bit line 13 changes from 0V to a high potential (for example, 1V) after charge sharing and sensing amplification processing, the mutual coupling between the bit lines will cause the voltage of the adjacent second common bit line 13 to increase, so that the potential of the adjacent second common bit line 13 may not accurately represent the data stored in the corresponding target memory cell. Similar problems also exist for writing data.

[0058] Simply put, in a memory array chip, local bit lines in the same memory layer group share a first common bit line and a second common bit line. A bit line selector determines whether to connect to the second common bit line, while a precharge switch determines whether to connect to the first common bit line. The second common bit lines of each layer are interconnected with the sense amplifier SA via corresponding step contact structures 14. In this case, the second common bit lines of each layer undergo sensing amplification on the same side, resulting in severe inter-bit line coupling, which in turn causes a loss of sensing margin.

[0059] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

[0060] In one embodiment of the present disclosure, a memory is provided, comprising a first chip 20. Referring to FIG4 , a schematic diagram illustrating the structure of the first chip 20 according to an embodiment of the present disclosure is shown. As shown in FIG4 , the first chip 20 comprises a plurality of memory array chips 21 (only one is shown in FIG4 ). The plurality of memory array chips 21 may be arranged along a first direction, along a second direction, or in an array along both the first and second directions.

[0061] Each memory array cell 21 includes multiple memory layer groups (e.g., 210o, 210e, ... in FIG4 ) stacked sequentially along a third direction. Each memory layer group includes multiple local bit lines extending along a first direction, and the multiple local bit lines are sequentially arranged along a second direction. A first common bit line 220 is provided on the first side of each memory layer group (e.g., the left side in FIG4 ), and a second common bit line 230 is provided on the second side of each memory layer group (e.g., the right side in FIG4 ).

[0062] It should be noted that the first side and the second side are opposite each other along a first direction; the first direction and the second direction intersect, and the third direction is perpendicular to the first direction and perpendicular to the second direction. For example, the first direction and the second direction are perpendicular, or the first direction and the second direction may form a certain angle. In Figure 4, the first common bit line 220 and the second common bit line 230 both extend along the second direction, but this does not constitute a limitation.

[0063] Each storage layer group further includes a plurality of bit line selectors Se and a plurality of precharge switches Eq, and each local bit line corresponds to a separate bit line selector Se, and each local bit line corresponds to a separate precharge switch Eq.

[0064] Here, the bit line selector Se and the plurality of pre-charge switches Eq are both switch devices. Exemplarily, the bit line selector Se is a CMOS switch, and the pre-charge switches Eq are CMOS switches.

[0065] For the convenience of explanation, multiple storage layer groups are numbered along the third direction. For example, in Figure 4, from bottom to top, the 0th storage layer group is numbered 210e, the 1st storage layer group is numbered 210o, the 2nd storage layer group is numbered 210e, the 3rd storage layer group is numbered 210o...

[0066] In the odd-numbered storage layer group 210o, each local bit line is coupled to its respective first common bit line 220 via its respective bit line selector Se, and each local bit line is coupled to its respective second common bit line 230 via its respective pre-charge switch Eq; in the even-numbered storage layer group 210e, each local bit line is coupled to its respective first common bit line 220 via its respective pre-charge switch Eq, and each local bit line is coupled to its respective second common bit line 230 via its respective bit line selector.

[0067] It should be noted that in Figure 4, each storage array chip includes 5 storage layer groups, but this is only for illustration and does not constitute a limitation; at the same time, each storage layer group is illustrated with 4 local bit lines, but in reality the number of local bit lines in each storage layer group can be more or less.

[0068] It should be understood that for those common bit lines connected to the local bit lines through the bit line selector Se, in read operations, write operations, or other operations involving data, their function is to share charge with the selected memory cells and perform sense amplification processing under the action of the sense amplifier; for those common bit lines connected to the local bit lines through the precharge switch Eq, in read operations, write operations, or other operations involving data, their function is to provide a precharge potential; illustratively, the precharge potential can be an intermediate potential of 1 / 2Vblh, where Vblh is the power supply potential of the memory array, and can also be understood as the power supply potential of the sense amplifier.

[0069] Please refer to Figure 5A, which shows a schematic top view of a memory array chip 11 (the memory array chip 11 shown in Figures 1A to 3). As shown in Figure 5, in memory array chip 11, for all memory layer groups, the pre-charge switches Eq are located on the left side, and the bit line selectors Se are located on the right side. In addition, the projections of the pre-charge switches Eq and bit line selectors Se of different memory layer groups along the third direction overlap, resulting in synchronous inductive amplification of multiple second common bit lines 13 aligned along the third direction, causing serious bit line coupling problems.

[0070] Please refer to Figure 5B, which shows a schematic top view of a memory array chip 21 provided by an embodiment of the present disclosure. As shown in Figure 5B, for the odd-numbered memory layer group 210o, its bit line selector Se is located on the left, and its pre-charge switch Eq is located on the right; for the even-numbered memory layer group 210e, its pre-charge switch Eq is located on the left, and its pre-charge switch Eq is located on the right. In particular, in Figure 5B, the bit line selector Se of the odd-numbered memory layer group 210o and the pre-charge switch Eq of the even-numbered memory layer group 210e can overlap, and the pre-charge switch Eq of the odd-numbered memory layer group 210o and the bit line selector Se of the even-numbered memory layer group 210e can overlap. They are drawn separately here only for the sake of convenience.

[0071] Specifically, for the first chip 20, the first common bit lines 220 of two adjacent storage layer groups are adjacent in the third direction, and the second common bit lines 230 of two adjacent storage layer groups are adjacent in the third direction, but any first common bit line 220 and any second common bit line 230 are not adjacent in the third direction; at the same time, for the odd-numbered storage layer group 210o, the local bit line is connected to the first common bit line 220 through the bit line selector Se, and is connected to the second common bit line 230 through the pre-charge switch Eq; for the even-numbered storage layer group 210e, the local bit line is connected to the second common bit line 230 through the bit line selector Se, and is connected to the first common bit line 220 through the pre-charge switch Eq. Therefore, during the sensing and amplification process, for the selected multiple storage layer groups, for two adjacent first common bit lines 220, one first common bit line 220 must be in the sensing and amplification state (high or low, depending on the specific data value), and the other first common bit line 220 must be in the precharge potential. For two adjacent second common bit lines 230, one second common bit line 230 must be in the sensing and amplification state (high or low, depending on the specific data value), and the other second common bit line must be in the precharge potential, with the low potential < precharge potential < high potential. However, the two adjacent common bit lines do not undergo sensing and amplification processing at the same time, so the two adjacent common bit lines along the third direction will not be in the sensing and amplification state at the same time. Therefore, the coupling between the two adjacent common bit lines is significantly reduced, thereby improving the sensing and amplification margin.

[0072] In some embodiments, referring to FIG6 , a first step contact structure 240 is further provided on the first side of the first common bit line 220, and a second step contact structure 250 is further provided on the second side of the second common bit line 230. Both the first step contact structure 240 and the second step contact structure 250 are connected to the sensing amplification region; the first common bit line 220 of the odd-numbered storage layer group 210o is connected to the first step contact structure 240, and the second common bit line 230 of the even-numbered storage layer group 220e is connected to the second step contact structure 250.

[0073] It should be noted that the sensing amplification area includes multiple sensing amplifiers (SA), also known as sensitive amplifiers, which sense and amplify the electrical signal of the common bit line connected to the selected memory cell, and finally the potential of the common bit line reaches a low potential or a high potential, thereby achieving the purpose of reading or writing data from the selected memory cell.

[0074] Here, since 3D DRAM mostly uses a vertical stacking of multiple layers of memory cells (i.e., multiple memory layer groups) to form a storage structure, in order to ensure that the sense amplifier can be smoothly connected to the common bit line in each memory layer group, it is necessary to form a 3D step contact structure (Staircase). The different steps of the step contact structure are electrically isolated, and one step is correspondingly connected to a common bit line (connected to the bit line connector Se), so that the common bit line is connected to the sense amplifier SA in the sense amplification area to realize the sense amplification processing.

[0075] At the same time, since the local bit lines of odd-numbered storage layer groups 210o are connected to the first common bit line 220 via bit line selector Se, and the local bit lines of even-numbered storage layer groups 210e are connected to the second common bit line 230 via bit line selector Se, the two adjacent storage layer groups along the third direction will perform sensing amplification on the first common bit line 220 and the second common bit line 230, respectively. For the two adjacent common bit lines along the third direction, one must be in a sensing amplification state (low potential or high potential) and the other must be in a precharge potential, thereby reducing bit line-to-bit line coupling and increasing the margin for sensitive amplification. At the same time, the step contact structure is evenly distributed on both sides of the memory array chip 21, without adding additional area.

[0076] In some embodiments, the first step contact structure 240 and the second step contact structure 250 both include multiple steps, and each first common bit line 220 of the odd-numbered storage layer group 210o is coupled to a sensing amplifier in the sensing amplification area via a step of the first step contact structure 240; each second common bit line 230 of the even-numbered storage layer group 210e is coupled to a sensing amplifier in the sensing amplification area via a step of the second step contact structure 250.

[0077] When the number of stacked memory layer groups is large, the area of ​​the step structure region gradually increases, resulting in an increase in chip manufacturing costs. In order to reduce the step area, the embodiment of the present disclosure adopts a grouped step contact structure.

[0078] In some embodiments, for the first step contact structure 240, several consecutive steps form a step group, and multiple step groups are arranged at intervals along the second direction; for the second step contact structure 250, several consecutive steps form a step group, and multiple step groups are arranged at intervals along the second direction.

[0079] Please refer to Figure 7, which shows a connection diagram of a step group provided by an embodiment of the present disclosure. Figure 7 shows an example in which each step group includes 3 steps. For the convenience of explanation, the storage layer groups are numbered from bottom to top. The second common bit lines 230 of the 0th, 2nd, and 4th storage layer groups are connected to the 1st step group of the second step contact structure 250 in a one-to-one correspondence. The second common bit lines 230 of the 6th, 8th, and 10th storage layer groups are connected to the 2nd step group of the second step contact structure 250 in a one-to-one correspondence. At the same time, the first common bit lines 220 of all odd-numbered storage layer groups (the 1st, 3rd, 5th... storage layer groups) are connected to the first step contact structure 240 (blocked in the figure and not shown).

[0080] In this way, different step groups are arranged in sequence along the second direction, and the size of each step along the first direction does not need to be designed to be too long.

[0081] In addition, in Figure 7, different steps in the same step group are separated, but this is only to more intuitively illustrate their connection relationship with the corresponding storage layer group. In actual application scenarios, different steps in the same step group can be closely connected, as long as they follow the above connection relationship with the storage layer group.

[0082] In some embodiments, referring to FIG8 , in the odd-numbered storage layer group 210o, each pre-charge switch Eq is located on the third side of the corresponding local bit line (for example, the side facing outward along the paper in FIG7 ), and each bit line selector Se is located on the fourth side of the corresponding local bit line (for example, the side facing inward along the paper in FIG7 ); the third side and the fourth side are opposite to each other along the second direction; in the even-numbered storage layer group 210e, each pre-charge switch Eq is located on the fourth side of the corresponding local bit line, and each bit line selector Se is located on the third side of the corresponding local bit line.

[0083] That is to say, referring to FIG5A , in the memory array chip 11, for all memory layer groups, the pre-charge switch Eq is located on the left, the bit line selector Se is located on the right, and the projections of the pre-charge switch Eq / bit line selector Se of different memory layer groups along the third direction overlap, resulting in synchronous induction amplification of multiple second common bit lines 13 aligned along the third direction, thereby causing serious bit line mutual coupling problems.

[0084] Please refer to Figure 5B. For the odd-numbered storage layer group 210o, its bit line selector Se is located at the lower left and its pre-charge switch Eq is located at the upper right; for the even-numbered storage layer group 210e, its pre-charge switch Eq is located at the upper left and its bit line selector Se is located at the lower right.

[0085] In this way, for the same storage layer group, its bit line selector Se and pre-charge switch Eq are respectively located on both sides of the local bit line to which they belong along the second direction, and the layout is more reasonable; at the same time, for two storage layer groups adjacent along the third direction, the projections of the bit line selector Se of one storage layer group and the pre-charge switch Eq of the other storage layer group along the third direction do not overlap, avoiding coupling between the switches.

[0086] In some embodiments, referring to FIG. 9 , the aforementioned memory is a three-dimensional memory, which further includes a second chip 30 , the first chip 20 and the second chip 30 are stacked along a third direction, and the first chip 20 and the second chip 30 are bonded and connected; the aforementioned sensing amplification area is located in the second chip 30 .

[0087] It should be noted that bonding connection refers to the electrical connection between two chips through a hybrid bonding structure (also known as bond pillars). Hybrid bonding is the process of creating a permanent bond between heterogeneous or homogeneous chips. "Hybrid" refers to the formation of dielectric-dielectric and metal-metal bonds between two surfaces, which has the following advantages: (1) Shorter interconnection distance: Not only does it not require wires to connect to each other, but it also does not require TSVs to pass through the entire CMOS layer. Interconnection can be achieved simply by connecting copper contacts in the back-end; (2) Higher interconnection density: The area of ​​copper contacts is very small. Compared with solder balls and TSVs with a diameter of 100 microns, the pitch size of copper contacts in the hybrid bonding process is even less than 10 microns, which can undoubtedly achieve higher interconnection density; (3) Lower cost: It is undeniable that interconnecting each chip individually requires more time. Through wafer bonding, large-area high-density interconnection can be achieved, which makes a significant contribution to the improvement of production capacity. Naturally, production costs can also be reduced.

[0088] In some embodiments, referring to FIG10 , each memory array chip 21 further includes multiple local word lines (only one is shown in FIG10 ), each of which extends along a third direction through multiple memory layer groups. The intersection of each local word line and the corresponding local bit line forms a memory cell (the five-pointed star in FIG10 ).

[0089] In this way, each local word line will open multiple memory cells aligned along the third direction, and these multiple memory cells will be read / written synchronously; at the same time, for two adjacent memory cells along the third direction, one memory cell must be read / written through the first common bit line 220 on one side, and the other memory cell must be read / written through the first common bit line 220 on the other side, so the impact of bit line coupling is small, which can improve the performance of the memory.

[0090] In some embodiments, referring to FIG. 10 , the memory further includes a plurality of common word lines (only one is shown in FIG. 10 ) extending along the second direction, and a plurality of local word lines aligned along the second direction are coupled to the same common word line.

[0091] Specifically, the first local word line in each sub-array tile is coupled to a common word line, the second local word line in each sub-array tile is coupled to another common word line, and the third local word line in each sub-array tile is coupled to yet another common word line.

[0092] In some embodiments, a memory cell formed at the intersection of a local word line and a local word line includes at least a 1T1C structure, or other known and feasible memory structures. The 1T1C structure includes an N-type transistor and a capacitor.

[0093] The memory 20 is configured such that, during a read operation or a write operation, for a selected memory cell, the bit line selector Se that controls the local bit line connected thereto is in an on state, and the pre-charge switch Eq that controls the local bit line connected thereto is in an off state; and for an unselected memory cell, the bit line selector Se that controls the local bit line connected thereto is in an off state, and the pre-charge switch Eq that controls the local bit line connected thereto is in an on state.

[0094] Please refer to Figure 11, which shows a schematic diagram of the working state of a memory array chip provided by an embodiment of the present disclosure. In particular, Figure 11 is a top view of an odd-numbered storage layer group 210o and an even-numbered storage layer group 210e. When the selected local word line Local WL is turned on, multiple memory cells aligned along the third direction are turned on. At this time, the bit line selector Se of the local bit line Local BL corresponding to the selected local word line is in the on state and the pre-charge switch Eq is in the off state; at the same time, the bit line selector Se of the local bit line Local BL corresponding to the unselected local word line is in the off state and the pre-charge switch Eq is in the on state. Specifically:

[0095] (1) Referring to FIG. 11 , for the odd-numbered storage layer group 210 o , the fourth local bit line Local BL (numbered from bottom to top) is connected to the first common bit line 220 o on the left side via the bit line selector Se, so that the voltage of the first common bit line 220 o gradually increases from 0 V (assuming data 1 is read out), and then reaches 1 V after sensing and amplification; however, the second common bit line 230 o is precharged to a precharge potential (e.g., 0.5 V), and the first to third local bit lines Local BL are all connected to the second common bit line 230 o via corresponding precharge switches Eq, so that the first to third local bit lines Local BL are maintained at a precharge potential of 0.5 V;

[0096] (2) Please refer to Figure 11. For the even-numbered storage layer group 210e, the fourth local bit line is connected to the second common bit line 230e on the right through the bit line selector Se, so that the voltage of the second common bit line 230e gradually increases from 0V (assuming that data 1 is read out), and then reaches 1V after sensing and amplification. However, the first common bit line 220e is pre-charged to a pre-charge potential of 0.5V, and the first to third local bit lines Local BL are all connected to the first common bit line 220e through corresponding pre-charge switches Eq, so that the first to third local bit lines Local BL are maintained at a pre-charge potential of 0.5V.

[0097] It should be understood that in the third direction, the first common bit line 220o (the voltage changes from 0V to 1V after charge sharing and sensing amplification) is adjacent to the first common bit line 220e (the voltage is a pre-charge potential of 0.5V), and the second common bit line 230o (the voltage is a pre-charge potential of 0.5V) is adjacent to the second common bit line 230e (the voltage changes from 0V to 1V after charge sharing and sensing amplification), that is, at most one of the two adjacent common bit lines performs sensing amplification processing, thereby reducing the bit line-bit line coupling problem.

[0098] Referring to FIG12 , taking a stack of five storage layer groups as an example, the first common bit lines 220o of the first and third storage layer groups are both changed from 0V to 1V, i.e., they undergo a sense amplification process. The first common bit lines 220e of the first, second, and fourth storage layer groups are all precharged to a potential of 0.5V and do not undergo a sense amplification process. Simultaneously, the second common bit lines 230e of the first, second, and fourth storage layer groups are both changed from 0V to 1V, i.e., they undergo a sense amplification process. The second common bit lines 230o of the first and third storage layer groups are all precharged to a potential of 0.5V and do not undergo a sense amplification process. Thus, for adjacent common bit lines on the same side, the data potential (low potential / high potential) after sense amplification and the precharge potential always appear alternately, thereby reducing bitline-bitline coupling problems and improving the sense amplification margin.

[0099] Of course, the above description only takes the high potential = 1V and the pre-charge potential = 0.5V as an example; of course, in other embodiments, the values ​​of the low potential, the pre-charge potential and the high potential can be arbitrary, as long as the low potential < pre-charge potential < high potential is satisfied.

[0100] In summary, the embodiment of the present disclosure provides a three-dimensional stereo memory, which includes a first chip 20 and a second chip 30. The first chip 20 and the second chip 30 are stacked along the third direction and connected by hybrid bonding. The first chip 20 is mainly used to make a memory array (Core), which is specifically divided into multiple memory array chips (Mat) for better control and management; the second chip 30 is mainly used to make a peripheral control area (Periphery) and a sensing amplification area. In the first chip 20, each memory array chip includes multiple memory layer groups stacked along the third direction. The common bit lines Common BL of the odd layers (i.e., odd-numbered memory layer groups) and the even layers (i.e., even-numbered memory layer groups) will be controlled by independent bit line selectors BL selector and pre-charge switches Eq Device respectively; the local bit lines Local BL between adjacent memory layer groups along the third direction will be sensed and amplified on both sides of the memory layer group along the first direction respectively. Common bit lines arranged continuously along the third direction are alternately arranged in a sensing amplification state (Sensing) and a precharge potential, thereby reducing BL-to-BL coupling. Furthermore, the memory array chip also includes staircase contact structures distributed on both sides, such that the first common bit lines of odd-numbered layers are connected to the staircase contact structure on a first side along the first direction, and the second common bit lines of even-numbered layers are connected to the staircase contact structure on a second side along the second direction. The staircase contact structures are arranged on both sides so as not to increase the area.

[0101] In another embodiment of the present disclosure, see FIG13 , which illustrates a flow chart of a test method provided by an embodiment of the present disclosure. As shown in FIG13 , the test method is applied to the memory device shown in FIG4 . The memory device includes a first chip 20 and a second chip 30 stacked along a first direction. The first chip 20 includes multiple memory array chips 21 . Each memory array chip includes multiple memory layer groups (e.g., 210o, 210e, etc. in FIG4 ) stacked sequentially along a third direction. Each memory layer group includes multiple local bit lines extending along the first direction, and the multiple local bit lines are sequentially arranged along a second direction. A first common bit line 220 is provided on the first side of each memory layer group (e.g., the left side in FIG4 ), and a second common bit line 230 is provided on the second side of each memory layer group (e.g., the right side in FIG4 ). Each memory layer group also includes multiple bit line selectors Se and multiple precharge switches Eq, with each local bit line corresponding to a separate bit line selector Se and a separate precharge switch Eq. For the sake of convenience of explanation, multiple storage layer groups are numbered along the third direction. In the odd-numbered storage layer group 210o, each local bit line is coupled to the respective first common bit line 220 via the respective bit line selector Se, and each local bit line is coupled to the respective second common bit line 230 via the respective pre-charge switch Eq; in the even-numbered storage layer group 210o, each local bit line is coupled to the respective first common bit line 220 via the respective pre-charge switch Eq, and each local bit line is coupled to the respective second common bit line 230 via the respective bit line selector.

[0102] The method includes:

[0103] S501: Based on the address signal, select a plurality of local bit lines aligned along a third direction in the target memory array slice;

[0104] S502: In the odd-numbered storage layer group, the selected local bit line is controlled to be electrically connected to the coupled first common bit line, and the unselected local bit line is controlled to be electrically connected to the coupled second common bit line; and, in the even-numbered storage layer group, the selected local bit line is controlled to be electrically connected to the coupled second common bit line, and the unselected local bit line is controlled to be electrically connected to the coupled first common bit line.

[0105] In some embodiments, the method further comprises:

[0106] Controlling the bit line selector of the selected local bit line to be in an on state and the precharge switch of the selected local bit line to be in an off state, so that the selected local bit line in the odd-numbered storage layer is electrically connected to the first common bit line, and the selected local bit line in the even-numbered storage layer is electrically connected to the second common bit line;

[0107] The bit line selector that controls the unselected local bit lines is in the off state, and the pre-charge switch of the unselected local bit lines is in the on state, so that the unselected local bit lines in the odd-numbered storage layer are electrically connected to the second common bit line, and the unselected local bit lines in the even-numbered storage layer are electrically connected to the first common bit line.

[0108] In some embodiments, the method further comprises:

[0109] For odd-numbered storage layer groups, the potential of the second common bit line is controlled to be a precharge potential; and the potential of the first common bit line is set to a low potential or a high potential through charge sharing and sense amplification processing, depending on the data to be written in a write operation or the data to be read in a read operation;

[0110] For even-numbered storage layer groups, the potential of the first common bit line is controlled to be a precharge potential; and, through charge sharing and sense amplification, the potential of the second common bit line is set to a low potential or a high potential, depending on the data to be written in a write operation or the data to be read in a read operation.

[0111] Among them, low potential < pre-charge potential < high level.

[0112] In this way, for the first chip 20, assuming that the selected local bit line in a storage layer group is sensed and amplified through the first common bit line on one side along the first direction, the selected local bit line in the adjacent storage layer group must be sensed and amplified through the second common bit line on the other side along the first direction, that is, the adjacent common bit lines in the two third directions will not be sensed and amplified at the same time, so that the coupling of adjacent common bit lines is significantly weakened, thereby improving the sensing amplification margin.

[0113] In another embodiment of the present disclosure, an electronic device is provided, which includes a memory as shown in FIG4 . The memory includes a first chip 20 and a second chip 30 stacked along a first direction. The first chip 20 includes a plurality of memory array chips 21. Each memory array chip includes a plurality of memory layer groups (e.g., 210o, 210e, ... in FIG4 ) stacked in sequence along a third direction. Each memory layer group includes a plurality of local bit lines extending in the first direction, and the plurality of local bit lines are arranged in sequence along a second direction. The first side of each memory layer group (e.g., the left side in FIG4 ) includes a first common bit line 220, and the second side of each memory layer group (e.g., the right side in FIG4 ) includes a second common bit line 230. Each memory layer group also includes a plurality of bit line selectors Se and a plurality of pre-charge switches Eq, and each local bit line corresponds to a separate bit line selector Se, and each local bit line corresponds to a separate pre-charge switch Eq. For the sake of convenience of explanation, multiple storage layer groups are numbered along the third direction. In the odd-numbered storage layer group 210o, each local bit line is coupled to the respective first common bit line 220 via the respective bit line selector Se, and each local bit line is coupled to the respective second common bit line 230 via the respective pre-charge switch Eq; in the even-numbered storage layer group 210o, each local bit line is coupled to the respective first common bit line 220 via the respective pre-charge switch Eq, and each local bit line is coupled to the respective second common bit line 230 via the respective bit line selector.

[0114] In this way, for the first chip 20, assuming that the selected local bit line in a storage layer group is sensed and amplified through the first common bit line on one side along the first direction, the selected local bit line in the adjacent storage layer group must be sensed and amplified through the second common bit line on the other side along the first direction, that is, the adjacent common bit lines in the two third directions will not be sensed and amplified at the same time, so that the coupling of adjacent common bit lines is significantly weakened, thereby improving the sensing amplification margin.

[0115] It should be noted that, in this document, the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or apparatus comprising the element.

[0116] The serial numbers of the embodiments of the present disclosure are for descriptive purposes only and do not represent the merits of the embodiments. The methods disclosed in the several method embodiments provided in the present disclosure can be arbitrarily combined to obtain new method embodiments when there is no conflict. The features disclosed in the several product embodiments provided in the present disclosure can be arbitrarily combined to obtain new product embodiments when there is no conflict. The features disclosed in the several method or device embodiments provided in the present disclosure can be arbitrarily combined to obtain new method embodiments or device embodiments when there is no conflict.

[0117] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A memory, characterized in that, The memory includes a first chip (20), the first chip includes a plurality of memory array slices (21), and each of the memory array slices includes a plurality of memory layer groups stacked in sequence along a third direction; each of the memory layer groups has a plurality of local bit lines extending along a first direction, and the plurality of local bit lines are arranged in sequence along a second direction; a first common bit line (220) is provided on a first side of each of the memory layer groups, a second common bit line (230) is provided on a second side of each of the memory layer groups, the first side and the second side are opposite to each other along the first direction, the first direction and the second direction intersect, and the third direction is perpendicular to the first direction and perpendicular to the second direction; Each of the memory layer groups further includes a plurality of bit line selectors (Se) and a plurality of precharge switches (Eq); the plurality of memory layer groups are numbered along the third direction: In the oddly numbered memory layer groups (210o), each of the local bit lines is coupled to its respective first common bit line via its respective bit line selector, and each of the local bit lines is coupled to its respective second common bit line via its respective precharge switch; In the evenly numbered memory layer groups (210e), each of the local bit lines is coupled to its respective first common bit line via its respective precharge switch, and each of the local bit lines is coupled to its respective second common bit line via its respective bit line selector.

2. The memory according to claim 1, wherein A first step contact structure (240) is further provided on a first side of the first common bit line, a second step contact structure (250) is further provided on a second side of the second common bit line, and both the first step contact structure and the second step contact structure are connected to a sense amplification region; The first common bit line of the oddly numbered memory layer groups is connected to the first step contact structure, and the second common bit line of the evenly numbered memory layer groups is connected to the second step contact structure.

3. The memory according to claim 2, wherein both the first step contact structure and the second step contact structure include multiple levels of steps, each first common bit line of the oddly numbered memory layer groups is coupled to a sense amplifier in the sense amplification region via a step of the first step contact structure; each second common bit line of the evenly numbered memory layer groups is coupled to a sense amplifier in the sense amplification region via a step of the second step contact structure.

4. The memory according to claim 2, wherein for the first step contact structure, a plurality of consecutive levels of steps form a step group, and a plurality of the step groups are arranged at intervals along the second direction; for the second step contact structure, a plurality of consecutive levels of steps form a step group, and a plurality of the step groups are arranged at intervals along the second direction.

5. The memory according to claim 2, wherein The memory further includes a second chip (30), the first chip and the second chip are stacked along the third direction, and the first chip and the second chip are bonded and connected; The sense amplification region is located in the second chip.

6. The memory according to claim 5, wherein Each of the memory array slices further includes a plurality of local word lines, and each of the local word lines penetrates a plurality of memory layer groups along a third direction.

7. The memory according to claim 6, wherein The memory further includes a plurality of common word lines extending along a second direction, and a plurality of the local word lines aligned along the second direction are coupled to the same common word line.

8. The memory according to claim 7, characterized in that, The memory layer group further includes a plurality of memory cells, and each memory cell is respectively connected to one of the local bit lines and one of the local word lines; The memory is configured to, during a read operation or a write operation, for the selected memory cell, control the bit line selector of the local bit line connected thereto to be in an on state, and control the precharge switch of the local bit line connected thereto to be in an off state; for the unselected memory cell, control the bit line selector of the local bit line connected thereto to be in an off state, and control the precharge switch of the local bit line connected thereto to be in an on state.

9. The memory according to any one of claims 1-8, wherein in the odd-numbered memory layer groups, each of the precharge switches is located on a third side of the corresponding local bit line and each of the bit line selectors is located on a fourth side of the corresponding local bit line; the third side and the fourth side are opposite to each other along the second direction; in the even-numbered memory layer groups, each of the precharge switches is located on the fourth side of the corresponding local bit line, and each of the bit line selectors is located on the third side of the corresponding local bit line.

10. The memory according to claim 9, wherein both the bit line selector and the precharge switch are CMOS switches.

11. A bit line control method, characterized in that Applied to the memory according to any one of claims 1-10, the method includes: Based on an address signal, selecting a plurality of local bit lines aligned along a third direction in a target memory array slice (S501); In the odd-numbered memory layer groups, controlling the selected local bit lines to be electrically connected to a first common bit line of the memory layer group to which they belong, and controlling the unselected local bit lines to be electrically connected to a second common bit line of the memory layer group to which they belong; and, in the even-numbered memory layer groups, controlling the selected local bit lines to be electrically connected to the second common bit line of the memory layer group to which they belong, and controlling the unselected local bit lines to be electrically connected to the first common bit line of the memory layer group to which they belong (S502).

12. The bit line control method according to claim 11, wherein The method further includes: Controlling the bit line selector of the selected local bit line to be in an on state, and the precharge switch of the selected local bit line to be in an off state, so that the selected local bit lines in the odd-numbered memory layers are electrically connected to the first common bit line, and the selected local bit lines in the even-numbered memory layers are electrically connected to the second common bit line; Controlling the bit line selector of the unselected local bit line to be in an off state, and the precharge switch of the unselected local bit line to be in an on state, so that the unselected local bit lines in the odd-numbered memory layers are electrically connected to the second common bit line, and the unselected local bit lines in the even-numbered memory layers are electrically connected to the first common bit line.

13. The bit line control method according to claim 11, wherein, The method further includes: For the odd-numbered storage layer groups, control the potential of the second common bit line to be the pre-charge potential; and, make the potential of the first common bit line be a low potential or a high potential through charge sharing and sense amplification processing; potential; For the even-numbered storage layer groups, control the potential of the first common bit line to be the pre-charge potential; and, make the potential of the second common bit line be a low potential or a high potential through charge sharing and sense amplification processing; wherein, the low potential < the pre-charge potential < the high level.

14. An electronic device, characterized in that, The electronic device includes the memory according to any one of claims 1-10.

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