Sequence processing method, and chip and optical module

Abstract

A sequence processing method, and a chip and an optical module, which belong to the technical field of communications. The sequence processing method comprises: after a plurality of intermediate bit sequences are acquired on the basis of an initial bit sequence and an expansion table, respectively performing distribution matching processing on the plurality of intermediate bit sequences, so as to obtain a plurality of target bit sequences, and combining the obtained target bit sequences, wherein the expansion table is used for indicating one-to-one correspondences between 2d first bit sequences and 2d second bit sequences, and the number of low-amplitude bits of each of the 2d second bit sequences is greater than or equal to the number of low-amplitude bits of each second bit sequence, other than the 2d second bit sequences, among 2h second bit sequences; and the number of low-amplitude bits of each second bit sequence is the number of bits, which are used for mapping to lowest-amplitude bits, among a plurality of target bit sequences corresponding to the second bit sequence. The present application solves the problem of a processing mode of a bit sequence being relatively limited, and the present application is used for sequence processing.

Description

Sequence processing method, chip and optical module

[0001] This application claims priority to Chinese patent application No. 202311864103.8 filed on December 29, 2023, entitled “Sequence processing method, chip and optical module”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of communication technology, and in particular to a sequence processing method, chip, and optical module. Background Art

[0003] In a communication system, a sending node and a receiving node can communicate with each other.

[0004] In related technologies, a sending node processes a bit sequence to be transmitted, modulates symbols based on the processed sequence, processes the modulated symbols again, and transmits them to a receiving node via a channel. The receiving node then performs the inverse of the processing performed by the sending node on the received symbols to recover the bit sequence.

[0005] However, in the related art, the sending node processes the bit sequence in a relatively simple manner. Summary of the Invention

[0006] The present application provides a sequence processing method, chip and optical module, which can solve the problem of the relatively single bit sequence processing method in related technologies.

[0007] In a first aspect, the present application provides a sequence processing method, which includes: obtaining multiple intermediate bit sequences based on an initial bit sequence and an expansion table, and then performing distribution matching processing on the multiple intermediate bit sequences respectively to obtain multiple target bit sequences; finally, merging the obtained target bit sequences.

[0008] The expansion table is used to indicate 2 d The first bit sequence and 2 d The first bit sequence is composed of first-category bit segments of multiple bit subsequences in the initial bit sequence, and the second bit sequence is composed of second-category bit segments of multiple intermediate bit sequences, wherein the second-category bit segments are multiple most significant bits of the intermediate bit sequences; d The number of low-amplitude bits of the second bit sequence is greater than or equal to 2 h The second bit sequence is divided by 2 dThe number of low-amplitude bits of a second bit sequence other than the second bit sequences; the number of low-amplitude bits of any second bit sequence is: the number of bits used for mapping to the lowest-amplitude bits in the multiple target bit sequences corresponding to any second bit sequence;

[0009] In the sequence processing method provided in the embodiments of this application, multiple intermediate bit sequences are first obtained based on the initial bit sequence and the expansion table. These intermediate bit sequences are then distributed and matched to obtain multiple target bit sequences. Finally, the obtained target bit sequences are combined. This sequence processing method differs from sequence processing methods in related arts and, therefore, enriches the sequence processing options.

[0010] Furthermore, the expansion table is used to indicate the one-to-one correspondence, 2 d The number of low-amplitude bits of the second bit sequence is greater than or equal to 2 h The second bit sequence is divided by the 2 d Therefore, the 2 in the one-to-one correspondence indicated in the above expansion table is d The number of low-amplitude bits in each of the second bit sequences is relatively large. Therefore, in the multiple target bit sequences obtained after the distribution matching process based on the multiple intermediate bit sequences obtained from the expansion table, the number of bits used to map to the lowest amplitude bit in each target bit sequence is relatively large. Generally, the larger the number of bits used to map to the lowest amplitude bit in the target bit sequence, the better the signal transmission effect. Since the number of bits used to map to the lowest amplitude bit in the multiple target bit sequences obtained by the distribution matching process is relatively large, the signal transmission effect in this application is relatively good. In addition, the sequence processing flow of the scheme provided by this application is relatively simple, and the implementation complexity is relatively low.

[0011] Optionally, 2 d The minimum number of low-amplitude bits in the second bit sequence is u+1,2 h The second bit sequence is divided by 2 d The maximum value of the number of low-amplitude bits of the second bit sequence other than the second bit sequences is u, where u≥0.

[0012] For example, the middle bit sequence includes 11 bits, and the second bit sequence includes: a first consecutive second type bit segment and a second second type bit segment; d The second bit sequence includes:

[0013] a second bit sequence in which the first second-category bit segment is (0, 0, 0) and the second second-category bit segment is (0, 0, 0);

[0014] a second bit sequence in which the first second-type bit segment is (0, 0, 0) and the second second-type bit segment is (1, 0, 0);

[0015] a second bit sequence in which the first second-type bit segment is (1, 0, 0) and the second second-type bit segment is (0, 0, 0);

[0016] a second bit sequence in which the first second-type bit segment is (0, 0, 0) and the second second-type bit segment is (0, 1, 0);

[0017] a second bit sequence in which the first second-category bit segment is (0, 1, 0) and the second second-category bit segment is (0, 0, 0);

[0018] a second bit sequence in which the first second-type bit segment is (1, 1, 0) and the second second-type bit segment is (0, 0, 0);

[0019] a second bit sequence in which the first second-type bit segment is (0, 0, 0) and the second second-type bit segment is (1, 1, 0);

[0020] a second bit sequence in which the first second-type bit segment is (1, 0, 0) and the second second-type bit segment is (1, 0, 0);

[0021] a second bit sequence in which the first second-type bit segment is (0, 0, 0) and the second second-type bit segment is (0, 0, 1);

[0022] a second bit sequence in which the first second-type bit segment is (0, 0, 1) and the second second-type bit segment is (0, 0, 0);

[0023] a second bit sequence in which the first second-type bit segment is (0, 1, 0) and the second second-type bit segment is (1, 0, 0);

[0024] a second bit sequence in which the first second-type bit segment is (1, 0, 0) and the second second-type bit segment is (0, 1, 0);

[0025] a second bit sequence in which the first second-type bit segment is (1, 0, 1) and the second second-type bit segment is (0, 0, 0);

[0026] a second bit sequence in which the first second-type bit segment is (0, 0, 0) and the second second-type bit segment is (1, 0, 1);

[0027] a second bit sequence in which the first second-type bit segment is (1, 1, 0) and the second second-type bit segment is (1, 0, 0);

[0028] a second bit sequence in which the first second-type bit segment is (1, 0, 0) and the second second-type bit segment is (1, 1, 0);

[0029] In the various second-category bit segments provided in this application, the bits in the second-category bit segments are arranged from left to right in the order of bit positions from low to high or from high to low. In each second-category bit segment, the bit position of the w-th bit from left to right is higher or lower than the bit position of the w+1-th bit, and w≥1. In addition, assuming that the second-category bit segment includes y bits, then the y bits in the second-category bit segment are also the y bits with the highest bit in the intermediate bit sequence including the second-category bit segment; and, the highest bit in each second-category bit segment is also the bit with the highest bit position in the intermediate bit sequence including the second-category bit segment. Subsequent examples of second-category bits also meet the above conditions, and this application will not repeat them.

[0030] Optionally, 2 d The minimum value of the number of low-amplitude bits in the second bit sequence is u,2 h The second bit sequence is divided by 2 d The maximum number of low-amplitude bits of the second bit sequence other than the second bit sequence is u, u≥0; 2 d The second bit sequence includes: 2 h v second bit sequences with a low amplitude bit number greater than u in the second bit sequences, and any 2 of the multiple second bit sequences with a low amplitude bit number u d -v second bit sequences, v ≥ 1.

[0031] For example, the middle bit sequence includes 10 bits, and the second bit sequence includes: a first consecutive second type bit segment and a second second type bit segment, 2 d The second bit sequence includes:

[0032] a second bit sequence in which the first second-category bit segment is (0, 0, 0) and the second second-category bit segment is (0, 0, 0);

[0033] a second bit sequence in which the first second-type bit segment is (0, 0, 0) and the second second-type bit segment is (1, 0, 0);

[0034] a second bit sequence in which the first second-type bit segment is (1, 0, 0) and the second second-type bit segment is (0, 0, 0);

[0035] a second bit sequence in which the first second-type bit segment is (0, 0, 0) and the second second-type bit segment is (0, 1, 0);

[0036] a second bit sequence in which the first second-category bit segment is (0, 1, 0) and the second second-category bit segment is (0, 0, 0);

[0037] a second bit sequence in which the first second-type bit segment is (1, 0, 0) and the second second-type bit segment is (1, 0, 0);

[0038] a second bit sequence in which the first second-type bit segment is (0, 0, 0) and the second second-type bit segment is (1, 1, 0);

[0039] a second bit sequence in which the first second-type bit segment is (1, 1, 0) and the second second-type bit segment is (0, 0, 0);

[0040] a second bit sequence in which the first second-type bit segment is (0, 0, 0) and the second second-type bit segment is (0, 0, 1);

[0041] a second bit sequence in which the first second-type bit segment is (0, 0, 1) and the second second-type bit segment is (0, 0, 0);

[0042] a second bit sequence in which the first second-type bit segment is (0, 1, 0) and the second second-type bit segment is (1, 0, 0);

[0043] a second bit sequence in which the first second-type bit segment is (1, 0, 0) and the second second-type bit segment is (0, 1, 0);

[0044] a second bit sequence in which the first second-type bit segment is (0, 1, 0) and the second second-type bit segment is (0, 1, 0);

[0045] a second bit sequence in which the first second-type bit segment is (1, 0, 1) and the second second-type bit segment is (0, 0, 0);

[0046] a second bit sequence in which the first second-type bit segment is (0, 0, 0) and the second second-type bit segment is (1, 0, 1);

[0047] And, any one of the following second bit sequences:

[0048] a second bit sequence in which the first second-type bit segment is (1, 1, 0) and the second second-type bit segment is (1, 0, 0);

[0049] a second bit sequence in which the first second-type bit segment is (1, 0, 0) and the second second-type bit segment is (1, 1, 0);

[0050] The bits in the second type of bit segment are arranged from left to right in the order of low to high or high to low.

[0051] For another example, the middle bit sequence includes 10 bits, and the second bit sequence includes: a first consecutive second type bit segment and a second second type bit segment, 2 d The second bit sequence includes:

[0052] a second bit sequence in which the first second-category bit segment is (0, 0, 0, 0) and the second second-category bit segment is (0, 0, 0, 0);

[0053] a second bit sequence in which the first second-type bit segment is (0, 0, 0, 0) and the second second-type bit segment is (1, 0, 0, 0);

[0054] a second bit sequence in which the first second-category bit segment is (1, 0, 0, 0) and the second second-category bit segment is (0, 0, 0, 0);

[0055] a second bit sequence in which the first second-type bit segment is (0, 0, 0, 0) and the second second-type bit segment is (0, 1, 0, 0);

[0056] a second bit sequence in which the first second-category bit segment is (0, 1, 0, 0) and the second second-category bit segment is (0, 0, 0, 0);

[0057] a second bit sequence in which the first second-category bit segment is (0, 0, 0, 0) and the second second-category bit segment is (1, 1, 0, 0);

[0058] a second bit sequence in which the first second-category bit segment is (0, 0, 0, 0) and the second second-category bit segment is (0, 0, 1, 0);

[0059] a second bit sequence in which the first second-category bit segment is (0, 0, 0, 0) and the second second-category bit segment is (1, 0, 1, 0);

[0060] a second bit sequence in which the first second-category bit segment is (1, 1, 0, 0) and the second second-category bit segment is (0, 0, 0, 0);

[0061] a second bit sequence in which the first second-category bit segment is (1, 0, 1, 0) and the second second-category bit segment is (0, 0, 0, 0);

[0062] a second bit sequence in which the first second-category bit segment is (0, 0, 1, 0) and the second second-category bit segment is (0, 0, 0, 0);

[0063] a second bit sequence in which the first second-type bit segment is (1, 0, 0, 0) and the second second-type bit segment is (1, 0, 0, 0);

[0064] a second bit sequence in which the first second-type bit segment is (0, 1, 0, 0) and the second second-type bit segment is (1, 0, 0, 0);

[0065] a second bit sequence in which the first second-type bit segment is (1, 0, 0, 0) and the second second-type bit segment is (0, 1, 0, 0);

[0066] a second bit sequence in which the first second-type bit segment is (0, 1, 0, 0) and the second second-type bit segment is (0, 1, 0, 0);

[0067] And, any one of the following second bit sequences:

[0068] a second bit sequence in which the first second-category bit segment is (0, 0, 0, 0) and the second second-category bit segment is (0, 1, 1, 0);

[0069] a second bit sequence in which the first second-category bit segment is (0, 1, 1, 0) and the second second-category bit segment is (0, 0, 0, 0);

[0070] The bits in the second type of bit segment are arranged from left to right in the order of low to high or high to low.

[0071] For another example, the middle bit sequence includes 11 bits, and the second bit sequence includes: a first consecutive second type bit segment and a second second type bit segment, 2 d The second bit sequence includes:

[0072] a second bit sequence in which the first second-category bit segment is (0, 0, 0, 0) and the second second-category bit segment is (0, 0, 0, 0);

[0073] a second bit sequence in which the first second-type bit segment is (0, 0, 0, 0) and the second second-type bit segment is (1, 0, 0, 0);

[0074] a second bit sequence in which the first second-category bit segment is (1, 0, 0, 0) and the second second-category bit segment is (0, 0, 0, 0);

[0075] a second bit sequence in which the first second-category bit segment is (0, 1, 0, 0) and the second second-category bit segment is (0, 0, 0, 0);

[0076] a second bit sequence in which the first second-type bit segment is (1, 0, 0, 0) and the second second-type bit segment is (1, 0, 0, 0);

[0077] a second bit sequence in which the first second-category bit segment is (1, 1, 0, 0) and the second second-category bit segment is (0, 0, 0, 0);

[0078] a second bit sequence in which the first second-category bit segment is (0, 0, 0, 0) and the second second-category bit segment is (0, 1, 0, 0);

[0079] a second bit sequence in which the first second-category bit segment is (0, 0, 0, 0) and the second second-category bit segment is (1, 1, 0, 0);

[0080] a second bit sequence in which the first second-category bit segment is (0, 0, 0, 0) and the second second-category bit segment is (0, 0, 1, 0);

[0081] a second bit sequence in which the first second-category bit segment is (0, 0, 1, 0) and the second second-category bit segment is (0, 0, 0, 0);

[0082] a second bit sequence in which the first second-type bit segment is (1, 0, 0, 0) and the second second-type bit segment is (1, 1, 0, 0);

[0083] a second bit sequence in which the first second-type bit segment is (1, 0, 0, 0) and the second second-type bit segment is (0, 1, 0, 0);

[0084] a second bit sequence in which the first second-type bit segment is (0, 1, 0, 0) and the second second-type bit segment is (1, 0, 0, 0);

[0085] a second bit sequence in which the first second-category bit segment is (1, 1, 0, 0) and the second second-category bit segment is (1, 0, 0, 0);

[0086] And, any two second bit sequences among the following second bit sequences:

[0087] a second bit sequence in which the first second-category bit segment is (0, 0, 0, 0) and the second second-category bit segment is (0, 1, 1, 0);

[0088] a second bit sequence in which the first second-category bit segment is (0, 0, 0, 0) and the second second-category bit segment is (1, 0, 1, 0);

[0089] a second bit sequence in which the first second-category bit segment is (1, 0, 1, 0) and the second second-category bit segment is (0, 0, 0, 0);

[0090] a second bit sequence in which the first second-category bit segment is (1, 1, 1, 0) and the second second-category bit segment is (0, 0, 0, 0);

[0091] a second bit sequence in which the first second-category bit segment is (0, 0, 0, 0) and the second second-category bit segment is (1, 1, 1, 0);

[0092] a second bit sequence in which the first second-category bit segment is (0, 1, 1, 0) and the second second-category bit segment is (0, 0, 0, 0);

[0093] The bits in the second type of bit segment are arranged from left to right in the order of low to high or high to low.

[0094] For another example, the middle bit sequence includes 10 bits, and the second bit sequence includes: a first consecutive second type bit segment and a second second type bit segment, 2 d The second bit sequence includes:

[0095] a second bit sequence in which the first second-category bit segment is (0, 0, 0, 0, 0), and the second second-category bit segment is (0, 0, 0, 0, 0);

[0096] a second bit sequence in which the first second-category bit segment is (0, 0, 0, 0, 0), and the second second-category bit segment is (1, 0, 0, 0, 0, 0);

[0097] a second bit sequence in which the first second-category bit segment is (0, 0, 0, 0, 0), and the second second-category bit segment is (0, 1, 0, 0, 0, 0);

[0098] a second bit sequence in which the first second-category bit segment is (1, 0, 0, 0, 0, 0) and the second second-category bit segment is (0, 0, 0, 0, 0, 0);

[0099] a second bit sequence in which the first second-category bit segment is (0, 1, 0, 0, 0, 0) and the second second-category bit segment is (0, 0, 0, 0, 0, 0);

[0100] a second bit sequence in which the first second-category bit segment is (0, 0, 0, 0, 0), and the second second-category bit segment is (1, 1, 0, 0, 0, 0);

[0101] a second bit sequence in which the first second-category bit segment is (1, 1, 0, 0, 0, 0) and the second second-category bit segment is (0, 0, 0, 0, 0, 0);

[0102] a second bit sequence in which the first second-category bit segment is (0, 1, 0, 0, 0, 0) and the second second-category bit segment is (0, 1, 0, 0, 0, 0);

[0103] a second bit sequence in which the first second-category bit segment is (0, 1, 0, 0, 0, 0) and the second second-category bit segment is (1, 0, 0, 0, 0, 0);

[0104] a second bit sequence in which the first second-category bit segment is (1, 0, 0, 0, 0, 0) and the second second-category bit segment is (1, 0, 0, 0, 0, 0);

[0105] a second bit sequence in which the first second-category bit segment is (1, 0, 0, 0, 0), and the second second-category bit segment is (0, 1, 0, 0, 0, 0);

[0106] And, any five second bit sequences among the following second bit sequences:

[0107] a second bit sequence in which the first second-category bit segment is (0, 0, 1, 0, 0, 0) and the second second-category bit segment is (0, 0, 0, 0, 0, 0);

[0108] a second bit sequence in which the first second-category bit segment is (1, 0, 1, 0, 0, 0) and the second second-category bit segment is (0, 0, 0, 0, 0, 0);

[0109] a second bit sequence in which the first second-category bit segment is (0, 1, 1, 0, 0, 0) and the second second-category bit segment is (0, 0, 0, 0, 0, 0);

[0110] a second bit sequence in which the first second-category bit segment is (0, 0, 0, 1, 0, 0) and the second second-category bit segment is (0, 0, 0, 0, 0, 0);

[0111] a second bit sequence in which the first second-category bit segment is (1, 0, 0, 1, 0, 0) and the second second-category bit segment is (0, 0, 0, 0, 0, 0);

[0112] a second bit sequence in which the first second-category bit segment is (0, 1, 0, 1, 0, 0) and the second second-category bit segment is (0, 0, 0, 0, 0, 0);

[0113] a second bit sequence in which the first second-category bit segment is (1, 1, 1, 0, 0, 0) and the second second-category bit segment is (0, 0, 0, 0, 0, 0);

[0114] a second bit sequence in which the first second-category bit segment is (0, 0, 0, 0, 0), and the second second-category bit segment is (0, 0, 0, 1, 0, 0);

[0115] a second bit sequence in which the first second-category bit segment is (0, 0, 0, 0, 0), and the second second-category bit segment is (0, 0, 1, 0, 0, 0);

[0116] a second bit sequence in which the first second-category bit segment is (0, 0, 0, 0, 0), and the second second-category bit segment is (1, 0, 1, 0, 0, 0);

[0117] a second bit sequence in which the first second-category bit segment is (0, 0, 0, 0, 0), and the second second-category bit segment is (0, 1, 1, 0, 0, 0);

[0118] a second bit sequence in which the first second-category bit segment is (0, 0, 0, 0, 0), and the second second-category bit segment is (1, 0, 0, 1, 0, 0);

[0119] a second bit sequence in which the first second-category bit segment is (0, 0, 0, 0, 0), and the second second-category bit segment is (1, 1, 1, 0, 0, 0);

[0120] a second bit sequence in which the first second-category bit segment is (0, 0, 0, 0, 0), and the second second-category bit segment is (0, 1, 0, 1, 0, 0);

[0121] The bits in the second type of bit segment are arranged from left to right in the order of low to high or high to low.

[0122] For another example, the middle bit sequence includes 11 bits, and the second bit sequence includes: a first consecutive second type bit segment and a second second type bit segment, 2 d The second bit sequence includes:

[0123] a second bit sequence in which the first second-category bit segment is (0, 0, 0, 0, 0, 0), and the second second-category bit segment is (0, 0, 0, 0, 0, 0);

[0124] a second bit sequence in which the first second-category bit segment is (0, 1, 0, 0, 0, 0, 0) and the second second-category bit segment is (0, 0, 0, 0, 0, 0, 0);

[0125] a second bit sequence in which the first second-category bit segment is (1, 1, 0, 0, 0, 0, 0) and the second second-category bit segment is (0, 0, 0, 0, 0, 0, 0);

[0126] a second bit sequence in which the first second-category bit segment is (1, 0, 0, 0, 0, 0), and the second second-category bit segment is (0, 0, 0, 0, 0, 0);

[0127] a second bit sequence in which the first second-category bit segment is (0, 0, 0, 0, 0, 0), and the second second-category bit segment is (1, 0, 0, 0, 0, 0);

[0128] a second bit sequence in which the first second-category bit segment is (0, 0, 0, 0, 0, 0), and the second second-category bit segment is (0, 1, 0, 0, 0, 0, 0);

[0129] a second bit sequence in which the first second-category bit segment is (0, 0, 0, 0, 0, 0), and the second second-category bit segment is (1, 1, 0, 0, 0, 0, 0);

[0130] And, any nine second bit sequences among the following second bit sequences:

[0131] a second bit sequence in which the first second-category bit segment is (0, 0, 0, 0, 0, 0), and the second second-category bit segment is (0, 0, 1, 0, 0, 0, 0);

[0132] a second bit sequence in which the first second-category bit segment is (1, 0, 0, 0, 0, 0), and the second second-category bit segment is (0, 1, 0, 0, 0, 0, 0);

[0133] a second bit sequence in which the first second-category bit segment is (1, 0, 0, 0, 0, 0), and the second second-category bit segment is (1, 1, 0, 0, 0, 0, 0);

[0134] a second bit sequence in which the first second-category bit segment is (0, 1, 0, 0, 0, 0, 0) and the second second-category bit segment is (1, 0, 0, 0, 0, 0, 0);

[0135] a second bit sequence in which the first second-category bit segment is (0, 1, 0, 0, 0, 0, 0) and the second second-category bit segment is (0, 1, 0, 0, 0, 0, 0);

[0136] a second bit sequence in which the first second-category bit segment is (0, 1, 0, 0, 0, 0, 0) and the second second-category bit segment is (1, 1, 0, 0, 0, 0, 0);

[0137] a second bit sequence in which the first second-category bit segment is (1, 1, 0, 0, 0, 0, 0) and the second second-category bit segment is (1, 0, 0, 0, 0, 0, 0);

[0138] a second bit sequence in which the first second-category bit segment is (1, 1, 0, 0, 0, 0, 0) and the second second-category bit segment is (0, 1, 0, 0, 0, 0, 0);

[0139] a second bit sequence in which the first second-category bit segment is (1, 1, 0, 0, 0, 0, 0) and the second second-category bit segment is (1, 1, 0, 0, 0, 0, 0);

[0140] a second bit sequence in which the first second-category bit segment is (1, 0, 0, 0, 0, 0), and the second second-category bit segment is (1, 0, 0, 0, 0, 0);

[0141] a second bit sequence in which the first second-category bit segment is (0, 0, 1, 0, 0, 0, 0) and the second second-category bit segment is (0, 0, 0, 0, 0, 0, 0);

[0142] The bits in the second type of bit segment are arranged from left to right in the order of low to high or high to low.

[0143] In a second aspect, the present application provides a sequence processing method, which includes: splitting a plurality of target bit sequences from a bit sequence; performing an inverse process of the distribution matching process on the plurality of target bit sequences to obtain a plurality of intermediate bit sequences; and obtaining an initial bit sequence based on the plurality of intermediate bit sequences and an expansion table. The expansion table is used to indicate 2 d The first bit sequence and 2 d The first bit sequence is composed of first-category bit segments of multiple bit subsequences in the initial bit sequence, and the second bit sequence is composed of second-category bit segments of multiple intermediate bit sequences, wherein the second-category bit segments are multiple most significant bits of the intermediate bit sequences; d The number of low-amplitude bits of the second bit sequence is greater than or equal to 2 h The second bit sequence is divided by 2 d The number of low-amplitude bits of any second bit sequence is: the number of bits used to map to the lowest-amplitude bit in multiple target bit sequences corresponding to any second bit sequence.

[0144] In a third aspect, the present application provides a chip, which includes a processor and an interface. The processor is used to run any one of the sequence processing methods provided in the first aspect to process a bit sequence. The processor is also used to obtain a data frame based on the bit sequence obtained by processing the bit sequence, and the interface is used to output the data frame.

[0145] In a fourth aspect, the present application provides a chip, which includes a processor and an interface, the interface being used to receive a data frame, the processor being used to obtain a bit sequence based on the data frame, and to run the method performed by the second sequence processing device provided in an embodiment of the present application to process the obtained bit sequence.

[0146] In a fifth aspect, an embodiment of the present application also provides an optical module, which includes an optical transceiver and a chip, wherein the chip is used to run the method described in any design of the first aspect to process a bit sequence, and the chip is also used to obtain a first data frame based on the bit sequence processed by running the method described in any design of the first aspect, and the optical transceiver is used to transmit a first optical signal based on the first data frame; the optical transceiver is used to obtain a second data frame based on a received second optical signal, and the chip is used to obtain a bit sequence based on the second data frame, and run the method described in any design of the second aspect to process the bit sequence obtained based on the second data frame.

[0147] The effects of the second to fifth aspects mentioned above can refer to the effects of the corresponding designs in the first aspect, and this application will not go into details here. BRIEF DESCRIPTION OF THE DRAWINGS

[0148] FIG1 is a schematic diagram of a communication system provided in an embodiment of the present application;

[0149] FIG2 is a schematic structural diagram of a first sequence processing module in FIG1 provided in an embodiment of the present application;

[0150] FIG3 is a flow chart of a sequence processing method provided in an embodiment of the present application;

[0151] FIG4 is a schematic diagram showing the relationship between a to-be-processed bit sequence and an initial bit sequence provided in an embodiment of the present application;

[0152] FIG5 is a schematic diagram showing the relationship between another to-be-processed bit sequence and the initial bit sequence provided in an embodiment of the present application;

[0153] FIG6 is a schematic diagram of Example 1 provided in an embodiment of the present application;

[0154] FIG7 is a schematic diagram of Example 2 provided in an embodiment of the present application;

[0155] FIG8 is a schematic diagram of Example 3 provided in an embodiment of the present application;

[0156] FIG9 is a schematic diagram of Example 4 provided in an embodiment of the present application;

[0157] FIG10 is a schematic diagram of Example 5 provided in an embodiment of the present application;

[0158] FIG11 is a schematic diagram of Example 6 provided in an embodiment of the present application;

[0159] FIG12 is a schematic structural diagram of a sequence processing device provided in an embodiment of the present application;

[0160] FIG13 is a schematic structural diagram of another sequence processing device provided in an embodiment of the present application;

[0161] FIG14 is a schematic diagram of a chip provided in an embodiment of the present application;

[0162] FIG15 is a schematic diagram of an optical module provided in an embodiment of the present application. DETAILED DESCRIPTION

[0163] In order to make the principles and technical solutions of the present application clearer, the implementation methods of the present application will be further described in detail below with reference to the accompanying drawings.

[0164] The present application provides a communication system, which may be an optical communication system such as a metropolitan area telecommunication transmission system, a metropolitan area data center interconnection (DCI) system, or the like.

[0165] As shown in Figure 1, the communication system includes a sending node 01 and a receiving node 02, and a communication connection is established between the sending node 01 and the receiving node 02 via a channel 03. The sending node 01 and the receiving node 02 can both be communication devices (such as routers, optical transmission devices (such as optical line terminals (OLTs), optical network devices (ONTs), etc.)), or can be part of a communication device, such as a chip in the communication device (such as an optical signal digital signal processing (ODSP) chip), an optical module (which can be a pluggable optical module, a non-pluggable optical module, or a coherent communication optical module), etc.

[0166] Channel 03 may be a wired channel, such as an optical fiber.

[0167] For example, consider a scenario where both transmitting node 01 and receiving node 02 are optical modules in a communications device. Transmitting node 01 can send signals to receiving node 02 via channel 03, enabling communication between the two devices. For example, transmitting node 01 can perform transmission processing on a bit sequence to obtain a data frame, and then transmit an optical signal based on this data frame to channel 03. Receiving node 02 can receive the optical signal sent by transmitting node 01 on channel 03, recover the data frame from this optical signal, and then perform reception processing on this data frame to obtain a bit sequence. This reception process is the inverse of the transmission process.

[0168] Continuing with Figure 1, transmitting node 01 includes: information source 011, first sequence processing module 012, first signal processing module 013, and optical transmitter 014. Information source 011, first sequence processing module 012, first signal processing module 013, optical transmitter 014, and channel 03 are sequentially connected. Information source 011 is configured to provide a bit sequence to first sequence processing module 012. This bit sequence includes multiple bits, which can be 0 or 1, and the values ​​of different bits in the bit sequence can be the same or different. First sequence processing module 012 can perform sequence processing (including encoding and modulation) on the bit sequence to obtain multiple symbols and transmit these multiple symbols to first signal processing module 013. First signal processing module 013 can frame these multiple symbols to obtain data frames. Optical transmitter 014 is configured to transmit an optical signal to channel 03 based on the data frame, so that the optical signal can be transmitted to receiving node 02 via channel 03.

[0169] Receiving node 02 includes: a destination 021, a second sequence processing module 022, a second signal processing module 023, and an optical receiver 024. Destination 021, second sequence processing module 022, second signal processing module 023, optical receiver 024, and channel 03 are sequentially connected. Optical receiver 024 can receive the optical signal transmitted by transmitting node 01 on channel 03 and recover the data frame from the optical signal. Second signal processing module 023 can perform operations such as dispersion compensation, synchronization, and phase recovery on the data frame, then perform the inverse of the framing process to obtain multiple symbols, which are then transmitted to second sequence processing module 022. Second sequence processing module 022 can perform the inverse of the sequence processing (including decoding and demodulation) on the multiple symbols to obtain a bit sequence, which is then transmitted to destination 021.

[0170] It is understandable that the sending node 01 can also have the function of the receiving node 02, so the sending node 01 can also serve as a receiving node; the receiving node 02 can also have the function of the sending node 01, so the receiving node 02 can also serve as a sending node, and this application does not limit this. When a node has the functions of both a sending node and a receiving node, the node includes the signal source 011, the first sequence processing module 012, the first signal processing module 013, the optical transmitter 014, the signal destination 021, the second sequence processing module 022, the second signal processing module 023 and the optical receiver 024 in Figure 1, and the optical transmitter 014 and the optical receiver 024 can be integrated into an optical transceiver. The signal source 011, the first sequence processing module 012, the first signal processing module 013, the signal destination 021, the second sequence processing module 022, and the second signal processing module 023 can be integrated into a chip.

[0171] Furthermore, probabilistic constellation shaping (PCS) technology is introduced into the transmitting node. For example, before the first signal processing module 013 processes the sequence to obtain symbols, the first signal processing module 013 first performs PCS processing on the sequence, and then processes the sequence obtained by PCS processing to obtain symbols. PCS technology can change the probability of occurrence of constellation point symbols (constellation point symbols are referred to as symbols) while maintaining the position of constellation point symbols (constellation point symbols are referred to as symbols) on the signal constellation diagram. This makes the probability of occurrence of each constellation point symbol non-uniformly distributed, thereby reducing the probability of occurrence of symbols with higher amplitude bits, improving signal transmission effect, enhancing the transmission performance of the communication system, and achieving a higher baud rate or longer transmission distance. By performing statistics on multiple groups of bit sequences (each group of bit sequences includes bit sequences before and after PCS processing, and the bit sequences before PCS processing are different in different groups of bit sequences), it can be found that: when the bit sequence before PCS processing is an equal-probability bit sequence (the probability of each bit in the bit sequence being 0 bit and 1 bit is approximately equal), the bit sequence after PCS processing is an unequal-probability bit sequence (the probability of each bit in the bit sequence being 0 bit and 1 bit is unequal).

[0172] For example, the structure of the first sequence processing module in the transmitting node can be shown in Figure 2. Referring to Figure 2, the first sequence processing module 012 includes a PCS processing module 0121, a forward error correction (FEC) encoding module 0122, and a symbol mapping module 0123. The PCS processing module 0121 can perform PCS processing on a bit sequence comprising k bits in a bit sequence provided by a signal source, thereby obtaining a bit sequence comprising N bits, where 1 < k < N. The FEC encoding module 0122 can perform FEC encoding on the bit sequence comprising N bits output by the PCS processing module 0121, as well as on the remaining bit sequences in the bit sequence provided by the signal source, excluding the bit sequence processed by the PCS processing module 0121, and transmit the bit sequence obtained by the FEC encoding to the symbol mapping module 0123. The symbol mapping module 0123 can modulate symbols based on the bit sequence obtained by the FEC encoding and output the modulated symbols. The bits in the bit sequence obtained by the PCS processing are mapped to the amplitude bits of the symbol by the symbol mapping module 0123. In an embodiment of the present application, a symbol has two amplitude bits, a high amplitude bit (referred to as the highest amplitude bit) and a low amplitude bit (referred to as the lowest amplitude bit), and the amplitude of the highest amplitude bit is higher than the amplitude of the lowest amplitude bit. For example, in the present application, it is taken that the 0 bit in the bit sequence will be mapped to a higher amplitude bit by the symbol mapping module 0123, and the 1 bit in the bit sequence will be mapped to a lower amplitude bit by the symbol mapping module 0123 as an example. Alternatively, it is also possible that the 1 bit in the bit sequence will be mapped to a higher amplitude bit, and the 0 bit in the bit sequence will be mapped to a lower amplitude bit. In general, the first bit is used to map to the first amplitude bit, and the second bit is used to map to the second amplitude bit, the first amplitude bit is higher than the second amplitude bit, the first bit is 0 bit and the second bit is 1 bit, or the first bit is 1 bit and the second bit is 0 bit.

[0173] It can be understood that, since the receiving process performed by the receiving node and the sending process performed by the sending node are inverse processes to each other, the second sequence processing module in the receiving node is configured to perform a process including an inverse process of the PCS process.

[0174] It can be seen that the method of processing the sequence by the sending node in the related art is relatively simple.

[0175] Based on this, embodiments of the present application provide a sequence processing method that processes bit sequences differently from methods provided in related arts, thereby enriching the bit sequence processing methods. Furthermore, the sequence processing method can process bit sequences to obtain unequally probable bit sequences containing a greater number of bits (e.g., 0 or 1) for mapping to the lowest amplitude bit.

[0176] The sequence processing method provided in the embodiment of the present application is performed by the sequence processing device in the above-mentioned sending node (referred to as the first sequence processing device) and the sequence processing device in the receiving node (referred to as the second sequence processing device). The first sequence processing device can be a sending node, or the first sequence processing device is a first sequence processing module or other modules such as a PCS processing module in the sending node; the second sequence processing device can be a receiving node, or the second sequence processing device is a second sequence processing module or other modules in the receiving node. For example, Figure 3 is a flowchart of a sequence processing method provided in an embodiment of the present application. As shown in Figure 3, the sequence processing method includes:

[0177] S101, the first sequence processing device obtains multiple intermediate bit sequences according to the initial bit sequence and the expansion table. d The first bit sequence and 2 d The first bit sequence is composed of first-category bit segments of a plurality of bit subsequences in the initial bit sequence, and the second bit sequence is composed of second-category bit segments of the plurality of intermediate bit sequences, wherein the second-category bit segments are the most significant bits of the intermediate bit sequences.

[0178] The initial bit sequence includes multiple bit subsequences. The initial bit sequence may be composed of bits in the multiple bit subsequences, or may be composed of bits in the multiple bit subsequences and other bits. The order of bits in the bit subsequences may be consistent with or inconsistent with the order of bits in the initial bit sequence. Optionally, the number of bits in the multiple bit subsequences may be the same or different. When the number of bits in the multiple bit subsequences is the same, the number of bits in these bit subsequences may all be values ​​such as 6, 7, 8, 9, or 10, which is not limited in the embodiments of the present application.

[0179] In S101 , the first sequence processing device obtains a plurality of intermediate bit sequences according to the initial bit sequence and the extended table.

[0180] The extension table is also called the correspondence table, decision table, decision extension table, mapping table, etc.

[0181] For example, the expansion table is used to indicate 2 d The first bit sequence and 2 d In a one-to-one correspondence between the first bit sequence and the second bit sequence, the first bit sequence includes multiple first-type bit segments, and the first bit sequence includes d bits in total; the second bit sequence includes multiple second-type bit segments, and the number of bits in the second bit sequence is h; the initial bit sequence includes multiple bit subsequences, and the i-th bit subsequence in the multiple bit subsequences includes: 2 dthe i-th first-category bit segment in the target first bit sequence in the first bit sequences, 1≥1; the multiple highest bits of the j-th intermediate bit sequence in the multiple intermediate bit sequences are: the j-th second-category bit segment in the target second bit sequence corresponding to the target first bit sequence, j≥1.

[0182] For example, taking d=2 as an example, 2 d The first bit sequence and 2 d The one-to-one correspondence between the second bit sequences can be shown in Table 1 below. The correspondence includes: a correspondence between the first bit sequence 1 and a second bit sequence (including second-type bit segments 2.1, 3.1, and 4.1); a correspondence between the first bit sequence 2 and another second bit sequence (including second-type bit segments 2.2, 3.2, and 4.2); a correspondence between the first bit sequence 3 and yet another second bit sequence (including second-type bit segments 2.3, 3.3, and 4.3); and a correspondence between the first bit sequence 4 and yet another second bit sequence (including second-type bit segments 2.4, 3.4, and 4.4). In S101, the first sequence processing device can first obtain a to-be-searched bit sequence based on the first-type bit segments in the plurality of bit subsequences. The to-be-searched bit sequence includes the first-type bit segments in the plurality of bit subsequences. The first sequence processing device then searches for the target bit sequence within the multiple first bit sequences until it finds a target first bit sequence that is identical to the target bit sequence. The first sequence processing device then further locates a target second bit sequence corresponding to the target first bit sequence. Based on the one-to-one correspondence between the multiple second-category bit segments in the target second bit sequence and the multiple intermediate bit sequences, the first sequence processing device uses each second-category bit segment in the target bit sequence group as a second-category bit segment in the corresponding intermediate bit sequence. Thus, the first sequence processing device can obtain the second-category bit segments in the multiple intermediate bit sequences.

[0183] Table 1

[0184] Furthermore, 2 d The first bit sequence and 2 dIn the one-to-one correspondence between the first and second bit sequences, the first bit sequence can also be represented by multiple first-category bit segments in the first bit sequence. The multiple first-category bit segments in the target first bit sequence correspond one-to-one to the first-category bit segments in the multiple bit subsequences, and the first-category bit segments in the target first bit sequence include the corresponding first-category bit segments. In this case, the correspondence shown in Table 1 can be shown as in Table 2. The first bit sequence 1 in Table 1 is represented by the first-category bit segment 1.1 and the first-category bit segment 1.2 in Table 2. The first bit sequence 2 in Table 1 is represented by the first-category bit segment 2.1 and the first-category bit segment 2.2 in Table 2. The first bit sequence 3 in Table 1 is represented by the first-category bit segment 3.1 and the first-category bit segment 3.2 in Table 2. The first bit sequence 4 in Table 1 is represented by the first-category bit segment 4.1 and the first-category bit segment 4.2 in Table 2.

[0185] Table 2

[0186] Optionally, the number of bits in the multiple intermediate bit sequences may be the same or different. When the number of bits in the multiple intermediate bit sequences is the same, the number of bits in the multiple intermediate bit sequences may all be 10 or 11, etc., which is not limited in this embodiment of the present application. Furthermore, the number of bit subsequences in the initial bit sequence and the number of bit sequences in the target bit sequence may be the same or different, which is not limited in this embodiment of the present application.

[0187] S102, the first sequence processing device performs distribution matching processing on the multiple intermediate bit sequences respectively to obtain multiple target bit sequences. The expansion table is used to indicate the one-to-one correspondence relationship, 2 d The number of low-amplitude bits of the second bit sequence is greater than or equal to 2 h The second bit sequence is divided by the 2 d The number of low-amplitude bits of any second bit sequence is: the number of bits used for mapping to the lowest-amplitude bit in multiple target bit sequences corresponding to the second bit sequence.

[0188] Multiple intermediate bit sequences correspond one-to-one to multiple target bit sequences. After obtaining the multiple intermediate bit sequences, the first sequence processing device can perform distribution matching processing on the multiple intermediate bit sequences respectively to obtain the target bit sequence corresponding to each intermediate bit sequence. Distribution matching (DM) processing is used to convert a bit sequence into a bit sequence with unequal probabilities. The intermediate bit sequences that need to be distributed matched can be bit sequences with equal probability or bit sequences with unequal probability. In the embodiment of the present application, the distribution matching processing is implemented as a lookup table (LUT) as an example. It can be understood that the distribution matching processing can also be implemented without using a lookup table, and the embodiment of the present application does not limit this.

[0189] When the distribution matching process is implemented in the form of a lookup table, multiple intermediate bit sequences each have their own corresponding table. The table includes a correspondence between multiple index bit sequences and multiple result bit sequences, and the number of bits (such as 0 bits) used to map to the lowest amplitude bit in the result bit sequence corresponding to the multiple index bit sequences is positively correlated with the value of the index bit sequence. The bit in the bit sequence can be 0 bit or 1 bit, and the value of the bit sequence refers to: the value of the binary number represented by the bit sequence. The first sequence processing device will search the table corresponding to each intermediate bit sequence according to the intermediate bit sequence, find the index bit sequence in the table that is the same as the intermediate bit sequence, and use the result bit sequence corresponding to the index bit sequence as the target bit sequence corresponding to the intermediate bit sequence.

[0190] In addition, the above-mentioned multiple index bit sequences are usually arranged in a certain order. Under this order, the second index bit sequence is obtained by changing the lowest bit of the first index bit sequence; the penultimate index bit sequence is obtained by changing the highest bit of the penultimate index bit sequence. When multiple index bit sequences are arranged in this order, the subsequent index bit sequences are obtained by changing one or more bits of the preceding index bit sequence, and the one or more bits initially include the lowest bit and gradually evolve to include the highest bit. Multiple index bit sequences include intermediate bit sequences, the lowest bit in the intermediate bit sequence is the lowest bit in the index bit sequence that is the same as the intermediate bit sequence, and the highest bit in the intermediate bit sequence is the highest bit in the index bit sequence that is the same as the intermediate bit sequence.

[0191] The distribution matching processes performed on different intermediate bit sequences can be the same or different. When the distribution matching processes are all implemented using a lookup table, the tables corresponding to different intermediate bit sequences can be the same or different, which is not limited in this embodiment of the present application.

[0192] Optionally, the sum of the number of bits in the multiple intermediate bit sequences is greater than the number of bits in the initial bit sequence, and the sum of the number of bits in the multiple target bit sequences is also greater than the number of bits in the initial bit sequence. Furthermore, the number of bits in the target bit sequence may be equal to the number of bits in the intermediate bit sequence corresponding to the target bit sequence. Of course, the number of bits in the target bit sequence may also be less than or greater than the number of bits in the intermediate bit sequence corresponding to the target bit sequence.

[0193] The expansion table is used to indicate a one-to-one correspondence in which the length of the bit in the second bit sequence is h, where h>d. d The second bit sequence is 2 h A part of the second bit sequence in the second bit sequence. d The second bit sequence can be in the 2 h The bit sequence selected from the second bit sequence. d The second bit sequence refers to the 2 in the one-to-one correspondence relationship indicated by the extended packet d A second bit sequence.

[0194] 2 h In the second bit sequences, each second bit sequence corresponds to multiple target bit sequences, and the multiple target bit sequences are obtained by respectively performing the above-mentioned distribution matching process on multiple intermediate bit sequences corresponding to the second bit sequence.

[0195] In one case, the multiple intermediate bit sequences are divided into multiple groups of intermediate bit sequences, each of which corresponds one-to-one to multiple second-category bit segments in the second bit sequence. Each second-category bit segment in the multiple second-category bit segments is the highest bit segment of each intermediate bit sequence in the corresponding group of intermediate bit sequences. Thus, each second-category bit segment corresponds to a group of intermediate bit sequences: each intermediate bit sequence whose highest bit segment is the second-category bit segment.

[0196] In another case, the multiple intermediate bit sequences correspond one-to-one to multiple second-category bit segments in the second bit sequence, and each second-category bit segment in the multiple second-category bit segments is the highest bit segment of the corresponding intermediate bit sequence. Thus, each second-category bit segment corresponds to an intermediate bit sequence where the highest bit segment is any intermediate bit sequence of the second-category bit segment.

[0197] Each second bit sequence has a number of low-amplitude bits, and the number of low-amplitude bits of each second bit sequence is: the number of bits used to map to the lowest amplitude bits in the multiple target bit sequences corresponding to the second bit sequence, that is, the sum of the numbers of bits used to map to the lowest amplitude bits in the multiple target bit sequences. Optionally, the number of low-amplitude bits of each second bit sequence may also be: the average number of bits used to map to the lowest amplitude bits in the multiple target bit sequences corresponding to the second bit sequence.

[0198] The second bit sequence has a total of h bits. In this application, each bit in the bit sequence has two values ​​(0 or 1). Therefore, the second bit sequence has a total of 2 values. h These values ​​are the above 2 h The second bit sequence. h 2 second bit sequences are selected d When the second bit sequence is h The number of low-amplitude bits of each second bit sequence in the second bit sequences is used to select the two sequences with the higher number of low-amplitude bits. d A second bit sequence. In this way, 2 d The number of low-amplitude bits of the second bit sequence is greater than or equal to 2 h The second bit sequence is divided by 2 d The number of low-amplitude bits of any second bit sequence other than the second bit sequences.

[0199] In 2 d The number of low-amplitude bits of the second bit sequence is greater than or equal to 2 h The second bit sequence is divided by 2 d When the number of low-amplitude bits of any second bit sequence other than the second bit sequence is 2 d The number of high-amplitude bits in the second bit sequence is less than or equal to 2 h The second bit sequence is divided by 2 d The number of high-amplitude bits of any second bit sequence other than the second bit sequences. The number of high-amplitude bits of each second bit sequence is: the number of bits used to map to the highest amplitude bit in the multiple target bit sequences corresponding to the second bit sequence, that is, the sum of the number of bits used to map to the highest amplitude bit in the multiple target bit sequences. Optionally, the number of high-amplitude bits of each second bit sequence may also be: the average value of the number of bits used to map to the highest amplitude bit in the multiple target bit sequences corresponding to the second bit sequence.

[0200] It can be seen that the 2 in the one-to-one correspondence indicated by the above expansion table dThe number of low-amplitude bits in each of the second bit sequences is relatively large. Therefore, in the multiple target bit sequences obtained after S102 from the multiple intermediate bit sequences obtained in S101 according to the extended table, the number of bits used to map to the lowest amplitude bit in each target bit sequence is relatively large. Generally, the larger the number of bits used to map to the lowest amplitude bit in the target bit sequence, the better the signal transmission effect. Since the multiple target bit sequences obtained in S102 have relatively large numbers of bits used to map to the lowest amplitude bit, the signal transmission effect in this application is relatively good.

[0201] S103: The first sequence processing device combines the obtained target bit sequence.

[0202] The first sequence processing device can merge the obtained target bit sequences in any order. Furthermore, when merging these target bit sequences, the first sequence processing device can combine these target bit sequences in order, or can also scatter the bits in these target bit sequences. The bit order in the target bit sequences and the bit order in the merged bit sequences can be the same or different, and this embodiment of the application does not limit this.

[0203] S104: The first sequence processing device transmits the bit sequence obtained by combining the target bit sequence to the second sequence processing device.

[0204] S105: The second sequence processing device separates a plurality of target bit sequences from the received bit sequence.

[0205] S106: The second sequence processing device performs an inverse process of the distribution matching process on the multiple target bit sequences to obtain multiple intermediate bit sequences.

[0206] S107: The second sequence processing device obtains an initial bit sequence according to the multiple intermediate bit sequences and the extended table.

[0207] The above S105 and S103 are inverse operations, S106 and S102 are inverse operations, and S107 and S101 are inverse operations. Therefore, S105 can refer to S103, S106 can refer to S102, and S107 can refer to S101. The embodiment of this application will not be repeated here.

[0208] In summary, the sequence processing method provided in the embodiments of the present application first generates multiple intermediate bit sequences based on the initial bit sequence and the expansion table. Distribution matching is then performed on each of these intermediate bit sequences to obtain multiple target bit sequences. Finally, the resulting target bit sequences are combined. This sequence processing method differs from sequence processing methods in related arts and, therefore, enriches the range of sequence processing options.

[0209] Furthermore, the expansion table is used to indicate the one-to-one correspondence, 2 d The number of low-amplitude bits of the second bit sequence is greater than or equal to 2 h The second bit sequence is divided by the 2 d Therefore, the 2 in the one-to-one correspondence indicated in the above expansion table is d The number of low-amplitude bits in each of the second bit sequences is relatively large. Therefore, in the multiple target bit sequences obtained after the distribution matching process using the multiple intermediate bit sequences obtained according to the expansion table, the number of bits used to map to the lowest amplitude bit in each target bit sequence is relatively large. Generally, the larger the number of bits used to map to the lowest amplitude bit in the target bit sequence, the better the signal transmission effect. Since the multiple target bit sequences obtained through the distribution matching process have relatively large numbers of bits used to map to the lowest amplitude bit, the signal transmission effect in this application is relatively good.

[0210] Furthermore, the sequence processing flow of the solution provided in this application is relatively simple and the implementation complexity is relatively low.

[0211] In related technologies, the rate loss R loss It is negatively correlated with the signal transmission effect. Therefore, if R loss However, reducing R loss It is necessary to increase the size of the table in the above-mentioned lookup table method, so that the storage space required for the table will increase exponentially. If it is necessary to make the signal transmission effect better, the storage space required for the table is very large. Moreover, when the storage space is large, the complexity of the lookup table method is high, and the power consumption required for the lookup table is also high. In the present application, the signal transmission effect can be improved without increasing the size of the above-mentioned table. Therefore, the present application will not cause the increase in the storage space required for the table, and the problems of high complexity and power consumption. Therefore, the method provided by the present application can be used for a sequence processing device with higher power consumption constraints, which is beneficial for the sequence processing device to achieve a longer transmission distance. Optionally, on the basis of the embodiment of the present application, the above-mentioned table can also be increased at the same time to reduce R loss , thereby improving the signal transmission effect, increasing the transmission distance and reducing the transmission bit error rate, which is not limited in this application.

[0212] Furthermore, 2 h There are second bit sequences with the same number of low-amplitude bits in the second bit sequences. h 2 second bit sequences are selected d When the second bit sequence is 2 d The minimum value of the number of low-amplitude bits in the second bit sequence is u,2 h The second bit sequence is divided by 2d The maximum number of low-amplitude bits of the second bit sequence other than the second bit sequence is also u, then, 2 d The second bit sequence includes: 2 h v second bit sequences with a low amplitude bit number greater than u in the second bit sequences, and any 2 of the multiple second bit sequences with a low amplitude bit number u d -v second bit sequences, where u and v are both integers greater than or equal to 1. h Select v second bit sequences with the number of low-amplitude bits greater than u from the second bit sequences, and then select 2 second bit sequences with the number of low-amplitude bits u at random. d -v second bit sequence, resulting in 2 d In this case, 2 d The number of low-amplitude bits of any second bit sequence in the second bit sequences is greater than 2 h The second bit sequence is divided by 2 d The number of low-amplitude bits of any second bit sequence other than the second bit sequences.

[0213] In addition, if 2 d The minimum number of low-amplitude bits in the second bit sequence is u+1, and 2 h The second bit sequence is divided by 2 d The maximum number of low-amplitude bits of the second bit sequence outside the second bit sequence is u. Then, we only need to add 2 h The second bit sequence with the number of low-amplitude bits greater than u is selected from the second bit sequences, and 2 d In this case, 2 d The number of low-amplitude bits of any second bit sequence in the second bit sequences is greater than or equal to 2 h The second bit sequence is divided by 2 d The number of low-amplitude bits of any second bit sequence other than the second bit sequences.

[0214] 2 d The first bit sequence and 2 d In the one-to-one correspondence between the second bit sequences, 2 d There are many ways to implement the second bit sequence, and several of the ways will be used as examples for illustration below.

[0215] 1, 2 d A first possible implementation of a second bit sequence.

[0216] In this first possible implementation, 2 d The number of low-amplitude bits of any second bit sequence in the second bit sequences is greater than 2h The second bit sequence is divided by 2 d The number of low-amplitude bits of any second bit sequence other than the second bit sequences.

[0217] In the first implementation, the intermediate bit sequence includes 11 bits, the second type bit segment includes 3 bits, and the second bit sequence includes: a first consecutive second type bit segment and a second second type bit segment; d The second bit sequences can be represented by the 16 second bit sequences shown in Table 3.

[0218] It can be seen that 2 d The second bit sequence includes:

[0219] a second bit sequence in which the first second-category bit segment is (0, 0, 0) and the second second-category bit segment is (0, 0, 0);

[0220] a second bit sequence in which the first second-type bit segment is (0, 0, 0) and the second second-type bit segment is (1, 0, 0);

[0221] a second bit sequence in which the first second-type bit segment is (1, 0, 0) and the second second-type bit segment is (0, 0, 0);

[0222] a second bit sequence in which the first second-type bit segment is (0, 0, 0) and the second second-type bit segment is (0, 1, 0);

[0223] a second bit sequence in which the first second-type bit segment is (0, 1, 0) and the second second-type bit segment is (0, 0, 0);

[0224] a second bit sequence in which the first second-type bit segment is (1, 1, 0) and the second second-type bit segment is (0, 0, 0);

[0225] a second bit sequence in which the first second-type bit segment is (0, 0, 0) and the second second-type bit segment is (1, 1, 0);

[0226] a second bit sequence in which the first second-type bit segment is (1, 0, 0) and the second second-type bit segment is (1, 0, 0);

[0227] a second bit sequence in which the first second-type bit segment is (0, 0, 0) and the second second-type bit segment is (0, 0, 1);

[0228] a second bit sequence in which the first second-type bit segment is (0, 0, 1) and the second second-type bit segment is (0, 0, 0);

[0229] a second bit sequence in which the first second-type bit segment is (0, 1, 0) and the second second-type bit segment is (1, 0, 0);

[0230] a second bit sequence in which the first second-type bit segment is (1, 0, 0) and the second second-type bit segment is (0, 1, 0);

[0231] a second bit sequence in which the first second-type bit segment is (1, 0, 1) and the second second-type bit segment is (0, 0, 0);

[0232] a second bit sequence in which the first second-type bit segment is (0, 0, 0) and the second second-type bit segment is (1, 0, 1);

[0233] a second bit sequence in which the first second-type bit segment is (1, 1, 0) and the second second-type bit segment is (1, 0, 0);

[0234] a second bit sequence in which the first second-type bit segment is (1, 0, 0) and the second second-type bit segment is (1, 1, 0);

[0235] In the various second-category bit segments provided in the embodiments of the present application (including the second-category bit segments provided in other subsequent implementable methods), the bits in the second-category bit segments are arranged from left to right in the order of bit positions from low to high or from high to low. In each second-category bit segment, the bit position of the w-th bit from left to right is higher or lower than the bit position of the w+1-th bit, w≥1. In addition, assuming that the second-category bit segment includes y bits, then the y bits in the second-category bit segment are also the y bits with the highest bit in the intermediate bit sequence including the second-category bit segment; and the highest bit in each second-category bit segment is also the bit with the highest bit in the intermediate bit sequence including the second-category bit segment. In the embodiment of the present application, the bit position of the bits in the second-category bit segment is the same as the bit position of the bits in the intermediate bit sequence where the second-category bit segment is located.

[0236] Optionally, in the first possible implementation, 2 d The first bit sequence may include 16 first bit sequences, 2 d The first bit sequence and the 2 d In the one-to-one correspondence between the second bit sequences:

[0237] In the second bit sequence corresponding to the first bit sequence (0, 0, 0, 0), the first second-category bit segment is (0, 0, 0), and the second second-category bit segment is (0, 0, 0);

[0238] In the second bit sequence corresponding to the first bit sequence (0, 0, 1, 0), the first second-category bit segment is (0, 0, 0), and the second second-category bit segment is (1, 0, 0);

[0239] In the second bit sequence corresponding to the first bit sequence (0, 0, 0, 1), the first second-category bit segment is (1, 0, 0), and the second second-category bit segment is (0, 0, 0);

[0240] In the second bit sequence corresponding to the first bit sequence (0, 0, 1, 1), the first second-category bit segment is (0, 0, 0), and the second second-category bit segment is (0, 1, 0);

[0241] In the second bit sequence corresponding to the first bit sequence (1, 0, 0, 0), the first second-category bit segment is (0, 1, 0), and the second second-category bit segment is (0, 0, 0);

[0242] In the second bit sequence corresponding to the first bit sequence (1, 0, 1, 0), the first second-category bit segment is (1, 1, 0), and the second second-category bit segment is (0, 0, 0);

[0243] In the second bit sequence corresponding to the first bit sequence (1, 0, 0, 1), the first second-category bit segment is (0, 0, 0), and the second second-category bit segment is (1, 1, 0);

[0244] In the second bit sequence corresponding to the first bit sequence (1, 0, 1, 1), the first second-category bit segment is (1, 0, 0), and the second second-category bit segment is (1, 0, 0);

[0245] In the second bit sequence corresponding to the first bit sequence (0, 1, 0, 0), the first second-category bit segment is (0, 0, 0), and the second second-category bit segment is (0, 0, 1);

[0246] In the second bit sequence corresponding to the first bit sequence (0, 1, 1, 0), the first second-category bit segment is (0, 0, 1), and the second second-category bit segment is (0, 0, 0);

[0247] In the second bit sequence corresponding to the first bit sequence (0, 1, 0, 1), the first second-category bit segment is (0, 1, 0), and the second second-category bit segment is (1, 0, 0);

[0248] In the second bit sequence corresponding to the first bit sequence (0, 1, 1, 1), the first second-category bit segment is (1, 0, 0), and the second second-category bit segment is (0, 1, 0);

[0249] In the second bit sequence corresponding to the first bit sequence (1, 1, 0, 0), the first second-category bit segment is (1, 0, 1), and the second second-category bit segment is (0, 0, 0);

[0250] In the second bit sequence corresponding to the first bit sequence (1, 1, 1, 0), the first second-category bit segment is (0, 0, 0), and the second second-category bit segment is (1, 0, 1);

[0251] In the second bit sequence corresponding to the first bit sequence (1, 1, 0, 1), the first second-category bit segment is (1, 1, 0), and the second second-category bit segment is (1, 0, 0);

[0252] In the second bit sequence corresponding to the first bit sequence (1, 1, 1, 1), the first second-type bit segment is (1, 0, 0), and the second second-type bit segment is (1, 1, 0).

[0253] 2 d The first bit sequence and 2 d The one-to-one correspondence between the first and second bit sequences can be shown in Table 3. The first bit sequence in Table 3 also includes a consecutive first first-class bit segment and a second first-class bit segment, and the first first-class bit segment and the second first-class bit segment are arranged from left to right in Table 3. The first first-class bit segment or the second first-class bit segment is the multiple most significant bits in the first bit sequence. The first second-class bit segment and the second second-class bit segment in the second bit sequence are also arranged from left to right in Table 3. The first second-class bit segment or the second second-class bit segment is the multiple most significant bits in the second bit sequence.

[0254] Table 3

[0255] It is understandable that in the above 2 d The first bit sequence and the above 2 d Based on the second bit sequences, the one-to-one correspondence between the first bit sequences and the second bit sequences may also be different from that shown in Table 3. For example, the second bit sequences corresponding to any two first bit sequences in the above example may be swapped. For another example, the order of the 16 second bit sequences in Table 3 may be shuffled, while the order of the 16 first bit sequences in Table 3 remains unchanged.

[0256] 2, 2 d A second possible implementation of the second bit sequence.

[0257] In this second possible implementation, 2 d The number of low-amplitude bits of any second bit sequence in the second bit sequences is greater than or equal to 2 hThe second bit sequence is divided by 2 d The number of low-amplitude bits of any second bit sequence other than the second bit sequences.

[0258] In the second possible implementation, the intermediate bit sequence includes 10 bits, the second type bit segment includes 3 bits, and the second bit sequence includes: a first consecutive second type bit segment and a second second type bit segment; d The second bit sequences may include the 15 second bit sequences shown in Table 4 and any one of the two second bit sequences shown in Table 5.

[0259] It can be seen that 2 d The second bit sequence includes:

[0260] a second bit sequence in which the first second-category bit segment is (0, 0, 0) and the second second-category bit segment is (0, 0, 0);

[0261] a second bit sequence in which the first second-type bit segment is (0, 0, 0) and the second second-type bit segment is (1, 0, 0);

[0262] a second bit sequence in which the first second-type bit segment is (1, 0, 0) and the second second-type bit segment is (0, 0, 0);

[0263] a second bit sequence in which the first second-type bit segment is (0, 0, 0) and the second second-type bit segment is (0, 1, 0);

[0264] a second bit sequence in which the first second-type bit segment is (0, 1, 0) and the second second-type bit segment is (0, 0, 0);

[0265] a second bit sequence in which the first second-type bit segment is (1, 0, 0) and the second second-type bit segment is (1, 0, 0);

[0266] a second bit sequence in which the first second-type bit segment is (0, 0, 0) and the second second-type bit segment is (1, 1, 0);

[0267] a second bit sequence in which the first second-type bit segment is (1, 1, 0) and the second second-type bit segment is (0, 0, 0);

[0268] a second bit sequence in which the first second-type bit segment is (0, 0, 0) and the second second-type bit segment is (0, 0, 1);

[0269] a second bit sequence in which the first second-type bit segment is (0, 0, 1) and the second second-type bit segment is (0, 0, 0);

[0270] a second bit sequence in which the first second-type bit segment is (0, 1, 0) and the second second-type bit segment is (1, 0, 0);

[0271] a second bit sequence in which the first second-type bit segment is (1, 0, 0) and the second second-type bit segment is (0, 1, 0);

[0272] a second bit sequence in which the first second-type bit segment is (0, 1, 0) and the second second-type bit segment is (0, 1, 0);

[0273] a second bit sequence in which the first second-type bit segment is (1, 0, 1) and the second second-type bit segment is (0, 0, 0);

[0274] a second bit sequence in which the first second-type bit segment is (0, 0, 0) and the second second-type bit segment is (1, 0, 1);

[0275] And, any one of the following second bit sequences:

[0276] a second bit sequence in which the first second-type bit segment is (1, 1, 0) and the second second-type bit segment is (1, 0, 0);

[0277] a second bit sequence in which the first second-type bit segment is (1, 0, 0) and the second second-type bit segment is (1, 1, 0);

[0278] The bits in the second type of bit segment are arranged from left to right in the order of low to high or high to low.

[0279] Optionally, in the second possible implementation, 2 d The first bit sequence may include 16 first bit sequences, 2 d The first bit sequence and the 2 d In the one-to-one correspondence between the second bit sequences:

[0280] In the second bit sequence corresponding to the first bit sequence (0, 0, 0, 0), the first second-category bit segment is (0, 0, 0), and the second second-category bit segment is (0, 0, 0);

[0281] In the second bit sequence corresponding to the first bit sequence (0, 0, 1, 0), the first second-category bit segment is (0, 0, 0), and the second second-category bit segment is (1, 0, 0);

[0282] In the second bit sequence corresponding to the first bit sequence (0, 0, 0, 1), the first second-category bit segment is (1, 0, 0), and the second second-category bit segment is (0, 0, 0);

[0283] In the second bit sequence corresponding to the first bit sequence (0, 0, 1, 1), the first second-category bit segment is (0, 0, 0), and the second second-category bit segment is (0, 1, 0);

[0284] In the second bit sequence corresponding to the first bit sequence (1, 0, 0, 0), the first second-category bit segment is (0, 1, 0), and the second second-category bit segment is (0, 0, 0);

[0285] In the second bit sequence corresponding to the first bit sequence (1, 0, 1, 0), the first second-category bit segment is (1, 0, 0), and the second second-category bit segment is (1, 0, 0);

[0286] In the second bit sequence corresponding to the first bit sequence (1, 0, 0, 1), the first second-category bit segment is (0, 0, 0), and the second second-category bit segment is (1, 1, 0);

[0287] In the second bit sequence corresponding to the first bit sequence (1, 0, 1, 1), the first second-category bit segment is (1, 1, 0), and the second second-category bit segment is (0, 0, 0);

[0288] In the second bit sequence corresponding to the first bit sequence (0, 1, 0, 0), the first second-category bit segment is (0, 0, 0), and the second second-category bit segment is (0, 0, 1);

[0289] In the second bit sequence corresponding to the first bit sequence (0, 1, 1, 0), the first second-category bit segment is (0, 0, 1), and the second second-category bit segment is (0, 0, 0);

[0290] In the second bit sequence corresponding to the first bit sequence (0, 1, 0, 1), the first second-category bit segment is (0, 1, 0), and the second second-category bit segment is (1, 0, 0);

[0291] In the second bit sequence corresponding to the first bit sequence (0, 1, 1, 1), the first second-category bit segment is (1, 0, 0), and the second second-category bit segment is (0, 1, 0);

[0292] In the second bit sequence corresponding to the first bit sequence (1, 1, 0, 0), the first second-category bit segment is (0, 1, 0), and the second second-category bit segment is (0, 1, 0);

[0293] In the second bit sequence corresponding to the first bit sequence (1, 1, 1, 0), the first second-category bit segment is (1, 0, 1), and the second second-category bit segment is (0, 0, 0);

[0294] In the second bit sequence corresponding to the first bit sequence (1, 1, 0, 1), the first second-category bit segment is (0, 0, 0), and the second second-category bit segment is (1, 0, 1);

[0295] In the second bit sequence corresponding to the first bit sequence (1, 1, 1, 1), the first second-category bit segment is (1, 1, 0) and the second second-category bit segment is (1, 0, 0), or, the first second-category bit segment is (1, 0, 0) and the second second-category bit segment is (1, 1, 0).

[0296] 2 d The first bit sequence and 2 d The one-to-one correspondence between the first and second bit sequences can be shown in Tables 4 and 5. Table 4 shows 16 first bit sequences and 15 second bit sequences, and the second bit sequence corresponding to a first bit sequence in Table 4 is empty. The second bit sequence can be any second bit sequence of the two second bit sequences shown in Table 5. The first bit sequence in Table 4 also includes a continuous first first-class bit segment and a second first-class bit segment, and the first first-class bit segment and the second first-class bit segment are arranged from left to right in Table 4. The first first-class bit segment or the second first-class bit segment is the most significant multiple bits in the first bit sequence. The first second-class bit segment and the second second-class bit segment in the second bit sequence are also arranged from left to right in Tables 4 and 5. The first second-class bit segment or the second second-class bit segment is the most significant multiple bits in the second bit sequence.

[0297] Table 4

[0298] Table 5

[0299] It is understandable that in the above 2 d The first bit sequence and the above 2 d Based on the second bit sequences, the one-to-one correspondence between the first bit sequence and the second bit sequence may also be different from that shown in Tables 4 and 5. For example, the second bit sequences corresponding to any two first bit sequences in the above examples may be swapped. For another example, the order of the 16 second bit sequences given in Tables 4 and 5 (the 15 second bit sequences in Table 4 and any one of the two second bit sequences given in Table 5) may be shuffled, while the order of the 16 first bit sequences in Table 4 remains unchanged.

[0300] 3.2 d A third possible implementation of the second bit sequence.

[0301] In the third possible implementation, 2d The number of low-amplitude bits of any second bit sequence in the second bit sequences is greater than or equal to 2 h The second bit sequence is divided by 2 d The number of low-amplitude bits of any second bit sequence other than the second bit sequences.

[0302] In the third implementation, the intermediate bit sequence includes 10 bits, the second type bit segment includes 4 bits, and the second bit sequence includes: a first consecutive second type bit segment and a second second type bit segment; d The second bit sequences may include the 15 second bit sequences shown in Table 6 and any one of the two second bit sequences shown in Table 7.

[0303] It can be seen that 2 d The second bit sequence includes:

[0304] a second bit sequence in which the first second-category bit segment is (0, 0, 0, 0) and the second second-category bit segment is (0, 0, 0, 0);

[0305] a second bit sequence in which the first second-type bit segment is (0, 0, 0, 0) and the second second-type bit segment is (1, 0, 0, 0);

[0306] a second bit sequence in which the first second-category bit segment is (1, 0, 0, 0) and the second second-category bit segment is (0, 0, 0, 0);

[0307] a second bit sequence in which the first second-type bit segment is (0, 0, 0, 0) and the second second-type bit segment is (0, 1, 0, 0);

[0308] a second bit sequence in which the first second-category bit segment is (0, 1, 0, 0) and the second second-category bit segment is (0, 0, 0, 0);

[0309] a second bit sequence in which the first second-category bit segment is (0, 0, 0, 0) and the second second-category bit segment is (1, 1, 0, 0);

[0310] a second bit sequence in which the first second-category bit segment is (0, 0, 0, 0) and the second second-category bit segment is (0, 0, 1, 0);

[0311] a second bit sequence in which the first second-category bit segment is (0, 0, 0, 0) and the second second-category bit segment is (1, 0, 1, 0);

[0312] a second bit sequence in which the first second-category bit segment is (1, 1, 0, 0) and the second second-category bit segment is (0, 0, 0, 0);

[0313] a second bit sequence in which the first second-category bit segment is (1, 0, 1, 0) and the second second-category bit segment is (0, 0, 0, 0);

[0314] a second bit sequence in which the first second-category bit segment is (0, 0, 1, 0) and the second second-category bit segment is (0, 0, 0, 0);

[0315] a second bit sequence in which the first second-type bit segment is (1, 0, 0, 0) and the second second-type bit segment is (1, 0, 0, 0);

[0316] a second bit sequence in which the first second-type bit segment is (0, 1, 0, 0) and the second second-type bit segment is (1, 0, 0, 0);

[0317] a second bit sequence in which the first second-type bit segment is (1, 0, 0, 0) and the second second-type bit segment is (0, 1, 0, 0);

[0318] a second bit sequence in which the first second-type bit segment is (0, 1, 0, 0) and the second second-type bit segment is (0, 1, 0, 0);

[0319] And, any one of the following second bit sequences:

[0320] a second bit sequence in which the first second-category bit segment is (0, 0, 0, 0) and the second second-category bit segment is (0, 1, 1, 0);

[0321] a second bit sequence in which the first second-category bit segment is (0, 1, 1, 0) and the second second-category bit segment is (0, 0, 0, 0);

[0322] The bits in the second type of bit segment are arranged from left to right in the order of low to high or high to low.

[0323] Optionally, in the third possible implementation, 2 d The first bit sequence may include 16 first bit sequences, 2 d The first bit sequence and the 2 d In the one-to-one correspondence between the second bit sequences:

[0324] In the second bit sequence corresponding to the first bit sequence (0, 0, 0, 0), the first second-category bit segment is (0, 0, 0, 0), and the second second-category bit segment is (0, 0, 0, 0);

[0325] In the second bit sequence corresponding to the first bit sequence (0, 0, 1, 0), the first second-category bit segment is (0, 0, 0, 0), and the second second-category bit segment is (1, 0, 0, 0);

[0326] In the second bit sequence corresponding to the first bit sequence (0, 0, 0, 1), the first second-category bit segment is (1, 0, 0, 0), and the second second-category bit segment is (0, 0, 0, 0);

[0327] In the second bit sequence corresponding to the first bit sequence (0, 0, 1, 1), the first second-category bit segment is (0, 0, 0, 0), and the second second-category bit segment is (0, 1, 0, 0);

[0328] In the second bit sequence corresponding to the first bit sequence (1, 0, 0, 0), the first second-category bit segment is (0, 1, 0, 0), and the second second-category bit segment is (0, 0, 0, 0);

[0329] In the second bit sequence corresponding to the first bit sequence (1, 0, 1, 0), the first second-category bit segment is (0, 0, 0, 0), and the second second-category bit segment is (1, 1, 0, 0);

[0330] In the second bit sequence corresponding to the first bit sequence (1, 0, 0, 1), the first second-category bit segment is (0, 0, 0, 0), and the second second-category bit segment is (0, 0, 1, 0);

[0331] In the second bit sequence corresponding to the first bit sequence (1, 0, 1, 1), the first second-category bit segment is (0, 0, 0, 0), and the second second-category bit segment is (1, 0, 1, 0);

[0332] In the second bit sequence corresponding to the first bit sequence (0, 1, 0, 0), the first second-category bit segment is (1, 1, 0, 0), and the second second-category bit segment is (0, 0, 0, 0);

[0333] In the second bit sequence corresponding to the first bit sequence (0, 1, 1, 0), the first second-category bit segment is (1, 0, 1, 0), and the second second-category bit segment is (0, 0, 0, 0);

[0334] In the second bit sequence corresponding to the first bit sequence (0, 1, 0, 1), the first second-category bit segment is (0, 0, 1, 0), and the second second-category bit segment is (0, 0, 0, 0);

[0335] In the second bit sequence corresponding to the first bit sequence (0, 1, 1, 1), the first second-category bit segment is (1, 0, 0, 0), and the second second-category bit segment is (1, 0, 0, 0);

[0336] In the second bit sequence corresponding to the first bit sequence (1, 1, 0, 0), the first second-category bit segment is (0, 1, 0, 0), and the second second-category bit segment is (1, 0, 0, 0);

[0337] In the second bit sequence corresponding to the first bit sequence (1, 1, 1, 0), the first second-category bit segment is (1, 0, 0, 0), and the second second-category bit segment is (0, 1, 0, 0);

[0338] In the second bit sequence corresponding to the first bit sequence (1, 1, 0, 1), the first second-category bit segment is (0, 1, 0, 0), and the second second-category bit segment is (0, 1, 0, 0);

[0339] In the second bit sequence corresponding to the first bit sequence (1, 1, 1, 1), the first second-category bit segment is (0, 0, 0, 0) and the second second-category bit segment is (0, 1, 1, 0), or, the first second-category bit segment is (0, 1, 1, 0) and the second second-category bit segment is (0, 0, 0, 0).

[0340] 2 d The first bit sequence and 2 d The one-to-one correspondence between the first and second bit sequences can be shown in Tables 6 and 7. Table 6 shows 16 first bit sequences and 15 second bit sequences, and the second bit sequence corresponding to a first bit sequence in Table 6 is empty. The second bit sequence can be any second bit sequence of the two second bit sequences shown in Table 7. The first bit sequence in Table 6 also includes a continuous first first-class bit segment and a second first-class bit segment, and the first first-class bit segment and the second first-class bit segment are arranged from left to right in Table 6. The first first-class bit segment or the second first-class bit segment is the most significant multiple bits in the first bit sequence. The first second-class bit segment and the second second-class bit segment in the second bit sequence are also arranged from left to right in Tables 6 and 7. The first second-class bit segment or the second second-class bit segment is the most significant multiple bits in the second bit sequence.

[0341] Table 6

[0342] Table 7

[0343] It is understandable that in the above 2 d The first bit sequence and the above 2 dBased on the second bit sequences, the one-to-one correspondence between the first bit sequence and the second bit sequence may also be different from that shown in Tables 6 and 7. For example, the second bit sequences corresponding to any two first bit sequences in the above example may be swapped. For another example, the order of the 16 second bit sequences given in Tables 6 and 7 (the 15 second bit sequences in Table 6 and any one of the two second bit sequences given in Table 7) may be shuffled, while the order of the 16 first bit sequences in Table 6 remains unchanged.

[0344] 4, 2 d A fourth possible implementation of the second bit sequence.

[0345] In the fourth possible implementation, 2 d The number of low-amplitude bits of any second bit sequence in the second bit sequences is greater than or equal to 2 h The second bit sequence is divided by 2 d The number of low-amplitude bits of any second bit sequence other than the second bit sequences.

[0346] In a fourth implementation, the intermediate bit sequence includes 11 bits, the second type bit segment includes 4 bits, and the second bit sequence includes: a first consecutive second type bit segment and a second second type bit segment; d The second bit sequences may include the 14 second bit sequences shown in Table 8 and any two second bit sequences among the 6 second bit sequences shown in Table 9.

[0347] It can be seen that 2 d The second bit sequence includes:

[0348] a second bit sequence in which the first second-category bit segment is (0, 0, 0, 0) and the second second-category bit segment is (0, 0, 0, 0);

[0349] a second bit sequence in which the first second-type bit segment is (0, 0, 0, 0) and the second second-type bit segment is (1, 0, 0, 0);

[0350] a second bit sequence in which the first second-category bit segment is (1, 0, 0, 0) and the second second-category bit segment is (0, 0, 0, 0);

[0351] a second bit sequence in which the first second-category bit segment is (0, 1, 0, 0) and the second second-category bit segment is (0, 0, 0, 0);

[0352] a second bit sequence in which the first second-type bit segment is (1, 0, 0, 0) and the second second-type bit segment is (1, 0, 0, 0);

[0353] a second bit sequence in which the first second-category bit segment is (1, 1, 0, 0) and the second second-category bit segment is (0, 0, 0, 0);

[0354] a second bit sequence in which the first second-category bit segment is (0, 0, 0, 0) and the second second-category bit segment is (0, 1, 0, 0);

[0355] a second bit sequence in which the first second-category bit segment is (0, 0, 0, 0) and the second second-category bit segment is (1, 1, 0, 0);

[0356] a second bit sequence in which the first second-category bit segment is (0, 0, 0, 0) and the second second-category bit segment is (0, 0, 1, 0);

[0357] a second bit sequence in which the first second-category bit segment is (0, 0, 1, 0) and the second second-category bit segment is (0, 0, 0, 0);

[0358] a second bit sequence in which the first second-type bit segment is (1, 0, 0, 0) and the second second-type bit segment is (1, 1, 0, 0);

[0359] a second bit sequence in which the first second-type bit segment is (1, 0, 0, 0) and the second second-type bit segment is (0, 1, 0, 0);

[0360] a second bit sequence in which the first second-type bit segment is (0, 1, 0, 0) and the second second-type bit segment is (1, 0, 0, 0);

[0361] a second bit sequence in which the first second-category bit segment is (1, 1, 0, 0) and the second second-category bit segment is (1, 0, 0, 0);

[0362] And, any two second bit sequences among the following second bit sequences:

[0363] a second bit sequence in which the first second-category bit segment is (0, 0, 0, 0) and the second second-category bit segment is (0, 1, 1, 0);

[0364] a second bit sequence in which the first second-category bit segment is (0, 0, 0, 0) and the second second-category bit segment is (1, 0, 1, 0);

[0365] a second bit sequence in which the first second-category bit segment is (1, 0, 1, 0) and the second second-category bit segment is (0, 0, 0, 0);

[0366] a second bit sequence in which the first second-category bit segment is (1, 1, 1, 0) and the second second-category bit segment is (0, 0, 0, 0);

[0367] a second bit sequence in which the first second-category bit segment is (0, 0, 0, 0) and the second second-category bit segment is (1, 1, 1, 0);

[0368] a second bit sequence in which the first second-category bit segment is (0, 1, 1, 0) and the second second-category bit segment is (0, 0, 0, 0);

[0369] The bits in the second type of bit segment are arranged from left to right in the order of low to high or high to low.

[0370] Optionally, in the fourth possible implementation, 2 d The first bit sequence may include 16 first bit sequences, 2 d The first bit sequence and 2 d In the one-to-one correspondence between the second bit sequences:

[0371] In the second bit sequence corresponding to the first bit sequence (0, 0, 0, 0), the first second-category bit segment is (0, 0, 0, 0), and the second second-category bit segment is (0, 0, 0, 0);

[0372] In the second bit sequence corresponding to the first bit sequence (0, 0, 1, 0), the first second-category bit segment is (0, 0, 0, 0), and the second second-category bit segment is (1, 0, 0, 0);

[0373] In the second bit sequence corresponding to the first bit sequence (0, 0, 0, 1), the first second-category bit segment is (1, 0, 0, 0), and the second second-category bit segment is (0, 0, 0, 0);

[0374] In the second bit sequence corresponding to the first bit sequence (0, 0, 1, 1), the first second-category bit segment is (0, 1, 0, 0), and the second second-category bit segment is (0, 0, 0, 0);

[0375] In the second bit sequence corresponding to the first bit sequence (1, 0, 0, 0), the first second-category bit segment is (1, 0, 0, 0), and the second second-category bit segment is (1, 0, 0, 0);

[0376] In the second bit sequence corresponding to the first bit sequence (1, 0, 1, 0), the first second-category bit segment is (1, 1, 0, 0), and the second second-category bit segment is (0, 0, 0, 0);

[0377] In the second bit sequence corresponding to the first bit sequence (1, 0, 0, 1), the first second-category bit segment is (0, 0, 0, 0), and the second second-category bit segment is (0, 1, 0, 0);

[0378] In the second bit sequence corresponding to the first bit sequence (1, 0, 1, 1), the first second-category bit segment is (0, 0, 0, 0), and the second second-category bit segment is (1, 1, 0, 0);

[0379] In the second bit sequence corresponding to the first bit sequence (0, 1, 0, 0), the first second-category bit segment is (0, 0, 0, 0), and the second second-category bit segment is (0, 0, 1, 0);

[0380] In the second bit sequence corresponding to the first bit sequence (0, 1, 1, 0), the first second-category bit segment is (0, 0, 1, 0), and the second second-category bit segment is (0, 0, 0, 0);

[0381] In the second bit sequence corresponding to the first bit sequence (0, 1, 0, 1), the first second-category bit segment is (1, 0, 0, 0), and the second second-category bit segment is (1, 1, 0, 0);

[0382] In the second bit sequence corresponding to the first bit sequence (0, 1, 1, 1), the first second-category bit segment is (1, 0, 0, 0), and the second second-category bit segment is (0, 1, 0, 0);

[0383] In the second bit sequence corresponding to the first bit sequence (1, 1, 0, 0), the first second-category bit segment is (0, 1, 0, 0), and the second second-category bit segment is (1, 0, 0, 0);

[0384] In the second bit sequence corresponding to the first bit sequence (1, 1, 1, 0), the first second-category bit segment is (1, 1, 0, 0), and the second second-category bit segment is (1, 0, 0, 0);

[0385] The second bit sequence corresponding to the first bit sequence (1, 1, 0, 1) and the second bit sequence corresponding to the first bit sequence (1, 1, 1, 1) are any two second bit sequences among the following second bit sequences:

[0386] a second bit sequence in which the first second-category bit segment is (0, 0, 0, 0) and the second second-category bit segment is (0, 1, 1, 0);

[0387] a second bit sequence in which the first second-category bit segment is (0, 0, 0, 0) and the second second-category bit segment is (1, 0, 1, 0);

[0388] a second bit sequence in which the first second-category bit segment is (1, 0, 1, 0) and the second second-category bit segment is (0, 0, 0, 0);

[0389] a second bit sequence in which the first second-category bit segment is (1, 1, 1, 0) and the second second-category bit segment is (0, 0, 0, 0);

[0390] a second bit sequence in which the first second-category bit segment is (0, 0, 0, 0) and the second second-category bit segment is (1, 1, 1, 0);

[0391] The first second-type bit segment is a second bit sequence of (0, 1, 1, 0), and the second second-type bit segment is a second bit sequence of (0, 0, 0, 0).

[0392] 2 d The first bit sequence and 2 d The one-to-one correspondence between the first and second bit sequences can be shown in Tables 8 and 9. Table 8 shows 16 first bit sequences and 14 second bit sequences, and the second bit sequences corresponding to the two first bit sequences in Table 8 are empty. The second bit sequences corresponding to the two first bit sequences can be any two second bit sequences among the 6 second bit sequences shown in Table 9. The first bit sequence in Table 8 also includes a continuous first first-class bit segment and a second first-class bit segment, and the first first-class bit segment and the second first-class bit segment are arranged from left to right in Table 8. The first first-class bit segment or the second first-class bit segment is the most significant multiple bits in the first bit sequence. The first second-class bit segment and the second second-class bit segment in the second bit sequence are also arranged from left to right in Tables 8 and 9. The first second-class bit segment or the second second-class bit segment is the most significant multiple bits in the second bit sequence.

[0393] Table 8

[0394] Table 9

[0395] It is understandable that in the above 2 d The first bit sequence and the above 2 d Based on the second bit sequences, the one-to-one correspondence between the first bit sequence and the second bit sequence may also be different from that shown in Tables 8 and 9. For example, the second bit sequences corresponding to any two first bit sequences in the above example are swapped. For another example, the order of the 16 second bit sequences given in Tables 8 and 9 (the 14 second bit sequences in Table 8 and any two of the six second bit sequences given in Table 9) is shuffled, and the order of the 16 first bit sequences in Table 8 remains unchanged.

[0396] 5.2 d A fifth possible implementation of the second bit sequence.

[0397] In the fifth possible implementation, 2d The number of low-amplitude bits of any second bit sequence in the second bit sequences is greater than or equal to 2 h The second bit sequence is divided by 2 d The number of low-amplitude bits of any second bit sequence other than the second bit sequences.

[0398] In a fifth implementation, the intermediate bit sequence includes 10 bits, the second type bit segment includes 6 bits, and the second bit sequence includes: a first consecutive second type bit segment and a second second type bit segment; d The second bit sequences may include the 11 second bit sequences shown in Table 10 and any 5 second bit sequences among the 14 second bit sequences shown in Table 11.

[0399] It can be seen that 2 d The second bit sequence includes:

[0400] a second bit sequence in which the first second-category bit segment is (0, 0, 0, 0, 0), and the second second-category bit segment is (0, 0, 0, 0, 0);

[0401] a second bit sequence in which the first second-category bit segment is (0, 0, 0, 0, 0), and the second second-category bit segment is (1, 0, 0, 0, 0, 0);

[0402] a second bit sequence in which the first second-category bit segment is (0, 0, 0, 0, 0), and the second second-category bit segment is (0, 1, 0, 0, 0, 0);

[0403] a second bit sequence in which the first second-category bit segment is (1, 0, 0, 0, 0, 0) and the second second-category bit segment is (0, 0, 0, 0, 0, 0);

[0404] a second bit sequence in which the first second-category bit segment is (0, 1, 0, 0, 0, 0) and the second second-category bit segment is (0, 0, 0, 0, 0, 0);

[0405] a second bit sequence in which the first second-category bit segment is (0, 0, 0, 0, 0), and the second second-category bit segment is (1, 1, 0, 0, 0, 0);

[0406] a second bit sequence in which the first second-category bit segment is (1, 1, 0, 0, 0, 0) and the second second-category bit segment is (0, 0, 0, 0, 0, 0);

[0407] a second bit sequence in which the first second-category bit segment is (0, 1, 0, 0, 0, 0) and the second second-category bit segment is (0, 1, 0, 0, 0, 0);

[0408] a second bit sequence in which the first second-category bit segment is (0, 1, 0, 0, 0, 0) and the second second-category bit segment is (1, 0, 0, 0, 0, 0);

[0409] a second bit sequence in which the first second-category bit segment is (1, 0, 0, 0, 0, 0) and the second second-category bit segment is (1, 0, 0, 0, 0, 0);

[0410] a second bit sequence in which the first second-category bit segment is (1, 0, 0, 0, 0), and the second second-category bit segment is (0, 1, 0, 0, 0, 0);

[0411] And, any five second bit sequences among the following second bit sequences:

[0412] a second bit sequence in which the first second-category bit segment is (0, 0, 1, 0, 0, 0) and the second second-category bit segment is (0, 0, 0, 0, 0, 0);

[0413] a second bit sequence in which the first second-category bit segment is (1, 0, 1, 0, 0, 0) and the second second-category bit segment is (0, 0, 0, 0, 0, 0);

[0414] a second bit sequence in which the first second-category bit segment is (0, 1, 1, 0, 0, 0) and the second second-category bit segment is (0, 0, 0, 0, 0, 0);

[0415] a second bit sequence in which the first second-category bit segment is (0, 0, 0, 1, 0, 0) and the second second-category bit segment is (0, 0, 0, 0, 0, 0);

[0416] a second bit sequence in which the first second-category bit segment is (1, 0, 0, 1, 0, 0) and the second second-category bit segment is (0, 0, 0, 0, 0, 0);

[0417] a second bit sequence in which the first second-category bit segment is (0, 1, 0, 1, 0, 0) and the second second-category bit segment is (0, 0, 0, 0, 0, 0);

[0418] a second bit sequence in which the first second-category bit segment is (1, 1, 1, 0, 0, 0) and the second second-category bit segment is (0, 0, 0, 0, 0, 0);

[0419] a second bit sequence in which the first second-category bit segment is (0, 0, 0, 0, 0), and the second second-category bit segment is (0, 0, 0, 1, 0, 0);

[0420] a second bit sequence in which the first second-category bit segment is (0, 0, 0, 0, 0), and the second second-category bit segment is (0, 0, 1, 0, 0, 0);

[0421] a second bit sequence in which the first second-category bit segment is (0, 0, 0, 0, 0), and the second second-category bit segment is (1, 0, 1, 0, 0, 0);

[0422] a second bit sequence in which the first second-category bit segment is (0, 0, 0, 0, 0), and the second second-category bit segment is (0, 1, 1, 0, 0, 0);

[0423] a second bit sequence in which the first second-category bit segment is (0, 0, 0, 0, 0), and the second second-category bit segment is (1, 0, 0, 1, 0, 0);

[0424] a second bit sequence in which the first second-category bit segment is (0, 0, 0, 0, 0), and the second second-category bit segment is (1, 1, 1, 0, 0, 0);

[0425] a second bit sequence in which the first second-category bit segment is (0, 0, 0, 0, 0), and the second second-category bit segment is (0, 1, 0, 1, 0, 0);

[0426] The bits in the second type of bit segment are arranged from left to right in the order of low to high or high to low.

[0427] Optionally, in the fifth possible implementation, 2 d The first bit sequence may include 16 first bit sequences, 2 d The first bit sequence and 2 d In the one-to-one correspondence between the second bit sequences:

[0428] In the second bit sequence corresponding to the first bit sequence (0, 0, 0, 0), the first second-category bit segment is (0, 0, 0, 0, 0, 0), and the second second-category bit segment is (0, 0, 0, 0, 0, 0);

[0429] In the second bit sequence corresponding to the first bit sequence (0, 0, 1, 0), the first second-category bit segment is (0, 0, 0, 0, 0, 0), and the second second-category bit segment is (1, 0, 0, 0, 0, 0);

[0430] In the second bit sequence corresponding to the first bit sequence (0, 0, 0, 1), the first second-category bit segment is (0, 0, 0, 0, 0, 0), and the second second-category bit segment is (0, 1, 0, 0, 0, 0);

[0431] In the second bit sequence corresponding to the first bit sequence (0, 0, 1, 1), the first second-category bit segment is (1, 0, 0, 0, 0, 0), and the second second-category bit segment is (0, 0, 0, 0, 0, 0);

[0432] In the second bit sequence corresponding to the first bit sequence (1, 0, 0, 0), the first second-category bit segment is (0, 1, 0, 0, 0, 0), and the second second-category bit segment is (0, 0, 0, 0, 0, 0);

[0433] In the second bit sequence corresponding to the first bit sequence (1, 0, 1, 0), the first second-category bit segment is (0, 0, 0, 0, 0, 0), and the second second-category bit segment is (1, 1, 0, 0, 0, 0);

[0434] In the second bit sequence corresponding to the first bit sequence (1, 0, 0, 1), the first second-category bit segment is (1, 1, 0, 0, 0, 0), and the second second-category bit segment is (0, 0, 0, 0, 0, 0);

[0435] In the second bit sequence corresponding to the first bit sequence (1, 0, 1, 1), the first second-category bit segment is (0, 1, 0, 0, 0, 0), and the second second-category bit segment is (0, 1, 0, 0, 0, 0);

[0436] In the second bit sequence corresponding to the first bit sequence (0, 1, 0, 0), the first second-category bit segment is (0, 1, 0, 0, 0, 0), and the second second-category bit segment is (1, 0, 0, 0, 0, 0);

[0437] In the second bit sequence corresponding to the first bit sequence (0, 1, 1, 0), the first second-category bit segment is (1, 0, 0, 0, 0, 0), and the second second-category bit segment is (1, 0, 0, 0, 0, 0);

[0438] In the second bit sequence corresponding to the first bit sequence (0, 1, 0, 1), the first second-category bit segment is (1, 0, 0, 0, 0, 0), and the second second-category bit segment is (0, 1, 0, 0, 0, 0);

[0439] The second bit sequence corresponding to the first bit sequence (0, 1, 1, 1), the second bit sequence corresponding to the first bit sequence (1, 1, 0, 0), the second bit sequence corresponding to the first bit sequence (1, 1, 1, 0), the second bit sequence corresponding to the first bit sequence (1, 1, 0, 1), and the second bit sequence corresponding to the first bit sequence (1, 1, 1, 1) are any five second bit sequences among the following second bit sequences:

[0440] a second bit sequence in which the first second-category bit segment is (0, 0, 1, 0, 0, 0) and the second second-category bit segment is (0, 0, 0, 0, 0, 0);

[0441] a second bit sequence in which the first second-category bit segment is (1, 0, 1, 0, 0, 0) and the second second-category bit segment is (0, 0, 0, 0, 0, 0);

[0442] a second bit sequence in which the first second-category bit segment is (0, 1, 1, 0, 0, 0) and the second second-category bit segment is (0, 0, 0, 0, 0, 0);

[0443] a second bit sequence in which the first second-category bit segment is (0, 0, 0, 1, 0, 0) and the second second-category bit segment is (0, 0, 0, 0, 0, 0);

[0444] a second bit sequence in which the first second-category bit segment is (1, 0, 0, 1, 0, 0) and the second second-category bit segment is (0, 0, 0, 0, 0, 0);

[0445] a second bit sequence in which the first second-category bit segment is (0, 1, 0, 1, 0, 0) and the second second-category bit segment is (0, 0, 0, 0, 0, 0);

[0446] a second bit sequence in which the first second-category bit segment is (1, 1, 1, 0, 0, 0) and the second second-category bit segment is (0, 0, 0, 0, 0, 0);

[0447] a second bit sequence in which the first second-category bit segment is (0, 0, 0, 0, 0), and the second second-category bit segment is (0, 0, 0, 1, 0, 0);

[0448] a second bit sequence in which the first second-category bit segment is (0, 0, 0, 0, 0), and the second second-category bit segment is (0, 0, 1, 0, 0, 0);

[0449] a second bit sequence in which the first second-category bit segment is (0, 0, 0, 0, 0), and the second second-category bit segment is (1, 0, 1, 0, 0, 0);

[0450] a second bit sequence in which the first second-category bit segment is (0, 0, 0, 0, 0), and the second second-category bit segment is (0, 1, 1, 0, 0, 0);

[0451] a second bit sequence in which the first second-category bit segment is (0, 0, 0, 0, 0), and the second second-category bit segment is (1, 0, 0, 1, 0, 0);

[0452] a second bit sequence in which the first second-category bit segment is (0, 0, 0, 0, 0), and the second second-category bit segment is (1, 1, 1, 0, 0, 0);

[0453] The first second-type bit segment is a second bit sequence of (0, 0, 0, 0, 0, 0), and the second second-type bit segment is a second bit sequence of (0, 1, 0, 1, 0, 0).

[0454] 2 d The first bit sequence and 2 d The one-to-one correspondence between the first and second bit sequences can be shown in Tables 10 and 11. Table 10 shows 16 first bit sequences and 11 second bit sequences, and the second bit sequences corresponding to five first bit sequences in Table 10 are empty. The second bit sequences corresponding to these five first bit sequences can be any five second bit sequences among the 14 second bit sequences shown in Table 11. The first bit sequence in Table 10 also includes a consecutive first-class bit segment and a second-class bit segment, and the first-class bit segment and the second-class bit segment are arranged from left to right in Table 10. The first-class bit segment or the second-class bit segment is the multiple most significant bits in the first bit sequence. The first-class bit segment and the second-class bit segment in the second bit sequence are also arranged from left to right in Tables 10 and 11. The first-class bit segment or the second-class bit segment is the multiple most significant bits in the second bit sequence.

[0455] Table 10

[0456] Table 11

[0457] It is understandable that in the above 2 d The first bit sequence and the above 2 d Based on the second bit sequences, the one-to-one correspondence between the first bit sequence and the second bit sequence may also be different from that shown in Tables 10 and 11. For example, the second bit sequences corresponding to any two first bit sequences in the above example are swapped. For another example, the order of the 16 second bit sequences given in Tables 10 and 11 (the 11 second bit sequences in Table 8 and any five of the 14 second bit sequences given in Table 11) is shuffled, and the order of the 16 first bit sequences in Table 10 remains unchanged.

[0458] 6, 2 d A sixth possible implementation of the second bit sequence.

[0459] In the sixth possible implementation, 2 dThe number of low-amplitude bits of any second bit sequence in the second bit sequences is greater than or equal to 2 h The second bit sequence is divided by 2 d The number of low-amplitude bits of any second bit sequence other than the second bit sequences.

[0460] In a sixth implementation, the intermediate bit sequence includes 11 bits, the second type bit segment includes 7 bits, and the second bit sequence includes: a first consecutive second type bit segment and a second second type bit segment; d The second bit sequences may include the 7 second bit sequences shown in Table 12 and any 9 second bit sequences among the 11 second bit sequences shown in Table 13.

[0461] It can be seen that 2 d The second bit sequence includes:

[0462] a second bit sequence in which the first second-category bit segment is (0, 0, 0, 0, 0, 0), and the second second-category bit segment is (0, 0, 0, 0, 0, 0);

[0463] a second bit sequence in which the first second-category bit segment is (0, 1, 0, 0, 0, 0, 0) and the second second-category bit segment is (0, 0, 0, 0, 0, 0, 0);

[0464] a second bit sequence in which the first second-category bit segment is (1, 1, 0, 0, 0, 0, 0) and the second second-category bit segment is (0, 0, 0, 0, 0, 0, 0);

[0465] a second bit sequence in which the first second-category bit segment is (1, 0, 0, 0, 0, 0), and the second second-category bit segment is (0, 0, 0, 0, 0, 0);

[0466] a second bit sequence in which the first second-category bit segment is (0, 0, 0, 0, 0, 0), and the second second-category bit segment is (1, 0, 0, 0, 0, 0);

[0467] a second bit sequence in which the first second-category bit segment is (0, 0, 0, 0, 0, 0), and the second second-category bit segment is (0, 1, 0, 0, 0, 0, 0);

[0468] a second bit sequence in which the first second-category bit segment is (0, 0, 0, 0, 0, 0), and the second second-category bit segment is (1, 1, 0, 0, 0, 0, 0);

[0469] And, any nine second bit sequences among the following second bit sequences:

[0470] a second bit sequence in which the first second-category bit segment is (0, 0, 0, 0, 0, 0), and the second second-category bit segment is (0, 0, 1, 0, 0, 0, 0);

[0471] a second bit sequence in which the first second-category bit segment is (1, 0, 0, 0, 0, 0), and the second second-category bit segment is (0, 1, 0, 0, 0, 0, 0);

[0472] a second bit sequence in which the first second-category bit segment is (1, 0, 0, 0, 0, 0), and the second second-category bit segment is (1, 1, 0, 0, 0, 0, 0);

[0473] a second bit sequence in which the first second-category bit segment is (0, 1, 0, 0, 0, 0, 0) and the second second-category bit segment is (1, 0, 0, 0, 0, 0, 0);

[0474] a second bit sequence in which the first second-category bit segment is (0, 1, 0, 0, 0, 0, 0) and the second second-category bit segment is (0, 1, 0, 0, 0, 0, 0);

[0475] a second bit sequence in which the first second-category bit segment is (0, 1, 0, 0, 0, 0, 0) and the second second-category bit segment is (1, 1, 0, 0, 0, 0, 0);

[0476] a second bit sequence in which the first second-category bit segment is (1, 1, 0, 0, 0, 0, 0) and the second second-category bit segment is (1, 0, 0, 0, 0, 0, 0);

[0477] a second bit sequence in which the first second-category bit segment is (1, 1, 0, 0, 0, 0, 0) and the second second-category bit segment is (0, 1, 0, 0, 0, 0, 0);

[0478] a second bit sequence in which the first second-category bit segment is (1, 1, 0, 0, 0, 0, 0) and the second second-category bit segment is (1, 1, 0, 0, 0, 0, 0);

[0479] a second bit sequence in which the first second-category bit segment is (1, 0, 0, 0, 0, 0), and the second second-category bit segment is (1, 0, 0, 0, 0, 0);

[0480] a second bit sequence in which the first second-category bit segment is (0, 0, 1, 0, 0, 0, 0) and the second second-category bit segment is (0, 0, 0, 0, 0, 0, 0);

[0481] The bits in the second type of bit segment are arranged from left to right in the order of low to high or high to low.

[0482] Optionally, in the sixth possible implementation, 2 d The first bit sequence may include 16 first bit sequences, 2 d The first bit sequence and 2 d In the one-to-one correspondence between the second bit sequences:

[0483] In the second bit sequence corresponding to the first bit sequence (0, 0, 0, 0), the first second-category bit segment is (0, 0, 0, 0, 0, 0, 0), and the second second-category bit segment is (0, 0, 0, 0, 0, 0, 0);

[0484] In the second bit sequence corresponding to the first bit sequence (0, 0, 1, 0), the first second-category bit segment is (0, 1, 0, 0, 0, 0, 0), and the second second-category bit segment is (0, 0, 0, 0, 0, 0, 0);

[0485] In the second bit sequence corresponding to the first bit sequence (0, 0, 0, 1), the first second-category bit segment is (1, 1, 0, 0, 0, 0, 0), and the second second-category bit segment is (0, 0, 0, 0, 0, 0, 0);

[0486] In the second bit sequence corresponding to the first bit sequence (0, 0, 1, 1), the first second-category bit segment is (1, 0, 0, 0, 0, 0, 0), and the second second-category bit segment is (0, 0, 0, 0, 0, 0, 0);

[0487] In the second bit sequence corresponding to the first bit sequence (1, 0, 0, 0), the first second-category bit segment is (0, 0, 0, 0, 0, 0), and the second second-category bit segment is (1, 0, 0, 0, 0, 0, 0);

[0488] In the second bit sequence corresponding to the first bit sequence (1, 0, 1, 0), the first second-category bit segment is (0, 0, 0, 0, 0, 0, 0), and the second second-category bit segment is (0, 1, 0, 0, 0, 0, 0);

[0489] In the second bit sequence corresponding to the first bit sequence (1, 0, 0, 1), the first second-category bit segment is (0, 0, 0, 0, 0, 0), and the second second-category bit segment is (1, 1, 0, 0, 0, 0, 0);

[0490] The second bit sequence corresponding to the first bit sequence (1, 0, 1, 1), the second bit sequence corresponding to the first bit sequence (0, 1, 0, 0), the second bit sequence corresponding to the first bit sequence (0, 1, 1, 0), the second bit sequence corresponding to the first bit sequence (0, 1, 0, 1), the second bit sequence corresponding to the first bit sequence (0, 1, 1, 1), the second bit sequence corresponding to the first bit sequence (1, 1, 0, 0), the second bit sequence corresponding to the first bit sequence (1, 1, 1, 0), and the second bit sequence corresponding to the first bit sequence (1, 1, 1, 1) are any nine second bit sequences among the following second bit sequences:

[0491] a second bit sequence in which the first second-category bit segment is (0, 0, 0, 0, 0, 0), and the second second-category bit segment is (0, 0, 1, 0, 0, 0, 0);

[0492] a second bit sequence in which the first second-category bit segment is (1, 0, 0, 0, 0, 0), and the second second-category bit segment is (0, 1, 0, 0, 0, 0, 0);

[0493] a second bit sequence in which the first second-category bit segment is (1, 0, 0, 0, 0, 0), and the second second-category bit segment is (1, 1, 0, 0, 0, 0, 0);

[0494] a second bit sequence in which the first second-category bit segment is (0, 1, 0, 0, 0, 0, 0) and the second second-category bit segment is (1, 0, 0, 0, 0, 0, 0);

[0495] a second bit sequence in which the first second-category bit segment is (0, 1, 0, 0, 0, 0, 0) and the second second-category bit segment is (0, 1, 0, 0, 0, 0, 0);

[0496] a second bit sequence in which the first second-category bit segment is (0, 1, 0, 0, 0, 0, 0) and the second second-category bit segment is (1, 1, 0, 0, 0, 0, 0);

[0497] a second bit sequence in which the first second-category bit segment is (1, 1, 0, 0, 0, 0, 0) and the second second-category bit segment is (1, 0, 0, 0, 0, 0, 0);

[0498] a second bit sequence in which the first second-category bit segment is (1, 1, 0, 0, 0, 0, 0) and the second second-category bit segment is (0, 1, 0, 0, 0, 0, 0);

[0499] a second bit sequence in which the first second-category bit segment is (1, 1, 0, 0, 0, 0, 0) and the second second-category bit segment is (1, 1, 0, 0, 0, 0, 0);

[0500] a second bit sequence in which the first second-category bit segment is (1, 0, 0, 0, 0, 0), and the second second-category bit segment is (1, 0, 0, 0, 0, 0);

[0501] The first second-type bit segment is a second bit sequence of (0, 0, 1, 0, 0, 0, 0), and the second second-type bit segment is a second bit sequence of (0, 0, 0, 0, 0, 0, 0).

[0502] 2 d The first bit sequence and 2 d The one-to-one correspondence between the first and second bit sequences can be shown in Tables 12 and 13. Table 12 shows 16 first bit sequences and 7 second bit sequences, and the second bit sequences corresponding to the 9 first bit sequences in Table 11 are empty. The second bit sequences corresponding to these five first bit sequences can be any 9 second bit sequences among the 11 second bit sequences shown in Table 12. The first bit sequence in Table 12 also includes a continuous first first-class bit segment and a second first-class bit segment, and the first first-class bit segment and the second first-class bit segment are arranged from left to right in Table 12. The first first-class bit segment or the second first-class bit segment is the most significant multiple bits in the first bit sequence. The first second-class bit segment and the second second-class bit segment in the second bit sequence are also arranged from left to right in Tables 12 and 13. The first second-class bit segment or the second second-class bit segment is the most significant multiple bits in the second bit sequence.

[0503] Table 12

[0504] Table 13

[0505] It is understandable that in the above 2 d The first bit sequence and the above 2 d Based on the second bit sequences, the one-to-one correspondence between the first bit sequence and the second bit sequence may also be different from that shown in Table 12 and Table 13. For example, the second bit sequences corresponding to any two first bit sequences in the above example are swapped. For another example, the order of the 16 second bit sequences given in Table 12 and Table 13 (the 7 second bit sequences in Table 12 and any 9 second bit sequences among the 11 second bit sequences given in Table 13) is shuffled, and the order of the 16 first bit sequences in Table 12 remains unchanged.

[0506] 7, 2 dA seventh possible implementation of the second bit sequence.

[0507] In the seventh possible implementation, 2 d The number of low-amplitude bits of any second bit sequence in the second bit sequences is greater than or equal to 2 h The second bit sequence is divided by 2 d The number of low-amplitude bits of any second bit sequence other than the second bit sequences.

[0508] In a seventh implementation, the intermediate bit sequence includes 10 bits, the second type of bit segment includes 3 bits, and the second bit sequence includes 4 second type of bit segments. d The second bit sequence includes 256 second bit sequences, and the 256 second bit sequences include the 246 second bit sequences shown in Table 14 and any 10 second bit sequences among the 24 second bit sequences shown in Table 15. In Tables 14 and 15, the second bit sequence includes four consecutive second-type bit segments, and these four second-type bit segments can be the four second-type bit segments arranged from left to right in Tables 14 and 15. The bits in the bit sequence are arranged from left to right in order of bit position from low to high.

[0509] Optionally, in the seventh possible implementation, 2 d The first bit sequence may include 256 first bit sequences, 2 d The first bit sequence and 2 d The one-to-one correspondence between the first bit sequences and the second bit sequences can be shown in Table 14. In addition, the second bit sequences corresponding to some first bit sequences in Table 14 are empty, and the second bit sequences corresponding to these first bit sequences can be any 10 second bit sequences among the 24 second bit sequences shown in Table 15. In Table 14, the first first-category bit segment or the second first-category bit segment, counted from left to right, is the multiple most significant bits in the first bit sequence; in Tables 14 and 15, the first second-category bit segment or the second second-category bit segment, counted from left to right, is the multiple most significant bits in the second bit sequence.

[0510] It is understandable that in the above 2 d The first bit sequence and the above 2 dBased on the second bit sequences, the one-to-one correspondence between the first bit sequence and the second bit sequence may also be different from that shown in Table 14 and Table 15. For example, the second bit sequences corresponding to any two first bit sequences in the above example are swapped. For another example, the order of the 256 second bit sequences given in Table 14 and Table 15 (the 246 second bit sequences in Table 14 and any 10 second bit sequences among the 24 second bit sequences given in Table 15) is shuffled, and the order of the 256 first bit sequences in Table 14 remains unchanged.

[0511] Table 14

[0512] Table 15

[0513] 8.2 d An eighth possible implementation of the second bit sequence.

[0514] In the eighth possible implementation, 2 d The number of low-amplitude bits of any second bit sequence in the second bit sequences is greater than 2 h The second bit sequence is divided by 2 d The number of low-amplitude bits of any second bit sequence other than the second bit sequences.

[0515] In an eighth implementation, the intermediate bit sequence includes 11 bits, the second type of bit segment includes 3 bits, and the second bit sequence includes 4 second type of bit segments. d The second bit sequence includes 256 second bit sequences, and the 256 second bit sequences include the 256 second bit sequences shown in Table 16. In Table 16, the second bit sequence includes four consecutive second-type bit segments, and these four second-type bit segments can be the four second-type bit segments arranged from left to right in Table 16. The bits in the second-type bit segments are arranged from left to right in the order of bit position from low to high or from high to low.

[0516] Optionally, in the eighth possible implementation, 2 d The first bit sequence may include 256 first bit sequences, 2 d The first bit sequence and 2 dThe one-to-one correspondence between the second bit sequences can be shown in Table 16. In Table 16, the first first-category bit segment or the second first-category bit segment counted from left to right is the multiple most significant bits in the first bit sequence, and the first second-category bit segment or the second second-category bit segment counted from left to right is the multiple most significant bits in the second bit sequence.

[0517] It is understandable that in the above 2 d The first bit sequence and the above 2 d Based on the second bit sequences, the one-to-one correspondence between the first bit sequences and the second bit sequences may also be different from that shown in Table 16. For example, the second bit sequences corresponding to any two first bit sequences in the above example may be swapped. For another example, the order of the 256 second bit sequences given in Table 16 may be shuffled, while the order of the 256 first bit sequences in Table 16 remains unchanged.

[0518] Table 16

[0519] 9, 2 d A ninth possible implementation of the second bit sequence.

[0520] In the ninth possible implementation, 2 d The number of low-amplitude bits of any second bit sequence in the second bit sequences is greater than or equal to 2 h The second bit sequence is divided by 2 d The number of low-amplitude bits of any second bit sequence other than the second bit sequences.

[0521] In a ninth implementation, the intermediate bit sequence includes 10 bits, the second type of bit segment includes 3 bits, and the second bit sequence includes 4 second type of bit segments. d The second bit sequences include 64 second bit sequences, and the 64 second bit sequences include the 61 second bit sequences shown in Table 17 and any three second bit sequences among the 12 second bit sequences shown in Table 18. In Tables 17 and 18, the second bit sequences include four consecutive second-type bit segments, and these four second-type bit segments can be the four second-type bit segments arranged from left to right in Tables 17 and 18. The bits in the second-type bit segments are arranged from left to right in the order of low to high or high to low bit positions.

[0522] Optionally, in the ninth possible implementation, 2 d The first bit sequence may include 64 first bit sequences, 2 dThe first bit sequence and 2 d The one-to-one correspondence between the first bit sequences and the second bit sequences can be shown in Table 17. In addition, the second bit sequences corresponding to some first bit sequences in Table 17 are empty, and the second bit sequences corresponding to these first bit sequences can be any three second bit sequences among the 12 second bit sequences shown in Table 18. In Table 17, the first first-category bit segment or the second first-category bit segment, counted from left to right, is the multiple most significant bits in the first bit sequence; in Tables 17 and 18, the first second-category bit segment or the second second-category bit segment, counted from left to right, is the multiple most significant bits in the second bit sequence.

[0523] It is understandable that in the above 2 d The first bit sequence and the above 2 d Based on the second bit sequences, the one-to-one correspondence between the first bit sequence and the second bit sequence may also be different from that shown in Table 17 and Table 18. For example, the second bit sequences corresponding to any two first bit sequences in the above example are swapped. For another example, the order of the 64 second bit sequences given in Table 17 and Table 18 (the 61 second bit sequences in Table 17 and any three of the 12 second bit sequences given in Table 18) is shuffled, and the order of the 64 first bit sequences in Table 17 remains unchanged.

[0524] Table 17

[0525] Table 18

[0526] 10, 2 d A tenth possible implementation of the second bit sequence.

[0527] In the tenth possible implementation, 2 d The number of low-amplitude bits of any second bit sequence in the second bit sequences is greater than or equal to 2 h The second bit sequence is divided by 2 d The number of low-amplitude bits of any second bit sequence other than the second bit sequences.

[0528] In a tenth possible implementation, the intermediate bit sequence includes 11 bits, the second type of bit segment includes 4 bits, and the second bit sequence includes 4 second type of bit segments. dThe second bit sequence includes 256 second bit sequences, and the 256 second bit sequences include the 212 second bit sequences shown in Table 19 and any 44 second bit sequences among the 56 second bit sequences shown in Table 20. In Tables 19 and 20, the second bit sequence includes four consecutive second-type bit segments, and these four second-type bit segments can be the four second-type bit segments arranged from left to right in Tables 19 and 20. The bits in the second-type bit segments are arranged from left to right in the order of low to high or high to low bit positions.

[0529] Optionally, in the tenth possible implementation, 2 d The first bit sequence may include 256 first bit sequences, 2 d The first bit sequence and 2 d The one-to-one correspondence between the first bit sequences and the second bit sequences can be shown in Table 19. In addition, the second bit sequences corresponding to some first bit sequences in Table 19 are empty, and the second bit sequences corresponding to these first bit sequences can be any 44 second bit sequences among the 56 second bit sequences shown in Table 20. In Table 19, the first first-category bit segment or the second first-category bit segment, counted from left to right, is the multiple most significant bits in the first bit sequence; in Tables 19 and 20, the first second-category bit segment or the second second-category bit segment, counted from left to right, is the multiple most significant bits in the second bit sequence.

[0530] It is understandable that in the above 2 d The first bit sequence and the above 2 d Based on the second bit sequences, the one-to-one correspondence between the first bit sequence and the second bit sequence may also be different from that shown in Table 19 and Table 20. For example, the second bit sequences corresponding to any two first bit sequences in the above example are swapped. For another example, the order of the 256 second bit sequences given in Table 19 and Table 20 (the 212 second bit sequences in Table 19 and any 44 second bit sequences among the 56 second bit sequences given in Table 20) is shuffled, and the order of the 256 first bit sequences in Table 19 remains unchanged.

[0531] Table 19

[0532] Table 20

[0533] 11, 2 d An eleventh possible implementation of the second bit sequence.

[0534] In the eleventh possible implementation, 2 d The number of low-amplitude bits of any second bit sequence in the second bit sequences is greater than or equal to 2 h The second bit sequence is divided by 2 d The number of low-amplitude bits of any second bit sequence other than the second bit sequences.

[0535] In an eleventh implementation manner, the intermediate bit sequence includes 10 bits, the second type of bit segment includes 6 bits, and the second bit sequence includes 4 second type of bit segments. d The second bit sequences include 256 second bit sequences, and the 256 second bit sequences include the 121 second bit sequences shown in Table 21 and any 135 second bit sequences among the 174 second bit sequences shown in Table 22. In Tables 21 and 22, the second bit sequences include four consecutive second-type bit segments, and these four second-type bit segments can be the four second-type bit segments arranged from left to right in Tables 20 and 21. The bits in the second-type bit segments are arranged from left to right in the order of low to high or high to low bit positions.

[0536] Optionally, in the eleventh possible implementation, 2 d The first bit sequence may include 256 first bit sequences, 2 d The first bit sequence and 2 d The one-to-one correspondence between the first bit sequences and the second bit sequences can be shown in Table 21. In addition, the second bit sequences corresponding to some first bit sequences in Table 21 are empty. The second bit sequences corresponding to these first bit sequences can be any 135 second bit sequences among the 174 second bit sequences shown in Table 22. In Table 21, the first first-category bit segment or the second first-category bit segment, counted from left to right, is the multiple most significant bits in the first bit sequence; in Tables 21 and 22, the first second-category bit segment or the second second-category bit segment, counted from left to right, is the multiple most significant bits in the second bit sequence.

[0537] It is understandable that in the above 2 d The first bit sequence and the above 2 dBased on the second bit sequences, the one-to-one correspondence between the first bit sequence and the second bit sequence may also be different from that shown in Table 21 and Table 22. For example, the second bit sequences corresponding to any two first bit sequences in the above example are swapped. For another example, the order of the 256 second bit sequences given in Table 21 and Table 22 (the 121 second bit sequences in Table 21 and any 135 second bit sequences among the 174 second bit sequences given in Table 22) is shuffled, and the order of the 256 first bit sequences in Table 21 remains unchanged.

[0538] Table 21

[0539] Table 22

[0540] 12, 2 d A twelfth possible implementation of the second bit sequence.

[0541] In the twelfth possible implementation, 2 d The number of low-amplitude bits of any second bit sequence in the second bit sequences is greater than or equal to 2 h The second bit sequence is divided by 2 d The number of low-amplitude bits of any second bit sequence other than the second bit sequences.

[0542] In a twelfth implementation, the intermediate bit sequence includes 10 bits, the second type of bit segment includes 7 bits, and the second bit sequence includes 4 second type of bit segments. d The second bit sequence includes 256 second bit sequences, and the 256 second bit sequences include the 255 second bit sequences shown in Table 23, and any one of the 324 second bit sequences shown in Table 24. In Tables 23 and 24, the second bit sequence includes four consecutive second-type bit segments, and these four second-type bit segments can be the four second-type bit segments arranged from left to right in Tables 23 and 24. The bits in the second-type bit segment are arranged from left to right in the order of bit position from low to high or from high to low.

[0543] Optionally, in the twelfth possible implementation, 2 d The first bit sequence may include 256 first bit sequences, 2 d The first bit sequence and 2d The one-to-one correspondence between the first bit sequences and the second bit sequences can be shown in Table 23. In addition, the second bit sequences corresponding to some first bit sequences in Table 23 are empty. The second bit sequences corresponding to these first bit sequences can be any one of the 324 second bit sequences shown in Table 24. In Table 23, the first first-category bit segment or the second first-category bit segment, counted from left to right, is the multiple most significant bits in the first bit sequence; in Tables 23 and 24, the first second-category bit segment or the second second-category bit segment, counted from left to right, is the multiple most significant bits in the second bit sequence.

[0544] It is understandable that in the above 2 d The first bit sequence and the above 2 d Based on the second bit sequences, the one-to-one correspondence between the first bit sequence and the second bit sequence may also be different from that shown in Table 23 and Table 24. For example, the second bit sequences corresponding to any two first bit sequences in the above example are swapped. For another example, the order of the 256 second bit sequences given in Table 23 and Table 24 (the 255 second bit sequences in Table 23 and any one of the 324 second bit sequences given in Table 24) is shuffled, and the order of the 256 first bit sequences in Table 23 remains unchanged.

[0545] Table 23

[0546] Table 24

[0547] 13, 2 d A thirteenth possible implementation of the second bit sequence.

[0548] In the thirteenth possible implementation, 2 d The number of low-amplitude bits of any second bit sequence in the second bit sequences is greater than or equal to 2 h The second bit sequence is divided by 2 d The number of low-amplitude bits of any second bit sequence other than the second bit sequences.

[0549] In a thirteenth possible implementation, the intermediate bit sequence includes 10 bits, the second type of bit segment includes 4 bits, and the second bit sequence includes 4 second type of bit segments. d The second bit sequence includes 1024 second bit sequences, and the 1024 second bit sequences include the 903 second bit sequences shown in Table 25 and any 121 second bit sequences among the 156 second bit sequences shown in Table 26. In Tables 25 and 26, the second bit sequence includes four consecutive second-type bit segments, and these four second-type bit segments can be the four second-type bit segments arranged from left to right in Tables 25 and 26. The bits in the second-type bit segments are arranged from left to right in the order of bit position from low to high or from high to low.

[0550] Optionally, in the thirteenth possible implementation, 2 d The first bit sequence may include 1024 first bit sequences, 2 d The first bit sequence and 2 d The one-to-one correspondence between the first bit sequences and the second bit sequences can be shown in Table 25. In addition, the second bit sequences corresponding to some first bit sequences in Table 25 are empty, and the second bit sequences corresponding to these first bit sequences can be any 121 second bit sequences among the 156 second bit sequences shown in Table 26. In Table 25, the first first-category bit segment or the second first-category bit segment, counted from left to right, is the multiple most significant bits in the first bit sequence; in Tables 25 and 26, the first second-category bit segment or the second second-category bit segment, counted from left to right, is the multiple most significant bits in the second bit sequence.

[0551] It is understandable that in the above 2 d The first bit sequence and the above 2 d Based on the second bit sequences, the one-to-one correspondence between the first bit sequence and the second bit sequence may also be different from that shown in Table 25 and Table 26. For example, the second bit sequences corresponding to any two first bit sequences in the above example are swapped. For another example, the order of the 1024 second bit sequences given in Table 25 and Table 26 (the 903 second bit sequences in Table 25 and any 121 second bit sequences among the 156 second bit sequences given in Table 26) is shuffled, and the order of the 1024 first bit sequences in Table 25 remains unchanged.

[0552] Table 25

[0553] Table 26

[0554] According to the above 2 d It can be seen from the various ways to realize the second bit sequence that 2 d The first bit sequence and 2 d In the one-to-one correspondence between the second bit sequences, 2 d The second bit sequence is not only related to d, but also to the number of bits in the intermediate bit sequence, the number of bits in the second type of bit segment, and the number of the second type of bit segments.

[0555] The number of bits in the intermediate bit sequence determines the size of the table searched in the subsequent distribution matching process, as well as the correspondence between each index bit sequence and the result bit sequence in the table.

[0556] For example, the table searched in the distribution matching processing corresponding to the above-mentioned multiple implementation methods may include the correspondence between a 10-bit index bit sequence and a 10-bit result bit sequence (as shown in Table 27), or the correspondence between an 11-bit index bit sequence and an 11-bit result bit sequence (as shown in Table 28).

[0557] Tables 27 and 28 use the example where bit 0 is mapped to the higher amplitude bit and bit 1 is mapped to the lower amplitude bit. The index bit sequence consists of Y bits, where Y > 1. In Table 27, Y = 10, and in Table 28, Y = 11. Bits 1 to 1 of the index bit sequence are represented as [1:Y]. The Yth bit is the most significant bit. The result bit sequence consists of N bits, where N > 1. In Table 27, N = 10, and in Table 28, N = 11. The first bit of the result bit sequence is represented as N[1], the second bit of the result bit sequence is represented as N[2], and so on.

[0558] Table 27

[0559] Table 28

[0560] Alternatively, assuming that the number of first-category bit segments in the first bit sequence is p, the number of second-category bit segments in the second bit sequence is q, the number of bits in the first-category bit segments is c, and the number of bits in the second-category bit segments is e, p, q, c, and e in this application may have various values.

[0561] For example, p=2, c=2, q=2, e=3; or, p=2, c=2, q=2, e=4; or, p=2, c=2, q=2, e=6; or, p=2, c=2, q=2, e=7; or, p=4, c=2, q=4, e=3; or, p=4, c=2, q=4, e=4; or, p=4, c=2, q=4, e=6; or, p=4, c=2, q=4, e=7; or, p=4, q=4, e=3; among the 4 first-class bit segments, c of two first-class bit segments are both 1, and c of the other two first-class bit segments are both 2; or, p=4, q=4, e=4; among the 4 first-class bit segments, c of two first-class bit segments are both 2, and c of the other two first-class bit segments are both 3. It is understandable that the values ​​of p, q, c and e may also be different from the values ​​listed here, and the embodiments of the present application are not limited to this.

[0562] Alternatively, the number of bits in the bit subsequence and the number of bits in the intermediate bit sequence may be implemented in multiple ways.

[0563] For example, the bit subsequence includes 6 bits, and the intermediate bit sequence includes 10 bits or 11 bits;

[0564] Alternatively, the bit subsequence includes 8 bits and the intermediate bit sequence includes 10 bits;

[0565] Alternatively, the bit subsequence includes 9 bits, and the intermediate bit sequence includes 10 bits or 11 bits;

[0566] Alternatively, the bit subsequence includes 10 bits, and the intermediate bit sequence includes 11 bits;

[0567] Alternatively, p=4, and among the four first-category bit segments, two first-category bit segments each include one bit, and the other two first-category bit segments each include two bits; among the four bit subsequences, two bit subsequences include eight bits, and the other two bit subsequences include nine bits; the intermediate bit sequence includes ten bits; the first-category bit segment in the bit subsequence including eight bits includes one bit; and the first-category bit segment in the bit subsequence including nine bits includes two bits;

[0568] Alternatively, p=4, among the four first-class bit segments, two first-class bit segments each include two bits, and the other two first-class bit segments each include 3 bits; among the four bit subsequences, two bit subsequences include 8 bits, and the other two bit subsequences include 9 bits; the intermediate bit sequence includes 10 bits; the first-class bit segment of the bit subsequence including 8 bits includes two bits; the first-class bit segment of the bit subsequence including 9 bits includes 3 bits.

[0569] It is understandable that the number of bits in the bit subsequence and the number of bits in the intermediate bit sequence may also be different from the number of bits listed here, and the embodiments of the present application are not limited to this.

[0570] Any of the above values ​​of p, q, c, and e can be combined with any of the above implementations of the number of bits in the bit subsequence and the number of bits in the intermediate bit sequence.

[0571] For example, when p=2, q=2, e=3, and c=2, the bit subsequence includes 9 bits and the intermediate bit sequence includes 10 bits;

[0572] Alternatively, when p=2, q=2, e=3, and c=2, the bit subsequence includes 10 bits and the intermediate bit sequence includes 11 bits;

[0573] Alternatively, when p=2, q=2, e=4, and c=2, the bit subsequence includes 8 bits and the intermediate bit sequence includes 10 bits;

[0574] Alternatively, when p=2, q=2, e=4, and c=2, the bit subsequence includes 9 bits and the intermediate bit sequence includes 11 bits;

[0575] Alternatively, when p=2, q=2, e=6, and c=2, the bit subsequence includes 6 bits and the intermediate bit sequence includes 10 bits;

[0576] Alternatively, when p=2, q=2, e=7, and c=2, the bit subsequence includes 6 bits and the intermediate bit sequence includes 11 bits;

[0577] Alternatively, when p=4, q=4, e=3, and c=2, the bit subsequence includes 9 bits and the intermediate bit sequence includes 10 bits;

[0578] Alternatively, when p=4, q=4, e=3, and c=2, the bit subsequence includes 10 bits and the intermediate bit sequence includes 11 bits;

[0579] Alternatively, when p=4, q=4, and e=3; and among the four first-category bit segments, c of two first-category bit segments is both 1, and c of the other two first-category bit segments is both 2, among the four bit subsequences, two bit subsequences include 8 bits, and the other two bit subsequences include 9 bits; the middle bit sequence includes 10 bits; the first-category bit segment in the bit subsequence including 8 bits includes 1 bit; and the first-category bit segment in the bit subsequence including 9 bits includes 2 bits;

[0580] Alternatively, when p=4, q=4, e=4, and c=2, the bit subsequence includes 9 bits and the intermediate bit sequence includes 11 bits;

[0581] Alternatively, when p=4, q=4, e=6, and c=2, the bit subsequence includes 6 bits and the intermediate bit sequence includes 10 bits;

[0582] Alternatively, when p=4, q=4, e=7, and c=2, the bit subsequence includes 6 bits and the intermediate bit sequence includes 11 bits;

[0583] Alternatively, when p=4, q=4, e=4; among the 4 first-class bit segments, c of two first-class bit segments are both 2, and c of the other two first-class bit segments are both 3, among the 4 bit subsequences, two bit subsequences include 8 bits, and the other two bit subsequences include 9 bits; the intermediate bit sequence includes 10 bits; the first-class bit segment in the bit subsequence including 8 bits includes 2 bits; and the first-class bit segment in the bit subsequence including 9 bits includes 3 bits.

[0584] Optionally, before S101, the first sequence processing device may further divide the to-be-processed bit sequence into a plurality of bit subsequences in the initial bit sequence. The to-be-processed bit sequence may belong to a bit stream received by the first sequence processing device. The first sequence processing device may select, from the received bit stream, a number of bits in the to-be-processed bit sequence as the to-be-processed bits based on the number of bits in the to-be-processed bit sequence.

[0585] Furthermore, in the above embodiment, a single initial bit sequence is used as an example. Optionally, there may be multiple initial bit sequences. In this case, the first sequence processing device may obtain multiple target bit sequences based on each initial bit sequence in S101 and S102, and merge all target bit sequences obtained from the multiple initial bit sequences in S103.

[0586] The multiple initial bit sequences may be received by the first sequence processing device, or may be obtained by the first sequence processing device dividing the bit sequence to be processed.

[0587] When multiple initial bit sequences are obtained by dividing the bit sequence to be processed, the first sequence processing device may divide the bit sequence to be processed into the multiple initial bit sequences, or the first sequence processing device may divide the bit sequence to be processed into multiple bit subsequences within the multiple initial bit sequences. Furthermore, the multiple initial bit sequences may be continuous or discontinuous within the bit sequence to be processed. In the embodiment of the present application, the multiple initial bit sequences are continuous within the bit sequence to be processed as an example.

[0588] In addition, when the first sequence processing device obtains the intermediate bit sequence according to different initial bit sequences, the extension tables based thereon may be the same or different, and this embodiment of the present application does not limit this.

[0589] For example, assuming that there are two initial bit sequences, namely initial bit sequence 1 and initial bit sequence 2, as shown in FIG4 , the first sequence processing device may split the bit sequence to be processed into initial bit sequence 1 and initial bit sequence 2.

[0590] The first sequence processing apparatus can obtain an intermediate bit sequence 1.1 and an intermediate bit sequence 1.2 based on the initial bit sequence 1. The intermediate bit sequence 1.1 is correlated with both the bit subsequence 1.1 and the bit subsequence 1.2 in the initial bit sequence 1, and the intermediate bit sequence 1.2 is correlated with both the bit subsequence 1.1 and the bit subsequence 1.2 in the initial bit sequence 1. The first sequence processing apparatus can also obtain a target bit sequence 1.1 based on the intermediate bit sequence 1.1, and obtain a target bit sequence 1.2 based on the intermediate bit sequence 1.2.

[0591] The first sequence processing apparatus may further obtain an intermediate bit sequence 2.1 and an intermediate bit sequence 2.2 based on the initial bit sequence 2. The intermediate bit sequence 2.1 is correlated with both the bit subsequence 2.1 and the bit subsequence 2.2 in the initial bit sequence 2, and the intermediate bit sequence 2.2 is correlated with both the bit subsequence 2.1 and the bit subsequence 2.2 in the initial bit sequence 2. The first sequence processing apparatus may further obtain a target bit sequence 2.1 based on the intermediate bit sequence 2.1 and obtain a target bit sequence 2.2 based on the intermediate bit sequence 2.2.

[0592] As another example, assuming there are two initial bit sequences, namely initial bit sequence 1 and initial bit sequence 2, as shown in FIG5 , the first sequence processing device may split the bit sequence to be processed into bit subsequence 1.1, bit subsequence 1.2, bit subsequence 2.1, and bit subsequence 2.2. Initial bit sequence 1 includes bit subsequence 1.1 and bit subsequence 1.2, and initial bit sequence 2 includes bit subsequence 2.1 and bit subsequence 2.2.

[0593] The first sequence processing device can obtain an intermediate bit sequence 1.1 and an intermediate bit sequence 1.2 based on the initial bit sequence 1 (including the bit subsequence 1.1 and the bit subsequence 1.2). The intermediate bit sequence 1.1 is correlated with both the bit subsequence 1.1 and the bit subsequence 1.2, and the intermediate bit sequence 1.2 is correlated with both the bit subsequence 1.1 and the bit subsequence 1.2. The first sequence processing device can also obtain a target bit sequence 1.1 based on the intermediate bit sequence 1.1 and obtain a target bit sequence 1.2 based on the intermediate bit sequence 1.2.

[0594] The first sequence processing device may also obtain an intermediate bit sequence 2.1 and an intermediate bit sequence 2.2 based on the initial bit sequence 2 (including the bit subsequence 2.1 and the bit subsequence 2.2). The intermediate bit sequence 2.1 is correlated with both the bit subsequence 2.1 and the bit subsequence 2.2, and the intermediate bit sequence 2.2 is correlated with both the bit subsequence 2.1 and the bit subsequence 2.2. The first sequence processing device may also obtain a target bit sequence 2.1 based on the intermediate bit sequence 2.1 and obtain a target bit sequence 2.2 based on the intermediate bit sequence 2.2.

[0595] In the embodiment of the present application, the number of initial bit sequences is taken as 2 as an example. It can be understood that the number of initial bit sequences can also be greater than 2.

[0596] Optionally, in an embodiment of the present application, the number of bits in the to-be-processed bit sequence is 72, 106 or 116, and the number of bits in the bit sequence obtained by merging the target bit sequence (ie, the bit sequence obtained after merging) is 128.

[0597] It is understandable that the number of bits in the to-be-processed bit sequence may not be 72, 106 or 116, and the number of bits in the bit sequence obtained after merging may not be 64 or 128, which is not limited in the embodiments of the present application.

[0598] The distribution matching process performed on the intermediate bit sequence in S102 may be implemented in a lookup table manner.

[0599] When using a lookup table for distribution matching, a table can be searched based on an intermediate bit sequence to obtain a target bit sequence corresponding to the intermediate bit sequence. The lookup table includes a one-to-one correspondence between multiple index bit sequences and multiple result bit sequences. The tables searched by the first sequence processing device in obtaining corresponding target bit sequences based on different intermediate bit sequences can be the same or different.

[0600] Optionally, when a 0 bit is mapped to a higher amplitude bit and a 1 bit is mapped to a lower amplitude bit, the value of the index bit sequence is positively correlated with the number of 0 bits in the result bit sequence. When a 1 bit is mapped to a higher amplitude bit and a 0 bit is mapped to a lower amplitude bit, the value of the index bit sequence is positively correlated with the number of 1 bits in the result bit sequence.

[0601] The multiple index bit sequences may be arranged in order of increasing or decreasing values. Of course, the multiple index bit sequences may not be arranged in this order, and this application does not limit this.

[0602] For example, taking the example that bit 0 is mapped to a higher amplitude bit and bit 1 is mapped to a lower amplitude bit, the one-to-one correspondence between multiple index bit sequences and multiple result bit sequences can be shown in Table 29 below. The index bit sequence includes Y bits in total, Y>1, and the first bit to the Yth bit of the index bit sequence are represented as [1:Y]. The Yth bit is the most significant bit. The result bit sequence includes N bits, N>1, and the first bit in the result bit sequence is represented as N[1], the second bit in the result bit sequence is represented as N[2], and so on. When Y=10, the one-to-one correspondence between multiple index bit sequences and multiple result bit sequences can be as shown in Table 27 above; when Y=11, the one-to-one correspondence between multiple index bit sequences and multiple result bit sequences can be as shown in Table 28 above.

[0603] Table 29

[0604] Assume that there are X index bit sequences, the number of 0 bits in the result bit sequence corresponding to the first index bit sequence is 0, and the number of 0 bits in the result bit sequence corresponding to the first index bit sequence is 0. The index bit sequence to the The number of 0 bits in the result bit sequence corresponding to the index bit sequence is s, and the number of 1 bits is NS, where s is a positive integer and 1≤s≤N. It represents the number of combinations, which means the number of all combinations of c (c≤N) elements taken from N different elements. It is called the number of combinations of c elements taken from N different elements. "!" means factorial. For example,

[0605] For example, as shown in Table 29, the number of 0 bits in the result bit sequence corresponding to the 1st index bit sequence is 0; the number of 0 bits in the result bit sequence corresponding to the 2nd index bit sequence to the 1+Nth index bit sequence is 1; the number of 0 bits in the result bit sequence corresponding to the 2+Nth index bit sequence to the 1+N+N(N-1) / 2th index bit sequence is 2; and so on.

[0606] It is worth noting that The index bit sequence to the The number of 0 bits in the result bit sequence corresponding to the index bit sequences is s, and the number of 1 bits is Ns. Therefore, there is no fixed order between these index bit sequences, and the order of these index bit sequences can be interchanged arbitrarily.

[0607] Optionally, the index bit sequences can be sorted based on the preference for placing 0 bits in the low bit positions of the result bit sequence. In a group of index bit sequences with the same number of 0 bits in the corresponding result bit sequences, the smaller the value of the index bit sequence, the smaller the sum of the number of 0 bits in the result bit sequence corresponding to the index bit sequence. For example, referring to Table 29, the number of 0 bits in the result bit sequence corresponding to the 2nd index bit sequence to the 1+Nth index bit sequence is 1, the number of 0 bits in the result bit sequence corresponding to the 2nd index bit sequence is 1, and the 0 bit is the lowest 1st bit in the result bit sequence; the number of 0 bits in the result bit sequence corresponding to the 1+Nth index bit sequence is 1+N, and the 0 bit is higher than the 1st bit 1+Nth bit in the result bit sequence; it can be seen that the number of 0 bits in the result bit sequence corresponding to the 2nd index bit sequence to the 1+Nth index bit sequence increases successively.

[0608] Alternatively, the index bit sequences can be sorted based on the probability of each bit in the result bit sequence being 0, so that the probability of each bit being 0 in multiple result bit sequences is the same. Bits of different orders have the same proportion of 0 bits in the multiple values ​​of the multiple result bit sequences. In other words, the index bit sequences can be sorted based on the principle of making the probability of each bit being 0 in all possible result bit sequences as close as possible. Which result bit sequences in the lookup table are usable is determined by the value range of the index bit sequence.

[0609] Taking Table 27 above as an example, Table 27 has 1024 rows, each row containing a 10-bit index bit sequence and a 10-bit result bit sequence, and the index bit sequences and result bit sequences of any two rows are different. Assuming that the first bit of the index bit sequence is the least significant bit and the tenth bit is the most significant bit, the 1024 rows are sorted from smallest to largest according to the value of the index bit sequence. In the result bit sequence in Table 27, bit 0 is used to map to the lowest amplitude, and bit 1 is used to map to the highest amplitude. To ensure that the target bit sequence generated by lookup table 27 has the best PCS performance, the result bit sequences with fewer 0 bits among all possible result bit sequences are preferentially placed in rows with smaller row numbers. For example, Table 27 can be divided into 11 regions according to the number of 0 bits in the result bit sequence, namely, row 1, rows 2 to 11, rows 12 to 56, rows 57 to 176, rows 177 to 386, rows 387 to 638, rows 639 to 848, rows 849 to 968, rows 969 to 1013, rows 1014 to 1023, and row 1024, corresponding to 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, and 10 bits 0 and 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, and 0 bits 1 in the result bit sequence, respectively. For regions corresponding to multiple rows, there is no ordering requirement for the output sequences within the region, that is, swapping the result bit sequences within the region does not affect PCS performance. In Table 27, the first bit of the result bit sequence is set as the least significant bit, and the tenth bit is set as the most significant bit. The values ​​of the result bit sequence are sorted from small to large within the region.

[0610] Taking Table 28 above as an example, Table 28 has 2048 rows, each row containing an 11-bit index bit sequence and an 11-bit result bit sequence. The index bit sequences and result bit sequences in any two rows are distinct. Assuming the first bit of the index bit sequence is the least significant bit and the tenth bit is the most significant bit, the 2048 rows are sorted from smallest to largest by the value of the index bit sequence. In Table 28, bit 0 of the result bit sequence is used to map to the lowest amplitude, and bit 1 is used to map to the highest amplitude. To ensure the target bit sequence generated by lookup Table 28 has the best PCS performance, sequences with fewer 0 bits among all possible result bit sequences are prioritized in rows with smaller row numbers. Specifically, Table 28 can be divided into 12 regions based on the number of 0 bits in the output sequence, namely, row 1, rows 2 to 12, rows 13 to 67, rows 68 to 232, rows 233 to 562, rows 563 to 1024, rows 1025 to 1486, rows 1487 to 1816, rows 1817 to 1981, rows 1982 to 2036, rows 2037 to 2047, and row 2048, corresponding to bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, and 11 of 0 and bits 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, and 0 of 1 in the result bit sequence, respectively. For regions corresponding to multiple rows, there is no ordering requirement for the output sequences within the region. That is, swapping the result bit sequence within the region does not affect PCS performance. In particular, in Table 28, the first bit of the result bit sequence is set as the least significant bit, the 11th bit is set as the most significant bit, and the values ​​of the result bit sequence are sorted from small to large within the region.

[0611] The number of index bit sequences in the above multiple index bit sequences is X≤2 N , and X≤2 Y .

[0612] Optionally, the number of bits in each of the multiple intermediate bit sequences is u, and the u-th bit of the intermediate bit sequence is the most significant bit; the multiple intermediate bit sequences include different intermediate bit sequences with different t-th bits. 1 < t = u; or 1 < t < u, and any bit from the t+1th bit to the u-th bit of the multiple intermediate bit sequences is the same. In this case, the first sequence processing device can use multiple methods to perform distribution matching processing on any intermediate bit sequence in the multiple intermediate bit sequences.

[0613] For example, when the first sequence processing device adopts the first method to perform distribution matching processing on any intermediate bit sequence among multiple intermediate bit sequences, it can use the first result bit sequence corresponding to the first index bit sequence in the multiple index bit sequences as the target bit sequence corresponding to the intermediate bit sequence based on the one-to-one correspondence between the multiple index bit sequences and the multiple result bit sequences; the first index bit sequence includes: a valid bit segment consisting of the 1st to t-1th bits in the intermediate bit sequence.

[0614] As another example, when the first sequence processing device uses the second method to perform distribution matching processing on any intermediate bit sequence among multiple intermediate bit sequences, when the t-th bit of the intermediate bit sequence is a target class bit, the first sequence processing device, based on a one-to-one correspondence between multiple index bit sequences and multiple result bit sequences, uses a first result bit sequence corresponding to a first index bit sequence among the multiple index bit sequences as the target bit sequence corresponding to the intermediate bit sequence; the first index bit sequence includes: a valid bit segment consisting of bits 1 to t-1 in the intermediate bit sequence; the target class bit is a 0 bit or a 1 bit; when the t-th bit is not a target class bit, the first sequence processing device performs inversion processing on the valid bit segment (the inversion processing is used to update a 0 bit to a 1 bit, and vice versa); thereafter, the first sequence processing device obtains a second result bit sequence corresponding to a second index bit sequence among the multiple index bit sequences based on the one-to-one correspondence between the multiple index bit sequences and the multiple result bit sequences (the second index bit sequence includes: the valid bit segment after the inversion processing), and performs inversion processing on the second result bit sequence to obtain the target bit sequence corresponding to the intermediate bit sequence.

[0615] In the second distributed matching process, in the one-to-one correspondence between multiple index bit sequences and multiple result bit sequences, fewer index bit sequences can be used. Therefore, the index bit sequences and their corresponding result bit sequences that are not used in the correspondence can be deleted from the correspondence. In this way, the number of index bit sequences and the number of result bit sequences in the correspondence can be smaller.

[0616] For example, the one-to-one correspondence between multiple index bit sequences and multiple result bit sequences under the second distributed matching processing method may be less than the one-to-one correspondence between multiple index bit sequences and multiple result bit sequences under the first distributed matching processing method. Furthermore, the one-to-one correspondence between multiple index bit sequences and multiple result bit sequences under the second distributed matching processing method may be greater than or equal to half the one-to-one correspondence between multiple index bit sequences and multiple result bit sequences under the first distributed matching processing method.

[0617] For example, in the process of obtaining the target bit sequence based on the intermediate bit sequence, the searched Table 27 can be replaced by the following Table 30, and the searched Table 28 can be replaced by the following Table 31. Furthermore, when searching Tables 30 and 31, the aforementioned second method can be used to perform distribution matching processing on any intermediate bit sequence among the multiple intermediate bit sequences. Table 30 includes the result bit sequence of the upper half of Table 27, and Table 30 can also be replaced by a table including the result bit sequence of the lower half of Table 27; Table 31 includes the result bit sequence of the upper half of Table 28, and Table 31 can also be replaced by a table including the result bit sequence of the lower half of Table 28.

[0618] Table 30

[0619] Table 31

[0620] Assume that the most significant bit among the middle bits is the t-th bit in the order of bits from low to high. Take lookup table 30 as an example. As shown in Table 30, the table has 512 rows, each row having a 9-bit index bit sequence and a 10-bit result bit sequence, and the index bit sequence and result bit sequence of any two rows are different.

[0621] When looking up table 30, if the most significant bit of the intermediate bit sequence is 0, then directly look up table 30 based on the sequence composed of bits in the intermediate bit sequence except the most significant bit, to obtain a result bit sequence, and use the result bit sequence as the target bit sequence corresponding to the intermediate bit sequence.

[0622] If the highest-order bit of the intermediate bit sequence is 1, the sequence consisting of the bits other than the highest-order bit in the intermediate bit sequence is inverted, and a result bit sequence is obtained by looking up the bit sequence table 30 based on the inverted bit sequence. The result bit sequence is then inverted, and the bit sequence obtained by the inverted bit sequence is used as the target bit sequence corresponding to the intermediate bit sequence.

[0623] The method of looking up table 31 is similar to that of looking up table 30 and will not be described in detail in this embodiment of the present application.

[0624] The number of index bit sequences X ≥ 2 (u-t-1) .

[0625] It can be understood that the one-to-one correspondence between multiple index bit sequences and multiple result bit sequences under the second distribution matching processing method can also be the same as the one-to-one correspondence between multiple index bit sequences and multiple result bit sequences under the first distribution matching processing method.

[0626] In general, the value of the number X of index bit sequences is divided into the following three cases.

[0627] The first case, X>2 (u-t) , at this time there is an index bit sequence that will not be found. When the number of bits Y in the index bit sequence exceeds ut (there are an additional Yut fixed bits), when looking up the table, the valid bit segment composed of the 1st to t-1th bits in the intermediate bit sequence and the additional Yut fixed bits can be combined to obtain a new bit sequence, and then the bit sequence is compared with multiple index bit sequences to find the corresponding index bit sequence and its corresponding result bit sequence. Among them, the above-mentioned additional Yut fixed bits can be the same as or different from the ut fixed bits in the intermediate bit sequence. When Y=u, when looking up the table, the intermediate bit sequence can be directly compared with multiple index bit sequences to find the corresponding index bit sequence and its corresponding result bit sequence. It can be seen that in the first case, the distribution matching processing of the first method mentioned above can be used to find the target bit sequence.

[0628] The second case, X = 2 (u-t) , there are no index bit sequences that will not be found. In this case, Y can be equal to ut. When looking up the table, the valid bit segment from bit 1 to bit t-1 in the intermediate bit sequence is directly compared with multiple index bit sequences to find the corresponding index bit sequence and its corresponding result bit sequence. Therefore, in the second case, the distribution matching process described in the first method can be used to find the target bit sequence.

[0629] The third case, 2 (u-t-1) ≤X<2 (u-t) In this case, the number of index bit sequences is small, and all rows in the table match at least half of all possible intermediate bit sequences. In this case, the number of bits Y in the index bit sequence can be ut-1. In the third case, the distribution matching process described in the second method can be used to find the target bit sequence.

[0630] Since the operation performed by the second sequence processing device is inverse to the operation performed by the first sequence processing device, the second sequence processing device can also use multiple methods to perform the inverse process of the distribution matching process on any target bit sequence among the multiple target bit sequences.

[0631] For example, if the number of bits in the intermediate bit sequence is equal to the number of bits in the index bit sequence, the first method can be used to perform the inverse distribution matching processing on the target bit sequence; if the number of bits in the intermediate bit sequence is less than the number of bits in the result bit sequence, the second method can be used to perform the inverse distribution matching processing on the target bit sequence.

[0632] When the first method is used to perform the inverse processing of the distribution matching processing on the target bit sequence, the first index bit sequence corresponding to the first result bit sequence in the multiple result bit sequences can be used as the intermediate bit sequence corresponding to the target bit sequence based on the one-to-one correspondence between the multiple index bit sequences and the multiple result bit sequences; the first result bit sequence includes: the target bit sequence.

[0633] When the second method is used to perform the inverse processing of the distribution matching processing on the target bit sequence, the above-mentioned first index bit sequence can be inverted, and then the target class bit (or the target class bit and at least one fixed bit in sequence) can be added after the highest bit to obtain the intermediate bit sequence corresponding to the target bit sequence.

[0634] The values ​​of the second-category bit segments in the multiple intermediate bit sequences depend on the values ​​of the first-category bit segments in the multiple bit subsequences, and each intermediate bit sequence is associated with each bit subsequence. When the first-category bit segment in any bit subsequence in the multiple bit subsequences changes, the values ​​of the second-category bit segments in the multiple intermediate bit sequences also change. The first sequence processing device will take into account the values ​​of the first-category bit segments in the multiple bit subsequences and determine the values ​​of the second-category bit segments in the multiple intermediate bit sequences based on a global consideration, so that the resulting values ​​of the intermediate bit sequences are more conducive to improving signal transmission performance.

[0635] For example, the bit subsequence includes a first type of bit segment, and the intermediate bit sequence includes a second type of bit segment. The above-mentioned multiple bit subsequences include: a first bit subsequence and a second bit subsequence, each bit subsequence in the multiple bit subsequences includes a first type of bit segment (also called a decision bit segment), and the number of bits in the first type of bit segment is greater than or equal to 1. The first type of bit segment in the bit subsequence may include the most significant bit in the bit subsequence, or may not include the most significant bit, which is not limited in this application. For example, assuming that the first bit subsequence includes a first type of bit segment D1, and the second bit subsequence includes a first type of bit segment D2; the first type of bit segment D1 is a higher-order bit segment in the first bit subsequence, and the first type of bit segment D1 includes the most significant bit in the first bit subsequence; the first type of bit segment D2 is a higher-order bit segment in the second bit subsequence, and the first type of bit segment D2 includes the most significant bit in the second bit subsequence. The first type of bit segment in the bit subsequence may be continuous bits or non-continuous bits in the intermediate bit sequence.

[0636] The second type of bit segment includes the most significant bit in the intermediate bit sequence; the second type of bit segment in the intermediate bit sequence may be a continuous bit including the most significant bit in the intermediate bit sequence. The above-mentioned multiple intermediate bit sequences include: a first intermediate bit sequence and a second intermediate bit sequence, each of the multiple intermediate bit sequences includes a second type of bit segment (also called an extended bit segment), and the second type of bit segment in the intermediate bit sequence includes the most significant bit in the intermediate bit sequence. The second type of bit segment in the intermediate bit sequence may be a continuous bit including the most significant bit in the intermediate bit sequence. For example, the first intermediate bit sequence includes a second type of bit segment E1, and the second intermediate bit sequence includes a second type of bit segment E2; the second type of bit segment E1 is a higher-order bit segment in the first intermediate bit sequence, and the second type of bit segment E1 includes the most significant bit in the first intermediate bit sequence; the second type of bit segment E2 is a higher-order bit segment in the second intermediate bit sequence, and the second type of bit segment E2 includes the most significant bit in the second intermediate bit sequence.

[0637] The value of the first type of bit segment in the first bit subsequence is a first numerical value, and the value of the first type of bit segment in the second bit subsequence is a second numerical value; the value of the second type of bit segment in the first intermediate bit sequence is a third numerical value, and the value of the second type of bit segment in the second intermediate bit sequence is a fourth numerical value. The absolute value of the difference between the first numerical value and the second numerical value is less than the absolute value of the difference between the third numerical value and the fourth numerical value; the third numerical value is greater than the first numerical value and the second numerical value, and the fourth numerical value is less than the first numerical value and the second numerical value.

[0638] Of course, the first value, the second value, the third value, and the fourth value may not satisfy this relationship, and this is not limited in the embodiments of the present application. For example, the absolute value of the difference between the first value and the second value may be equal to the absolute value of the difference between the third value and the fourth value. The third value may be less than or equal to the first value or the second value, and the fourth value may be greater than or equal to the first value or the second value.

[0639] Assuming that the amplitude bit (amplitude bit of the symbol) to which the 0 bits in the result bit sequence are mapped is higher, if the number of 0 bits in the result bit sequence is larger, the more symbols with higher amplitude bits are obtained by modulating the result bit sequence, and the worse the signal transmission effect is. Therefore, in the related art, before searching for the sequence in the table, 0 bits are added to the end of the bit sequence to lock the bit sequence in the index bit sequence with fewer 0 bits in the corresponding result bit sequence among multiple index bit sequences. Then, the number of 0 bits in the result bit sequence found in the table according to the bit sequence after adding 0 bits is smaller, which is conducive to improving the transmission effect of the signal. However, the sending node usually performs PCS processing on multiple bit sequences in parallel, and then merges the multiple bit sequences obtained after PCS processing and outputs them. When the sending node performs PCS processing on multiple bit sequences in parallel, in some cases, the total number of 0 bits in the merged bit sequence is still relatively large.

[0640] Assume that the value of the sequence obtained by padded with 0 bits after the most significant bit (one bit higher than the most significant bit) of the first bit subsequence is the fifth value, and the value of the sequence obtained by padded with 0 bits after the most significant bit of the second bit subsequence is the sixth value. Then, the absolute value of the difference between the first and second values ​​is less than the absolute value of the difference between the third and fourth values; if the third value is greater than the first and second values, and the fourth value is less than the first and second values, the absolute value of the difference between the fifth and sixth values ​​is less than the absolute value of the difference between the third and fourth values; and if the third value is greater than the fifth and sixth values, and the fourth value is less than the fifth and sixth values.

[0641] Take the example that 0 bits will be mapped to higher amplitude bits and 1 bits will be mapped to lower amplitude bits. Assume that the above distribution matching process is implemented by a lookup table, and the table searched in the lookup table includes a one-to-one correspondence between multiple index bit sequences and multiple result bit sequences, and the number of 0 bits in the result bit sequence corresponding to the multiple index bit sequences is positively correlated with the value of the index bit sequence. Then, the number of 0 bits in the result bit sequence obtained by searching the table according to the sequence obtained by directly filling 0 bits after the highest bit of the first bit subsequence is the first number, and the number of 0 bits in the result bit sequence obtained by searching the table according to the sequence obtained by directly filling 0 bits after the highest bit of the second bit subsequence is the second number; the number of 0 bits in the result bit sequence (target bit sequence) obtained by searching the table according to the first intermediate bit sequence is the third number, and the number of 0 bits in the result bit sequence (target bit sequence) obtained by searching the table according to the fourth intermediate bit sequence is the fourth number; the sum of the third number and the fourth number is less than the sum of the first number and the second number. In this way, after merging the two target bit sequences, a bit sequence with fewer 0 bits can be obtained, which is conducive to improving the transmission effect of the signal.

[0642] In the embodiment of the present application, the absolute value of the difference between the first and second values ​​is less than the absolute value of the difference between the third and fourth values; the third value is greater than the first and second values, and the fourth value is less than the first and second values. Of course, the first, second, third and fourth values ​​may not satisfy this relationship, and the embodiment of the present application does not limit this. The absolute value of the difference between the first and second values ​​may also be equal to the absolute value of the difference between the third and fourth values. The third value may also be less than or equal to the first or second value, and the fourth value may also be greater than or equal to the first or second value. For example, the first value is equal to the third value, and the second value is equal to the third value.

[0643] In the embodiment of the present application, the absolute value of the difference between the first and second values ​​is less than the absolute value of the difference between the third and fourth values, and the third value is greater than the first and second values, and the fourth value is less than the first and second values. It is understandable that the absolute value of the difference between the first and second values ​​may also be equal to the absolute value of the difference between the third and fourth values; the third value may also be less than or equal to the first and second values; and the fourth value may also be greater than or equal to the first and second values. In other words, at least one of the three conditions that the absolute value of the difference between the first and second values ​​is less than the absolute value of the difference between the third and fourth values, the third value is greater than the first and second values, and the fourth value is less than the first and second values ​​is satisfied, or none of the three conditions are satisfied.

[0644] Furthermore, the bit subsequences further include a third type of bit segments (also called to-be-reallocated bit segments) in addition to the first type of bit segments; and the intermediate bit sequences further include a fourth type of bit segments (also called reallocated bit segments) in addition to the second type of bit segments. The fourth type of bit segments in the plurality of intermediate bit sequences include bits in the third type of bit segments in the plurality of bit subsequences.

[0645] For example, the first bit subsequence includes, in addition to the first type of bit segment D1, a third type of bit segment f1; the second bit subsequence includes, in addition to the first type of bit segment D2, a third type of bit segment f2; the first intermediate bit sequence includes, in addition to the second type of bit segment E1, a fourth type of bit segment F1; and the second intermediate bit sequence includes, in addition to the second type of bit segment E2, a fourth type of bit segment F2. Furthermore, the fourth type of bit segment F1 and the fourth type of bit segment F2 comprise the bits in the third type of bit segment f1 and the third type of bit segment f2.

[0646] Optionally, when multiple intermediate bit sequences correspond one-to-one to multiple bit subsequences, the fourth type of bit segment in each of the multiple intermediate bit sequences includes bits in the third type of bit segment in the bit subsequence corresponding to the intermediate bit sequence. Furthermore, the fourth type of bit segment in the intermediate bit sequence includes bits in the third type of bit segment in the bit subsequence corresponding to the intermediate bit sequence.

[0647] The multiple fourth-category bit segments in the multiple intermediate bit sequences may or may not include third-category bit segments. In other words, a third-category bit segment may serve as all or part of a fourth-category bit segment in an intermediate bit sequence, or bits in the third-category bit segment may be scattered and used as all or part of the fourth-category bit segments in multiple intermediate bit sequences.

[0648] Furthermore, the number of bits in the above-mentioned to-be-processed bit sequence, the bit sequence obtained after merging, the bit subsequence, and the intermediate bit sequence may be in various situations.

[0649] For example, the number of bits in the to-be-processed bit sequence is 116, and the number of bits in the bit sequence obtained after merging is 128. The to-be-processed bit sequence is divided into 12 bit subsequences, and the number of bits in the 12 bit subsequences is 9, 9, 9, 10, 10, 10, 10, 10, 10, and 10, respectively; the number of bits in the intermediate bit sequence is 10, 10, 10, 10, 11, 11, 11, 11, 11, 11, 11, 11; two intermediate bit sequences with a bit number of 10 are obtained based on two bit subsequences with a bit number of 9; two intermediate bit sequences with a bit number of 11 are obtained based on two bit subsequences with a bit number of 10;

[0650] Alternatively, the number of bits in the to-be-processed bit sequence is 106, the number of bits in the bit sequence obtained after merging is 128, the to-be-processed bit sequence is divided into 12 bit subsequences, and the numbers of bits in the 12 bit subsequences are 9, 9, 8, 8, 9, 9, 9, 9, 9, 9, and 9, respectively; the numbers of bits in the intermediate bit sequences are 10, 10, 10, 10, 11, 11, 11, 11, 11, 11, 11, 11; two intermediate bit sequences with a number of 10 bits are obtained from two bit subsequences with a number of 8 bits; in a portion of the bit subsequences with a number of 9 bits, two intermediate bit sequences with a number of 10 bits are obtained from two bit subsequences with a number of 9 bits; and in another portion of the bit subsequences with a number of 9 bits, two intermediate bit sequences with a number of 11 bits are obtained from two bit subsequences with a number of 9 bits;

[0651] Alternatively, the number of bits in the to-be-processed bit sequence is 72, the number of bits in the bit sequence obtained after merging is 128, the to-be-processed bit sequence is divided into 12 bit subsequences, and the number of bits in each of the 12 bit subsequences is 6; the number of bits in the 12 intermediate bit sequences is 10, 10, 10, 10, 11, 11, 11, 11, 11, 11, 11, 11; in a portion of the bit subsequences with 6 bits, two intermediate bit sequences with 10 bits are obtained based on two bit subsequences with 6 bits; in another portion of the bit subsequences with 6 bits, two intermediate bit sequences with 11 bits are obtained based on two bit subsequences with 6 bits;

[0652] The number of bits in the to-be-processed bit sequence is 116, and the number of bits in the bit sequence obtained after merging is 128; the to-be-processed bit sequence is divided into 12 bit subsequences; the number of bits in the 12 bit subsequences is 9, 9, 9, 10, 10, 10, 10, 10, 10, 10, and 10, respectively; the number of bits in the intermediate bit sequences is 10, 10, 10, 10, 11, 11, 11, and 11, respectively; four intermediate bit sequences with a number of 10 bits are obtained based on four bit subsequences with a number of 9 bits, and four intermediate bit sequences with a number of 11 bits are obtained based on four bit subsequences with a number of 10 bits;

[0653] Alternatively, the number of bits in the to-be-processed bit sequence is 106, the number of bits in the bit sequence obtained after merging is 128, the to-be-processed bit sequence is divided into 12 bit subsequences, the numbers of bits in the 12 bit subsequences are 8, 8, 9, 9, 9, 9, 9, 9, 9, 9, and 9, respectively; the numbers of bits in the intermediate bit sequences are 10, 10, 10, 10, 11, 11, 11, 11, 11, 11, 11, 11; four intermediate bit sequences each with 10 bits are obtained based on two bit subsequences each with 8 bits and two bit sequences each with 9 bits; four intermediate bit sequences each with 11 bits are obtained based on four bit subsequences each with 9 bits;

[0654] Alternatively, the number of bits in the bit sequence to be processed is 72, the number of bits in the bit sequence obtained after merging is 128, the bit sequence to be processed is divided into 12 bit subsequences, and the number of bits in each of the 12 bit subsequences is 6; the number of bits in the 12 intermediate bit sequences is 10, 10, 10, 10, 11, 11, 11, 11, 11, 11, 11; in a part of the bit subsequences with 6 bits, 4 intermediate bit sequences with 10 bits are obtained based on 4 bit subsequences with 6 bits; in another part of the bit subsequences with 6 bits, 4 intermediate bit sequences with 11 bits are obtained based on 4 bit subsequences with 6 bits.

[0655] The present embodiment does not limit the order of the bit subsequences. Accordingly, the order of the intermediate bit sequences obtained based on the bit subsequences is also not limited. Furthermore, elements in a bit subsequence may or may not be continuous within the bit sequence to be processed, and multiple bit subsequences may or may not be continuous within the bit sequence to be processed.

[0656] The sequence processing method provided in the embodiments of the present application will be further illustrated below through the following examples. In the following examples, the bits in each bit sequence are arranged from left to right in order from low to high bit position, and the xth bit in the bit sequence is lower than the x+1th bit, and x ≥ 1.

[0657] Example 1: As shown in FIG6 , the number of bits in the to-be-processed bit sequence is 116, and the number of bits in the bit sequence obtained after merging is 128.

[0658] The bit sequence to be processed is divided into 12 bit subsequences, the bits in the bit subsequences are continuous in the bit sequence to be processed, and the rth bit subsequence and the r+1th bit subsequence in the 12 bit subsequences are continuous in the bit sequence to be processed, and r≥1; the numbers of bits in the 1st to 12th bit subsequences in the 12 bit subsequences are 9, 9, 9, 9, 10, 10, 10, 10, 10, 10, 10, and 10, respectively.

[0659] Among the 12 bit subsequences, every two consecutive bit subsequences in the bit sequence to be processed constitute an initial bit sequence, and the 12 bit subsequences constitute a total of 6 initial bit sequences. Moreover, among the 6 initial bit sequences, the sth initial bit sequence and the s+1th initial bit sequence are consecutive in the bit sequence to be processed, and s≥1.

[0660] As shown in Figure 6, the bit subsequence represents the p-th bit subsequence in the m-th initial bit sequence (also called initial bit sequence m), m≥1, p≥1. For example, represents the first bit subsequence in the first initial bit sequence, Represents the second bit subsequence in the first initial bit sequence. represents the first bit subsequence in the second initial bit sequence, Represents the second bit subsequence in the second initial bit sequence. Similarly, the embodiments of the present application are not described in detail here.

[0661] k[B:C] represents: bit subsequence Includes A bits, which are bits B to C in the bit sequence to be processed. A>1, 1≤B<C. For example, k[1:9] represents: bit subsequence It includes 9 bits, which are the 1st bit to the 9th bit in the bit sequence to be processed. k[10:18] represents: bit subsequence The 9 bits are from the 10th bit to the 18th bit in the bit sequence to be processed.

[0662] The first sequence processing device needs to perform bit processing 1 on initial bit sequence 1, bit processing 2 on initial bit sequence 2, bit processing 3 on initial bit sequence 3, bit processing 4 on initial bit sequence 4, bit processing 5 on initial bit sequence 5, and bit processing 6 on initial bit sequence 6. The first sequence processing device obtains intermediate bit sequences with the following number of bits, respectively, from the first to sixth initial bit sequences of the six initial bit sequences: 10, 10, 11, 11, 11, and 11. The first sequence processing device can obtain two intermediate bit sequences from each of the six initial bit sequences. The number of bits in the two intermediate bit sequences obtained by the first sequence processing apparatus based on the first initial bit sequence is both 10; the number of bits in the two intermediate bit sequences obtained by the first sequence processing apparatus based on the second initial bit sequence is both 10; the number of bits in the two intermediate bit sequences obtained by the first sequence processing apparatus based on the third initial bit sequence is both 11; the number of bits in the two intermediate bit sequences obtained by the first sequence processing apparatus based on the fourth initial bit sequence is both 11; the number of bits in the two intermediate bit sequences obtained by the first sequence processing apparatus based on the fifth initial bit sequence is both 11; and the number of bits in the two intermediate bit sequences obtained by the first sequence processing apparatus based on the sixth initial bit sequence is both 11.

[0663] As shown in FIG6 , the first sequence processing device performs bit processing on the mth initial bit sequence, and the obtained qth intermediate bit sequence is expressed as q≥1. express: It includes D bits, D>1. For example, the first sequence processing device performs bit processing on the first initial bit sequence, and the obtained first intermediate bit sequence is expressed as express: The first sequence processing device performs bit processing on the first initial bit sequence, and the obtained second intermediate bit sequence is expressed as express: The embodiment of the present application will not be described in detail here.

[0664] The first sequence processing device can query the extended table based on the first type of bit segments in multiple subsequences of the initial bit sequence to obtain the second type of bit segments in multiple intermediate bit sequences. The first sequence processing device can also obtain the fourth type of bit segments in multiple intermediate bit sequences based on the third type of bit segments in the multiple subsequences. In this way, multiple intermediate bit sequences can be obtained.

[0665] In the process of the first sequence processing device obtaining the intermediate bit sequence according to different initial bit sequences, the queried extension tables may be the same or different.

[0666] For example, the above bit subsequence and In each bit subsequence in , the first type of bit segment includes the 8th to 9th bits from left to right in the bit subsequence (expressed as [8:9]), and the third type of bit segment includes the 1st to 7th bits from left to right in the bit subsequence (expressed as [1:7]). and In each intermediate bit sequence in , the second type of bit segment includes the 8th bit to the 10th bit from left to right in the intermediate bit sequence (expressed as [8:10]), and the fourth type of bit segment includes the 1st bit to the 7th bit from left to right in the intermediate bit sequence (expressed as [1:7]). The first sequence processing device processes the bit subsequence according to the bit subsequence. By querying the extended tables shown in Table 4 and Table 5, we can obtain the intermediate bit sequence. The first sequence processing device processes the bit subsequence according to and By querying the extended tables shown in Tables 4 and 5, the intermediate bit sequence can be obtained. and

[0667] The above bit subsequence In each bit subsequence in , the first type of bit segment includes the 9th to 10th bits of the most significant bit in the bit subsequence from left to right (expressed as [9:10]), and the third type of bit segment includes the 1st to 8th bits of the most significant bit in the bit subsequence from left to right (expressed as [1:8]). In each intermediate bit sequence in , the second type of bit segment includes the 9th bit to the 11th bit from left to right in the intermediate bit sequence (expressed as [9:11]), and the fourth type of bit segment includes the 1st bit to the 8th bit from left to right in the intermediate bit sequence (expressed as [1:8]). The first sequence processing device processes the bit subsequence according to the bit subsequence. By querying the extended table shown in Table 3, we can get the intermediate bit sequence The first sequence processing device processes the bit subsequence according to By querying the extended table shown in Table 3, we can get the intermediate bit sequence The first sequence processing device processes the bit subsequence according to By querying the extended table shown in Table 3, we can get the intermediate bit sequence The first sequence processing device processes the bit subsequence according to By querying the extended table shown in Table 3, we can get the intermediate bit sequence

[0668] The first sequence processing device performs bit processing m on the mth initial bit sequence to obtain an intermediate bit sequence Here, it is taken as an example that the extended tables used in bit processing 1 to 2 are both used to indicate the one-to-one correspondence shown in Table 4 and Table 5, and the extended tables used in bit processing 3 to 6 are both used to indicate the one-to-one correspondence shown in Table 3.

[0669] The first sequence processing device performs bit processing on the mth initial bit sequence to obtain an intermediate bit sequence The distribution matching process performed is called distribution matching process mq. For example, the first sequence processing device performs bit processing on the first initial bit sequence, and the intermediate bit sequence obtained is The distribution matching process 1-1 is performed.

[0670] N[V:Z] represents the middle bit sequence Corresponding target bit sequence Including G bits, G>1, target bit sequence Including the Vth bit to the Zth bit in the combined bit sequence, 1≤V<Z. For example, N[1:10] represents the middle bit sequence Corresponding target bit sequence Contains 10 bits, target bit sequence Including the 1st bit to the 10th bit in the combined bit sequence. N[11:20] represents the middle bit sequence Corresponding target bit sequence Contains 10 bits, target bit sequence Including the 11th bit to the 20th bit in the combined bit sequence.

[0671] The first sequence processing device processes the intermediate bit sequence and When performing distribution matching processing on each intermediate bit sequence in to obtain the corresponding target bit sequence, the corresponding target bit sequence can be obtained by searching the table shown in Table 27. When performing distribution matching processing on each intermediate bit sequence in to obtain the corresponding target bit sequence, the corresponding target bit sequence can be obtained by looking up the table shown in Table 28.

[0672] After the bit sequence to be processed is processed using the solution of this example, the probability of the combined bit sequence being mapped to a high-amplitude bit is reduced to approximately 36.52%.

[0673] Example 2: As shown in FIG7 , the number of bits in the to-be-processed bit sequence is 106, and the number of bits in the bit sequence obtained after merging is 128.

[0674] The meanings of the various symbols in FIG7 can refer to the meanings of the various symbols in FIG6 , and are not described in detail in this application.

[0675] The bit sequence to be processed is divided into 12 bit subsequences, the bits in the bit subsequences are continuous in the bit sequence to be processed, and the rth bit subsequence and the r+1th bit subsequence in the 12 bit subsequences are continuous in the bit sequence to be processed, and r≥1; the numbers of bits in the 1st to 12th bit subsequences in the 12 bit subsequences are 9, 9, 8, 8, 9, 9, 9, 9, 9, 9, and 9, respectively.

[0676] Among the 12 bit subsequences, every two consecutive bit subsequences in the bit sequence to be processed constitute an initial bit sequence, and the 12 bit subsequences constitute a total of 6 initial bit sequences. Moreover, among the 6 initial bit sequences, the sth initial bit sequence and the s+1th initial bit sequence are consecutive in the bit sequence to be processed, and s≥1.

[0677] The first sequence processing device needs to perform bit processing 1 on initial bit sequence 1, bit processing 2 on initial bit sequence 2, bit processing 3 on initial bit sequence 3, bit processing 4 on initial bit sequence 4, bit processing 55 on initial bit sequence 5, and bit processing 6 on initial bit sequence 6. The first sequence processing device obtains intermediate bit sequences with the following number of bits, respectively, from the first to sixth initial bit sequences of the six initial bit sequences: 10, 10, 11, 11, 11, and 11. The first sequence processing device can obtain two intermediate bit sequences from each of the six initial bit sequences. The number of bits in the two intermediate bit sequences obtained by the first sequence processing apparatus based on the first initial bit sequence is both 10; the number of bits in the two intermediate bit sequences obtained by the first sequence processing apparatus based on the second initial bit sequence is both 10; the number of bits in the two intermediate bit sequences obtained by the first sequence processing apparatus based on the third initial bit sequence is both 11; the number of bits in the two intermediate bit sequences obtained by the first sequence processing apparatus based on the fourth initial bit sequence is both 11; the number of bits in the two intermediate bit sequences obtained by the first sequence processing apparatus based on the fifth initial bit sequence is both 11; and the number of bits in the two intermediate bit sequences obtained by the first sequence processing apparatus based on the sixth initial bit sequence is both 11.

[0678] The first sequence processing device can query the extended table based on the first type of bit segments in multiple subsequences of the initial bit sequence to obtain the second type of bit segments in multiple intermediate bit sequences. The first sequence processing device can also obtain the fourth type of bit segments in multiple intermediate bit sequences based on the third type of bit segments in the multiple subsequences. In this way, multiple intermediate bit sequences can be obtained.

[0679] When the first sequence processing device derives intermediate bit sequences from different initial bit sequences, the extended tables queried can be the same or different. Furthermore, in each bit subsequence, the first type of bit segment includes the two most significant bits of the bit subsequence, and the third type of bit segment includes all bits of the bit subsequence excluding these two bits. In each intermediate bit sequence, the second type of bit segment includes the three most significant bits of the intermediate bit sequence, and the fourth type of bit segment includes all bits of the intermediate bit sequence excluding these three bits.

[0680] For example, the above bit subsequence In each bit subsequence in , the first type of bit segment includes the 8th bit to the 9th bit from left to right in the bit subsequence (expressed as [8:9]), and the third type of bit segment includes the 1st bit to the 7th bit from left to right in the bit subsequence (expressed as [1:7]).

[0681] The above bit subsequence and In each bit subsequence in , the first type of bit segment includes the 7th bit to the 8th bit from left to right in the bit subsequence (expressed as [7:8]), and the third type of bit segment includes the 1st bit to the 6th bit from left to right in the bit subsequence (expressed as [1:6]).

[0682] The above intermediate bit sequence and In each intermediate bit sequence in the , the second type of bit segment includes the 7th bit to the 10th bit from left to right in the intermediate bit sequence (expressed as [7:10]), and the fourth type of bit segment includes the 1st bit to the 6th bit from left to right in the intermediate bit sequence (expressed as [1:6]).

[0683] The above intermediate bit sequence In each intermediate bit sequence in the , the second type of bit segment includes the 8th bit to the 11th bit from left to right in the intermediate bit sequence (expressed as [8:11]), and the fourth type of bit segment includes the 1st bit to the 7th bit from left to right in the intermediate bit sequence (expressed as [1:7]).

[0684] The first sequence processing device performs bit processing m on the mth initial bit sequence to obtain an intermediate bit sequence Here, the example is taken as follows: the extended tables used in bit processing 1 are all used to indicate the one-to-one correspondence shown in Table 4 and Table 5, the extended tables used in bit processing 2 are all used to indicate the one-to-one correspondence shown in Table 6 and Table 7, and the extended tables used in bit processing 3 to 6 are all used to indicate the one-to-one correspondence shown in Table 8 and Table 9.

[0685] The first sequence processing device processes the intermediate bit sequence and When performing distribution matching processing on each intermediate bit sequence in to obtain the corresponding target bit sequence, the corresponding target bit sequence can be obtained by searching the table shown in Table 27. When performing distribution matching processing on each intermediate bit sequence in to obtain the corresponding target bit sequence, the corresponding target bit sequence can be obtained by looking up the table shown in Table 28.

[0686] After the bit sequence to be processed is processed using the solution of this example, the probability of the combined bit sequence being mapped to a high-amplitude bit is reduced to approximately 30.69%.

[0687] Example 3: As shown in FIG8 , the number of bits in the to-be-processed bit sequence is 72, and the number of bits in the bit sequence obtained after merging is 128.

[0688] The meanings of the various symbols in FIG8 can refer to the meanings of the various symbols in FIG6 , and are not described in detail in this application.

[0689] Referring to FIG8 , the bit sequence to be processed is divided into 12 bit subsequences. The bits in the bit subsequences are continuous in the bit sequence to be processed, and the rth bit subsequence and the r+1th bit subsequence in the 12 bit subsequences are continuous in the bit sequence to be processed, where r ≥ 1. In the 12 bit subsequences, every two consecutive bit subsequences in the bit sequence to be processed constitute an initial bit sequence. In the six initial bit sequences composed of the 12 bit subsequences, the sth initial bit sequence and the s+1th initial bit sequence are continuous in the bit sequence to be processed, where s ≥ 1. The number of bits in the first to twelfth bit subsequences in the 12 bit subsequences is 6. The numbers of bits in the intermediate bit sequences obtained from the first to sixth initial bit sequences in the six initial bit sequences are 10, 10, 11, 11, 11, and 11, respectively. The first sequence processing device can obtain two intermediate bit sequences based on each of the six initial bit sequences. The number of bits in the two intermediate bit sequences obtained by the first sequence processing apparatus based on the first initial bit sequence is both 10; the number of bits in the two intermediate bit sequences obtained by the first sequence processing apparatus based on the second initial bit sequence is both 10; the number of bits in the two intermediate bit sequences obtained by the first sequence processing apparatus based on the third initial bit sequence is both 11; the number of bits in the two intermediate bit sequences obtained by the first sequence processing apparatus based on the fourth initial bit sequence is both 11; the number of bits in the two intermediate bit sequences obtained by the first sequence processing apparatus based on the fifth initial bit sequence is both 11; and the number of bits in the two intermediate bit sequences obtained by the first sequence processing apparatus based on the sixth initial bit sequence is both 11.

[0690] The first sequence processing module can query the extended table based on the first type of bit segments in multiple subsequences in the initial bit sequence to obtain the second type of bit segments in multiple intermediate bit sequences. The first sequence processing module can also obtain the fourth type of bit segments in multiple intermediate bit sequences based on the third type of bit segments in the multiple subsequences. In this way, multiple intermediate bit sequences can be obtained based on the initial bit sequence.

[0691] In the process of the first sequence processing device obtaining the intermediate bit sequence according to different initial bit sequences, the queried extension tables may be the same or different.

[0692] For example, the above bit subsequence In each bit subsequence in , the first type of bit segment includes the 5th bit to the 6th bit from left to right in the bit subsequence (expressed as [5:6]), and the third type of bit segment includes the 1st bit to the 4th bit from left to right in the bit subsequence (expressed as [1:4]).

[0693] The above intermediate bit sequence In each intermediate bit sequence in the , the second type of bit segment includes the 5th bit to the 10th bit from left to right in the intermediate bit sequence (expressed as [5:10]), and the fourth type of bit segment includes the 1st bit to the 4th bit from left to right in the intermediate bit sequence (expressed as [1:4]).

[0694] The above intermediate bit sequence In each intermediate bit sequence in the , the second type of bit segment includes the 5th bit to the 11th bit from left to right in the intermediate bit sequence (expressed as [5:11]), and the fourth type of bit segment includes the 1st bit to the 4th bit from left to right in the intermediate bit sequence (expressed as [1:4]).

[0695] The first sequence processing device performs bit processing m on the mth initial bit sequence to obtain an intermediate bit sequence Here, it is taken as an example that the extended tables used in bit processing 1 and 2 are both used to indicate the one-to-one correspondence shown in Table 10 and Table 11, and the extended tables used in bit processing 3 to 6 are both used to indicate the one-to-one correspondence shown in Table 12 and Table 13.

[0696] The first sequence processing module processes the intermediate bit sequence When performing distribution matching processing on each intermediate bit sequence in to obtain the corresponding target bit sequence, the corresponding target bit sequence can be obtained by searching the table shown in Table 27. When performing distribution matching processing on each intermediate bit sequence in to obtain the corresponding target bit sequence, the corresponding target bit sequence can be obtained by looking up the table shown in Table 28.

[0697] After the bit sequence to be processed is processed using the solution of this example, the probability of the combined bit sequence being mapped to a high-amplitude bit is reduced to approximately 17.11%.

[0698] Example 4: As shown in FIG9 , the number of bits in the to-be-processed bit sequence is 116, and the number of bits in the bit sequence obtained after merging is 128.

[0699] The meanings of the various symbols in FIG9 can refer to the meanings of the various symbols in FIG6 , and are not described in detail in this application.

[0700] Referring to Figure 9, the bit sequence to be processed is divided into 12 bit subsequences, the bits in the bit subsequences are continuous in the bit sequence to be processed, and the rth bit subsequence and the r+1th bit subsequence in the 12 bit subsequences are continuous in the bit sequence to be processed, and r ≥ 1; in the 12 bit subsequences, every 4 consecutive bit subsequences in the bit sequence to be processed constitute an initial bit sequence, and in the three initial bit sequences composed of the 12 bit subsequences, the sth initial bit sequence and the s+1th initial bit sequence are continuous in the bit sequence to be processed, and s ≥ 1; the number of bits in the first to fourth bit subsequences in the 12 bit subsequences is 9, and the number of bits in the fifth to twelfth bit subsequences in the 12 bit subsequences is 10; the numbers of bits in the intermediate bit sequences obtained from the first to third initial bit sequences in the three initial bit sequences are 10, 11, and 11, respectively. The first sequence processing device can obtain four intermediate bit sequences based on each of the three initial bit sequences. The number of bits in the four intermediate bit sequences obtained by the first sequence processing device based on the first initial bit sequence is 10; the number of bits in the four intermediate bit sequences obtained by the first sequence processing device based on the second initial bit sequence is 11; and the number of bits in the four intermediate bit sequences obtained by the first sequence processing device based on the third initial bit sequence is 11.

[0701] The first sequence processing module can query the extended table based on the first type of bit segments in multiple subsequences in the initial bit sequence to obtain the second type of bit segments in multiple intermediate bit sequences. The first sequence processing module can also obtain the fourth type of bit segments in multiple intermediate bit sequences based on the third type of bit segments in the multiple subsequences. In this way, multiple intermediate bit sequences can be obtained based on the initial bit sequence.

[0702] In the process of obtaining the intermediate bit sequence according to different initial bit sequences by the first sequence processing device, the query expansion table can be the same or different. The first sequence processing device performs bit processing m on the mth initial bit sequence to obtain the intermediate bit sequence Here, it is taken as an example that the extended tables used in bit processing 1 are used to indicate the one-to-one correspondence shown in Table 14 and Table 15, and the extended tables used in bit processing 2 to 3 are used to indicate the one-to-one correspondence shown in Table 16.

[0703] For example, the above bit subsequence In each bit subsequence in , the first type of bit segment includes the 8th to 9th bits from left to right in the bit subsequence (expressed as [8:9]), and the third type of bit segment includes the 1st to 7th bits from left to right in the bit subsequence (expressed as [1:7]). In each bit subsequence in , the first type of bit segment includes the 9th bit to the 10th bit from left to right in the bit subsequence (expressed as [9:10]), and the third type of bit segment includes the 1st bit to the 8th bit from left to right in the bit subsequence (expressed as [1:8]).

[0704] The above intermediate bit sequence In each intermediate bit sequence in the , the second type of bit segment includes the 8th bit to the 10th bit from left to right in the intermediate bit sequence (expressed as [8:10]), and the fourth type of bit segment includes the 1st bit to the 7th bit from left to right in the intermediate bit sequence (expressed as [1:7]).

[0705] The above intermediate bit sequence In each intermediate bit sequence in the , the second type of bit segment includes the 9th bit to the 11th bit from left to right in the intermediate bit sequence (expressed as [9:11]), and the fourth type of bit segment includes the 1st bit to the 8th bit from left to right in the intermediate bit sequence (expressed as [1:8]).

[0706] The first sequence processing module processes the intermediate bit sequence When performing distribution matching processing on each intermediate bit sequence in to obtain the corresponding target bit sequence, the corresponding target bit sequence can be obtained by searching the table shown in Table 27. When performing distribution matching processing on each intermediate bit sequence in to obtain the corresponding target bit sequence, the corresponding target bit sequence can be obtained by looking up the table shown in Table 28.

[0707] After the bit sequence to be processed is processed using the solution of this example, the probability of the combined bit sequence being mapped to a high-amplitude bit is reduced to approximately 35.57%.

[0708] Example 5: As shown in FIG10 , the number of bits in the to-be-processed bit sequence is 106, and the number of bits in the bit sequence obtained after merging is 128.

[0709] The meanings of the various symbols in FIG10 can refer to the meanings of the various symbols in FIG6 , and are not described in detail in this application.

[0710] Referring to Figure 10, the bit sequence to be processed is divided into 12 bit subsequences, the bits in the bit subsequences are continuous in the bit sequence to be processed, and the rth bit subsequence and the r+1th bit subsequence in the 12 bit subsequences are continuous in the bit sequence to be processed, and r ≥ 1; in the 12 bit subsequences, every 4 consecutive bit subsequences in the bit sequence to be processed constitute an initial bit sequence, and in the three initial bit sequences composed of the 12 bit subsequences, the sth initial bit sequence and the s+1th initial bit sequence are continuous in the bit sequence to be processed, and s ≥ 1; the number of bits from the first bit subsequence to the second bit subsequence in the 12 bit subsequences is 8, and the number of bits from the third bit subsequence to the twelfth bit subsequence in the 12 bit subsequences is 9; the numbers of bits in the intermediate bit sequences obtained from the first initial bit sequence to the third initial bit sequence in the three initial bit sequences are 10, 11, and 11, respectively. The first sequence processing device can obtain four intermediate bit sequences based on each of the three initial bit sequences. The number of bits in the four intermediate bit sequences obtained by the first sequence processing device based on the first initial bit sequence is 10; the number of bits in the four intermediate bit sequences obtained by the first sequence processing device based on the second initial bit sequence is 11; and the number of bits in the four intermediate bit sequences obtained by the first sequence processing device based on the third initial bit sequence is 11.

[0711] The first sequence processing module can query the extended table based on the first type of bit segments in multiple subsequences in the initial bit sequence to obtain the second type of bit segments in multiple intermediate bit sequences. The first sequence processing module can also obtain the fourth type of bit segments in multiple intermediate bit sequences based on the third type of bit segments in the multiple subsequences. In this way, multiple intermediate bit sequences can be obtained based on the initial bit sequence.

[0712] In the process of obtaining the intermediate bit sequence according to different initial bit sequences by the first sequence processing device, the query expansion table can be the same or different. The first sequence processing device performs bit processing m on the mth initial bit sequence to obtain the intermediate bit sequence Here, it is taken as an example that the extended tables used in bit processing 1 are used to indicate the one-to-one correspondence shown in Table 17 and Table 18, and the extended tables used in bit processing 2 to 3 are used to indicate the one-to-one correspondence shown in Table 19 and Table 20.

[0713] For example, the above bit subsequence In each bit subsequence in , the first type of bit segment includes the 8th bit from left to right in the bit subsequence (expressed as [8]), and the third type of bit segment includes the 1st bit to the 7th bit from left to right in the bit subsequence (expressed as [1:7]). In each bit subsequence in , the first type of bit segment includes the 8th bit to the 9th bit from left to right in the bit subsequence (expressed as [8:9]), and the third type of bit segment includes the 1st bit to the 7th bit from left to right in the bit subsequence (expressed as [1:7]).

[0714] The above intermediate bit sequence In each intermediate bit sequence in the , the second type of bit segment includes the 8th bit to the 10th bit from left to right in the intermediate bit sequence (expressed as [8:10]), and the fourth type of bit segment includes the 1st bit to the 7th bit from left to right in the intermediate bit sequence (expressed as [1:7]).

[0715] The above intermediate bit sequence In each intermediate bit sequence in the , the second type of bit segment includes the 8th bit to the 11th bit from left to right in the intermediate bit sequence (expressed as [8:11]), and the fourth type of bit segment includes the 1st bit to the 7th bit from left to right in the intermediate bit sequence (expressed as [1:7]).

[0716] The first sequence processing module processes the intermediate bit sequence When performing distribution matching processing on each intermediate bit sequence in to obtain the corresponding target bit sequence, the corresponding target bit sequence can be obtained by searching the table shown in Table 27. When performing distribution matching processing on each intermediate bit sequence in to obtain the corresponding target bit sequence, the corresponding target bit sequence can be obtained by looking up the table shown in Table 28.

[0717] After the bit sequence to be processed is processed using the solution of this example, the probability of the combined bit sequence being mapped to a high-amplitude bit is reduced to approximately 29.81%.

[0718] Example 6: As shown in FIG11 , the number of bits in the to-be-processed bit sequence is 72, and the number of bits in the bit sequence obtained after merging is 128.

[0719] The meanings of the various symbols in FIG11 can refer to the meanings of the various symbols in FIG6 , and are not described in detail in this application.

[0720] Referring to FIG. 11 , the bit sequence to be processed is divided into 12 bit subsequences. The bits in the bit subsequences are continuous in the bit sequence to be processed, and the rth bit subsequence and the r+1th bit subsequence in the 12 bit subsequences are continuous in the bit sequence to be processed, where r ≥ 1. Within the 12 bit subsequences, every four consecutive bit subsequences in the bit sequence to be processed constitute an initial bit sequence. Within the three initial bit sequences composed of the 12 bit subsequences, the sth initial bit sequence and the s+1th initial bit sequence are continuous in the bit sequence to be processed, where s ≥ 1. The number of bits in each of the 12 bit subsequences is 6. The numbers of bits in the intermediate bit sequences obtained from the first to third initial bit sequences of the three initial bit sequences are 10, 11, and 11, respectively. The first sequence processing device can obtain four intermediate bit sequences based on each of the three initial bit sequences. The number of bits in the four intermediate bit sequences obtained by the first sequence processing device based on the first initial bit sequence is 10; the number of bits in the four intermediate bit sequences obtained by the first sequence processing device based on the second initial bit sequence is 11; and the number of bits in the four intermediate bit sequences obtained by the first sequence processing device based on the third initial bit sequence is 11.

[0721] The first sequence processing module can query the extended table based on the first type of bit segments in multiple subsequences in the initial bit sequence to obtain the second type of bit segments in multiple intermediate bit sequences. The first sequence processing module can also obtain the fourth type of bit segments in multiple intermediate bit sequences based on the third type of bit segments in the multiple subsequences. In this way, multiple intermediate bit sequences can be obtained based on the initial bit sequence.

[0722] In the process of obtaining the intermediate bit sequence according to different initial bit sequences by the first sequence processing device, the query expansion table can be the same or different. The first sequence processing device performs bit processing m on the mth initial bit sequence to obtain the intermediate bit sequence Here, it is taken as an example that the extended tables used in bit processing 1 are used to indicate the one-to-one correspondence shown in Table 21 and Table 22, and the extended tables used in bit processing 2 to 3 are used to indicate the one-to-one correspondence shown in Table 23 and Table 24.

[0723] For example, the above bit subsequence In each bit subsequence in , the first type of bit segment includes the 5th bit to the 6th bit from left to right in the bit subsequence (expressed as [5:6]), and the third type of bit segment includes the 1st bit to the 4th bit from left to right in the bit subsequence (expressed as [1:4]).

[0724] The above intermediate bit sequence In each intermediate bit sequence in the , the second type of bit segment includes the 5th bit to the 10th bit from left to right in the intermediate bit sequence (expressed as [5:10]), and the fourth type of bit segment includes the 1st bit to the 4th bit from left to right in the intermediate bit sequence (expressed as [1:4]).

[0725] The above intermediate bit sequence In each intermediate bit sequence in the , the second type of bit segment includes the 5th bit to the 11th bit from left to right in the intermediate bit sequence (expressed as [5:11]), and the fourth type of bit segment includes the 1st bit to the 4th bit from left to right in the intermediate bit sequence (expressed as [1:4]).

[0726] The first sequence processing module processes the intermediate bit sequence When performing distribution matching processing on each intermediate bit sequence in to obtain the corresponding target bit sequence, the corresponding target bit sequence can be obtained by searching the table shown in Table 27. When performing distribution matching processing on each intermediate bit sequence in to obtain the corresponding target bit sequence, the corresponding target bit sequence can be obtained by looking up the table shown in Table 28.

[0727] After the bit sequence to be processed is processed using the solution of this example, the probability of the combined bit sequence being mapped to a high-amplitude bit is reduced to approximately 16.27%.

[0728] Example 7: Based on the above-mentioned Example 5, the extended table used in bit processing 1 is changed. The extended table is used to indicate the one-to-one correspondence shown in Table 25 and Table 26.

[0729] Furthermore, the above bit subsequence In each bit subsequence in , the first type of bit segment includes the 7th bit to the 8th bit from left to right in the bit subsequence (expressed as [7:8]), and the third type of bit segment includes the 1st bit to the 6th bit from left to right in the bit subsequence (expressed as [1:6]). In each bit subsequence in , the first type of bit segment includes the 7th bit to the 9th bit from left to right in the bit subsequence (expressed as [7:9]), and the third type of bit segment includes the 1st bit to the 6th bit from left to right in the bit subsequence (expressed as [1:6]).

[0730] The above intermediate bit sequence In each intermediate bit sequence in the , the second type of bit segment includes the 7th bit to the 10th bit from left to right in the intermediate bit sequence (expressed as [7:10]), and the fourth type of bit segment includes the 1st bit to the 6th bit from left to right in the intermediate bit sequence (expressed as [1:6]).

[0731] After the bit sequence to be processed is processed using the solution of this example, the probability of the combined bit sequence being mapped to a high-amplitude bit is reduced to approximately 29.56%.

[0732] The above examples may also have other variations.

[0733] For example, the above examples provide various bit processing scenarios, such as bit processing 1 to 6 in each of Examples 1, 2, and 3, bit processing 1 to 3 in each of Examples 4, 5, and 6, and bit processing 1 in Example 7. Each bit processing is used to obtain multiple intermediate bit sequences based on an initial bit sequence. Based on this, these bit processings can be arbitrarily combined to obtain new examples, in which the number of bits in the to-be-processed bit sequence and / or the number of bits in the resulting bit sequence after combination differ from those in Examples 1 to 6.

[0734] Furthermore, the processing performed by the above-mentioned first sequence processing device can be called PCS encoding processing. The serial-to-parallel conversion process of splitting the bit sequence to be processed in the PCS encoding processing can be implemented by a demultiplexer (DeMUX). The process of obtaining multiple intermediate bit sequences based on the initial bit sequence can be called a redistribution and bit extension process. The parallel-to-serial conversion process of merging multiple target bit sequences can be implemented by a multiplexer (MUX).

[0735] It is understood that the process of splitting the to-be-processed bit sequence can also be implemented without using devices, for example, by connecting multiple data lines through a single data line, wherein the single data line is used to transmit the to-be-processed bits, and the multiple data lines are used to transmit multiple bit subsequences (or multiple initial bit sequences) respectively. The process of merging multiple target bit sequences can also be implemented without using devices, for example, by connecting multiple data lines through a single data line, wherein the multiple data lines are used to transmit multiple target bit sequences respectively, and the single data line is used to transmit the merged bit sequence.

[0736] Optionally, in the sequence processing method provided in the embodiments of the present application, the operations performed by the first sequence processing device may not include S102 and S103 described above, and the operations performed by the second sequence processing device may not include S105 and S106 described above. The first sequence processing device may simply derive multiple intermediate bit sequences based on the initial bit sequence. The second sequence processing device may simply derive the initial bit sequence based on the multiple intermediate bit sequences.

[0737] In the embodiment of the present application, the first bit in a bit sequence or bit segment is represented as 1 as an example. Optionally, the first bit may also be represented as 0.

[0738] Based on the sequence processing method provided in the embodiments of the present application, the embodiments of the present application also provide the following sequence processing devices.

[0739] For example, Figure 12 is a structural schematic diagram of a sequence processing device provided in an embodiment of the present application. The sequence processing device can be the aforementioned first sequence processing device. The sequence processing device shown in Figure 12 has the functions of the aforementioned first sequence processing device. The functions of the sequence processing device shown in Figure 12 can refer to the functions of the aforementioned first sequence processing device.

[0740] As shown in FIG12 , the sequence processing apparatus includes: an acquisition module 1201 , a distribution matching module 1202 and a merging module 1203 .

[0741] The acquisition module 1201 is used to obtain multiple intermediate bit sequences according to the initial bit sequence and the expansion table; the expansion table is used to indicate 2 d The first bit sequence and 2 d a one-to-one correspondence between the first bit sequence and the second bit sequence, the number of bits in the first bit sequence is d, d ≥ 2, and the number of bits in the second bit sequence is h, h > d; the first bit sequence is composed of first-type bit segments of multiple bit subsequences in the initial bit sequence, and the second bit sequence is composed of second-type bit segments of multiple intermediate bit sequences, where the second-type bit segments are multiple most significant bits of the intermediate bit sequences;

[0742] The distribution matching module 1202 is used to perform distribution matching processing on multiple intermediate bit sequences respectively to obtain multiple target bit sequences; d The number of low-amplitude bits of the second bit sequence is greater than or equal to 2 h The second bit sequence is divided by 2 dThe number of low-amplitude bits of any second bit sequence other than the second bit sequences; the number of low-amplitude bits of any second bit sequence is: the number of bits used to map to the lowest-amplitude bit in the multiple target bit sequences corresponding to any second bit sequence; the multiple intermediate bit sequences correspond one-to-one to the multiple target bit sequences, and each target bit sequence is obtained by the corresponding intermediate bit sequence through distribution matching processing.

[0743] The merging module 1203 is used to merge the obtained target bit sequences.

[0744] Optionally, 2 d The minimum number of low-amplitude bits in the second bit sequence is u+1,2 h The second bit sequence is divided by 2 d The maximum value of the number of low-amplitude bits of the second bit sequence other than the second bit sequences is u, where u≥0.

[0745] For example, the middle bit sequence includes 11 bits, and the second bit sequence includes: a first consecutive second type bit segment and a second second type bit segment; d The second bit sequence includes:

[0746] a second bit sequence in which the first second-category bit segment is (0, 0, 0) and the second second-category bit segment is (0, 0, 0);

[0747] a second bit sequence in which the first second-type bit segment is (0, 0, 0) and the second second-type bit segment is (1, 0, 0);

[0748] a second bit sequence in which the first second-type bit segment is (1, 0, 0) and the second second-type bit segment is (0, 0, 0);

[0749] a second bit sequence in which the first second-type bit segment is (0, 0, 0) and the second second-type bit segment is (0, 1, 0);

[0750] a second bit sequence in which the first second-type bit segment is (0, 1, 0) and the second second-type bit segment is (0, 0, 0);

[0751] a second bit sequence in which the first second-type bit segment is (1, 1, 0) and the second second-type bit segment is (0, 0, 0);

[0752] a second bit sequence in which the first second-type bit segment is (0, 0, 0) and the second second-type bit segment is (1, 1, 0);

[0753] a second bit sequence in which the first second-type bit segment is (1, 0, 0) and the second second-type bit segment is (1, 0, 0);

[0754] a second bit sequence in which the first second-type bit segment is (0, 0, 0) and the second second-type bit segment is (0, 0, 1);

[0755] a second bit sequence in which the first second-type bit segment is (0, 0, 1) and the second second-type bit segment is (0, 0, 0);

[0756] a second bit sequence in which the first second-type bit segment is (0, 1, 0) and the second second-type bit segment is (1, 0, 0);

[0757] a second bit sequence in which the first second-type bit segment is (1, 0, 0) and the second second-type bit segment is (0, 1, 0);

[0758] a second bit sequence in which the first second-type bit segment is (1, 0, 1) and the second second-type bit segment is (0, 0, 0);

[0759] a second bit sequence in which the first second-type bit segment is (0, 0, 0) and the second second-type bit segment is (1, 0, 1);

[0760] a second bit sequence in which the first second-type bit segment is (1, 1, 0) and the second second-type bit segment is (1, 0, 0);

[0761] a second bit sequence in which the first second-type bit segment is (1, 0, 0) and the second second-type bit segment is (1, 1, 0);

[0762] In the various second-category bit segments provided in the embodiments of the present application, the bits in the second-category bit segments are arranged from left to right in the order of bit position from low to high or from high to low. In each second-category bit segment, the bit position of the w-th bit from left to right is higher or lower than the bit position of the w+1-th bit, where w ≥ 1. In addition, assuming that the second-category bit segment includes y bits, then the y bits in the second-category bit segment are also the y most significant bits in the intermediate bit sequence including the second-category bit segment; and the most significant bit in each second-category bit segment is also the bit with the most significant bit in the intermediate bit sequence including the second-category bit segment.

[0763] Optionally, 2 d The minimum value of the number of low-amplitude bits in the second bit sequence is u,2 h The second bit sequence is divided by 2 d The maximum number of low-amplitude bits of the second bit sequence other than the second bit sequence is u, u≥0; 2 d The second bit sequence includes: 2 h v second bit sequences with a low amplitude bit number greater than u in the second bit sequences, and any 2 of the multiple second bit sequences with a low amplitude bit number ud -v second bit sequences, v ≥ 1.

[0764] For example, the middle bit sequence includes 10 bits, and the second bit sequence includes: a first consecutive second type bit segment and a second second type bit segment, 2 d The second bit sequence includes:

[0765] a second bit sequence in which the first second-category bit segment is (0, 0, 0) and the second second-category bit segment is (0, 0, 0);

[0766] a second bit sequence in which the first second-type bit segment is (0, 0, 0) and the second second-type bit segment is (1, 0, 0);

[0767] a second bit sequence in which the first second-type bit segment is (1, 0, 0) and the second second-type bit segment is (0, 0, 0);

[0768] a second bit sequence in which the first second-type bit segment is (0, 0, 0) and the second second-type bit segment is (0, 1, 0);

[0769] a second bit sequence in which the first second-type bit segment is (0, 1, 0) and the second second-type bit segment is (0, 0, 0);

[0770] a second bit sequence in which the first second-type bit segment is (1, 0, 0) and the second second-type bit segment is (1, 0, 0);

[0771] a second bit sequence in which the first second-type bit segment is (0, 0, 0) and the second second-type bit segment is (1, 1, 0);

[0772] a second bit sequence in which the first second-type bit segment is (1, 1, 0) and the second second-type bit segment is (0, 0, 0);

[0773] a second bit sequence in which the first second-type bit segment is (0, 0, 0) and the second second-type bit segment is (0, 0, 1);

[0774] a second bit sequence in which the first second-type bit segment is (0, 0, 1) and the second second-type bit segment is (0, 0, 0);

[0775] a second bit sequence in which the first second-type bit segment is (0, 1, 0) and the second second-type bit segment is (1, 0, 0);

[0776] a second bit sequence in which the first second-type bit segment is (1, 0, 0) and the second second-type bit segment is (0, 1, 0);

[0777] a second bit sequence in which the first second-type bit segment is (0, 1, 0) and the second second-type bit segment is (0, 1, 0);

[0778] a second bit sequence in which the first second-type bit segment is (1, 0, 1) and the second second-type bit segment is (0, 0, 0);

[0779] a second bit sequence in which the first second-type bit segment is (0, 0, 0) and the second second-type bit segment is (1, 0, 1);

[0780] And, any one of the following second bit sequences:

[0781] a second bit sequence in which the first second-type bit segment is (1, 1, 0) and the second second-type bit segment is (1, 0, 0);

[0782] a second bit sequence in which the first second-type bit segment is (1, 0, 0) and the second second-type bit segment is (1, 1, 0);

[0783] For another example, the middle bit sequence includes 10 bits, and the second bit sequence includes: a first consecutive second type bit segment and a second second type bit segment, 2 d The second bit sequence includes:

[0784] a second bit sequence in which the first second-category bit segment is (0, 0, 0, 0) and the second second-category bit segment is (0, 0, 0, 0);

[0785] a second bit sequence in which the first second-type bit segment is (0, 0, 0, 0) and the second second-type bit segment is (1, 0, 0, 0);

[0786] a second bit sequence in which the first second-category bit segment is (1, 0, 0, 0) and the second second-category bit segment is (0, 0, 0, 0);

[0787] a second bit sequence in which the first second-type bit segment is (0, 0, 0, 0) and the second second-type bit segment is (0, 1, 0, 0);

[0788] a second bit sequence in which the first second-category bit segment is (0, 1, 0, 0) and the second second-category bit segment is (0, 0, 0, 0);

[0789] a second bit sequence in which the first second-category bit segment is (0, 0, 0, 0) and the second second-category bit segment is (1, 1, 0, 0);

[0790] a second bit sequence in which the first second-category bit segment is (0, 0, 0, 0) and the second second-category bit segment is (0, 0, 1, 0);

[0791] a second bit sequence in which the first second-category bit segment is (0, 0, 0, 0) and the second second-category bit segment is (1, 0, 1, 0);

[0792] a second bit sequence in which the first second-category bit segment is (1, 1, 0, 0) and the second second-category bit segment is (0, 0, 0, 0);

[0793] a second bit sequence in which the first second-category bit segment is (1, 0, 1, 0) and the second second-category bit segment is (0, 0, 0, 0);

[0794] a second bit sequence in which the first second-category bit segment is (0, 0, 1, 0) and the second second-category bit segment is (0, 0, 0, 0);

[0795] a second bit sequence in which the first second-type bit segment is (1, 0, 0, 0) and the second second-type bit segment is (1, 0, 0, 0);

[0796] a second bit sequence in which the first second-type bit segment is (0, 1, 0, 0) and the second second-type bit segment is (1, 0, 0, 0);

[0797] a second bit sequence in which the first second-type bit segment is (1, 0, 0, 0) and the second second-type bit segment is (0, 1, 0, 0);

[0798] a second bit sequence in which the first second-type bit segment is (0, 1, 0, 0) and the second second-type bit segment is (0, 1, 0, 0);

[0799] And, any one of the following second bit sequences:

[0800] a second bit sequence in which the first second-category bit segment is (0, 0, 0, 0) and the second second-category bit segment is (0, 1, 1, 0);

[0801] a second bit sequence in which the first second-category bit segment is (0, 1, 1, 0) and the second second-category bit segment is (0, 0, 0, 0);

[0802] For another example, the middle bit sequence includes 11 bits, and the second bit sequence includes: a first consecutive second type bit segment and a second second type bit segment, 2 d The second bit sequence includes:

[0803] a second bit sequence in which the first second-category bit segment is (0, 0, 0, 0) and the second second-category bit segment is (0, 0, 0, 0);

[0804] a second bit sequence in which the first second-type bit segment is (0, 0, 0, 0) and the second second-type bit segment is (1, 0, 0, 0);

[0805] a second bit sequence in which the first second-category bit segment is (1, 0, 0, 0) and the second second-category bit segment is (0, 0, 0, 0);

[0806] a second bit sequence in which the first second-category bit segment is (0, 1, 0, 0) and the second second-category bit segment is (0, 0, 0, 0);

[0807] a second bit sequence in which the first second-type bit segment is (1, 0, 0, 0) and the second second-type bit segment is (1, 0, 0, 0);

[0808] a second bit sequence in which the first second-category bit segment is (1, 1, 0, 0) and the second second-category bit segment is (0, 0, 0, 0);

[0809] a second bit sequence in which the first second-type bit segment is (0, 0, 0, 0) and the second second-type bit segment is (0, 1, 0, 0);

[0810] a second bit sequence in which the first second-category bit segment is (0, 0, 0, 0) and the second second-category bit segment is (1, 1, 0, 0);

[0811] a second bit sequence in which the first second-category bit segment is (0, 0, 0, 0) and the second second-category bit segment is (0, 0, 1, 0);

[0812] a second bit sequence in which the first second-category bit segment is (0, 0, 1, 0) and the second second-category bit segment is (0, 0, 0, 0);

[0813] a second bit sequence in which the first second-type bit segment is (1, 0, 0, 0) and the second second-type bit segment is (1, 1, 0, 0);

[0814] a second bit sequence in which the first second-type bit segment is (1, 0, 0, 0) and the second second-type bit segment is (0, 1, 0, 0);

[0815] a second bit sequence in which the first second-type bit segment is (0, 1, 0, 0) and the second second-type bit segment is (1, 0, 0, 0);

[0816] a second bit sequence in which the first second-category bit segment is (1, 1, 0, 0) and the second second-category bit segment is (1, 0, 0, 0);

[0817] And, any two second bit sequences among the following second bit sequences:

[0818] a second bit sequence in which the first second-category bit segment is (0, 0, 0, 0) and the second second-category bit segment is (0, 1, 1, 0);

[0819] a second bit sequence in which the first second-category bit segment is (0, 0, 0, 0) and the second second-category bit segment is (1, 0, 1, 0);

[0820] a second bit sequence in which the first second-category bit segment is (1, 0, 1, 0) and the second second-category bit segment is (0, 0, 0, 0);

[0821] a second bit sequence in which the first second-category bit segment is (1, 1, 1, 0) and the second second-category bit segment is (0, 0, 0, 0);

[0822] a second bit sequence in which the first second-category bit segment is (0, 0, 0, 0) and the second second-category bit segment is (1, 1, 1, 0);

[0823] a second bit sequence in which the first second-category bit segment is (0, 1, 1, 0) and the second second-category bit segment is (0, 0, 0, 0);

[0824] For another example, the middle bit sequence includes 10 bits, and the second bit sequence includes: a first consecutive second type bit segment and a second second type bit segment, 2 d The second bit sequence includes:

[0825] a second bit sequence in which the first second-category bit segment is (0, 0, 0, 0, 0), and the second second-category bit segment is (0, 0, 0, 0, 0);

[0826] a second bit sequence in which the first second-category bit segment is (0, 0, 0, 0, 0), and the second second-category bit segment is (1, 0, 0, 0, 0, 0);

[0827] a second bit sequence in which the first second-category bit segment is (0, 0, 0, 0, 0), and the second second-category bit segment is (0, 1, 0, 0, 0, 0);

[0828] a second bit sequence in which the first second-category bit segment is (1, 0, 0, 0, 0, 0) and the second second-category bit segment is (0, 0, 0, 0, 0, 0);

[0829] a second bit sequence in which the first second-category bit segment is (0, 1, 0, 0, 0, 0) and the second second-category bit segment is (0, 0, 0, 0, 0, 0);

[0830] a second bit sequence in which the first second-category bit segment is (0, 0, 0, 0, 0), and the second second-category bit segment is (1, 1, 0, 0, 0, 0);

[0831] a second bit sequence in which the first second-category bit segment is (1, 1, 0, 0, 0, 0) and the second second-category bit segment is (0, 0, 0, 0, 0, 0);

[0832] a second bit sequence in which the first second-category bit segment is (0, 1, 0, 0, 0, 0) and the second second-category bit segment is (0, 1, 0, 0, 0, 0);

[0833] a second bit sequence in which the first second-category bit segment is (0, 1, 0, 0, 0, 0) and the second second-category bit segment is (1, 0, 0, 0, 0, 0);

[0834] a second bit sequence in which the first second-category bit segment is (1, 0, 0, 0, 0, 0) and the second second-category bit segment is (1, 0, 0, 0, 0, 0);

[0835] a second bit sequence in which the first second-category bit segment is (1, 0, 0, 0, 0), and the second second-category bit segment is (0, 1, 0, 0, 0, 0);

[0836] And, any five second bit sequences among the following second bit sequences:

[0837] a second bit sequence in which the first second-category bit segment is (0, 0, 1, 0, 0, 0) and the second second-category bit segment is (0, 0, 0, 0, 0, 0);

[0838] a second bit sequence in which the first second-category bit segment is (1, 0, 1, 0, 0, 0) and the second second-category bit segment is (0, 0, 0, 0, 0, 0);

[0839] a second bit sequence in which the first second-category bit segment is (0, 1, 1, 0, 0, 0) and the second second-category bit segment is (0, 0, 0, 0, 0, 0);

[0840] a second bit sequence in which the first second-category bit segment is (0, 0, 0, 1, 0, 0) and the second second-category bit segment is (0, 0, 0, 0, 0, 0);

[0841] a second bit sequence in which the first second-category bit segment is (1, 0, 0, 1, 0, 0) and the second second-category bit segment is (0, 0, 0, 0, 0, 0);

[0842] a second bit sequence in which the first second-category bit segment is (0, 1, 0, 1, 0, 0) and the second second-category bit segment is (0, 0, 0, 0, 0, 0);

[0843] a second bit sequence in which the first second-category bit segment is (1, 1, 1, 0, 0, 0) and the second second-category bit segment is (0, 0, 0, 0, 0, 0);

[0844] a second bit sequence in which the first second-category bit segment is (0, 0, 0, 0, 0), and the second second-category bit segment is (0, 0, 0, 1, 0, 0);

[0845] a second bit sequence in which the first second-category bit segment is (0, 0, 0, 0, 0), and the second second-category bit segment is (0, 0, 1, 0, 0, 0);

[0846] a second bit sequence in which the first second-category bit segment is (0, 0, 0, 0, 0), and the second second-category bit segment is (1, 0, 1, 0, 0, 0);

[0847] a second bit sequence in which the first second-category bit segment is (0, 0, 0, 0, 0), and the second second-category bit segment is (0, 1, 1, 0, 0, 0);

[0848] a second bit sequence in which the first second-category bit segment is (0, 0, 0, 0, 0), and the second second-category bit segment is (1, 0, 0, 1, 0, 0);

[0849] a second bit sequence in which the first second-category bit segment is (0, 0, 0, 0, 0), and the second second-category bit segment is (1, 1, 1, 0, 0, 0);

[0850] a second bit sequence in which the first second-category bit segment is (0, 0, 0, 0, 0), and the second second-category bit segment is (0, 1, 0, 1, 0, 0);

[0851] For another example, the middle bit sequence includes 11 bits, and the second bit sequence includes: a first consecutive second type bit segment and a second second type bit segment, 2 d The second bit sequence includes:

[0852] a second bit sequence in which the first second-category bit segment is (0, 0, 0, 0, 0, 0), and the second second-category bit segment is (0, 0, 0, 0, 0, 0);

[0853] a second bit sequence in which the first second-category bit segment is (0, 1, 0, 0, 0, 0, 0) and the second second-category bit segment is (0, 0, 0, 0, 0, 0, 0);

[0854] a second bit sequence in which the first second-category bit segment is (1, 1, 0, 0, 0, 0, 0) and the second second-category bit segment is (0, 0, 0, 0, 0, 0, 0);

[0855] a second bit sequence in which the first second-category bit segment is (1, 0, 0, 0, 0, 0), and the second second-category bit segment is (0, 0, 0, 0, 0, 0);

[0856] a second bit sequence in which the first second-category bit segment is (0, 0, 0, 0, 0, 0), and the second second-category bit segment is (1, 0, 0, 0, 0, 0);

[0857] a second bit sequence in which the first second-category bit segment is (0, 0, 0, 0, 0, 0), and the second second-category bit segment is (0, 1, 0, 0, 0, 0, 0);

[0858] a second bit sequence in which the first second-category bit segment is (0, 0, 0, 0, 0, 0), and the second second-category bit segment is (1, 1, 0, 0, 0, 0, 0);

[0859] And, any nine second bit sequences among the following second bit sequences:

[0860] a second bit sequence in which the first second-category bit segment is (0, 0, 0, 0, 0, 0), and the second second-category bit segment is (0, 0, 1, 0, 0, 0, 0);

[0861] a second bit sequence in which the first second-category bit segment is (1, 0, 0, 0, 0, 0), and the second second-category bit segment is (0, 1, 0, 0, 0, 0, 0);

[0862] a second bit sequence in which the first second-category bit segment is (1, 0, 0, 0, 0, 0), and the second second-category bit segment is (1, 1, 0, 0, 0, 0, 0);

[0863] a second bit sequence in which the first second-category bit segment is (0, 1, 0, 0, 0, 0, 0) and the second second-category bit segment is (1, 0, 0, 0, 0, 0, 0);

[0864] a second bit sequence in which the first second-category bit segment is (0, 1, 0, 0, 0, 0, 0) and the second second-category bit segment is (0, 1, 0, 0, 0, 0, 0);

[0865] a second bit sequence in which the first second-category bit segment is (0, 1, 0, 0, 0, 0, 0) and the second second-category bit segment is (1, 1, 0, 0, 0, 0, 0);

[0866] a second bit sequence in which the first second-category bit segment is (1, 1, 0, 0, 0, 0, 0) and the second second-category bit segment is (1, 0, 0, 0, 0, 0, 0);

[0867] a second bit sequence in which the first second-category bit segment is (1, 1, 0, 0, 0, 0, 0) and the second second-category bit segment is (0, 1, 0, 0, 0, 0, 0);

[0868] a second bit sequence in which the first second-category bit segment is (1, 1, 0, 0, 0, 0, 0) and the second second-category bit segment is (1, 1, 0, 0, 0, 0, 0);

[0869] a second bit sequence in which the first second-category bit segment is (1, 0, 0, 0, 0, 0), and the second second-category bit segment is (1, 0, 0, 0, 0, 0);

[0870] a second bit sequence in which the first second-category bit segment is (0, 0, 1, 0, 0, 0, 0) and the second second-category bit segment is (0, 0, 0, 0, 0, 0, 0);

[0871] For another example, the middle bit sequence includes 10 bits, the second type of bit segment includes 3 bits, and the second bit sequence includes 4 second type of bit segments. d The second bit sequences include 256 second bit sequences, and the 256 second bit sequences include the 246 second bit sequences shown in Table 14 and any 10 second bit sequences among the 24 second bit sequences shown in Table 15. In Tables 14 and 15, the second bit sequence includes four consecutive second-category bit segments, and these four second-category bit segments can be the four second-category bit segments arranged from left to right in Tables 14 and 15.

[0872] For another example, the middle bit sequence includes 11 bits, the second type of bit segment includes 3 bits, and the second bit sequence includes 4 second type of bit segments. d The second bit sequence includes 256 second bit sequences, and the 256 second bit sequences include the 256 second bit sequences shown in Table 16. In Table 16, the second bit sequence includes four consecutive second-category bit segments, and these four second-category bit segments can be the four second-category bit segments arranged from left to right in Table 16.

[0873] For another example, the middle bit sequence includes 10 bits, the second type of bit segment includes 3 bits, and the second bit sequence includes 4 second type of bit segments. dThe second bit sequences include 64 second bit sequences, and the 64 second bit sequences include the 61 second bit sequences shown in Table 17 and any three second bit sequences among the 12 second bit sequences shown in Table 18. In Tables 17 and 18, the second bit sequence includes four consecutive second-category bit segments, and these four second-category bit segments can be the four second-category bit segments arranged from left to right in Tables 17 and 18.

[0874] For another example, the middle bit sequence includes 11 bits, the second type of bit segment includes 4 bits, and the second bit sequence includes 4 second type of bit segments. d The second bit sequences include 256 second bit sequences, and the 256 second bit sequences include the 212 second bit sequences shown in Table 19 and any 44 second bit sequences among the 56 second bit sequences shown in Table 20. In Tables 19 and 20, the second bit sequence includes four consecutive second-category bit segments, and these four second-category bit segments can be the four second-category bit segments arranged from left to right in Tables 19 and 20.

[0875] For another example, the middle bit sequence includes 10 bits, the second type of bit segment includes 6 bits, and the second bit sequence includes 4 second type of bit segments. d The second bit sequences include 256 second bit sequences, and the 256 second bit sequences include the 121 second bit sequences shown in Table 21 and any 135 second bit sequences among the 174 second bit sequences shown in Table 22. In Tables 21 and 22, the second bit sequences include four consecutive second-category bit segments, and these four second-category bit segments can be the four second-category bit segments arranged from left to right in Tables 20 and 21.

[0876] For another example, the middle bit sequence includes 10 bits, the second type of bit segment includes 7 bits, and the second bit sequence includes 4 second type of bit segments. d The second bit sequence includes 256 second bit sequences, and the 256 second bit sequences include the 255 second bit sequences shown in Table 23 and any one of the 324 second bit sequences shown in Table 24. In Tables 23 and 24, the second bit sequence includes four consecutive second-category bit segments, and these four second-category bit segments can be the four second-category bit segments arranged from left to right in Tables 23 and 24.

[0877] For another example, the middle bit sequence includes 10 bits, the second type of bit segment includes 4 bits, and the second bit sequence includes 4 second type of bit segments. dThe second bit sequences include 1024 second bit sequences, and the 1024 second bit sequences include the 903 second bit sequences shown in Table 25 and any 121 second bit sequences among the 156 second bit sequences shown in Table 26. In Tables 25 and 26, the second bit sequence includes four consecutive second-category bit segments, and these four second-category bit segments can be the four second-category bit segments arranged from left to right in Tables 25 and 26.

[0878] Optionally, 2 d The first bit sequence and 2 d The one-to-one correspondence between the second bit sequences can be shown in Table 3; or, d The first bit sequence and 2 d The one-to-one correspondence between the second bit sequences can be shown by Table 4 and Table 5; or, d The first bit sequence and 2 d The one-to-one correspondence between the second bit sequences can be shown by Table 6 and Table 7; or, d The first bit sequence and 2 d The one-to-one correspondence between the second bit sequences can be shown by Table 8 and Table 9; or, d The first bit sequence and 2 d The one-to-one correspondence between the second bit sequences can be shown by Table 10 and Table 11; or, d The first bit sequence and 2 d The one-to-one correspondence between the second bit sequences can be shown by Table 12 and Table 13; or, d The first bit sequence and 2 d The one-to-one correspondence between the second bit sequences can be shown by Table 14 and Table 15; or, d The first bit sequence and 2 d The one-to-one correspondence between the second bit sequences can be as shown in Table 16; or, d The first bit sequence and 2 d The one-to-one correspondence between the second bit sequences can be shown by Table 17 and Table 18; or, d The first bit sequence and 2 d The one-to-one correspondence between the second bit sequences can be shown by Table 19 and Table 20; or, d The first bit sequence and 2 d The one-to-one correspondence between the second bit sequences can be shown by Table 21 and Table 22; or, d The first bit sequence and 2 d The one-to-one correspondence between the second bit sequences can be shown by Table 23 and Table 24; or, d The first bit sequence and 2d The one-to-one correspondence between the second bit sequences can be shown by Table 25 and Table 26.

[0879] For example, Figure 13 is a structural schematic diagram of another sequence processing device provided in an embodiment of the present application. The sequence processing device can be the aforementioned second sequence processing device. The sequence processing device shown in Figure 13 has the functions of the aforementioned second sequence processing device. The functions of the sequence processing device shown in Figure 13 can refer to the functions of the aforementioned second sequence processing device.

[0880] As shown in FIG13 , the sequence processing device includes: a splitting module 1301 , a distribution matching module 1302 and an acquisition module 1303 .

[0881] The splitting module 1301 is used to split a plurality of target bit sequences from a bit sequence;

[0882] The distribution matching module 1302 is used to perform an inverse process of the distribution matching process on the multiple target bit sequences to obtain multiple intermediate bit sequences;

[0883] The acquisition module 1303 is used to obtain an initial bit sequence according to multiple intermediate bit sequences and an expansion table; the expansion table is used to indicate 2 d The first bit sequence and 2 d The first bit sequence is composed of first-category bit segments of multiple bit subsequences in the initial bit sequence, and the second bit sequence is composed of second-category bit segments of multiple intermediate bit sequences, wherein the second-category bit segments are multiple most significant bits of the intermediate bit sequences; d The number of low-amplitude bits of the second bit sequence is greater than or equal to 2 h The second bit sequence is divided by 2 d The number of low-amplitude bits of any second bit sequence is: the number of bits used to map to the lowest-amplitude bit in multiple target bit sequences corresponding to any second bit sequence.

[0884] An embodiment of the present application further provides a chip, as shown in FIG14 , which includes a processor 1401 and an interface 1402 , and the processor 1401 is connected to the interface 1402 .

[0885] Processor 1401 is configured to execute the method provided by the first sequence processing apparatus in accordance with an embodiment of the present application to process a bit sequence, which may be the aforementioned initial bit sequence or the aforementioned sequence to be processed. The processor is further configured to obtain a data frame based on the bit sequence processed by the method provided by the first sequence processing apparatus in accordance with an embodiment of the present application, and interface 1402 is configured to output the data frame. For example, the process by which processor 1401 obtains a data frame based on the processed bit sequence may refer to the process by which the first sequence processing module 012 obtains a data frame based on the bit sequence.

[0886] And / or, interface 1402 is configured to receive a data frame, processor 1401 is configured to obtain a bit sequence based on the data frame, and execute the method provided by the second sequence processing apparatus in an embodiment of the present application to process the obtained bit sequence. The process by which processor 1401 obtains a bit sequence based on the data frame can refer to the process by which the second sequence processing module 022 obtains a bit sequence based on the data frame.

[0887] The chip can be integrated by the signal source 011, the first sequence processing module 012, and the first signal processing module 013 in Figure 1; or, the chip can be integrated by the signal sink 021, the second sequence processing module 022, and the second signal processing module 023 in Figure 1; or, the chip can be integrated by the signal source 011, the first sequence processing module 012, the first signal processing module 013, the signal sink 021, the second sequence processing module 022, and the second signal processing module 023 in Figure 1.

[0888] The embodiment of the present application also provides an optical module, as shown in Figure 15, which includes an optical transceiver 130 and a chip 140. The chip 140 can be the chip shown in Figure 14. The chip 140 is used to run any one of the methods provided in the embodiment of the present application and executed by the first sequence processing device to process the bit sequence. The chip is also used to obtain a first data frame based on the bit sequence obtained by running any one of the methods provided in the embodiment of the present application and executed by the first sequence processing device. The optical transceiver 130 is used to transmit a first optical signal according to the first data frame; the optical transceiver 130 is used to obtain a second data frame according to the received second optical signal. The chip is used to obtain a bit sequence according to the second data frame, and to run any one of the methods provided in the embodiment of the present application and executed by the second sequence processing device to process the bit sequence obtained according to the second data frame.

[0889] The present application provides a computer-readable storage medium, characterized in that the computer-readable storage medium stores instructions, and when the instructions are executed on a computer, the computer executes the method performed by the first sequence processing device or the second sequence processing device in any one of the sequence processing methods provided in the embodiments of the present application.

[0890] The present application provides a computer program product comprising instructions. When the computer program product is run on a computer, the computer is enabled to execute a method performed by a first sequence processing device or a second sequence processing device in any one of the sequence processing methods provided in the embodiments of the present application.

[0891] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When software is used for implementation, it can be implemented in whole or in part in the form of a computer program product, which includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the process or function described in the embodiment of the present application is generated in whole or in part. The computer can be a general-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from a website, computer, server or data center to another website, computer, server or data center via a wired (e.g., coaxial cable, optical fiber, digital subscriber line) or wireless (e.g., infrared, wireless, microwave, etc.) mode. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that includes one or more available media integrations. The available medium can be a magnetic medium (e.g., a floppy disk, a hard disk, a tape), an optical medium, or a semiconductor medium (e.g., a solid-state hard disk).

[0892] The method embodiments provided in the embodiments of the present application can be cross-referenced with the corresponding device embodiments, and the embodiments of the present application are not limited thereto. The order of the steps of the method embodiments provided in the embodiments of the present application can be appropriately adjusted, and the steps can be increased or decreased accordingly according to the circumstances. Any person skilled in the art who can easily think of a method of variation within the technical scope disclosed in this application should be included in the scope of protection of this application, and therefore will not be described in detail.

[0893] In this application, the terms "first" and "second" etc. are used for descriptive purposes only and are not to be understood as indicating or implying relative importance. The term "at least one" refers to one or more, and "a plurality of" refers to two or more, unless otherwise expressly defined. In the corresponding embodiments provided in this application, it should be understood that the disclosed structure can be implemented by other construction methods. For example, the embodiments described above are merely illustrative. The term "and / or" in this application is merely a description of the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the related objects before and after are in an "or" relationship.

[0894] The above are merely optional embodiments of the present application, but the scope of protection of the present application is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in this application, and such modifications or substitutions should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A sequence processing method, characterized in that, The method includes: Obtain a plurality of intermediate bit sequences according to an initial bit sequence and an expansion table; the expansion table is used to indicate a one-to-one correspondence between 2 d first bit sequences and 2 d second bit sequences, the number of bits in the first bit sequence is d, d≥2, and the number of bits in the second bit sequence is h, h>d; the first bit sequence is composed of first-class bit segments of a plurality of bit subsequences in the initial bit sequence, and the second bit sequence is composed of second-class bit segments of the plurality of intermediate bit sequences, and the second-class bit segments are a plurality of bits at the highest position of the intermediate bit sequence; Perform distribution matching processing on the multiple intermediate bit sequences respectively to obtain multiple target bit sequences; d The number of low-amplitude bits of the second bit sequences is greater than or equal to 2 h The second bit sequence is divided into 2 d The number of low amplitude bits of a second bit sequence other than a second bit sequence; the number of low amplitude bits of any second bit sequence is: the number of bits used for mapping to the lowest amplitude bit in a plurality of target bit sequences corresponding to any second bit sequence; merging the obtained target bit sequence.

2. The method according to claim 1, characterized in that, The said 2 d The minimum value of the number of low-amplitude bits in the said 2 h second bit sequences is u + 1, and the maximum value of the number of low-amplitude bits in the second bit sequences other than the said 2 d second bit sequences among the said 2 second bit sequences is u, where u ≥ 0.

3. The method according to claim 2, characterized in that, The middle bit sequence includes 11 bits, and the second bit sequence includes: a consecutive first second-type bit segment and a second second-type bit segment; the 2 d second bit sequences include: A second bit sequence where the first second - type bit segment is (0, 0, 0) and the second second - type bit segment is (0, 0, 0); A second bit sequence where the first second - type bit segment is (0, 0, 0) and the second second - type bit segment is (1, 0, 0); A second bit sequence where the first second - type bit segment is (1, 0, 0) and the second second - type bit segment is (0, 0, 0); A second bit sequence where the first second - type bit segment is (0, 0, 0) and the second second - type bit segment is (0, 1, 0); A second bit sequence where the first second - type bit segment is (0, 1, 0) and the second second - type bit segment is (0, 0, 0); A second bit sequence where the first second - type bit segment is (1, 1, 0) and the second second - type bit segment is (0, 0, 0); A second bit sequence where the first second - type bit segment is (0, 0, 0) and the second second - type bit segment is (1, 1, 0); A second bit sequence where the first second - type bit segment is (1, 0, 0) and the second second - type bit segment is (1, 0, 0); A second bit sequence where the first second - type bit segment is (0, 0, 0) and the second second - type bit segment is (0, 0, 1); A second bit sequence where the first second - type bit segment is (0, 0, 1) and the second second - type bit segment is (0, 0, 0); A second bit sequence where the first second - type bit segment is (0, 1, 0) and the second second - type bit segment is (1, 0, 0); A second bit sequence where the first second - type bit segment is (1, 0, 0) and the second second - type bit segment is (0, 1, 0); A second bit sequence where the first second - type bit segment is (1, 0, 1) and the second second - type bit segment is (0, 0, 0); A second bit sequence where the first second - type bit segment is (0, 0, 0) and the second second - type bit segment is (1, 0, 1); A second bit sequence where the first second - type bit segment is (1, 1, 0) and the second second - type bit segment is (1, 0, 0); A second bit sequence where the first second - type bit segment is (1, 0, 0) and the second second - type bit segment is (1, 1, 0); Wherein, the bits in the second - type bit segment are arranged from left to right in ascending or descending order of bit positions.

4. The method according to claim 1, wherein The said 2 d The minimum value of the number of low-amplitude bits in the said 2 h second bit sequences is u, and the maximum value of the number of low-amplitude bits in the second bit sequences other than the said 2 d second bit sequences among the said 2 second bit sequences is u, where u ≥ 0; The said 2 d The two second bit sequences include: the said 2 h v second bit sequences in the two second bit sequences where the number of low-amplitude bits is greater than u, and any 2 of the multiple second bit sequences where the number of low-amplitude bits is u d -v second bit sequences, where v≥1.

5. The method according to claim 4, wherein The middle bit sequence includes 10 bits, and the second bit sequence includes: a consecutive first second-type bit segment and a second second-type bit segment, the 2 d second bit sequences include: A second bit sequence where the first second - type bit segment is (0, 0, 0) and the second second - type bit segment is (0, 0, 0); A second bit sequence where the first second - type bit segment is (0, 0, 0) and the second second - type bit segment is (1, 0, 0); A second bit sequence where the first second - type bit segment is (1, 0, 0) and the second second - type bit segment is (0, 0, 0); The second bit sequence where the first second - type bit segment is (0, 0, 0) and the second second - type bit segment is (0, 1, 0); The second bit sequence where the first second - type bit segment is (0, 1, 0) and the second second - type bit segment is (0, 0, 0); The second bit sequence where the first second - type bit segment is (1, 0, 0) and the second second - type bit segment is (1, 0, 0); The second bit sequence where the first second - type bit segment is (0, 0, 0) and the second second - type bit segment is (1, 1, 0); The second bit sequence where the first second - type bit segment is (1, 1, 0) and the second second - type bit segment is (0, 0, 0); The second bit sequence where the first second - type bit segment is (0, 0, 0) and the second second - type bit segment is (0, 0, 1); The second bit sequence where the first second - type bit segment is (0, 0, 1) and the second second - type bit segment is (0, 0, 0); The second bit sequence where the first second - type bit segment is (0, 1, 0) and the second second - type bit segment is (1, 0, 0); The second bit sequence where the first second - type bit segment is (1, 0, 0) and the second second - type bit segment is (0, 1, 0); The second bit sequence where the first second - type bit segment is (0, 1, 0) and the second second - type bit segment is (0, 1, 0); The second bit sequence where the first second - type bit segment is (1, 0, 1) and the second second - type bit segment is (0, 0, 0); The second bit sequence where the first second - type bit segment is (0, 0, 0) and the second second - type bit segment is (1, 0, 1); And any one of the following second bit sequences: The second bit sequence where the first second - type bit segment is (1, 1, 0) and the second second - type bit segment is (1, 0, 0); The second bit sequence where the first second - type bit segment is (1, 0, 0) and the second second - type bit segment is (1, 1, 0); Wherein, the bits in the second - type bit segment are arranged from left to right in ascending or descending order of bit positions.

6. The method according to claim 4, wherein The middle bit sequence includes 10 bits. The second bit sequence includes: a consecutive first second-type bit segment and a second second-type bit segment. The 2 d second bit sequences include: The second bit sequence where the first second - type bit segment is (0, 0, 0, 0) and the second second - type bit segment is (0, 0, 0, 0); The second bit sequence where the first second - type bit segment is (0, 0, 0, 0) and the second second - type bit segment is (1, 0, 0, 0); The second bit sequence where the first second - type bit segment is (1, 0, 0, 0) and the second second - type bit segment is (0, 0, 0, 0); The second bit sequence where the first second - type bit segment is (0, 0, 0, 0) and the second second - type bit segment is (0, 1, 0, 0); The second bit sequence where the first second - type bit segment is (0, 1, 0, 0) and the second second - type bit segment is (0, 0, 0, 0); The second bit sequence where the first second - type bit segment is (0, 0, 0, 0) and the second second - type bit segment is (1, 1, 0, 0); The second bit sequence where the first second - type bit segment is (0, 0, 0, 0) and the second second - type bit segment is (0, 0, 1, 0); The second bit sequence where the first second - type bit segment is (0, 0, 0, 0) and the second second - type bit segment is (1, 0, 1, 0); The second bit sequence where the first second - type bit segment is (1, 1, 0, 0) and the second second - type bit segment is (0, 0, 0, 0); The second bit sequence where the first second - type bit segment is (1, 0, 1, 0) and the second second - type bit segment is (0, 0, 0, 0); The second bit sequence where the first second - type bit segment is (0, 0, 1, 0) and the second second - type bit segment is (0, 0, 0, 0); The second bit sequence where the first second - type bit segment is (1, 0, 0, 0) and the second second - type bit segment is (1, 0, 0, 0); The second bit sequence where the first second - type bit segment is (0, 1, 0, 0) and the second second - type bit segment is (1, 0, 0, 0); The second bit sequence where the first second - type bit segment is (1, 0, 0, 0) and the second second - type bit segment is (0, 1, 0, 0); The second bit sequence where the first second - type bit segment is (0, 1, 0, 0) and the second second - type bit segment is (0, 1, 0, 0); And any one of the following second bit sequences: The second bit sequence where the first second - type bit segment is (0, 0, 0, 0) and the second second - type bit segment is (0, 1, 1, 0); The second bit sequence where the first second - type bit segment is (0, 1, 1, 0) and the second second - type bit segment is (0, 0, 0, 0); Wherein, the bits in the second - type bit segment are arranged from left to right in the order from the lowest bit position to the highest bit position or from the highest bit position to the lowest bit position.

7. The method according to claim 4, wherein The middle bit sequence includes 11 bits, and the second bit sequence includes: a consecutive first second-type bit segment and a second second-type bit segment, and the 2 d second bit sequences include: The second bit sequence where the first second - type bit segment is (0, 0, 0, 0) and the second second - type bit segment is (0, 0, 0, 0); The second bit sequence where the first second - type bit segment is (0, 0, 0, 0) and the second second - type bit segment is (1, 0, 0, 0); The second bit sequence where the first second - type bit segment is (1, 0, 0, 0) and the second second - type bit segment is (0, 0, 0, 0); The second bit sequence where the first second - type bit segment is (0, 1, 0, 0) and the second second - type bit segment is (0, 0, 0, 0); The second bit sequence where the first second - type bit segment is (1, 0, 0, 0) and the second second - type bit segment is (1, 0, 0, 0); The second bit sequence where the first second - type bit segment is (1, 1, 0, 0) and the second second - type bit segment is (0, 0, 0, 0); The second bit sequence where the first second - type bit segment is (0, 0, 0, 0) and the second second - type bit segment is (0, 1, 0, 0); The second bit sequence where the first second - type bit segment is (0, 0, 0, 0) and the second second - type bit segment is (1, 1, 0, 0); The second bit sequence where the first second - type bit segment is (0, 0, 0, 0) and the second second - type bit segment is (0, 0, 1, 0); The second bit sequence where the first second - type bit segment is (0, 0, 1, 0) and the second second - type bit segment is (0, 0, 0, 0); The second bit sequence where the first second - type bit segment is (1, 0, 0, 0) and the second second - type bit segment is (1, 1, 0, 0); The second bit sequence where the first second - type bit segment is (1, 0, 0, 0) and the second second - type bit segment is (0, 1, 0, 0); The second bit sequence where the first second - type bit segment is (0, 1, 0, 0) and the second second - type bit segment is (1, 0, 0, 0); The second bit sequence where the first second - type bit segment is (1, 1, 0, 0) and the second second - type bit segment is (1, 0, 0, 0); And any two of the following second bit sequences: The second bit sequence where the first second - type bit segment is (0, 0, 0, 0) and the second second - type bit segment is (0, 1, 1, 0); The second bit sequence where the first second - type bit segment is (0, 0, 0, 0) and the second second - type bit segment is (1, 0, 1, 0); The second bit sequence where the first second - type bit segment is (1, 0, 1, 0) and the second second - type bit segment is (0, 0, 0, 0); The second bit sequence where the first second - type bit segment is (1, 1, 1, 0) and the second second - type bit segment is (0, 0, 0, 0); The second bit sequence where the first second - type bit segment is (0, 0, 0, 0) and the second second - type bit segment is (1, 1, 1, 0); The second bit sequence where the first second - type bit segment is (0, 1, 1, 0) and the second second - type bit segment is (0, 0, 0, 0); Wherein, the bits in the second - type bit segment are arranged from left to right in the order from the lowest bit position to the highest bit position or from the highest bit position to the lowest bit position.

8. The method according to claim 4, characterized in that The middle bit sequence includes 10 bits. The second bit sequence includes: a consecutive first second-type bit segment and a second second-type bit segment. The 2 d second bit sequences include: The second bit sequence where the first second - type bit segment is (0, 0, 0, 0, 0, 0) and the second second - type bit segment is (0, 0, 0, 0, 0, 0); The second bit sequence where the first second - type bit segment is (0, 0, 0, 0, 0, 0) and the second second - type bit segment is (1, 0, 0, 0, 0, 0); The second bit sequence where the first second - type bit segment is (0, 0, 0, 0, 0, 0) and the second second - type bit segment is (0, 1, 0, 0, 0, 0); The second bit sequence in which the first second - type bit segment is (1, 0, 0, 0, 0, 0) and the second second - type bit segment is (0, 0, 0, 0, 0, 0); The second bit sequence in which the first second - type bit segment is (0, 1, 0, 0, 0, 0) and the second second - type bit segment is (0, 0, 0, 0, 0, 0); The second bit sequence in which the first second - type bit segment is (0, 0, 0, 0, 0, 0) and the second second - type bit segment is (1, 1, 0, 0, 0, 0); The second bit sequence in which the first second - type bit segment is (1, 1, 0, 0, 0, 0) and the second second - type bit segment is (0, 0, 0, 0, 0, 0); The second bit sequence in which the first second - type bit segment is (0, 1, 0, 0, 0, 0) and the second second - type bit segment is (0, 1, 0, 0, 0, 0); The second bit sequence in which the first second - type bit segment is (0, 1, 0, 0, 0, 0) and the second second - type bit segment is (1, 0, 0, 0, 0, 0); The second bit sequence in which the first second - type bit segment is (1, 0, 0, 0, 0, 0) and the second second - type bit segment is (1, 0, 0, 0, 0, 0); The second bit sequence in which the first second - type bit segment is (1, 0, 0, 0, 0, 0) and the second second - type bit segment is (0, 1, 0, 0, 0, 0); And any five second bit sequences from the following second bit sequences: The second bit sequence in which the first second - type bit segment is (0, 0, 1, 0, 0, 0) and the second second - type bit segment is (0, 0, 0, 0, 0, 0); The second bit sequence in which the first second - type bit segment is (1, 0, 1, 0, 0, 0) and the second second - type bit segment is (0, 0, 0, 0, 0, 0); The second bit sequence in which the first second - type bit segment is (0, 1, 1, 0, 0, 0) and the second second - type bit segment is (0, 0, 0, 0, 0, 0); The second bit sequence in which the first second - type bit segment is (0, 0, 0, 1, 0, 0) and the second second - type bit segment is (0, 0, 0, 0, 0, 0); The second bit sequence in which the first second - type bit segment is (1, 0, 0, 1, 0, 0) and the second second - type bit segment is (0, 0, 0, 0, 0, 0); The second bit sequence in which the first second - type bit segment is (0, 1, 0, 1, 0, 0) and the second second - type bit segment is (0, 0, 0, 0, 0, 0); The second bit sequence in which the first second - type bit segment is (1, 1, 1, 0, 0, 0) and the second second - type bit segment is (0, 0, 0, 0, 0, 0); The second bit sequence in which the first second - type bit segment is (0, 0, 0, 0, 0, 0) and the second second - type bit segment is (0, 0, 0, 1, 0, 0); The second bit sequence in which the first second - type bit segment is (0, 0, 0, 0, 0, 0) and the second second - type bit segment is (0, 0, 1, 0, 0, 0); The second bit sequence in which the first second - type bit segment is (0, 0, 0, 0, 0, 0) and the second second - type bit segment is (1, 0, 1, 0, 0, 0); The second bit sequence in which the first second - type bit segment is (0, 0, 0, 0, 0, 0) and the second second - type bit segment is (0, 1, 1, 0, 0, 0); The second bit sequence in which the first second - type bit segment is (0, 0, 0, 0, 0, 0) and the second second - type bit segment is (1, 0, 0, 1, 0, 0); The second bit sequence in which the first second - type bit segment is (0, 0, 0, 0, 0, 0) and the second second - type bit segment is (1, 1, 1, 0, 0, 0); The second bit sequence in which the first second - type bit segment is (0, 0, 0, 0, 0, 0) and the second second - type bit segment is (0, 1, 0, 1, 0, 0); Wherein, the bits in the second - type bit segment are arranged from left to right in the order from the lowest bit position to the highest bit position or from the highest bit position to the lowest bit position.

9. The method according to claim 4, characterized in that, The intermediate bit sequence includes 11 bits, and the second bit sequence includes: a consecutive first second-type bit segment and a second second-type bit segment, the 2 d second bit sequences include: The second bit sequence in which the first second - type bit segment is (0, 0, 0, 0, 0, 0, 0) and the second second - type bit segment is (0, 0, 0, 0, 0, 0, 0); The second bit sequence in which the first second - type bit segment is (0, 1, 0, 0, 0, 0, 0) and the second second - type bit segment is (0, 0, 0, 0, 0, 0, 0); The second bit sequence in which the first second - type bit segment is (1, 1, 0, 0, 0, 0, 0) and the second second - type bit segment is (0, 0, 0, 0, 0, 0, 0); The second bit sequence in which the first second - type bit segment is (1, 0, 0, 0, 0, 0, 0) and the second second - type bit segment is (0, 0, 0, 0, 0, 0, 0); The second bit sequence in which the first second - type bit segment is (0, 0, 0, 0, 0, 0, 0) and the second second - type bit segment is (1, 0, 0, 0, 0, 0, 0); The second bit sequence in which the first second - type bit segment is (0, 0, 0, 0, 0, 0, 0) and the second second - type bit segment is (0, 1, 0, 0, 0, 0, 0); The second bit sequence in which the first second - type bit segment is (0, 0, 0, 0, 0, 0, 0) and the second second - type bit segment is (1, 1, 0, 0, 0, 0, 0); And any nine of the following second bit sequences: The second bit sequence in which the first second - type bit segment is (0, 0, 0, 0, 0, 0, 0) and the second second - type bit segment is (0, 0, 1, 0, 0, 0, 0); The second bit sequence in which the first second - type bit segment is (1, 0, 0, 0, 0, 0, 0) and the second second - type bit segment is (0, 1, 0, 0, 0, 0, 0); The first second - type bit segment is (1, 0, 0, 0, 0, 0, 0), and the second second - type bit segment is (1, 1, 0, 0, 0, 0, 0) of the second bit sequence; The first second - type bit segment is (0, 1, 0, 0, 0, 0, 0), and the second second - type bit segment is (1, 0, 0, 0, 0, 0, 0) of the second bit sequence; The first second - type bit segment is (0, 1, 0, 0, 0, 0, 0), and the second second - type bit segment is (0, 1, 0, 0, 0, 0, 0) of the second bit sequence; The first second - type bit segment is (0, 1, 0, 0, 0, 0, 0), and the second second - type bit segment is (1, 1, 0, 0, 0, 0, 0) of the second bit sequence; The first second - type bit segment is (1, 1, 0, 0, 0, 0, 0), and the second second - type bit segment is (1, 0, 0, 0, 0, 0, 0) of the second bit sequence; The first second - type bit segment is (1, 1, 0, 0, 0, 0, 0), and the second second - type bit segment is (0, 1, 0, 0, 0, 0, 0) of the second bit sequence; The first second - type bit segment is (1, 1, 0, 0, 0, 0, 0), and the second second - type bit segment is (1, 1, 0, 0, 0, 0, 0) of the second bit sequence; The first second - type bit segment is (1, 0, 0, 0, 0, 0, 0), and the second second - type bit segment is (1, 0, 0, 0, 0, 0, 0) of the second bit sequence; The first second - type bit segment is (0, 0, 1, 0, 0, 0, 0), and the second second - type bit segment is (0, 0, 0, 0, 0, 0, 0) of the second bit sequence; Wherein, the bits in the second - type bit segment are arranged from left to right in the order from low to high or from high to low according to the bit positions.

10. A sequence processing method, characterized in that, The method includes: Splitting a plurality of target bit sequences from a bit sequence; Performing an inverse process of distribution matching processing on the plurality of target bit sequences to obtain a plurality of intermediate bit sequences; Obtain an initial bit sequence according to the multiple intermediate bit sequences and an expansion table; the expansion table is used to indicate a one-to-one correspondence between 2 d first bit sequences and 2 d second bit sequences, the number of bits in the first bit sequence is d, d≥2, and the number of bits in the second bit sequence is h, h>d; the first bit sequence is composed of a first type of bit segments of multiple bit subsequences in the initial bit sequence, and the second bit sequence is composed of a second type of bit segments of the multiple intermediate bit sequences, and the second type of bit segments are multiple bits of the highest bit of the intermediate bit sequence; the low-amplitude bit numbers of the 2 d second bit sequences are all greater than or equal to the low-amplitude bit numbers of the 2 h second bit sequences except the 2 d second bit sequences; the low-amplitude bit number of any one of the second bit sequences is: the number of bits used to map to the lowest amplitude bit among the multiple target bit sequences corresponding to the any one of the second bit sequences.

11. A chip, characterized in that, The chip includes a processor and an interface. The processor is configured to run the method according to any one of claims 1 to 9 to process the bit sequence, and the processor is further configured to obtain a data frame according to the processed bit sequence, and the interface is configured to output the data frame.

12. A chip, characterized in that, The chip includes a processor and an interface. The interface is configured to receive a data frame, the processor is configured to obtain a bit sequence according to the data frame, and run the method according to claim 10 to process the obtained bit sequence.

13. An optical module, characterized in that, Including an optical transceiver and a chip; The chip is configured to run the method according to any one of claims 1 to 9 to process the bit sequence, and the chip is further configured to obtain a first data frame according to the bit sequence processed by running the method according to any one of claims 1 to 9, and the optical transceiver is configured to transmit a first optical signal according to the first data frame; The optical transceiver is configured to obtain a second data frame based on the received second optical signal. The chip is configured to obtain a bit sequence based on the second data frame and execute the method recited in claim 10 to process the bit sequence obtained based on the second data frame.

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