Display panel and manufacturing method therefor, and display apparatus

Abstract

A display panel and a manufacturing method therefor, and a display apparatus. The display panel comprises a base substrate, a pixel define layer located on the base substrate, and a light-emitting functional layer located on the side of the pixel define layer away from the base substrate. The pixel define layer comprises a defining portion for defining a pixel opening. The light-emitting functional layer comprises carrier layers, wherein the carrier layers are consecutive and cover the pixel define layer. Each carrier layer comprises a first area and a second area except the first area, wherein the orthographic projection of the first area on a first surface of the base substrate is located in the orthographic projection of the defining portion on the first surface of the base substrate, and the carrier mobility of the first area is smaller than the carrier mobility of the second area. The present application can prevent a crosstalk current from being formed between adjacent sub-pixels of the display panel.

Description

Display panel and manufacturing method thereof, and display device

[0001] This application claims priority to Chinese patent application number 202311813450.8 filed on December 26, 2023, entitled “Display panel, preparation method thereof, and display device”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to a display panel, a method for manufacturing the same, and a display device. Background Art

[0003] With the continuous development of display technology, organic light emitting diode (LED) display panels can not only meet the needs of small-size displays, but also be used in high-resolution and large-size displays. LED display panels can be used in televisions, video players, personal computers (PCs), home theaters, smartphones, virtual reality devices, and so on. Resolution is the number of pixels per inch (PPI). Virtual reality devices include virtual reality (VR) devices and augmented reality (AR) devices.

[0004] At the same time, LED display panels have excellent display characteristics, such as high resolution, high brightness, rich colors, low driving voltage, fast response speed, and low power consumption, giving them broad development prospects. Summary of the Invention

[0005] The present application provides a display panel, a method for manufacturing the same, and a display device.

[0006] In a first aspect, a display panel is provided, comprising:

[0007] substrate;

[0008] a pixel definition layer, located on the base substrate, comprising a defining portion for defining a pixel opening;

[0009] A light-emitting functional layer is located on a side of the pixel definition layer away from the base substrate, and includes a carrier layer. The carrier layer is continuous and covers the pixel definition layer. The carrier layer includes a first region and a second region other than the first region. The orthographic projection of the first region on the first surface of the base substrate is located within the orthographic projection of the limiting portion on the first surface of the base substrate. The carrier mobility of the first region is less than the carrier mobility of the second region.

[0010] Optionally, the first region is a region that has been doped or photoirradiated.

[0011] Optionally, the carrier layer includes at least one of a hole injection layer, a hole transport layer, an electron injection layer, an electron transport layer and a charge generation layer.

[0012] Optionally, the display panel also includes: a packaging structure located on the side of the light-emitting functional layer away from the base substrate, the surface of the packaging structure away from the base substrate having a first thinning groove, the orthographic projection of the first thinning groove on the first surface of the base substrate coincides with the orthographic projection of the first region on the first surface of the base substrate.

[0013] Optionally, a minimum distance between the bottom surface of the first thinning groove and the surface of the packaging structure close to the substrate is greater than 1000 angstroms.

[0014] Optionally, a width of a first cross-section of the first thinning groove is smaller than a width of the limiting portion away from a surface of the base substrate, and the first cross-section is parallel to a thickness direction of the base substrate.

[0015] Optionally, two edges of the defining portion away from the surface of the base substrate have a raised structure, and the two edges are two edges arranged along the width direction of the defining portion away from the surface of the base substrate, and a second thinning groove is provided between the raised structures of the two edges, and the thickness of the portion of the light-emitting functional layer located in the second thinning groove is smaller than the thickness of the portion of the light-emitting functional layer located in the pixel opening.

[0016] Optionally, the orthographic projection of the second thinning groove on the first surface of the base substrate is located within the orthographic projection of the first thinning groove on the first surface of the base substrate.

[0017] Optionally, a slope angle of a side surface of the protruding structure facing the pixel opening is smaller than a slope angle of a side surface of the protruding structure facing the second thinning groove.

[0018] Optionally, the display panel also includes: an anode layer, located between the pixel definition layer and the base substrate, the anode layer includes a plurality of anodes, the pixel definition layer includes a plurality of pixel openings, the plurality of anodes are located one-to-one in the plurality of pixel openings, the limiting portion for limiting any pixel opening covers the edge of the anode in any pixel opening, the width of the first cross-section of the second thinning groove is smaller than the width of the gap between two adjacent anodes, and the first cross-section of the second thinning groove is parallel to the thickness direction of the base substrate.

[0019] Optionally, the material of the pixel definition layer is an inorganic material, the slope angle of the defining portion is greater than 45°, and the distance between the surface of the defining portion away from the base substrate and the surface of the anode layer away from the base substrate is less than or equal to 1000 angstroms.

[0020] Optionally, the material of the pixel definition layer is an organic material, the slope angle of the defining portion is less than 45°, and the distance between the surface of the defining portion away from the base substrate and the surface of the anode layer away from the base substrate is greater than 1000 angstroms.

[0021] Optionally, the display panel further includes: an etching stop layer located on a side of the light-emitting functional layer away from the base substrate.

[0022] Optionally, the packaging structure includes a plurality of stacked packaging layers, and the plurality of packaging layers include the etch stop layer.

[0023] Optionally, the multiple encapsulation layers further include two first encapsulation layers located on both sides of the etch stop layer.

[0024] Optionally, the multiple encapsulation layers further include a second encapsulation layer located on a side of the first encapsulation layer away from the etch stop layer.

[0025] Optionally, the etch stop layer, the first encapsulation layer and the second encapsulation layer satisfy at least one of the following: the material of the etch stop layer includes aluminum oxide (Al2O3); the material of the first encapsulation layer includes silicon nitride (SiN); and the material of the second encapsulation layer includes silicon oxide (SiO).

[0026] Optionally, the light-emitting functional layer is an organic light-emitting functional layer or an inorganic light-emitting functional layer.

[0027] In a second aspect, a display device is provided, comprising the display panel as described in the first aspect and its optional implementation manner.

[0028] In a third aspect, a method for manufacturing a display panel is provided, the method comprising:

[0029] forming a pixel definition layer on the base substrate, wherein the pixel definition layer includes a defining portion for defining a pixel opening;

[0030] forming a light-emitting functional layer on a side of the pixel definition layer away from the base substrate, wherein the light-emitting functional layer includes a carrier layer, the carrier layer is continuous, and the carrier layer covers the pixel definition layer;

[0031] The first region of the carrier layer is modified so that the carrier mobility of the first region is less than the carrier mobility of the second region of the carrier layer, the second region is the region on the carrier layer except the first region, and the orthographic projection of the first region on the first surface of the base substrate is located within the orthographic projection of the limiting portion on the first surface of the base substrate.

[0032] Optionally, the modifying the first region of the carrier layer includes: modifying the first region of the carrier layer by doping or light irradiation.

[0033] Optionally, before performing the modification treatment on the first region of the carrier layer, the method further includes:

[0034] forming a packaging structure on a side of the light-emitting functional layer away from the base substrate;

[0035] forming a first thinning groove on a surface of the packaging structure away from the base substrate, wherein an orthographic projection of the first thinning groove on the first surface of the base substrate coincides with an orthographic projection of the first region on the first surface of the base substrate;

[0036] The modifying the first region of the carrier layer includes: modifying the first region of the carrier layer starting from the location of the first thinning groove.

[0037] Optionally, after performing the modification treatment on the first region of the carrier layer, the method further includes: filling the first thinning groove.

[0038] Optionally, the carrier layer includes at least one of a hole injection layer, a hole transport layer, an electron injection layer, an electron transport layer and a charge generation layer.

[0039] Optionally, a minimum distance between the bottom surface of the first thinning groove and the surface of the packaging structure close to the substrate is greater than 1000 angstroms.

[0040] Optionally, a width of a first cross-section of the first thinning groove is smaller than a width of the limiting portion away from a surface of the base substrate, and the first cross-section is parallel to a thickness direction of the base substrate.

[0041] Optionally, two edges of the defining portion away from the surface of the base substrate have a raised structure, and the two edges are two edges arranged along the width direction of the defining portion away from the surface of the base substrate, and a second thinning groove is provided between the raised structures of the two edges, and the thickness of the portion of the light-emitting functional layer located in the second thinning groove is smaller than the thickness of the portion of the light-emitting functional layer located in the pixel opening.

[0042] Optionally, the orthographic projection of the second thinning groove on the first surface of the base substrate is located within the orthographic projection of the first thinning groove on the first surface of the base substrate.

[0043] Optionally, a slope angle of a side surface of the protruding structure facing the pixel opening is smaller than a slope angle of a side surface of the protruding structure facing the second thinning groove.

[0044] Optionally, before forming the pixel definition layer on the base substrate, the method further comprises: forming an anode layer on the base substrate, wherein the anode layer comprises a plurality of anodes;

[0045] The method of forming a pixel definition layer on a base substrate includes: forming a pixel definition layer on a side of the anode layer away from the base substrate, the pixel definition layer including a plurality of pixel openings, the plurality of anodes being located one-to-one in the plurality of pixel openings, a limiting portion for limiting any pixel opening covering an edge of the anode in any pixel opening, a width of a first cross-section of the second thinning groove being smaller than a width of a gap between two adjacent anodes, and the first cross-section of the second thinning groove being parallel to a thickness direction of the base substrate.

[0046] Optionally, the material of the pixel definition layer is an inorganic material, the slope angle of the defining portion is greater than 45°, and the distance between the surface of the defining portion away from the base substrate and the surface of the anode layer away from the base substrate is less than or equal to 1000 angstroms.

[0047] Optionally, the material of the pixel definition layer is an organic material, the slope angle of the defining portion is less than 45°, and the distance between the surface of the defining portion away from the base substrate and the surface of the anode layer away from the base substrate is greater than 1000 angstroms.

[0048] Optionally, the display panel further includes: an etching stop layer located on a side of the light-emitting functional layer away from the base substrate.

[0049] Optionally, forming an encapsulation structure on a side of the light-emitting functional layer away from the base substrate includes: forming a plurality of stacked encapsulation layers on a side of the light-emitting functional layer away from the base substrate, the plurality of encapsulation layers including the etching stop layer.

[0050] Optionally, the multiple encapsulation layers further include two first encapsulation layers located on both sides of the etch stop layer.

[0051] Optionally, the multiple encapsulation layers further include a second encapsulation layer located on a side of the first encapsulation layer away from the etch stop layer.

[0052] Optionally, the etch stop layer, the first encapsulation layer and the second encapsulation layer satisfy at least one of the following: a material of the etch stop layer includes aluminum oxide; a material of the first encapsulation layer includes silicon nitride; and a material of the second encapsulation layer includes silicon oxide.

[0053] Optionally, the light-emitting functional layer is an organic light-emitting functional layer or an inorganic light-emitting functional layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0054] In order to more clearly illustrate the technical solutions in this application or related technologies, the following briefly introduces the drawings required for use in the embodiments or related technical descriptions. Obviously, the drawings described below are merely embodiments of this application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0055] FIG1 is a schematic structural diagram of an OLED display panel with a dual-stack structure;

[0056] FIG2 is a schematic structural diagram of a WOLED display panel;

[0057] FIG3 is a schematic circuit diagram of a sub-pixel in the WOLED display panel shown in FIG2 ;

[0058] FIG4 is a schematic cross-sectional view of a pixel in a display panel at position AA;

[0059] FIG5 is a schematic diagram of a circuit principle in which crosstalk occurs;

[0060] FIG6 is a diagram showing the relationship between the voltage and current density of each sub-pixel when crosstalk occurs;

[0061] FIG7 is a schematic structural diagram of a display panel according to an embodiment of the present application;

[0062] FIG8 is a schematic structural diagram of another display panel according to an embodiment of the present application;

[0063] FIG9 is a schematic structural diagram of another display panel according to an embodiment of the present application;

[0064] FIG10 is a flow chart of a method for manufacturing a display panel according to an embodiment of the present application;

[0065] 11 to 14 are schematic diagrams of a process for preparing a display panel provided in an embodiment of the present application. DETAILED DESCRIPTION

[0066] To make the principles, technical solutions, and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the embodiments and with reference to the accompanying drawings. It should be noted that unless otherwise specified, the relative arrangement of the components, numerical expressions, and numerical values ​​described in these embodiments do not limit the scope of the present application. At the same time, it should be understood that for ease of description, the dimensions of the various parts shown in the drawings are not drawn according to the actual proportional relationship. The following description of at least one exemplary embodiment is actually merely illustrative and is in no way intended to limit the present application, its application, or use.

[0067] It should be noted that, unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present application should have the usual meanings understood by people with ordinary skills in the field to which this application belongs. "At least one" used in the embodiments of the present application refers to one or more, and "a plurality of" refers to two or more. "First", "second", "third" and similar words do not indicate any order, quantity or importance, but are only used to distinguish different components. "Include" or "comprising" and similar words mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0068] With the continuous development of display technology, light emitting diode (OLED) display panels can not only meet the display needs of small sizes, but can also be used in high-resolution and large-size display fields. Depending on the light-emitting functional layer in the LED display panel, the LED display panel may include an organic light emitting diode (OLED) display panel and an inorganic light emitting diode display panel. The light-emitting functional layer in the OLED display panel is an organic light-emitting functional layer, and the light-emitting functional layer in the inorganic light emitting diode display panel is an inorganic light-emitting functional layer. Typically, a small-sized OLED display panel adopts a dual-stack OLED structure (hereinafter referred to as a dual-stack structure). High-resolution OLED display panels and large-sized OLED display panels use refined masks, such as fine metal masks (FMM) during the preparation process. In order to adapt to the process limitations of the refined mask itself, high-resolution OLED display panels and large-sized OLED display panels usually adopt a white organic light emitting diode (WOLED) structure.

[0069] Please refer to Figure 1, which shows a schematic diagram of the structure of a dual-stack OLED display panel. The OLED display panel includes an anode layer 1, a first structure layer group 2-1, a charge generation layer 3, a second structure layer group 2-2, an electron injection layer (EIL) 4, and a cathode (CTD) layer 5, which are stacked in sequence. The first structure layer group 2-1 and the second structure layer group 2-2 are both used for light emission.

[0070] The first structure layer group 2-1 includes: a hole injection layer (HIL) 201, a hole transport layer (HTL) 202, an electron block layer (EBL) 203, an emission layer (EML) 204, a hole block layer (HBL) 205, and an electron transport layer (ETL) 206, which are stacked in sequence in a direction away from the anode layer 1. The electron blocking layer 203 includes a plurality of electron blocking patterns 2031. The emission layer 204 includes a B emission pattern 2041 for emitting blue light, a G emission pattern 2041 for emitting green light, and an R emission pattern 2041 for emitting red light, and the distribution of the B emission pattern 2041, the G emission pattern 2041, and the R emission pattern 2041 adopts an RGB-SBS structure. The plurality of emission patterns 2041 correspond one-to-one to the plurality of electron blocking patterns 2031. Each electron blocking pattern 2031 can have a different thickness according to its corresponding light-emitting pattern 2041. The thickness of the electron blocking pattern 2031 corresponding to the B light-emitting pattern 2041 is the smallest, the thickness of the electron blocking pattern 2031 corresponding to the R light-emitting pattern 2041 is the largest, and the thickness of the electron blocking pattern 2031 corresponding to the G light-emitting pattern 2041 is between the thickness of the electron blocking pattern 2031 corresponding to the R light-emitting pattern 2041 and the thickness of the electron blocking pattern 2031 corresponding to the B light-emitting pattern 2041.

[0071] The structure of the second structural layer group 2 - 2 is the same as that of the first structural layer group 2 - 1 .

[0072] In the dual-stack OLED display panel as shown in Figure 1, each sub-pixel includes: an anode layer 1, a hole injection layer 201 in the first structure layer group 2-1, a hole transport layer 202 in the first structure layer group 2-1, an electron blocking pattern 2031 in the first structure layer group 2-1, a light-emitting pattern 2041 corresponding to the electron blocking pattern 2031 in the first structure layer group 2-1, a hole blocking layer 205 in the first structure layer group 2-1, an electron transport layer 206 in the first structure layer group 2-1, a charge generation layer 3, a hole injection layer 201 in the second structure layer group 2-2, a hole transport layer 202 in the second structure layer group 2-2, an electron blocking pattern 2031 in the second structure layer group 2-2, a light-emitting pattern 2041 corresponding to the electron blocking pattern 2031 in the second structure layer group 2-2, a hole blocking layer 205 in the second structure layer group 2-2, an electron transport layer 206 in the second structure layer group 2-2, an electron injection layer 4 and a cathode 5. In each sub-pixel, the electron blocking pattern 2031 in the first structure layer group 2-1, the luminescent pattern 2041 in the first structure layer group 2-1, the electron blocking pattern 2031 in the second structure layer group 2-2, and the luminescent pattern 2041 in the second structure layer group 2-2 correspond one to one.

[0073] In the dual-stack OLED display panel shown in FIG1 , each sub-pixel can be controlled individually to control the light output intensity of sub-pixels of different colors according to display requirements, thereby achieving full-color display.

[0074] The dual-stack OLED display panel shown in FIG1 includes two structural layer groups for emitting light, each structural layer group including a light-emitting layer 204. Therefore, the OLED display panel includes two stacked light-emitting layers 204. The number of light-emitting layers in the dual-stack OLED display panel is twice that of a single-stack OLED display panel, and the service life of the dual-stack OLED display panel is four times that of a single-stack OLED display panel.

[0075] Please refer to Figure 2, which shows a schematic diagram of the structure of a WOLED display panel. The WOLED display panel includes a backplane 25 and, stacked in a direction away from the backplane 25, an anode layer 1, a hole injection layer 201, a hole transport layer 202, a blue fluorescent light-emitting layer (FL Blue EML) 21, an electron transport layer 206, a charge generation layer 3, a hole transport layer 202, a red and green phosphorescent light-emitting layer (Ph.RG EML) 22, an electron transport layer 206, an electron injection layer 4, a cathode 5, a thin film encapsulation layer 23 (TFE), and a color filter layer 24. The color filter layer is also called a color filter (CF). The anode layer 1 includes multiple anodes 101, and the color filter layer 24 includes multiple color resist blocks 2401 corresponding to the multiple anodes 101. The multiple color resist blocks 2041 include R color resist blocks 2401 for transmitting red light, G color resist blocks 2401 for transmitting green light, and B color resist blocks 2401 for transmitting blue light.

[0076] In the WOLED display panel shown in Figure 2, each subpixel includes a stacked anode 101, a hole injection layer 201, a hole transport layer 202, a blue fluorescent light-emitting layer 21, an electron transport layer 206, a charge generation layer 3, a hole transport layer 202, a red and green phosphorescent light-emitting layer 22, an electron transport layer 206, an electron injection layer 4, a cathode 5, and a color resist block 2401 corresponding to the anode 101. Figure 3 shows a schematic circuit diagram of a subpixel in the WOLED display panel shown in Figure 2. Node a in Figure 3 represents the cathode 5, node b represents the anode 101, EL1 represents the blue fluorescent light-emitting layer 21, EL2 represents the red and green phosphorescent light-emitting layer 22, and CGL represents the charge generation layer 3. As can be seen from Figures 2 and 3, the blue fluorescent light-emitting layer 21 and the red and green phosphorescent light-emitting layer 22 are connected in series via the charge generation layer 3. The blue fluorescence emitted by the blue fluorescent light-emitting layer 21 and the red and green phosphorescent light emitted by the red and green phosphorescent light-emitting layer 22 mix to form white light, which, combined with the color filter layer 24, enables full-color display.

[0077] It is understood that the mixing of blue fluorescence and red and green phosphorescence to form white light is merely illustrative and not limiting. For example, a blue fluorescent layer and a yellow phosphorescent layer can be connected in series, and white light can be generated by mixing the blue fluorescence emitted by the blue fluorescent layer and the yellow phosphorescent light emitted by the yellow phosphorescent layer.

[0078] Based on the above description, it can be seen that the display panel shown in Figure 2 and the display panel shown in Figure 3 both include a hole injection layer 201, a hole transport layer 202, an electron injection layer 4, an electron transport layer 206 and a charge generation layer 3. Carriers can migrate in these structural layers, so these structural layers can be called carrier layers (or charge connection layers). According to Figures 1 and 2, it can be seen that the carrier layer can be a whole layer structure, and all sub-pixels in the display panel share the carrier layer. When carriers migrate in the carrier layer, although most of the carriers will migrate toward the light-emitting layer, there is still a small part of the carriers that will migrate laterally along the carrier layer. The lateral migration of this small part of the carriers will cause crosstalk current to form between adjacent sub-pixels.

[0079] Figure 4 shows a schematic cross-sectional view of a pixel 31 in a display panel at position AA. Pixel 31 includes a red sub-pixel (also known as an R sub-pixel) 3101 for emitting red light, a green sub-pixel (also known as a G sub-pixel) 3101 for emitting green light, and a blue sub-pixel (also known as a B sub-pixel) 3101 for emitting blue light. To highlight the direction of crosstalk current, Figure 4 simplifies the structural layers of the display panel. Referring to the schematic cross-sectional view in Figure 4, the defining portion 33 corresponds to the area between the red sub-pixel 3101 and the blue sub-pixel 3101 at position AA. The portion to the left of the defining portion 33 corresponds to the red sub-pixel 3101 at position AA, and the portion to the right of the defining portion 33 corresponds to the blue sub-pixel 3101 at position AA. The defining portion 33 covers the edge of the anode 101 of the red sub-pixel 3101 and the edge of the anode 101 of the blue sub-pixel 3101. The anode 101 of the red sub-pixel 3101 and the anode 101 of the blue sub-pixel 3101 are respectively connected to the pixel control circuit. The hole injection layer 201 covers the anode 101 and the defining portion 33, and the hole transport layer 202 is located on the side of the hole injection layer 201 away from the anode 101. The structure located on the left side of the defining portion 33 and covering the hole transport layer 202 is the light-emitting pattern 2041 of the red sub-pixel 3101 (i.e., red light-emitting pattern 2041). The structure located on the right side of the defining portion 33 and covering the hole transport layer 202 is the light-emitting pattern 2041 of the blue sub-pixel 3101 (i.e., blue light-emitting pattern 2041). The structural layer 32 includes a stacked electron transport layer and a cathode, and the structural layer 32 covers the light-emitting pattern 2041 and a portion of the hole transport layer 202.

[0080] When the blue sub-pixel 3101 is required to emit light and the red sub-pixel 3101 is not required to emit light, ideally, the carriers migrate from the hole injection layer 201 through the hole transport layer 202 to the blue light-emitting pattern 2041 (as shown by the hollow arrows in Figure 4). However, in actual applications, a portion of the carriers will migrate laterally in the hole injection layer 201, and these laterally migrated carriers will migrate across the limiting portion 33 to the red sub-pixel 3101, resulting in the formation of a crosstalk current flowing from the blue sub-pixel 3101 to the red sub-pixel 3101 (as shown by the dotted arrows in Figure 4). Since the cathode 5 is a whole-layer structure, under the action of this crosstalk current, not only the blue sub-pixel 3101 will emit light, but the red sub-pixel 3101 will also emit light, which will cause poor display.

[0081] Figure 5 illustrates the above process in the form of a circuit diagram. Position d in Figure 5 represents the anode of the blue sub-pixel, and position c represents the common cathode. Light-emitting element B is the light-emitting element for the blue sub-pixel, light-emitting element R is the light-emitting element for the red sub-pixel, and light-emitting element G is the light-emitting element for the green sub-pixel. As shown in Figure 5, when the blue sub-pixel emits light, the red and green sub-pixels also emit light due to the crosstalk current.

[0082] FIG6 shows a graph of the current (i.e., crosstalk current) measured at the anode of the red sub-pixel and the anode of the green sub-pixel when the blue sub-pixel is lit and the red sub-pixel and the green sub-pixel are not lit. The horizontal axis in FIG6 represents voltage in volts (V); the vertical axis represents current density in milliamperes per square centimeter (mA / cm 2 As shown in Figure 6, when the blue sub-pixel is lit and the red and green sub-pixels are not lit, current (i.e., crosstalk current) can be measured at both the anodes of the red and green sub-pixels. Furthermore, as the voltage increases, the current measured at both the anodes of the red and green sub-pixels increases. These crosstalk currents cause crosstalk.

[0083] After research, the applicant found that since the lateral migration of carriers in the carrier layer will form crosstalk current, then in the carrier layer, hindering the lateral migration of carriers between adjacent sub-pixels can at least to a certain extent avoid the formation of crosstalk current and reduce the display defects caused by crosstalk current.

[0084] In view of this, embodiments of the present application provide a display panel, a method for manufacturing the same, and a display device. In the display panel, lateral migration of carriers between adjacent sub-pixels is hindered in the carrier layer.

[0085] Please refer to Figure 7, which shows a schematic structural diagram of a display panel provided by an embodiment of the present application. The display panel includes: a base substrate 41, a pixel definition layer 42 located on the base substrate 41, and a light-emitting functional layer 43 located on the side of the pixel definition layer 42 away from the base substrate 41. The pixel definition layer 42 includes a defining portion 4201 for defining a pixel opening. The light-emitting functional layer 43 includes a carrier layer 4301, the carrier layer 4301 is continuous, and the carrier layer 4301 covers the pixel definition layer 42. The carrier layer 4301 includes a first region 44 and a second region 45 other than the first region 44. The orthographic projection of the first region 44 on the first surface of the base substrate 41 is located within the orthographic projection of the defining portion 4201 on the first surface of the base substrate 41. The carrier mobility of the first region 44 is less than the carrier mobility of the second region 45.

[0086] The first surface of the base substrate 41 can be a surface of the base substrate 41 close to the pixel definition layer 42, or a surface of the base substrate 41 away from the pixel definition layer 42, which is not limited in the embodiments of the present application. The pixel definition layer 42 is in a grid shape, and the pixel definition layer 42 includes a plurality of pixel openings and a limiting portion 4201 for limiting the plurality of pixel openings. Each pixel opening corresponds to a sub-pixel (or each pixel opening is used to set a sub-pixel), and each sub-pixel includes a light-emitting functional layer 43. Multiple sub-pixels (for example, all sub-pixels) of the display panel can share the light-emitting functional layer 43. The carrier layer 4301 is a whole-layer structure, and multiple sub-pixels (for example, all sub-pixels) of the display panel can share the carrier layer 4301.

[0087] The first region 44 of the carrier layer 4301 corresponds to the defined portion 4201 of the pixel definition layer 42, and the second region 45 of the carrier layer 4301 corresponds to the pixel opening of the pixel definition layer 42. The orthographic projection of the first region 44 on the first surface of the substrate 41 lies within the orthographic projection of the corresponding defined portion 4201 on the first surface of the substrate 41; the orthographic projection of the second region 45 on the first surface of the substrate 41 overlaps the orthographic projection of the corresponding pixel opening on the first surface of the substrate 41. When carriers migrate laterally in the carrier layer 4301, the carrier mobility of the first region 44 is lower than that of the second region 45, resulting in a lower carrier mobility in the first region 44 and a higher carrier mobility in the second region 45. Therefore, the first region 44 will hinder the lateral migration of carriers, while the second region 45 will not hinder the lateral migration of carriers. Thus, the lateral migration range of carriers in the carrier layer 4301 is limited to the second region 45, thereby avoiding crosstalk between adjacent sub-pixels caused by the lateral migration of carriers between adjacent second regions 45, thereby ensuring the display effect of the display panel.

[0088] The light-emitting functional layer 43 is a structural layer having a light-emitting function, which may include a stacked hole injection layer, a hole transport layer, a light-emitting layer, an electron transport layer, and an electron injection layer. For example, the light-emitting functional layer 43 includes a structural layer between the anode layer 1 and the cathode 5 in the display panel shown in Figure 1. For another example, the light-emitting functional layer 43 includes a structural layer between the anode layer 1 and the cathode 5 in the display panel shown in Figure 2.

[0089] In the embodiment of the present application, the following two implementation methods can be used to achieve that the carrier mobility of the first region 44 of the carrier layer 4301 is lower than the carrier mobility of the second region 45 of the carrier layer 4301.

[0090] In one implementation, different materials are used to form the first region 44 and the second region 45 of the carrier layer 4301. That is, the first region 44 of the carrier layer 4301 is formed using a material with lower carrier mobility, while the second region 45 of the carrier layer 4301 is formed using a material with higher carrier mobility. In another implementation, the carrier layer 4301 is formed using the same material, and then the first region 44 of the carrier layer 4301 is modified to change its electrical properties, thereby reducing its carrier mobility. Considering production costs and process complexity, in actual production, one can choose to first form the carrier layer 4301 using the same material and then modify the first region 44. The choice of modification method requires, on the one hand, a low process difficulty, and, on the other hand, the modification process must minimize the structural changes to the carrier layer 4301. In an optional embodiment, the first region 44 is modified through a doping process or a light irradiation process. That is, the first region 44 is modified by doping or light irradiating the first region 44 .

[0091] In the embodiment of the present application, carrier layer 4301 includes at least one of a hole injection layer, a hole transport layer, an electron injection layer, an electron transport layer, and a charge generation layer. For example, carrier layer 4301 includes a hole injection layer. First, the hole injection layer is formed from the same material, and the carrier mobility of each region of the hole injection layer is the same. Then, a first region 44 of the hole injection layer is modified by a doping process or a light irradiation process to reduce the carrier mobility of the first region 44. The carrier mobility of the first region 44 is less than the carrier mobility of the second region 45 of the hole injection layer excluding the first region 44.

[0092] In an optional embodiment, the doping process includes an ion implantation process, in which ions are doped into the first region 44 of the carrier layer 4301 to change the electrical properties of the first region 44, thereby modifying the first region 44. The ion implantation process accelerates ions using an electric field, so that after ions with a certain energy enter the carrier layer 4301, they gradually lose energy through nuclear energy loss and electronic energy loss, and eventually remain in the carrier layer 4301. The ion implantation process can change the electrical properties of the ion implantation area (that is, the first region 44 of the carrier layer 4301). The ion implantation process can achieve directionally controlled material properties.

[0093] In an optional embodiment, the first region 44 of the carrier layer 4301 is irradiated with light through a light irradiation process (e.g., a laser irradiation process) to change the electrical properties of the first region 44, thereby modifying the first region 44. The light irradiation process uses light to irradiate the first region 44 of the carrier layer 4301 to transfer the energy of the light to the first region 44 of the carrier layer 4301, causing the first region 44 to be ionized and excited, releasing orbital electrons to form free radicals, thereby changing the electrical properties of the first region 44. By controlling the conditions of the light irradiation, the electrical properties of the first region 44 of the carrier layer 4301 can be changed.

[0094] During the modification process of the first region 44 of the carrier layer 4301 by an ion implantation process or a light irradiation process, the second region 45 of the carrier layer 4301 can be shielded by using a mask or by coating a shielding material on the light-emitting functional layer 43, thereby preventing the modification process from affecting the electrical properties of the second region 45. Furthermore, the above two modification methods can also prevent changes in the structure of the carrier layer 4301 and will not affect the subsequent preparation of other structures (such as the cathode 5).

[0095] In an embodiment of the present application, the carrier layer 4301 includes at least one of a hole injection layer, a hole transport layer, an electron injection layer, an electron transport layer, and a charge generation layer. In the case where the carrier layer 4301 includes at least two of the hole injection layer, the hole transport layer, the electron injection layer, the electron transport layer, and the charge generation layer, the carrier layer may be modified after each carrier layer is formed, or all carrier layers may be uniformly modified after all carrier layers are formed. For example, if the carrier layer 4301 includes a hole injection layer and a hole transport layer, the hole injection layer may be formed first and the hole injection layer may be modified, and then the hole transport layer may be formed and the hole transport layer may be modified, or the hole injection layer and the hole transport layer may be formed first, and then the hole injection layer and the hole transport layer may be uniformly modified.

[0096] The process parameters for modifying the carrier layer 4301 can be set based on actual conditions. Taking ion implantation as an example, the number of ions implanted is determined by the accumulated beam current, and the implantation depth is determined by the voltage used to accelerate the ions (referred to as the acceleration voltage). These two parameters, the accumulated beam current and the acceleration voltage, can be precisely measured and strictly controlled by an external system. By controlling these two parameters, the carrier layer 4301 can be modified according to design requirements.

[0097] In an optional embodiment, as shown in FIG7 , the display panel further includes an encapsulation structure 46. The encapsulation structure 46 is located on a side of the light-emitting functional layer 43 away from the base substrate 41. The surface of the encapsulation structure 46 away from the base substrate 41 has a first thinning groove 4601. The orthographic projection of the first thinning groove 4601 on the first surface of the base substrate 41 coincides with the orthographic projection of the first region 44 of the carrier layer 4301 on the first surface of the base substrate 41.

[0098] In an optional embodiment, after forming the packaging structure 46, the first region 44 of the carrier layer 4301 is modified starting from the location of the first thinning groove 4601. In this way, the area of ​​the packaging structure 46 other than the area where the first thinning groove 4601 is located can block the second region 45 of the carrier layer 4301. Therefore, there is no need to use a mask or apply a shielding material on the light-emitting functional layer 43 to block the second region 45 of the carrier layer 4301. This can simplify the process flow of modifying the carrier layer 4301 and reduce the process difficulty and cost. In other embodiments, the first region 44 of the carrier layer 4301 can be modified before forming the packaging structure 46, which is not limited in this embodiment of the present application.

[0099] In an optional embodiment, after the encapsulation structure 46 is formed, the first region 44 of the carrier layer 4301 is modified by an ion implantation process or a light irradiation process. The greater the thickness of the encapsulation structure 46, the less likely it is for ions or light to penetrate the encapsulation structure 46. The smaller the thickness of the encapsulation structure 46, the easier it is for ions or light to penetrate the encapsulation structure 46. In an embodiment of the present application, since the surface of the encapsulation structure 46 away from the base substrate 41 has a first thinning groove 4601, the orthographic projection of the first thinning groove 4601 on the first surface of the base substrate 41 coincides with the orthographic projection of the first region 44 of the carrier layer 4301 on the first surface of the base substrate 41, that is, the position of the first thinning groove 4601 corresponds to the position of the first region 44 of the carrier layer 4301. Therefore, the thickness of the region of the package structure 46 corresponding to the first region 44 of the carrier layer 4301 (i.e., the region where the first thinning groove 4601 is located) is relatively small, while the thickness of the region of the package structure 46 corresponding to the second region 45 of the carrier layer 4301 (i.e., the region excluding the region where the first thinning groove 4601 is located) is relatively large. By controlling the process parameters of the modification treatment, ions or light can be allowed to pass through the thinner regions of the package structure 46 while being unable to pass through the thicker regions of the package structure 46, thereby achieving modification of the first region 44 of the carrier layer 4301. Taking the ion implantation process as an example, the acceleration voltage can be controlled so that ions can pass through the thinner regions of the package structure 46 while being unable to pass through the thicker regions of the package structure 46.

[0100] In an optional embodiment, as shown in FIG7 , the minimum distance f between the bottom surface of the first thinning groove 4601 and the surface of the package structure 46 proximate to the base substrate 41 is greater than 1000 angstroms. That is, the thickness of the region of the package structure 46 having the first thinning groove 4601 is greater than 1000 angstroms. In this way, the thickness of the region of the package structure 46 having the first thinning groove 4601 is not too small, thereby preventing the package structure 46 from having a too small thickness and thereby reducing its packaging capability. For example, this prevents the package structure 46 from having a too small thickness and thereby reducing its ability to block water and oxygen intrusion, thereby ensuring its ability to block water and oxygen intrusion.

[0101] In an optional embodiment, an etching process is used to form a first thinning groove 4601 on a surface of the encapsulation structure 46 away from the base substrate 41. The display panel further includes an etch stop layer located on a side of the light-emitting functional layer 43 away from the base substrate 41. The etch stop layer can provide an etching barrier to prevent over-etching during the process of forming the first thinning groove 4601 using the etching process, thereby preventing adverse effects on the light-emitting functional layer 43.

[0102] The etch stop layer and the encapsulation structure 46 are independent of each other, and the etch stop layer is located between the encapsulation structure 46 and the light-emitting functional layer 43. Alternatively, the encapsulation structure 46 includes a plurality of stacked encapsulation layers, each of which includes the etch stop layer; that is, the etch stop layer is one of the encapsulation layers in the encapsulation structure 46.

[0103] Please refer to Figure 8, which shows a schematic diagram of another display panel provided by an embodiment of the present application. As shown in Figure 8, the display panel also includes an etch stop layer 4602, which is located on the side of the light-emitting functional layer 43 away from the substrate 41. The etch stop layer 4602 is an encapsulation layer in the encapsulation structure 46.

[0104] In an optional embodiment, encapsulation structure 46 includes a plurality of stacked encapsulation layers, including an etch stop layer 4602 and two first encapsulation layers (not shown in FIG8 ) located on either side of the etch stop layer 4602. The plurality of encapsulation layers may further include a second encapsulation layer (not shown in FIG8 ) located on a side of the first encapsulation layer away from the etch stop layer 4602. Etch stop layer 4602, the first encapsulation layer, and the second encapsulation layer may satisfy at least one of the following conditions: the material of etch stop layer 4602 includes aluminum oxide (Al2O3); the material of the first encapsulation layer includes silicon nitride (SiN); and the material of the second encapsulation layer includes silicon oxide (SiO).

[0105] In one embodiment, package structure 46 includes an etch stop layer 4602 and two first encapsulation layers located on either side of etch stop layer 4602. The etch stop layer 4602 is made of Al2O3, and the first encapsulation layers are made of SiN. That is, package structure 46 includes a SiN layer, an Al2O3 layer, and a SiN layer stacked in sequence. In another embodiment, package structure 46 includes an etch stop layer 4602, two first encapsulation layers located on either side of etch stop layer 4602, and a second encapsulation layer located on a side of the first encapsulation layer away from the etch stop layer. The etch stop layer 4602 is made of Al2O3, the first encapsulation layers are made of SiN, and the second encapsulation layers are made of SiO. That is, package structure 46 includes a SiO layer, a SiN layer, an Al2O3 layer, and a SiN layer stacked in sequence. Alternatively, package structure 46 includes a SiN layer, an Al2O3 layer, a SiN layer, and a SiO layer stacked in sequence. Alternatively, the encapsulation structure 46 includes a SiO layer, a SiN layer, an Al 2 O 3 layer, a SiN layer, and a SiO layer stacked in sequence.

[0106] In addition to the above film layers, the packaging structure 46 may also include other film layers. The embodiment of the present application does not limit the structure of the packaging structure 46 and the film layers included in the packaging structure 46.

[0107] In an optional embodiment, as shown in Figures 7 and 8, the display panel further includes an anode layer 1. The anode layer 1 is located between the pixel definition layer 42 and the base substrate 41. The anode layer 1 includes a plurality of anodes 101, which are arranged at intervals. The pixel definition layer 42 includes a plurality of pixel openings, and the plurality of anodes 101 are located in the plurality of pixel openings in a one-to-one correspondence. The defining portion 4201 for defining any pixel opening covers the edge of the anode 101 in any pixel opening, thereby preventing edge leakage of the anode 101.

[0108] In an optional embodiment, as shown in Figures 7 and 8, the width g of the first cross-section of the first thinning groove 4601 is less than the width h of the defining portion 4201 away from the surface of the substrate 41 (i.e., g < h). The first cross-section of the first thinning groove 4601 is parallel to the thickness direction y of the substrate 41, and the first cross-section of the first thinning groove 4601 is perpendicular to the first surface of the substrate 41. In a specific embodiment, the orthographic projection of the first thinning groove 4601 on the first surface of the substrate 41 is located within the orthographic projection of the defining portion 4201 on the first surface of the substrate 41. Therefore, during the process of modifying the carrier layer 4301 at the location of the first thinning groove 4601 through a doping process or a light irradiation process, the scope of the modification process is limited to the area between the defining portion 4201 and the first thinning groove 4601 (i.e., the first region 44 of the carrier layer 4301). The pixel opening is located on both sides of the defining portion 4201. Therefore, the modification process does not affect the area of ​​the light-emitting functional layer 43 located within the pixel opening. Furthermore, it is possible to ensure that the thickness of the region corresponding to the pixel opening in the encapsulation structure 46 is greater, thereby reducing the risk of water and oxygen intruding into the pixel region.

[0109] In an embodiment of the present application, the width h of the defining portion 4201 away from the surface of the base substrate 41 can also be referred to as the width of the top of the defining portion 4201. The shape of the first cross-section of the defining portion 4201 can be semicircular or polygonal. The polygon can be a trapezoid or a rectangle, or other polygons, and the polygon can be a regular polygon or an irregular polygon. Figures 7 and 8 both take the shape of the first cross-section of the defining portion 4201 as a trapezoid as an example, then the width h of the defining portion 4201 away from the surface of the base substrate 41 is the width of the upper base of the trapezoid. Among them, the first cross-section of the defining portion 4201 is parallel to the thickness direction y of the base substrate 41, and the first cross-section of the defining portion 4201 is perpendicular to the first surface of the base substrate 41. For example, the first cross-section of the defining portion 4201 is parallel to the first cross-section of the first thinning groove 4601.

[0110] In an embodiment of the present application, the pixel definition layer 42 can be formed by an evaporation (EV) process. In the process of forming the pixel definition layer 42, an evaporation mask is required, and due to the different support functions of different positions of the evaporation mask or the different flatness of different positions on the substrate surface, an evaporation shadow area may be formed near the frame of the evaporation mask. That is, an evaporation shadow is formed. The formation of an evaporation shadow area during the formation of the pixel definition layer 42 can be avoided by controlling the height of the defining portion 4201 (that is, the thickness of the pixel definition layer 42).

[0111] In the embodiment of the present application, the material of the pixel definition layer 42 is an inorganic material or an organic material. The thickness of the pixel definition layer 42 may vary depending on the material of the pixel definition layer 42. The inorganic material may include SiO or SiN, and the organic material may include polyimide (PI).

[0112] As shown in Figures 7 and 8, the slope angle of the defining portion 4201 is α. In one embodiment, the material of the pixel definition layer 42 is an inorganic material, the slope angle α of the defining portion 4201 is greater than 45°, and the distance i between the surface of the defining portion 4201 away from the base substrate 41 and the surface of the anode layer 1 away from the base substrate 41 is less than or equal to 1000 angstroms. In another embodiment, the material of the pixel definition layer 42 is an organic material, the slope angle α of the defining portion 4201 is less than 45°, and the distance i between the surface of the defining portion 4201 away from the base substrate 41 and the surface of the anode layer 1 away from the base substrate 41 is greater than 1000 angstroms.

[0113] In an embodiment of the present application, the light-emitting functional layer 43 can be formed by an evaporation process. In combination with the foregoing, an evaporation shadow area may be formed during the evaporation process. When the evaporation shadow area is formed, the thickness of the portion of the structural layer located in the evaporation shadow area is generally less than the thickness of other areas. Generally, this is a process defect, which will cause the thickness of the structural layer to be uneven or even the structural layer to break. However, in an embodiment of the present application, the evaporation shadow area can make the thickness of the area corresponding to the limiting portion 4201 in the light-emitting functional layer 43 smaller, so as to facilitate the modification process. Since the effective area of ​​the light-emitting functional layer 43 is located in the pixel opening, the smaller thickness of the area corresponding to the limiting portion 4201 on the light-emitting functional layer 43 does not affect the normal display of the display panel.

[0114] In an optional embodiment, please refer to FIG9 , which shows a schematic diagram of another display panel provided in an embodiment of the present application. As shown in FIG9 , two edges of the defining portion 4201 away from the surface of the base substrate 41 have a raised structure 4202. The two edges are two edges distributed along the width direction x of the defining portion 4201 away from the surface of the base substrate 41. The raised structure 4202 of any edge extends along the any edge. A second thinning groove 4203 is provided between the raised structures 4202 of the two edges. The thickness of the portion of the light-emitting functional layer 43 located in the second thinning groove 4203 (or the portion corresponding to the second thinning groove 4203) is less than the thickness of the portion of the light-emitting functional layer 43 located in the pixel opening (or the portion corresponding to the pixel opening).

[0115] For the display panel shown in Figure 9, during the process of forming the light-emitting functional layer 43 through the evaporation process, due to the shielding effect of the protruding structure 4202, an evaporation shadow area will be formed in the second thinning groove 4203, resulting in the thickness of the portion of the light-emitting functional layer 43 located in the second thinning groove 4203 being relatively small. Correspondingly, the thickness of the portion of the carrier layer 4301 located in the second thinning groove 4203 is also relatively small. In the process of modifying the carrier layer 4301, taking ion implantation as an example, since the thickness of the portion of the carrier layer 4301 located in the second thinning groove 4203 is relatively small, ions are more easily implanted into the portion of the carrier layer 4301 located in the second thinning groove 4203, which helps to better change the carrier mobility of the first region 44 of the carrier layer 4301, thereby achieving the effect of preventing crosstalk.

[0116] 9 , the orthographic projection of the second thinning groove 4203 on the first surface of the base substrate 41 is located within the orthographic projection of the first thinning groove 4601 on the first surface of the base substrate 41. Exemplarily, the second thinning groove 4203 is directly opposite to the first thinning groove 4601.

[0117] In an optional embodiment, as shown in FIG9 , the width j of the first cross-section of the second thinning groove 4203 is less than the width g of the first cross-section of the first thinning groove 4601. This ensures that the portion of the light-emitting functional layer 43 located in the second thinning groove 4203 corresponds to the first thinning groove 4601, reducing the impact of the portion of the light-emitting functional layer 43 located in the second thinning groove 4203 on the effective area of ​​the light-emitting functional layer 43 (the portion of the light-emitting functional layer 43 located in the pixel opening), thereby ensuring normal display of the display panel. The first cross-section of the second thinning groove 101 is parallel to the thickness direction y of the base substrate 41, and the first cross-section of the second thinning groove 101 is perpendicular to the first surface of the base substrate 41. For example, the first cross-section of the second thinning groove 101 is parallel to the first cross-section of the first thinning groove 4601.

[0118] In an optional embodiment, as shown in FIG9 , the slope angle β of the side of the protruding structure 4202 facing the pixel opening is smaller than the slope angle γ of the side of the protruding structure 4202 facing the second thinning groove 4203. The intensity of the evaporation shadow effect in the process of forming the light-emitting functional layer 43 using an evaporation process is related to the slope angle of the side of the protruding structure 4202. In the embodiment of the present application, the slope angle β of the side of the protruding structure 4202 facing the pixel opening is smaller than the slope angle γ of the side of the protruding structure 4202 facing the second thinning groove 4203, that is, the slope angle β of the side of the protruding structure 4202 facing the pixel opening is smaller, and the slope angle γ of the side of the protruding structure 4202 facing the second thinning groove 4203 is larger. In this way, the evaporation shadow effect on the side of the protruding structure 4202 facing the pixel opening can be weakened, and the evaporation shadow effect on the side of the protruding structure 4202 facing the second thinning groove 4203 can be enhanced, which helps to ensure that the thickness of the portion of the light-emitting functional layer 43 located in the pixel opening is larger, thereby ensuring that the portion of the light-emitting functional layer 43 located in the pixel opening works normally; and makes the portion of the carrier layer 4301 located in the second thinning groove 4203 thinner, which facilitates the modification process.

[0119] In an optional embodiment, as shown in FIG9 , the width j of the first cross section of the second thinning groove 4203 is smaller than the width k of the gap between two adjacent anodes 101. This can reduce the impact of the portion of the light-emitting functional layer 43 located in the second thinning groove 4203 on the effective area of ​​the light-emitting functional layer 43.

[0120] In an optional embodiment, as shown in Figures 7 to 9, the display panel further includes a cathode 5. Cathode 5 is located on the side of the light-emitting functional layer 43 away from the base substrate 41, and the encapsulation structure 46 is located on the side of the cathode 5 away from the base substrate 41. That is, cathode 5 is stacked between the encapsulation structure 46 and the light-emitting functional layer 43. Cathode 5 is a single-layer structure and is a common cathode shared by all sub-pixels in the display panel.

[0121] In optional embodiments, as shown in Figures 7 to 9, the display panel further includes a protective layer 47 and a color filter layer 24. The protective layer 47 is located on the side of the encapsulation structure 46 away from the base substrate 41. The color filter layer 24 is located on the side of the protective layer 47 away from the base substrate 41. The protective layer 47 is also referred to as an over cover (OC) layer. The color filter layer 24 includes a plurality of color resist blocks 2401 corresponding one-to-one to the plurality of pixel openings in the pixel definition layer. The orthographic projection of each color resist block 2401 on the first surface of the base substrate 41 overlaps the orthographic projection of the corresponding pixel opening on the first surface of the base substrate 41. The plurality of color resist blocks 2401 may include R color resist blocks 2401, B color resist blocks 2401, and G color resist blocks 2401. The R color resist blocks 2401 are configured to transmit red light while preventing the transmission of light other than red light; the B color resist blocks 2401 are configured to transmit blue light while preventing the transmission of light other than blue light; and the G color resist blocks 2401 are configured to transmit green light while preventing the transmission of light other than green light.

[0122] In the embodiments of the present application, the light-emitting functional layer 43 is an organic light-emitting functional layer or an inorganic light-emitting functional layer. For example, if the display panel shown in any of Figures 7 to 9 is an organic light-emitting diode display panel, then the light-emitting functional layer 43 in the display panel is an organic light-emitting functional layer. For another example, if the display panel shown in any of Figures 7 to 9 is an inorganic light-emitting diode display panel, then the light-emitting functional layer 43 in the display panel is an inorganic light-emitting functional layer. The methods for modifying the first region 44 of the carrier layer 4301 to prevent crosstalk provided in the above embodiments are applicable to both organic light-emitting diode display panels and inorganic light-emitting diode display panels.

[0123] It should be noted that Figures 7 to 9 and their descriptions can refer to each other. Details not shown in any of the figures in Figures 7 to 9 and their descriptions can refer to other figures in Figures 7 to 9 and their descriptions. For example, the carrier layer 4301 not shown in Figures 8 and 9 and its description can refer to Figure 7 and its related description. For another example, the display panel shown in Figures 7 and 9 may also include an etch stop layer, and the related description of the etch stop layer in the display panel shown in Figures 7 and 9 can refer to the related description of the display panel shown in Figure 8. For another example, for the display panel shown in Figures 8 and 9, the minimum distance f between the bottom surface of the first thinning groove 4601 and the surface of the encapsulation structure 46 close to the base substrate 41 is also greater than 1000 angstroms. For another example, for the display panel shown in Figure 9, the width g of the first cross-section of the first thinning groove 4601 is also less than the width h of the limiting portion 4201 away from the surface of the base substrate 41. For the display panel shown in FIG9 , when the material of the pixel definition layer 42 is an inorganic material, the slope angle α of the defining portion 4201 is also greater than 45°, and the distance i between the surface of the defining portion 4201 away from the substrate 41 and the surface of the anode layer 1 away from the substrate 41 is also less than or equal to 1000 angstroms; when the material of the pixel definition layer 42 is an organic material, the slope angle α of the defining portion 4201 is also less than 45°, and the distance i between the surface of the defining portion 4201 away from the substrate 41 and the surface of the anode layer 1 away from the substrate 41 is also greater than 1000 angstroms. It should be noted that, for the display panel shown in FIG9 , the distance i between the surface of the defining portion 4201 away from the substrate 41 and the surface of the anode layer 1 away from the substrate 41 can be the distance between the surface of the protruding structure 4202 away from the substrate 41 and the surface of the anode layer 1 away from the substrate 41, which is not limited in the embodiments of the present application.

[0124] Based on the same inventive concept, an embodiment of the present application further provides a method for manufacturing a display panel. An embodiment of the method for manufacturing a display panel of the present application is described below.

[0125] Please refer to Figure 10, which shows a flow chart of a method for manufacturing a display panel provided in an embodiment of the present application. This method is used to manufacture a display panel as shown in any one of Figures 7 to 9. Figure 10 uses the manufacture of the display panel shown in Figure 7 as an example. As shown in Figure 10, the method includes the following steps S101 to S103.

[0126] S101. Form a pixel definition layer on a base substrate, wherein the pixel definition layer includes a defining portion for defining a pixel opening.

[0127] Please refer to Figure 11, which shows a schematic diagram of a pixel definition layer 42 formed on a base substrate 41 according to an embodiment of the present application. The pixel definition layer 42 includes a plurality of pixel openings Q and a defining portion 4201 for defining the plurality of pixel openings Q. The material of the pixel definition layer 42 can be an inorganic material or an organic material. The inorganic material can include SiO or SiN, and the organic material can include PI.

[0128] In an optional embodiment, the pixel definition layer 42 is formed by an evaporation process.

[0129] In an optional embodiment, the display panel further includes an anode layer 1, which is located between the base substrate 41 and the pixel definition layer 42. Before forming the pixel definition layer 42 on the base substrate 41, the anode layer 1 is formed on the base substrate 41, and the anode layer 1 includes a plurality of anodes 101. The pixel definition layer 42 is formed on a side of the anode layer 1 away from the base substrate 41. The plurality of anodes 101 are located in a one-to-one correspondence within the plurality of pixel openings Q, and a defining portion 4201 for defining any pixel opening covers the edge of the anode 101 in any pixel opening.

[0130] The material of the anode layer 1 can be a metal material, including but not limited to metal Mo (molybdenum), metal Cu (copper), metal Al (aluminum), and alloys thereof. In an optional embodiment, a metal material layer is formed on the base substrate 41 and processed through a single patterning process to obtain the anode layer 1. The process for forming the metal material layer includes but is not limited to magnetron sputtering, thermal evaporation, or plasma enhanced chemical vapor deposition (PECVD).

[0131] In the embodiments of the present application, the thickness of the pixel definition layer 42 may vary depending on the material of the pixel definition layer 42. In one embodiment, the pixel definition layer 42 is made of an inorganic material, the slope angle of the defining portion 4201 is greater than 45°, and the distance between the surface of the defining portion 4201 away from the base substrate 41 and the surface of the anode layer 1 away from the base substrate 41 is less than or equal to 1000 angstroms. In another embodiment, the pixel definition layer 42 is made of an organic material, the slope angle of the defining portion 4201 is less than 45°, and the distance between the surface of the defining portion 4201 away from the base substrate 41 and the surface of the anode layer 1 away from the base substrate 41 is greater than 1000 angstroms.

[0132] S102. Form a light-emitting functional layer on a side of the pixel definition layer away from the substrate. The light-emitting functional layer includes a carrier layer. The carrier layer is continuous and covers the pixel definition layer.

[0133] Please refer to Figure 12, which shows a schematic diagram of an embodiment of the present application after forming a light-emitting functional layer 43 on a side of the pixel definition layer 42 away from the base substrate 41. The light-emitting functional layer 43 includes a carrier layer 4301. The carrier layer 4301 is continuous and covers the pixel definition layer 42. The carrier layer 4301 includes a first region 44 and a second region 45 in addition to the first region 44. The orthographic projection of the first region 44 on the first surface of the base substrate 41 is located within the orthographic projection of the defining portion 4201 on the first surface of the base substrate 41. The orthographic projection of the second region 45 on the first surface of the base substrate 41 covers the pixel opening. For example, the first region 44 corresponds to the defining portion 4201 and is located directly above the defining portion 4201. It should be noted that in the light-emitting functional layer 43 formed in step S102, the carrier mobility of the first region 44 of the carrier layer 4301 can be equal to the carrier mobility of the second region 45 of the carrier layer 4301.

[0134] The light-emitting functional layer 43 includes at least one of a hole injection layer, a hole transport layer, an electron injection layer, an electron transport layer, and a charge generation layer. For example, the light-emitting functional layer 43 includes a structural layer between the anode layer 1 and the cathode 5 in the display panel shown in FIG1 . For another example, the light-emitting functional layer 43 includes a structural layer between the anode layer 1 and the cathode 5 in the display panel shown in FIG2 . The carrier layer 4301 includes at least one of a hole injection layer, a hole transport layer, an electron injection layer, an electron transport layer, and a charge generation layer.

[0135] In one embodiment, the light-emitting functional layer 43 includes a structural layer between the anode layer 1 and the cathode layer 5 in Figure 1. In this step, the light-emitting functional layer 43 is formed on the side of the pixel definition layer 42 away from the base substrate 41, including: forming a first structural layer group 2-1, a charge generation layer 3, a second structural layer group 2-2, and an electron injection layer 4 in sequence on the side of the pixel definition layer 42 away from the base substrate 41. Forming each structural layer group in the first structural layer group 2-1 and the second structural layer group 2-2 includes: forming a hole injection layer 201, a hole transport layer 202, an electron blocking layer 203, a light-emitting layer 204, a hole blocking layer 205, and an electron transport layer 206 stacked in sequence.

[0136] In another embodiment, the light-emitting functional layer 43 includes a structural layer between the anode layer 1 and the cathode layer 5 in Figure 2. In this step, the light-emitting functional layer 43 is formed on the side of the pixel definition layer 42 away from the base substrate 41, including: a hole injection layer 201, a hole transport layer 202, a blue fluorescent light-emitting layer 21, an electron transport layer 206, a charge generation layer 3, a hole transport layer 202, a red and green phosphorescent light-emitting layer 22, an electron transport layer 206, and an electron injection layer 4 are sequentially formed on the side of the pixel definition layer 42 away from the base substrate 41.

[0137] S103. Perform modification treatment on the first region of the carrier layer so that the carrier mobility of the first region is smaller than the carrier mobility of the second region of the carrier layer, wherein the second region is a region on the carrier layer other than the first region, and the orthographic projection of the first region on the first surface of the substrate is located within the orthographic projection of the limiting portion on the first surface of the substrate.

[0138] Referring to FIG12 , the first region 44 of the carrier layer 4301 is modified to reduce the carrier mobility of the first region 44 . As a result, the first region 44 can hinder the lateral migration of carriers in the carrier layer 4301 and prevent crosstalk between adjacent sub-pixels. It should be noted that the carrier layer 4301 includes at least one of a hole injection layer, a hole transport layer, an electron injection layer, an electron transport layer, and a charge generation layer. Here, “lateral migration of carriers in the carrier layer 4301” refers to the lateral migration of carriers in a single carrier layer. For example, the carrier layer 4301 includes a hole injection layer and a hole transport layer, and the single carrier layer may be a hole injection layer or a hole transport layer. The lateral migration of carriers in a single carrier layer refers to the lateral migration of carriers in the hole injection layer or the lateral migration of carriers in the hole transport layer.

[0139] In an optional embodiment, the first region 44 of the carrier layer 4301 is modified by a doping process or a light irradiation process to reduce the carrier mobility of the first region 44. In one embodiment, the doping process includes an ion implantation process, and the first region 44 of the carrier layer 4301 is ion doped by the ion implantation process to change the electrical properties of the first region 44, thereby achieving the modification of the first region 44. In another embodiment, the first region 44 of the carrier layer 4301 is light irradiated by a light irradiation process to change the electrical properties of the first region 44, thereby achieving the modification of the first region 44. In the process of modifying the first region 44 of the carrier layer 4301 by the ion implantation process or the light irradiation process, the second region 45 of the carrier layer 4301 can be shielded by using a mask or by coating a shielding material on the light-emitting functional layer 43 to prevent the modification process from affecting the electrical properties of the second region 45.

[0140] As previously described, carrier layer 4301 includes at least one of a hole injection layer, a hole transport layer, an electron injection layer, an electron transport layer, and a charge generation layer. When carrier layer 4301 includes at least two of the hole injection layer, the hole transport layer, the electron injection layer, the electron transport layer, and the charge generation layer, each carrier layer may be modified after it is formed, or all carrier layers may be modified uniformly after all carrier layers are formed. This is not limited in the present embodiment.

[0141] In an optional embodiment, the display panel further includes an encapsulation structure 46. Before the first region of the carrier layer 4301 is modified, as shown in FIG13 , the encapsulation structure 46 is formed on a side of the light-emitting functional layer 43 away from the base substrate 41, and a first thinning groove 4601 is formed on a surface of the encapsulation structure 46 away from the base substrate 41. The orthographic projection of the first thinning groove 4601 on the first surface of the base substrate 41 coincides with the orthographic projection of the first region 44 of the carrier layer 4301 on the first surface of the base substrate 41. The minimum distance between the bottom surface of the first thinning groove 4601 and the surface of the encapsulation structure 46 close to the base substrate 41 is greater than 1000 angstroms, and the width of the first cross-section of the first thinning groove 4601 is less than the width of the surface of the defining portion 4201 away from the base substrate 41. After the packaging structure 46 is formed, the first region 44 of the carrier layer 4301 is modified from the location of the first thinning groove 4601. Thus, the area on the packaging structure 46 other than the area where the first thinning groove 4601 is located can block the second region 45 of the carrier layer 4301, thereby eliminating the need to use a mask or coat a shielding material on the light-emitting functional layer 43 to block the second region 45 of the carrier layer 4301. This can simplify the process flow of modifying the carrier layer 4301 and reduce the process difficulty and cost.

[0142] In an optional embodiment, after the packaging structure 46 is formed, an ion implantation process or a light irradiation process is used to modify the first region 44 of the carrier layer 4301 starting from the location of the first thinning groove 4601 .

[0143] In an optional embodiment, the encapsulation structure 46 includes a plurality of stacked encapsulation layers. The plurality of encapsulation layers are first formed on the side of the light-emitting functional layer 43 away from the base substrate 41 to obtain the encapsulation structure 46. Then, a first thinning groove 4601 is formed on the surface of the encapsulation structure 46 away from the base substrate 41. For example, an etching process is used to form the first thinning groove 4601 on the surface of the encapsulation structure 46 away from the base substrate 41 according to the designed depth and width of the first thinning groove 4601. This allows ions or light to pass through the portion of the encapsulation structure 46 where the first thinning groove 4601 is located during the modification process of the first region 44 of the carrier layer 4301 from the location of the first thinning groove 4601. In an optional embodiment, the encapsulation structure 46 includes a plurality of stacked encapsulation layers, the plurality of encapsulation layers including an etch stop layer, two first encapsulation layers located on both sides of the etch stop layer, and a second encapsulation layer located on the side of the first encapsulation layer away from the etch stop layer. The etch stop layer, the first encapsulation layer and the second encapsulation layer satisfy at least one of the following: a material of the etch stop layer includes Al2O3; a material of the first encapsulation layer includes SiN; and a material of the second encapsulation layer includes SiO.

[0144] In an optional embodiment, before forming the encapsulation structure 46, as shown in FIG13 , a cathode 5 is formed on the side of the light-emitting functional layer 43 away from the base substrate 41. The cathode 5 is stacked with the light-emitting functional layer 43. The material of the cathode 5 is a transparent conductive material, which includes but is not limited to metal oxides such as indium tin oxide (ITO), indium zinc oxide (IZO) or aluminum-doped zinc oxide (ZnO:Al). Taking the material of the cathode 5 as ITO as an example, a layer of ITO is deposited on the side of the light-emitting functional layer 43 away from the base substrate 41 as the cathode 5. Among them, the process of depositing ITO includes but is not limited to magnetron sputtering, thermal evaporation, PECVD or vapor deposition.

[0145] In an optional embodiment, after the first region 44 of the carrier layer 4301 is modified from the position where the first thinning groove 4601 is located, the first thinning groove 4601 is filled. For example, the first thinning groove 4601 is filled with a packaging material (that is, the material of the packaging structure 46) or other materials to at least reduce the depth of the first thinning groove 4601 and improve the ability of the packaging structure 46 to block water and oxygen intrusion. In one embodiment, as shown in Figure 14, a protective layer 47 is formed on the side of the packaging structure 46 away from the base substrate 41. The protective layer 47 is partially filled in the first thinning groove 4601. The protective layer 47 is also called an OC layer. In the embodiment of the present application, the protective layer 47 can protect the packaging structure 46 on the one hand, and fill the first thinning groove 4601 on the other hand.

[0146] In an optional embodiment, after the protective layer 47 is sequentially formed on the side of the packaging structure 46 away from the base substrate 41 , as shown in FIG. 7 , the color filter layer 24 is sequentially formed on the side of the protective layer 47 away from the base substrate 41 .

[0147] It should be noted that in the above embodiment, the encapsulation structure 46 is first formed, and then a first thinning groove 4601 is formed on the surface of the encapsulation structure 46 away from the base substrate 41. Then, the first region 44 of the carrier layer 4301 is modified from the location of the first thinning groove 4601. In other embodiments, the encapsulation structure 46 includes multiple stacked encapsulation layers. First, a portion of the multiple encapsulation layers is formed on the side of the light-emitting functional layer 43 away from the base substrate 41. Then, the first region 44 of the carrier layer 4301 is modified through the portion of the encapsulation layer, and then the remaining encapsulation layers are formed. In these other embodiments, the encapsulation structure does not have a first thinning groove, and the encapsulation structure has a stronger ability to block the intrusion of water and oxygen.

[0148] It should also be noted that the above embodiments are described by taking the modification treatment of the first region 44 of the carrier layer 4301 after the packaging structure 46 is formed as an example. In other embodiments, the first region 44 of the carrier layer 4301 is modified before the packaging structure 46 is formed, and the embodiments of the present application do not limit this.

[0149] In the method for preparing the display panel provided in the embodiment of the present application, the one-time patterning process involved may include photoresist coating, exposure, development, etching and photoresist stripping. Processing a material layer (e.g., a metal material layer) through a one-time patterning process may include: coating a layer of photoresist on the material layer (e.g., a metal material layer) to obtain a photoresist layer, exposing the photoresist layer using a mask so that the photoresist layer forms a completely exposed area and a non-exposed area, then using a development process to completely remove the photoresist in the completely exposed area and retain all the photoresist in the non-exposed area, etching the area on the material layer (e.g., a metal material layer) corresponding to the completely exposed area using an etching process, and finally stripping the photoresist in the non-exposed area to obtain a corresponding structure (e.g., anode 101). Positive photoresist is used as an example for explanation here. For negative photoresist, the process of the one-time patterning process can refer to the description in this paragraph.

[0150] The embodiment shown in Figure 11 is described by taking the preparation of the display panel shown in Figure 7 as an example. The preparation process of the display panel shown in Figure 8 and the preparation process of the display panel shown in Figure 9 can both refer to the embodiment shown in Figure 11. It should be noted that, unlike the display panel shown in FIG7 , in the display panel shown in FIG9 , the two edges of the defining portion 4201 away from the surface of the base substrate 41 have a raised structure 4202, a second thinning groove 4203 is provided between the raised structures 4202 on the two edges, the thickness of the portion of the light-emitting functional layer 43 located in the second thinning groove 4203 is less than the thickness of the portion of the light-emitting functional layer 43 located in the pixel opening, the orthographic projection of the second thinning groove 4203 on the first surface of the base substrate 41 is located within the orthographic projection of the first thinning groove 4601 on the first surface of the base substrate 41, the slope angle of the side of the raised structure 4202 toward the pixel opening is less than the slope angle of the side of the raised structure 4202 toward the second thinning groove 4203, and the width of the first cross-section of the second thinning groove 4203 is less than the width of the gap between two adjacent anodes 101. Therefore, in the process of preparing the display panel shown in FIG9 , it is necessary to form raised structures 4202 on the two edges of the defining portion 4201 away from the surface of the base substrate 41. For example, the protruding structure 4202 and the defining portion 4201 are an integrated structure, and the defining portion 4201 having the protruding structure 4202 is formed during the process of preparing the pixel definition layer 42 .

[0151] Take the case where the material of the pixel definition layer 42 is an inorganic material as an example. For the display panel shown in FIG9 , after the anode layer 1 is formed on the base substrate 41, an inorganic material layer is formed on the side of the anode layer 1 away from the base substrate 41, and the inorganic material layer is processed through a single patterning process to obtain the pixel definition layer 42. In this single patterning process, the mask used for exposure is a grayscale mask, which includes: a completely light-transmitting area corresponding to the pixel opening, a light-shielding area corresponding to the raised structure 4202 on the limiting portion 4201, and a non-completely light-transmitting area corresponding to the second thinning groove 4203. In a specific embodiment, first, a layer of photoresist is coated on the side of the inorganic material layer away from the base substrate 41 to obtain a photoresist layer. Then, the grayscale mask is used to expose the photoresist layer, so that the photoresist layer forms a fully exposed area, a partially exposed area, and a non-exposed area. The fully exposed area corresponds to the fully transparent area of ​​the grayscale mask, the partially exposed area corresponds to the non-fully transparent area of ​​the grayscale mask, and the non-exposed area corresponds to the light-shielding area of ​​the grayscale mask. Next, the exposed photoresist layer is developed to obtain a photoresist pattern, which includes a first photoresist area, a second photoresist area, and a photoresist completely removed area. The first photoresist area is the non-exposed area, the second photoresist area corresponds to the non-completely exposed area, the thickness of the second photoresist area is less than the thickness of the first photoresist area, and the photoresist completely removed area corresponds to the fully exposed area. Thereafter, the area on the inorganic material layer corresponding to the photoresist completely removed area is etched to form a pixel opening on the inorganic material layer. After forming the pixel opening, the photoresist pattern is treated with an ashing process to remove the photoresist in the second photoresist region. The region corresponding to the second photoresist region on the inorganic material layer is then half-etched to form a second thinning groove 4203 in the inorganic material layer. Finally, the photoresist in the first photoresist region is removed to obtain a defining portion 4201 having a protruding structure 4202.

[0152] Based on the same inventive concept, an embodiment of the present application provides a display device, which includes the display panel provided in the embodiments shown in Figures 7 to 9. The display device has the corresponding technical effects of the display panel in the embodiments shown in Figures 7 to 9, which will not be described in detail here.

[0153] The display device is any product or component with a display function, such as a display screen, electronic paper, mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, navigator or wearable device.

[0154] It should be noted that the above describes some embodiments of the present application. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps described in the claims can be performed in an order different from that in the above embodiments and still achieve the desired results. In addition, the processes depicted in the accompanying drawings do not necessarily require the specific order or continuous order shown to achieve the desired results. In some embodiments, multi-tasking and parallel processing are also possible or may be advantageous. The various embodiments in this application are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0155] The description of this application is provided for purposes of illustration and description and is not intended to be exhaustive or to limit the application to the disclosed form. Many modifications and variations will be apparent to those skilled in the art. The embodiments are selected and described in order to better illustrate the principles and practical applications of the application and to enable those skilled in the art to understand the application and design various embodiments with various modifications suitable for specific applications.

[0156] Those skilled in the art should understand that the discussion of any of the above embodiments is merely illustrative and is not intended to imply that the scope of the present application (including the claims) is limited to these examples. Within the scope of the present application, the technical features in the above embodiments or different embodiments may be combined, the steps may be implemented in any order, and there are many other variations of the different aspects of the embodiments of the present application as described above, which are not provided in detail for the sake of simplicity.

[0157] While the present application has been described in conjunction with specific embodiments thereof, many alternatives, modifications and variations of these embodiments will be apparent to those skilled in the art in light of the foregoing description.

[0158] The embodiments of the present application are intended to cover all such substitutions, modifications, and variations that fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the embodiments of the present application should be included in the scope of protection of this application.

Claims

1. A display panel, comprising: A substrate substrate; A pixel definition layer located on the substrate substrate, including a defining portion for defining a pixel opening; A light-emitting functional layer located on a side of the pixel definition layer away from the substrate substrate, including a carrier layer, the carrier layer being continuous, and the carrier layer covering the pixel definition layer, the carrier layer including a first region and a second region other than the first region, a positive projection of the first region on a first surface of the substrate substrate is located within a positive projection of the defining portion on the first surface of the substrate substrate, and a carrier mobility of the first region is less than a carrier mobility of the second region.

2. The display panel according to claim 1, wherein, The first region is a region subjected to doping or light irradiation treatment.

3. The display panel according to claim 1 or 2, wherein The carrier layer includes at least one of a hole injection layer, a hole transport layer, an electron injection layer, an electron transport layer, and a charge generation layer.

4. The display panel according to any one of claims 1 to 3, wherein, The display panel further includes: A packaging structure located on a side of the light-emitting functional layer away from the substrate substrate, a first thinning groove is provided on a surface of the packaging structure away from the substrate substrate, and a positive projection of the first thinning groove on the first surface of the substrate substrate coincides with a positive projection of the first region on the first surface of the substrate substrate.

5. The display panel according to claim 4, wherein, A minimum distance between a bottom surface of the first thinning groove and a surface of the packaging structure close to the substrate substrate is greater than 1000 angstroms.

6. The display panel according to claim 4 or 5, wherein A width of a first cross-section of the first thinning groove is less than a width of a surface of the defining portion away from the substrate substrate, and the first cross-section is parallel to a thickness direction of the substrate substrate.

7. The display panel according to any one of claims 4-6, wherein, Two edges of a surface of the defining portion away from the substrate substrate have a convex structure, the two edges are two edges arranged along a width direction of the surface of the defining portion away from the substrate substrate, and a second thinning groove is provided between the convex structures of the two edges, and a thickness of a portion of the light-emitting functional layer located in the second thinning groove is less than a thickness of a portion of the light-emitting functional layer located in the pixel opening.

8. The display panel according to claim 7, wherein, A positive projection of the second thinning groove on the first surface of the substrate substrate is located within a positive projection of the first thinning groove on the first surface of the substrate substrate.

9. The display panel according to claim 7 or 8, wherein, A slope angle of a side surface of the convex structure facing the pixel opening is less than a slope angle of a side surface of the convex structure facing the second thinning groove.

10. The display panel according to any one of claims 7-9, wherein, The display panel further includes: An anode layer located between the pixel definition layer and the substrate substrate, the anode layer includes a plurality of anodes, the pixel definition layer includes a plurality of pixel openings, the plurality of anodes are respectively located in the plurality of pixel openings, a defining portion for defining any one pixel opening covers an edge of the anode in the any one pixel opening, a width of a first cross-section of the second thinning groove is less than a width of a gap between adjacent two anodes, and the first cross-section of the second thinning groove is parallel to a thickness direction of the substrate substrate.

11. The display panel according to claim 10, wherein, A material of the pixel definition layer is an inorganic material, a slope angle of the defining portion is greater than 45°, and a distance between a surface of the defining portion away from the substrate substrate and a surface of the anode layer away from the substrate substrate is less than or equal to 1000 angstroms.

12. The display panel according to claim 10, wherein, The material of the pixel definition layer is an organic material. The slope angle of the defining portion is less than 45°. The distance between the surface of the defining portion away from the substrate and the surface of the anode layer away from the substrate is greater than 1000 angstroms.

13. The display panel according to any one of claims 4-12, wherein, The display panel further includes: an etching stop layer located on a side of the light-emitting functional layer away from the substrate.

14. The display panel according to claim 13, wherein, The encapsulation structure includes a plurality of stacked encapsulation layers, and the plurality of encapsulation layers includes the etching stop layer.

15. The display panel according to claim 14, wherein, The plurality of encapsulation layers further includes two first encapsulation layers located on two sides of the etching stop layer.

16. The display panel according to claim 15, wherein, The plurality of encapsulation layers further includes a second encapsulation layer located on a side of the first encapsulation layer away from the etching stop layer.

17. The display panel according to claim 16, wherein, The etching stop layer, the first encapsulation layer, and the second encapsulation layer satisfy at least one of the following: The material of the etching stop layer includes aluminum oxide; The material of the first encapsulation layer includes silicon nitride; The material of the second encapsulation layer includes silicon oxide.

18. The display panel according to any one of claims 1-17, wherein, The light-emitting functional layer is an organic light-emitting functional layer or an inorganic light-emitting functional layer.

19. A display device, including the display panel according to any one of claims 1-18.

20. A method for manufacturing a display panel, the method including: forming a pixel definition layer on a substrate, the pixel definition layer including a defining portion for defining a pixel opening; forming a light-emitting functional layer on a side of the pixel definition layer away from the substrate, the light-emitting functional layer including a carrier layer, the carrier layer being continuous, and the carrier layer covering the pixel definition layer; performing a modification process on a first region of the carrier layer to make the carrier mobility of the first region less than the carrier mobility of a second region of the carrier layer, the second region being a region of the carrier layer other than the first region, and the positive projection of the first region on a first surface of the substrate being located within the positive projection of the defining portion on the first surface of the substrate.

21. The method according to claim 20, wherein The performing a modification process on a first region of the carrier layer includes: performing a modification process on the first region of the carrier layer by doping or light irradiation.

22. The method according to claim 20 or 21, wherein, Before performing the modification process on a first region of the carrier layer, the method further includes: forming an encapsulation structure on a side of the light-emitting functional layer away from the substrate; forming a first thinning groove on a surface of the encapsulation structure away from the substrate, and the positive projection of the first thinning groove on a first surface of the substrate coincides with the positive projection of the first region on the first surface of the substrate; The performing a modification process on a first region of the carrier layer includes: performing a modification process on the first region of the carrier layer from a position where the first thinning groove is located.

23. The method according to claim 22, wherein, After performing the modification process on a first region of the carrier layer, the method further includes: filling the first thinning groove.

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