Chip, electric-motor driving system, and electric valve

Abstract

Provided in the embodiments of the present application are a chip, an electric-motor driving system, and an electric valve. The chip comprises a first substrate, a first peripheral device and a first wafer structure, which is at least provided with one of a communication module, a signal processing module and a driving module, that are fixed to a first side of the first substrate, and a first encapsulation layer for encapsulating the first peripheral device and the first wafer structure. By means of encapsulating the first peripheral device and the first wafer structure, which is at least provided with one of the communication module, the signal processing module and the driving module, together by means of the first encapsulation layer, the cost of encapsulating the chip is reduced, and then the cost and volume of the chip are reduced; in addition, in the specific application of the chip, the first wafer structure and the first peripheral device are used as a whole product, so that the development difficulty of developers when using the chip is reduced, the development period is shortened, and thus the development investment cost is reduced.

Description

Chip and motor drive system, electric valve

[0001] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office on December 28, 2023, with application number 202311844967.3 and invention name “Chip and motor drive system, electric valve”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of thermal management technology, and in particular to a chip, a motor drive system including the chip, and an electric valve including the chip. Background Art

[0003] With the development of new energy technologies, the use of new energy vehicles is becoming increasingly common, and thermal management in new energy vehicles directly affects their range. In specific applications, the thermal management pathways of new energy vehicles include multiple heat dissipation paths, and the operating status of each heat dissipation path is controlled by components such as dampers and valves that require low-power motor drive. As a result, the number of components in new energy vehicles that require low-power motor drive is increasing, making the research of low-power motor drive a hot topic in this field.

[0004] Application Contents

[0005] In view of this, the present application provides a chip, a motor drive system including the chip, and an electric valve including the chip. The specific solutions are as follows:

[0006] A chip for controlling the operation of a motor, the chip comprising a communication module, a signal processing module, and a drive module. The signal processing module outputs a control signal to the drive module based on a communication signal obtained by the communication module, so that the drive module controls the operation of the motor in response to the control signal. The chip comprises:

[0007] a first substrate;

[0008] a first wafer structure fixed to the first side of the first substrate, the first wafer structure comprising at least one wafer, and the first wafer structure having at least one module among the communication module, the signal processing module, and the driving module;

[0009] a first peripheral component fixed to the first side of the first substrate, the first peripheral component including at least one passive component;

[0010] A first packaging layer encapsulates the first wafer structure and the first peripheral device.

[0011] A motor drive system includes a chip and a motor, wherein the chip is used to control the operation of the motor, wherein the chip is the aforementioned chip, and the motor drive system further includes: at least one module selected from the group consisting of a power management module, a voltage stabilization module, and a Hall detection module;

[0012] Wherein, the voltage stabilizing module is used to convert the first voltage into a second voltage to power the signal processing module;

[0013] The power management module is used to convert the third voltage into the second voltage and supply it to the voltage stabilizing module, the communication module and the driving module;

[0014] The Hall detection module is used to detect the operating state of the motor and feed back the state to the signal processing module.

[0015] An electric valve is used in a thermal management system. The electric valve has the aforementioned chip, which is located in the space inside the electric valve. The electric valve has a motor. The chip can control the operation of the motor, and the motor can drive the valve core of the electric valve to move.

[0016] The chip and motor drive system provided in the embodiment of the present application encapsulate a first peripheral device and a first wafer structure having at least one of the three modules, namely, the communication module, the signal processing module, and the drive module, together through a first packaging layer, thereby reducing the packaging cost of the chip, and further reducing the cost and volume of the chip. In the specific application of the chip, the first wafer structure and the first peripheral device are applied as a whole product, reducing the development difficulty of developers when applying the chip, shortening the development cycle, and reducing development investment costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present application or related technologies, the following briefly introduces the drawings required for use in the embodiments or descriptions of the prior art. Obviously, the drawings described below are merely embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without any creative work.

[0018] FIG1 is a cross-sectional schematic diagram of a chip provided in one embodiment of the present application;

[0019] FIG2 is a schematic diagram of the appearance of the chip shown in FIG1 ;

[0020] FIG3 is a block diagram of a chip system according to an embodiment of the present application;

[0021] FIG4 is a schematic diagram of a chip system according to an embodiment of the present application;

[0022] FIG5 is a layout diagram of a first wafer structure before the chip is plastic-sealed according to an embodiment of the present application;

[0023] FIG6 is a schematic diagram of electrical connections of functional modules corresponding to each wafer in the first wafer structure of the chip shown in FIG5 ;

[0024] FIG7 is a schematic diagram of a chip system according to another embodiment of the present application;

[0025] FIG8 is a schematic diagram of a chip provided in an embodiment of the present application with a pad welded on the back side;

[0026] FIG9 is a flow chart of a chip manufacturing method according to an embodiment of the present application;

[0027] 10-13 are cross-sectional views of some structures involved in the manufacturing process of a chip provided in one embodiment of the present application. DETAILED DESCRIPTION

[0028] The following will be combined with the accompanying drawings in the embodiments of this application to clearly and completely describe the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0029] As described in the background technology section, the number of components in new energy vehicles that require low-power motor drive is increasing, making the research on low-power motor drive one of the research hotspots in this field.

[0030] In view of this, an embodiment of the present application provides a chip and a motor drive system including the chip, wherein the chip is used to control the operation of the motor, has low manufacturing cost and low process difficulty, so as to reduce the cost and process difficulty of the structure of the drive motor.

[0031] The chip provided in the embodiments of the present application and the motor drive system including the chip are described below in conjunction with specific embodiments.

[0032] Example 1

[0033] The chip provided in the embodiment of the present application is used to control the operation of the motor. Specifically, as shown in Figures 1 and 2, Figure 1 is a cross-sectional view of the chip provided in one embodiment of the present application, and Figure 2 is a schematic diagram of the appearance of the chip shown in Figure 1. The chip includes:

[0034] a first substrate 11;

[0035] a first wafer structure 12 fixed to a first side of the first substrate 11, wherein the first wafer structure 12 includes at least one wafer;

[0036] a first peripheral device 13 fixed to the first side of the first substrate 11, wherein the first peripheral device 13 includes at least one passive device;

[0037] A first packaging layer 14 encapsulates the first wafer structure 12 and the first peripheral device 13 .

[0038] As shown in Figure 3, the chip provided in the embodiment of the present application includes a communication module 21, a signal processing module 22, and a driver module 23. The signal processing module 22 outputs a control signal to the driver module 23 based on the communication signal obtained by the communication module 21, so that the driver module 23 controls the operation of the motor 15 in response to the control signal. It should be noted that in this embodiment, the first wafer structure 12 has at least one of the communication module 21, the signal processing module 22, and the driver module 23.

[0039] It should be noted that, in this embodiment, the wafer in the first wafer structure does not have a separate packaging structure and is a bare wafer. The chip adopts SIP (system in package) technology, and uses the first packaging layer to package the first wafer structure and the first peripheral device as a whole onto the first substrate, so that the process of chip manufacturing is less difficult and the cost is lower.

[0040] Optionally, in one embodiment of the present application, the passive device may be a capacitor, a resistor, or an inductor. It should be noted that, in this embodiment, the first peripheral device includes at least one of the three passive devices of capacitor, resistor and inductor, and the same passive device in the first peripheral device may include one or more. This application does not limit this, and it depends on the specific situation.

[0041] Based on the above embodiments, in one embodiment of the present application, the first peripheral device may further include non-passive devices, such as sensors and other components. The present application does not limit this, and it depends on the application requirements of the chip.

[0042] From the above, it can be seen that the chip provided in the embodiment of the present application packages the first peripheral device and the first wafer structure having at least one of the three modules, namely the communication module, the signal processing module and the driving module, together through a first packaging layer, thereby reducing the packaging cost of the chip, and further reducing the cost and volume of the chip. In the specific application of the chip, the first wafer structure and the first peripheral device are applied as a whole product, reducing the development difficulty of developers when applying the chip, shortening the development cycle, and reducing development investment costs.

[0043] In addition, in the chip provided in the embodiment of the present application, the first wafer structure and the first peripheral device are protected by the first packaging layer on the side away from the first substrate, thereby reducing the probability of damage to the first wafer structure of the chip during application.

[0044] Continuing with FIG3 , based on any of the above embodiments, in one embodiment of the present application, the communication module 21 is used to transmit communication signals, specifically, LIN signals, CAN signals, and PWM signals. This application does not limit this, and the specific use depends on the circumstances. Taking the communication module 21 used to transmit LIN signals as an example, in one embodiment of the present application, the communication module 21 is used to convert LIN signals and UART signals into each other. LIN communication is a low-cost serial communication network used to implement distributed electronic system control in automobiles. Its goal is to provide auxiliary functions for existing automobile networks (such as the CAN bus) and reduce communication costs in situations where the bandwidth and multi-functions of the CAN bus are not required, such as communication between smart sensors and braking devices. UART (i.e., Universal Asynchronous Receiver / Transmitter) is a universal data communication protocol and a general term for asynchronous serial communication ports (serial ports). It converts parallel data into serial data for transmission when sending data and converts received serial data into parallel data when receiving data.

[0045] Continuing as shown in Figure 3, in one embodiment of the present application, the signal processing module 22 is used to cooperate with relevant peripherals to execute the functions set by software programming according to the host computer instructions and feedback relevant information to the host computer. Wherein, the host computer is a system that communicates with the chip through a communication port, such as the whole vehicle system of a new energy vehicle. Optionally, in this embodiment, the signal processing module 22 includes a signal processing unit 221, a communication peripheral serial-parallel bus 222, an analog peripheral signal converter 223 and an input / output port 224; wherein, the communication peripheral serial-parallel bus 222 is used to transmit signals between the communication module 21, the analog peripheral signal converter 223 is used to realize analog-to-digital signal conversion and digital-to-analog signal conversion, and the signal processing unit 221 is used to process the signal it receives from the host computer, generate a control signal, and output it to the drive module 23 through the input / output port (I / O) 224. It should be noted that, in this embodiment, the signal processing unit 221 is further configured to obtain the operating status of the driver module 23 through the input / output port 224, and output the information to the communication module 21 through the communication peripheral serial-parallel bus 222, and then feed the information back to the host computer through the communication module 21. Optionally, in one embodiment of the present application, the signal processing module 221 is an MCU, i.e., a microprocessor, but this application does not limit this, and the specific configuration depends on the circumstances.

[0046] Continuing with FIG3 , in one embodiment of the present application, the driving module 23 is configured to drive the motor connected to the chip to operate according to instructions from the signal processing module 22. Optionally, the driving module 23 includes a storage unit 231, a pre-driving unit 232, and a thin-film transistor circuit 233, wherein the storage unit 231 stores a control algorithm, which is configured to parse the signal output by the signal processing module 22 so that the pre-driving unit 232 can control the operating state of each transistor in the thin-film transistor circuit 233 based on the signal output by the signal processing module 22, thereby controlling the operating state of the motor.

[0047] Optionally, in one embodiment of the present application, the first wafer structure includes multiple wafers, and each wafer has one of the communication module, the signal processing module, and the driving module.

[0048] Specifically, in one embodiment of the present application, the first wafer structure includes a first wafer, a second wafer and a third wafer, wherein the first wafer has the communication module, the second wafer has the signal processing module, and the third wafer has the drive module; specifically, the first wafer is used to realize the communication between the chip and the host computer (such as the whole vehicle system used by the motor); the second wafer is used to process the signal received through the first wafer and output a control signal to the third wafer, so that the third wafer responds to the control signal and controls the operating state of the motor. Optionally, in one embodiment of the present application, the first wafer is a LIN wafer, the second wafer is an MCU wafer, and the third wafer is a motor drive wafer, but this application does not limit this, and it depends on the specific circumstances.

[0049] It should be noted that, in the above embodiment, when the chip is manufactured, the first peripheral device is first fixed on the first substrate, and each bare wafer in the first wafer structure is fixed on the first substrate, and then a first packaging layer is formed to utilize the first packaging layer to package the first peripheral device and the first wafer structure as a whole.

[0050] In another embodiment of the present application, the first wafer structure includes a plurality of wafers, and at least one of the plurality of wafers has two modules among the communication module, the signal processing module, and the driving module.

[0051] Specifically, in one embodiment of the present application, the first wafer structure includes a fourth wafer and a fifth wafer; optionally, in an implementation of this embodiment, the fourth wafer has the communication module and the signal processing module, and the fifth wafer has the driving module; in another implementation of this embodiment, the fourth wafer has the communication module and the driving module, and the fifth wafer has the signal processing module; in yet another implementation of this embodiment, the fourth wafer has the signal processing module and the driving module, and the fifth wafer has the communication module; so that the first wafer structure has three modules, namely, the communication module, the signal processing module, and the driving module, by having the fourth wafer have two modules among the communication module, the signal processing module, and the driving module, and the fifth wafer has the remaining module among the communication module, the signal processing module, and the driving module.

[0052] In another embodiment of the present application, the first wafer structure includes a sixth wafer, and the sixth wafer has three modules: the communication module, the signal processing module, and the driving module, so that the first wafer structure has the three modules: the communication module, the signal processing module, and the driving module at the same time through one wafer, thereby improving the integration of the first wafer structure.

[0053] It should be noted that in the above embodiment, compared with the implementation method in which a wafer has at least two modules and a wafer has a single function, the manufacturing process of the wafer with a single function is simpler, thereby making the cost of the chip provided in the embodiment of the present application lower.

[0054] In addition, due to the different process capabilities of different manufacturers, they are good at producing different types of wafers. In the chip provided in the embodiment of the present application, the first wafer structure uses a single-function wafer. Wafers with corresponding functions can be obtained from different channels and then fixed on the first substrate. This allows the chip to have a wider range of wafer choices when it is manufactured, and can be flexibly configured according to actual application requirements in specific applications, reducing the risk of the chip being stuck.

[0055] It should be noted that, in actual application, the operating voltage of the signal processing module 22 is relatively low, while the operating voltages of the communication module 21 and the driver module 23 are relatively high. Therefore, based on any of the above embodiments, in one embodiment of the present application, as shown in FIG3 , the chip further includes a voltage stabilizing module 24, which is used to convert a first voltage into a second voltage to power the signal processing module 22. The first voltage is greater than the second voltage, so that the communication module 21, the signal processing module 22, and the driver module 23 can share the same power supply signal. Optionally, the voltage stabilizing module is an LDO (low voltage linear regulator); the first voltage is 12V and the second voltage is 5V, but this application does not limit this, and the specific situation depends on the circumstances.

[0056] Based on the above embodiments, in one embodiment of the present application, the first wafer structure further has the voltage stabilizing module. It should be noted that the voltage stabilizing module can be implemented by a wafer alone, or it can be implemented by sharing a wafer with other functional modules. The present application does not limit this, and the specific situation depends on the circumstances.

[0057] Specifically, in one embodiment of the present application, the first wafer structure further includes a seventh wafer having the voltage stabilizing module, so that a wafer having the voltage stabilizing module is separately provided in the first wafer structure. In other embodiments of the present application, the voltage stabilizing module can be integrated on the same wafer as the communication module, the signal processing module, or the driver module.

[0058] Optionally, in one embodiment of the present application, when the first wafer structure includes a first wafer, a second wafer and a third wafer, in this embodiment, the first wafer may have the voltage stabilizing module, such as the first wafer having a LIN function and a LDO function, the second wafer having an MCU function, and the third wafer having a motor drive function (i.e., having a drive module function); the second wafer may have the voltage stabilizing module, such as the first wafer having a LIN function, the second wafer having an MCU function and an LDO function, and the third wafer having a motor drive function; the third wafer may also have the voltage stabilizing module, such as the first wafer having a LIN function, the second wafer having an MCU function, and the third wafer having a motor drive function and an LDO function; but the present application does not limit this, and it depends on the specific circumstances.

[0059] In another embodiment of the present application, the first wafer structure includes a fourth wafer and a fifth wafer. In this embodiment, the fourth wafer may have the voltage stabilizing module, or the fifth wafer may have the voltage stabilizing module.

[0060] Specifically, in one implementation of this embodiment, the fourth wafer has the communication module, the signal processing module and the voltage stabilizing module, and the fifth wafer has the driving module; in another implementation of this embodiment, the fourth wafer has the communication module, the driving module and the voltage stabilizing module, and the fifth wafer has the signal processing module; in yet another implementation of this embodiment, the fourth wafer has the signal processing module, the driving module and the voltage stabilizing module, and the fifth wafer has the communication module; in yet another implementation of this embodiment, the fourth wafer has the communication module and the signal processing module, and the fifth wafer has the driving module and the voltage stabilizing module; this application does not limit this, and in other embodiments of the present application, other combinations can also be used, as long as the fourth wafer and the fifth wafer jointly implement the communication module, the signal processing module, the voltage stabilizing module and the driving module.

[0061] In another embodiment of the present application, the first wafer structure includes a sixth wafer. In this embodiment, the sixth wafer further has the voltage stabilizing module, that is, in this embodiment, the sixth wafer has the communication module, the signal processing module, the voltage stabilizing module and the driving module.

[0062] It should be noted that, in actual applications, the power supply voltage of the chip is often greater than the voltage required by the communication module, the signal processing module and the driving module. Therefore, in one embodiment of the present application, as shown in FIG3 , the chip further includes: a power management module 25, the power management module 25 is used to convert the third voltage into the second voltage, and supply it to the voltage stabilizing module 24, the communication module 21 and the driving module 23; wherein, the third voltage is greater than the second voltage. Optionally, the first voltage is 48V and the second voltage is 12V, but the present application does not limit this, and it depends on the specific situation.

[0063] Optionally, based on the above embodiment, in one embodiment of the present application, the power management module is further used to implement anti-reverse connection and filtering functions, specifically to prevent the chip from being damaged due to reverse connection of the power supply, and to filter out noise signals and EMC interference on the power supply of the chip, thereby providing a stable and clean power supply signal for other components of the chip. It should be noted that EMC includes EMI (electromagnetic interference) and EMS (electromagnetic tolerance). The so-called EMI electromagnetic interference is the electromagnetic noise generated by the machine itself in the process of performing its due functions, which is detrimental to other systems; and EMS refers to the ability of the machine to be unaffected by the surrounding electromagnetic environment in the process of performing its due functions.

[0064] Specifically, in one embodiment of the present application, as shown in Figure 4, the power management module 25 includes: an anti-reverse circuit and a first filtering circuit. The anti-reverse circuit is used to prevent the power supply of the chip from being reversed, causing damage to the chip. The first filtering circuit is used to filter out noise signals and EMC interference on the power supply of the chip, and provide a stable and clean power supply signal for other components of the chip. The first filtering circuit can be a π filtering circuit, but this application does not limit this, and it depends on the specific situation.

[0065] Based on the above embodiment, in one embodiment of the present application, the first wafer structure further includes the power management module. However, the present application does not limit this. In other embodiments of the present application, the first wafer structure may also not include the power management module, depending on the specific circumstances.

[0066] The chip provided in the embodiment of the present application is described below by taking the first wafer structure having the power management module as an example.

[0067] Specifically, in one embodiment of the present application, the first wafer structure includes an eighth wafer, and the eighth wafer has the power management module, so that a wafer having the power management module is separately provided in the first wafer structure. In other embodiments of the present application, the power management module may also share the same wafer with other modules in the first wafer structure. This application does not impose any limitation on this, and the specific circumstances may vary.

[0068] Optionally, in one embodiment of the present application, the first wafer structure includes a first wafer, a second wafer and a third wafer. In this embodiment, the first wafer may have the power management module, the second wafer may have the power management module, or the third wafer may have the power management module.

[0069] In another embodiment of the present application, the first wafer structure includes a fourth wafer and a fifth wafer. In this embodiment, the fourth wafer may have the power management module, or the fifth wafer may have the power management module.

[0070] In another embodiment of the present application, the first wafer structure includes a sixth wafer. In this embodiment, the sixth wafer may have the power management module.

[0071] In yet another embodiment of the present application, the first wafer structure includes a seventh wafer. In this embodiment, the seventh wafer may also have the power management module.

[0072] Based on any of the above embodiments, in one embodiment of the present application, as shown in FIG4 , the chip further includes a Hall detection module 26, which is used to detect the operating status of the motor and provide feedback to the signal processing module 22. For example, if the motor is a stepper motor, the stepper motor includes a coil stator and a rotor. The Hall detection module 26 is used to identify changes in the rotor magnetic field of the stepper motor during its rotation, and convert the changes into electrical signals and output them to the signal processing module 22, so that the signal processing module 22 can determine whether the stepper motor is stalled based on the electrical signals.

[0073] Based on the above embodiment, in one embodiment of the present application, the first wafer structure further includes the Hall detection module. However, the present application does not limit this. In other embodiments of the present application, the first wafer structure may not include the Hall detection module, depending on the specific circumstances. It should be noted that when the first wafer structure does not include the Hall detection module, the Hall detection module can be implemented by a Hall circuit.

[0074] The chip provided in the embodiment of the present application is described below by taking the first wafer structure having the Hall detection module as an example.

[0075] Specifically, in one embodiment of the present application, the first wafer structure includes a ninth wafer, and the ninth wafer has the Hall detection module, so that a wafer having the Hall detection module is separately provided in the first wafer structure. In other embodiments of the present application, the Hall detection module may also share the same wafer with other modules in the first wafer structure. This application does not impose any limitation on this, and the specific circumstances may vary.

[0076] Optionally, in one embodiment of the present application, the first wafer structure includes a first wafer, a second wafer and a third wafer. In this embodiment, the first wafer may have the Hall detection module, the second wafer may have the Hall detection module, and the third wafer may have the Hall detection module.

[0077] In another embodiment of the present application, the first wafer structure includes a fourth wafer and a fifth wafer. In this embodiment, the fourth wafer may have the power management module, or the fifth wafer may have the Hall detection module.

[0078] In another embodiment of the present application, the first wafer structure includes a sixth wafer. In this embodiment, the sixth wafer may have the Hall detection module.

[0079] In yet another embodiment of the present application, the first wafer structure includes a seventh wafer. In this embodiment, the seventh wafer may also have the Hall detection module.

[0080] In yet another embodiment of the present application, the first wafer structure includes an eighth wafer. In this embodiment, the eighth wafer may have the Hall detection module.

[0081] On the basis of any of the above embodiments, in one embodiment of the present application, as shown in FIG4 , the chip further has a voltage acquisition module 27, which is used to divide the voltage output by the power management module 25 and feed it back to the signal processing module 22, so as to calculate the voltage of the power supply port of the chip, thereby determining whether the voltage provided by the power management module 25 to the driving module 23 is within the operating voltage range of the motor driven by the chip.

[0082] Based on the above embodiment, in one embodiment of the present application, the first wafer structure further includes the voltage acquisition module. However, the present application is not limited to this. In other embodiments of the present application, the first wafer structure may also not include the voltage acquisition module. For example, a voltage acquisition circuit may be provided outside the first wafer structure to implement the voltage acquisition module, depending on the specific circumstances.

[0083] The chip provided in the embodiment of the present application is described below by taking the first wafer structure having the voltage acquisition module as an example.

[0084] Specifically, in one embodiment of the present application, the first wafer structure includes a tenth wafer, the tenth wafer having the voltage acquisition module, so that a wafer having the voltage acquisition module is separately provided in the first wafer structure. In other embodiments of the present application, the voltage acquisition module may also share the same wafer with any other module in the first wafer structure. This application does not impose any limitation on this, and the specific circumstances may vary.

[0085] The chip provided in the embodiment of the present application is described below by taking the example that each wafer in the first wafer structure has a single function.

[0086] As shown in Figure 5, Figure 5 is a structural schematic diagram of the first wafer structure in the chip provided by an embodiment of the present application. In this embodiment, the first wafer structure has a first wafer 111, a second wafer 112, a third wafer 113, an eighth wafer 114, a ninth wafer 115 and a tenth wafer 116, wherein the first wafer 111 has the communication module, the second wafer 112 has the signal processing module, the third wafer 113 has the driving module, the eighth wafer 114 has a power management module, the ninth wafer 115 has a Hall detection module, and the tenth wafer 116 has a voltage acquisition module.

[0087] Optionally, in one embodiment of the present application, as shown in FIG5 , each wafer in the first wafer structure is electrically connected to the first substrate via an electrical connection line 117 , thereby achieving electrical connection between different wafers through the first substrate.

[0088] As shown in Figure 6, Figure 6 shows a schematic diagram of the electrical connection between the functional modules corresponding to each wafer in the first wafer structure shown in Figure 5. In this embodiment, the power management module 25 is connected to the power port of the chip, and after performing noise reduction and other processing on the power signal received by the power port of the chip, it outputs it to the communication module 21, the voltage acquisition module 27 and the driving module 23, providing a voltage signal for the communication module 21, the voltage acquisition module 27 and the driving module 23; the communication module 21 is used to realize the communication between the host computer and the signal processing module 22, send control instructions to the signal processing module 22, and receive feedback information output by the signal processing module 22 and transmit it to the host computer, and the feedback information is used to Feedback the operating status of the motor 15; the voltage acquisition module 27 judges the voltage signal output to it by the power management module 25, and when the voltage signal output by the power management module 25 is within the voltage operating range of the motor 15, based on the control instruction received through the communication module 21, outputs a control signal to the drive module 23 to control the drive module 23 to drive the motor 15 to operate, and when the voltage signal output by the power management module 25 is not within the voltage operating range of the motor 15 (such as overvoltage or undervoltage), controls the drive module 23 to stop driving the motor to operate.

[0089] On the basis of any of the above embodiments, in one embodiment of the present application, as shown in FIG4 , the chip further includes a temperature acquisition module 28 , which is used to acquire the operating temperature of the driving module 23 and output it to the signal processing module 22 .

[0090] Based on the above embodiment, in one embodiment of the present application, the first wafer structure further includes the temperature acquisition module. However, the present application does not limit this. In other embodiments of the present application, the first wafer structure may also not include the temperature acquisition module. For example, a temperature acquisition circuit may be provided outside the first wafer structure to implement the temperature acquisition module, depending on the specific circumstances.

[0091] The chip provided in the embodiment of the present application is described below by taking the first wafer structure having the temperature acquisition module as an example.

[0092] Specifically, in one embodiment of the present application, the first wafer structure includes an eleventh wafer, and the eleventh wafer has the temperature acquisition module, so that a wafer having the temperature acquisition module is separately provided in the first wafer structure. In other embodiments of the present application, the temperature acquisition module may also share the same wafer with any of the other modules in the first wafer structure. This application does not impose any limitation on this, and the specific circumstances may vary.

[0093] On the basis of any of the above embodiments, in one embodiment of the present application, as shown in FIG4 , the chip further includes a communication filtering module 29 for filtering the communication signal between the LIN communication module and the host computer.

[0094] Based on the above embodiments, in one embodiment of the present application, the first wafer structure further includes the communication filter module. However, the present application does not limit this. In other embodiments of the present application, the first wafer structure may also not include the communication filter module, such as by providing a LIN filter circuit outside the first wafer structure to implement the communication filter module, depending on the specific circumstances. The following describes the chip provided in the embodiment of the present application, taking the first wafer structure having the communication filter module as an example.

[0095] Specifically, in one embodiment of the present application, the first wafer structure includes a twelfth wafer, the twelfth wafer having the communication filter module, so that a wafer having the communication filter module is separately provided in the first wafer structure. In other embodiments of the present application, the communication filter module may also share the same wafer with any other module in the first wafer structure. This application does not impose any limitation on this, and the specific circumstances may vary.

[0096] Based on any of the above embodiments, in one embodiment of the present application, the chip further includes: a control switch 30 electrically connected to the voltage stabilizing module 24, for controlling the sleep current of each component that uses the signal output by the voltage stabilizing module 24 as the power supply signal. Optionally, the control switch 30 is a 5V control switch, but this application does not limit this, and the specific situation depends on the specific situation.

[0097] Based on any of the above embodiments, in one embodiment of the present application, as shown in FIG7 , the communication module 21 and the voltage stabilization module 24 can be integrated into a single wafer. In this embodiment, the chip may not include a control switch to simplify the chip structure. However, this application does not limit this, and the specific implementation depends on the specific situation.

[0098] Based on any of the above embodiments, in one embodiment of the present application, as shown in FIG7 , the chip further includes an electromagnetic compatibility (EMC) module 31 for filtering out glitches and noise on a drive line electrically connected to the output end of the driver module 23. Optionally, in this embodiment, the electromagnetic compatibility (EMC) module 31 may be implemented using the first wafer structure or may not be implemented using the first wafer structure. This is not limited to this in the present application and depends on the specific implementation.

[0099] It should be noted that in specific applications, in some application scenarios, the chip may even need to have a position detection function, that is, the chip includes a position detection module to enable the chip to have a position detection function, but this application does not limit this, and the specific situation depends on the situation. Similarly, the position detection module can be implemented through the first wafer structure or not, and this application will not elaborate on this.

[0100] On the basis of any of the above embodiments, in one embodiment of the present application, as shown in FIG3 , the chip further has a port module 32 for realizing communication connection between the chip and other structures.

[0101] Specifically, in one embodiment of the present application, the chip has multiple communication ports. Specifically, the chip has at least one group of first communication ports to enable communication between the chip and a host computer.

[0102] Optionally, in one embodiment of the present application, the first communication port is a LIN communication port. In this embodiment, the chip has at least one group of LIN communication ports to achieve communication with the host computer through LIN communication; in another embodiment of the present application, the first communication port is a CAN communication port. In this embodiment, the chip has at least one group of CAN communication ports to achieve communication with the host computer through CAN communication; optionally, in this embodiment, the chip includes one of the LIN communication port and the CAN communication port, and this application does not limit this, depending on the specific circumstances.

[0103] Based on any of the above embodiments, in one embodiment of the present application, the chip further has at least one second communication port. Specifically, the second communication port may include a SENT (Single Edge Nibble Transmission) communication port, a PWM port, or an SPI communication port to realize signal transmission between the chip and other peripheral structures or internal structures. The present application does not limit this, and the specific situation depends on the circumstances.

[0104] Based on any of the above embodiments, in one embodiment of the present application, the chip also has at least one IO port, i.e., an input / output port, to realize the input or output of at least one of AD signals, PWM signals, test signals, simulation signals, and burning signals.

[0105] Optionally, based on any of the above embodiments, in one embodiment of the present application, the chip has at least two motor drive ports, and the motor drive ports are used to realize electrical connection between the chip and the motor, thereby providing a drive signal to the motor.

[0106] Specifically, in one embodiment of the present application, the chip is used to drive a brushed DC motor (i.e., a BDC motor, a Brush Direct Current motor). In this embodiment, the chip has two motor drive ports; in another embodiment of the present application, the chip is used to drive a brushless DC motor (i.e., a BLDC motor, a Brushless Direct Current motor). In this embodiment, the chip has three motor drive ports; in another embodiment of the present application, the chip is used to drive a stepper motor (i.e., an STP motor, a stepping motor). In this embodiment, the chip has four motor drive ports; the present application does not limit this. In other embodiments of the present application, the chip may also have other numbers of motor drive ports, depending on the type of motor driven by the chip.

[0107] Based on any of the above embodiments, in one embodiment of the present application, the chip further includes at least one power port for electrically connecting to a power source; the chip further includes at least one ground port for electrically connecting to a ground terminal.

[0108] Based on any of the above embodiments, in one embodiment of the present application, the second side of the first substrate is fixed on a PCB circuit board to achieve electrical connection between the first wafer structure and the first peripheral device located on the first side of the first substrate and the PCB circuit board, and to achieve electrical connection with other devices located on the PCB circuit board through the PCB circuit board.

[0109] In another embodiment of the present application, the chip further includes a second packaging layer located on the second side of the first substrate, the second side being opposite to the first side; in another embodiment of the present application, the second side of the first substrate is not provided with a second packaging layer, but is also provided with a device. Specifically, in this embodiment, the chip further includes: a preset device located on the second side of the first substrate, the second side being opposite to the first side. Optionally, in one embodiment of the present application, as shown in FIG8 , the preset device includes a solder pad 33, which is soldered to the second side of the first substrate, but the present application does not limit this. In other embodiments of the present application, the preset device may also include a preset chip, which is fixed to the second side of the first substrate by a surface mounting process. The present application does not limit this, and the specific circumstances may vary.

[0110] In one embodiment of the present application, when the preset device is a chip, the preset device is a chip with a relatively high height, such as a height of not less than 3 mm, but the present application does not limit this, and it depends on the specific circumstances. It should be noted that when a chip with a relatively high height is fixed on the first substrate, the chip with a relatively high height is not suitable for integrated packaging using a packaging layer. Therefore, unlike the wafers in the first wafer structure, the wafers in the first wafer structure do not have independently packaged wafers. After being fixed on the first substrate, they are packaged as a whole using the first packaging layer and the first peripheral layer, while the preset device is an independently packaged device, which is fixed on the first substrate in a packaged form.

[0111] It should be noted that in the above embodiment, when a second packaging layer or a preset device is provided on the second side of the first substrate, a via is further provided on the first substrate to lead out the pins of the first wafer structure and the first peripheral device located on the first side of the first substrate through the via, thereby facilitating electrical connection with other devices. Optionally, in this embodiment, a via area is provided on the first substrate for providing vias for leading out the pins of the first wafer structure and the first peripheral device located on the first side of the first substrate.

[0112] It should also be noted that in the above embodiment, when a second packaging layer or a preset device is provided on the second side of the first substrate, the chip can be directly connected to other devices when electrically connected without adding a PCB circuit board, so as to further simplify the chip structure of the chip application scenario.

[0113] Based on any of the above embodiments, in one embodiment of the present application, the first wafer structure includes multiple wafers, at least some of which are arranged in a plane parallel to the first substrate, so as to reduce the thickness of the chip by tiling at least some of the wafers. In another embodiment of the present application, the first wafer structure includes multiple wafers, at least some of which are arranged in a plane perpendicular to the first substrate, so as to reduce the planar size of the chip by stacking at least some of the wafers.

[0114] It should be noted that when at least some of the multiple wafers are arranged in a plane perpendicular to the plane where the first substrate is located, there is an intermediate layer between the two adjacent wafers arranged in the plane perpendicular to the first substrate to avoid short circuit between adjacent wafers. It should also be noted that in this embodiment, the chip can be a 2.5D packaging structure or a 3D packaging structure. This application does not limit this, and it depends on the specific situation.

[0115] As can be seen from the description of the above embodiments, the above embodiments are described as an example in which the first wafer structure has communication functions, signal processing functions, and drive functions at the same time, but the present application is not limited to this. In other embodiments of the present application, the communication functions, signal processing functions, and drive functions in the chip can also be implemented by at least two wafer structures. The following describes the chip provided in the embodiment of the present application, assuming that the communication functions, signal processing functions, and drive functions in the driver chip are implemented by two wafer structures.

[0116] Specifically, in one embodiment of the present application, the chip further includes: a second substrate; a second wafer structure fixed to the first side of the second substrate, the second wafer structure including at least one wafer, the second wafer structure having at least one of the three modules: the communication module, the signal processing module, and the driver module, and the second wafer structure and the first wafer structure having different functions; and a third packaging layer encapsulating the second wafer structure. That is, in this embodiment, the chip includes a first sub-chip and a second sub-chip, the first sub-chip including the first substrate, the first wafer structure, and a first peripheral device, and the second sub-chip including the second substrate, the second wafer structure, and a second peripheral device.

[0117] On the basis of the above embodiments, in one embodiment of the present application, the first wafer structure has at least two module functions among the communication module, the signal processing module and the driving module, and the second wafer structure has at least one module function among the communication module, the signal processing module and the driving module; such as the first wafer structure has a communication module and a signal processing module, and the second wafer structure has a driving module; or, the first wafer structure has a communication module and a driving module, and the second wafer structure has the signal processing module; or, the first wafer structure has a signal processing module and a driving module, and the second wafer structure has a communication module. In other embodiments of the present application, the first wafer structure may also have at least one module function among the communication module, the signal processing module and the driving module, and the second wafer structure may have at least two module functions among the communication module, the signal processing module and the driving module. The present application does not limit this, and the specific circumstances may vary.

[0118] Based on any of the above embodiments, in one embodiment of the present application, the chip also includes a second peripheral device fixed on the second substrate, the second peripheral device includes at least one passive device, and the second peripheral device and the second wafer structure are integrally packaged through the third packaging layer, but the present application is not limited to this. In other embodiments of the present application, the second peripheral device may not be set on the second substrate, depending on the specific circumstances.

[0119] It should be noted that in other embodiments of the present application, the chip may also include three wafer structures or more wafer structures, that is, the chip may include three sub-chips or more sub-chips. The present application does not limit this, and it depends on the application requirements of the chip.

[0120] Accordingly, an embodiment of the present application further provides a motor drive system, as shown in FIG6 , including a chip 16 and a motor 15 , wherein the chip is used to control the operation of the motor, wherein the chip is the chip provided in any of the above embodiments.

[0121] It should be noted that in the embodiment of the chip, the power management module, voltage stabilization module and Hall detection module serve as the internal structure of the chip to realize their corresponding functions, but the present application does not limit this. In other embodiments of the present application, the power management module, voltage stabilization module and Hall detection module can also serve as the external structure of the chip to realize their corresponding functions.

[0122] Specifically, in one embodiment of the present application, the motor drive system further includes: at least one module among a power management module, a voltage stabilization module and a Hall detection module;

[0123] Wherein, the voltage stabilizing module is used to convert the first voltage into a second voltage to power the signal processing module;

[0124] The power management module is used to convert the third voltage into the second voltage and supply it to the voltage stabilizing module, the communication module and the driving module;

[0125] The Hall detection module is used to detect the operating state of the motor and feed back the state to the signal processing module.

[0126] Since the specific functions and electrical connection relationships of the power management module, the voltage stabilization module and the Hall detection module have been described in detail in the embodiments of the chip, they will not be repeated here.

[0127] In addition, an embodiment of the present application also provides an electric valve, which has a chip provided by any of the above embodiments. In this embodiment, the chip is located in the space inside the electric valve. The electric valve has a motor. The chip can control the operation of the motor, and the motor can drive the valve core of the electric valve to move.

[0128] Specifically, in one embodiment of the present application, the electric valve includes an electronic expansion valve, an electric ball valve, etc.; wherein, the electronic expansion valve can be used to adjust the flow rate of the refrigerant in thermal management, especially the automotive electronic expansion valve, which is the control core of the automotive air-conditioning system. The controller sends a drive signal to the motor, and uses the transmission system to convert the motor's rotational motion into linear motion to drive the valve core up and down to achieve a change in the valve opening, thereby adjusting the refrigerant flow rate; the electric ball valve is a valve that rotates around the axis of the valve stem according to the movement form of the valve disc. The change of its valve seat opening is directly proportional to the valve disc stroke. It is mainly used to cut off or connect the medium in the pipeline, and can also be used for the regulation and control of the refrigerant.

[0129] Optionally, in one embodiment of the present application, the electric valve further includes an electric control board, the chip is electrically and / or signal-connected to the electric control board, and the motor is connected to the electric control board to realize the connection between the chip and the motor through the electric control board, so that the chip can control the operation of the motor, but the present application does not limit this. In other embodiments of the present application, the chip can also be directly connected to the motor to reduce the volume of the electric valve, which is conducive to the miniaturization of the electric valve, but the present application does not limit this, and it depends on the specific situation.

[0130] In addition, an embodiment of the present application further provides a chip manufacturing method, which is applied to the manufacturing of the chip provided in any of the above embodiments. As shown in FIG9 , the manufacturing method includes:

[0131] S1: As shown in FIG10 , a first peripheral device 13 is fixed on a first side of a first substrate 11 , wherein the first peripheral device 13 includes at least one passive device;

[0132] S2: As shown in FIG11 , a first wafer structure 12 is fixed on a first side of the first substrate 11 , wherein the first wafer structure 12 includes at least one wafer and has at least one of the three modules: the communication module, the signal processing module, and the driving module;

[0133] S3 : As shown in FIG. 12 , a first packaging layer 40 is formed to package the first peripheral device 13 and the first wafer structure 12 .

[0134] Optionally, in one embodiment of the present application, the formation process of the first peripheral device is a welding process. Specifically, in one embodiment of the present application, fixing the first peripheral device on the first side of the first substrate includes: fixing the first peripheral device on the first side of the first substrate using solder paste, but the present application does not limit this, and it depends on the specific situation.

[0135] Based on any of the above embodiments, in one embodiment of the present application, fixing the first wafer structure on the first side of the semiconductor includes: using a surface mounting process to fix the first wafer structure on the first side of the first substrate, but the present application does not limit this, and the specific situation depends on the circumstances.

[0136] Optionally, in one embodiment of the present application, after fixing the first peripheral device and the first wafer structure on the first side of the first substrate and before forming the first packaging layer, the method further includes:

[0137] As shown in FIG13 , the first wafer structure and the first substrate are electrically connected by using a wire bonding process.

[0138] Based on any of the above embodiments, in one embodiment of the present application, forming a first packaging layer that encapsulates the first peripheral device and the first wafer structure includes: using an injection molding process to form a first packaging layer that encapsulates the first peripheral device and the first wafer structure.

[0139] Based on any of the above embodiments, in one embodiment of the present application, the method further includes: forming a second packaging layer on a second side of the first substrate using an injection molding process, where the second side is opposite to the first side.

[0140] In another embodiment of the present application, the method further includes: fixing a preset device on the second side of the first substrate. The preset device may be a solder pad or a preset chip, etc., so that the chip has a structure that does not require a circuit board. It should be noted that in this embodiment, if the preset device is a solder pad, the preset device is fixed by welding, and if the preset device is a chip, the preset device is fixed by surface mounting. This application does not limit this, and the specific method will depend on the specific situation.

[0141] Based on any of the above embodiments, in one embodiment of the present application, the method further includes:

[0142] A port structure for electrically connecting the chip to an external structure is manufactured in the packaging layer, and the port structure includes at least one port.

[0143] Optionally, in one embodiment of the present application, the chip has at least two motor drive ports, and the motor drive ports are used to achieve electrical connection between the chip and the motor, thereby providing a drive signal to the motor.

[0144] Based on any of the above embodiments, in one embodiment of the present application, the manufacturing method also includes: fixing a second wafer structure on the first side of the second substrate, the second wafer structure includes at least one wafer, the second wafer structure has at least one of the three modules of the communication module, the signal processing module and the driving module, and the functions of the first wafer structure and the second wafer structure are different; forming a third packaging layer to encapsulate the second wafer structure.

[0145] Optionally, based on the above embodiment, in one embodiment of the present application, the manufacturing method further includes: before forming the third encapsulation layer, fixing a second peripheral device on the second substrate, wherein the second peripheral device includes at least one passive device. However, this application does not limit this, and the specific method will depend on the specific circumstances.

[0146] In summary, in the chip and its manufacturing method, as well as the motor drive system provided in the embodiments of the present application, the first wafer structure and the first peripheral device located on the first substrate are integrally packaged using the first packaging layer, which has the advantages of saving IC material packaging costs, lightweight system design, and small size.

[0147] Moreover, in the chip and its manufacturing method, as well as the motor drive system provided in the embodiment of the present application, the first wafer structure and the first peripheral device are applied as a whole product, which reduces the development difficulty of developers when applying the chip, shortens the development cycle, and reduces development investment costs.

[0148] In addition, in the chip and its manufacturing method, as well as the motor drive system provided in the embodiments of the present application, the first wafer structure and the first peripheral device are packaged using SIP (System In a Package), which has lower power consumption and better performance compared to SOB (System on Board) design.

[0149] It can be seen that the chip and motor drive system provided in the embodiments of the present application can achieve comprehensive cost-effectiveness in terms of power consumption, efficiency, size, design cycle, design cost and design flexibility, and have a good product strength improvement effect on the valve electronic control design in new energy vehicles.

[0150] The various embodiments in this specification are described in a progressive, parallel, or combined manner. Each embodiment focuses on the differences from other embodiments, and reference can be made to the common and similar parts between the various embodiments. For the devices disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the description is relatively simple. For relevant parts, refer to the description of the methods.

Claims

1. A chip for controlling the operation of a motor, characterized in that, The chip includes a communication module (21), a signal processing module (22), and a driving module (23). The signal processing module (22) outputs a control signal to the driving module (23) based on the communication signal obtained by the communication module (21), so that the driving module (23) controls the operation of the motor (15) in response to the control signal. The chip includes: A first substrate (11); A first wafer structure (12) fixed to the first side of the first substrate (11). The first wafer structure (12) includes at least one wafer, and the first wafer structure (12) has at least one of the three modules: the communication module (21), the signal processing module (22), and the driving module (23); A first peripheral device (13) fixed to the first side of the first substrate (11). The first peripheral device (13) includes at least one passive device; A first encapsulation layer (14) encapsulating the first wafer structure (12) and the first peripheral device (13).

2. The chip according to claim 1, characterized in that The first wafer structure (12) includes multiple wafers, and each wafer has one of the communication module (21), the signal processing module (22), and the driving module (23).

3. The chip according to claim 2, wherein The first wafer structure (12) includes: a first wafer (111), a second wafer (112), and a third wafer (113). Among them, the first wafer (111) has the communication module (21), the second wafer (112) has the signal processing module (22), and the third wafer (113) has the driving module (23).

4. The chip according to claim 1, wherein The first wafer structure (12) includes multiple wafers, and at least one of the multiple wafers has two of the communication module (21), the signal processing module (22), and the driving module (23).

5. The chip according to claim 4, wherein, The first wafer structure (12) includes a fourth wafer and a fifth wafer, where The fourth wafer has the communication module (21) and the signal processing module (22), and the fifth wafer has the driving module (23); Or, the fourth wafer has the communication module (21) and the driving module (23), and the fifth wafer has the signal processing module (22); Or, the fourth wafer has the signal processing module (22) and the driving module (23), and the fifth wafer has the communication module (21).

6. The chip according to claim 1, characterized in that, The first wafer structure (12) includes a sixth wafer, and the sixth wafer has the three modules: the communication module (21), the signal processing module (22), and the driving module (23).

7. The chip according to any one of claims 1-6, characterized in that, The chip further includes a voltage regulation module (24), and the voltage regulation module (24) is used to convert a first voltage into a second voltage to supply power to the signal processing module (22); The first wafer structure (12) also has the voltage regulation module (24).

8. The chip according to claim 7, characterized in that The chip further includes: a power management module (25) configured to convert a third voltage into the second voltage to supply power to the voltage stabilizing module (24), the communication module (21), and the driving module (23); The first wafer structure (12) further has the power management module (25).

9. The chip according to any one of claims 1-6 or 8, characterized in that The chip further includes a Hall detection module (26) configured to detect the operating state of the motor (15) and feed it back to the signal processing module (23); The first wafer structure (12) further has the Hall detection module (26).

10. The chip according to any one of claims 1-6, characterized in that, The first wafer structure includes a plurality of wafers, and at least some of the plurality of wafers are arranged in a plane parallel to the plane where the first substrate is located; Or, The first wafer structure includes a plurality of wafers, and at least some of the plurality of wafers are arranged in a plane perpendicular to the plane where the first substrate is located.

11. The chip according to any one of claims 1-6, characterized in that, The chip further includes: a second encapsulation layer located on the second side of the first substrate, where the second side is opposite to the first side; Or, The chip further includes: a preset device located on the second side of the first substrate, where the second side is opposite to the first side; wherein, the preset device includes at least one of a pad or a preset chip.

12. The chip according to claim 1, characterized in that, The chip further includes: A second substrate; A second wafer structure fixed to the first side of the second substrate, the second wafer structure includes at least one wafer, the second wafer structure has at least one of the three modules of the communication module, the signal processing module, and the driving module, and the functions of the second wafer structure and the first wafer structure are different; A third encapsulation layer encapsulating the second wafer structure.

13. A motor drive system, characterized in that, Comprising a chip and a motor, the chip is used to control the operation of the motor, wherein, the chip is the chip according to any one of claims 1-6, 10-12, and the motor drive system further includes: at least one of a power management module, a voltage stabilizing module, and a Hall detection module; Wherein, the voltage stabilizing module is configured to convert a first voltage into a second voltage to supply power to the signal processing module; The power management module is configured to convert a third voltage into the second voltage to supply power to the voltage stabilizing module, the communication module, and the driving module; The Hall detection module is configured to detect the operating state of the motor and feed it back to the signal processing module.

14. An electric valve, applied to a thermal management system, characterized in that, The electric valve has the chip according to any one of claims 1-12, the chip is located in the space inside the electric valve, the electric valve has a motor, the chip can control the operation of the motor, and the motor can drive the valve core of the electric valve to act.

15. The electric valve according to claim 14, wherein, The electric valve further includes an electronic control board, the chip is electrically connected and / or signal-connected to the electronic control board, and the motor is connected to the electronic control board; or, the chip is connected to the motor.

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