Multilayer ceramic electronic component

Abstract

The purpose of the present invention is to provide a multilayer ceramic electronic component that suppresses the complication of a manufacturing process and the increase in manufacturing cost associated therewith while sufficiently reducing the generation of squeaking noise. In a multilayer ceramic electronic component 1, a first external electrode 40 has a first main surface band portion 51, and a second external electrode 41 has a second main surface band portion 56. A first spacer portion 70 is disposed on the first main surface band portion 51, and a second spacer portion 71 is disposed on the second main surface band portion 56. The first spacer portion 70 and the second spacer portion 71 are formed of a conductive material. A first insulating layer 110 continuously covers a first connection portion 50, the first side surface band portion 53, and a third side surface band portion 54, and a second insulating layer 120 continuously covers a second connection portion 55, a second side surface band portion 58, and a fourth side surface band portion 59.

Description

Multilayer ceramic electronic components

[0001] The present invention relates to a multilayer ceramic electronic component.

[0002] Multilayer ceramic capacitors are an example of multilayer ceramic electronic components. Multilayer ceramic capacitors, each comprising a dielectric layer, an internal electrode facing the dielectric layer, and an external electrode connected to the internal electrode, are essential for the normal operation of electronic devices such as mobile phones, personal computers, and medical devices. However, the dielectric constituting the dielectric layer of a multilayer ceramic capacitor is typically a perovskite-type dielectric ceramic such as barium titanate. Therefore, when an AC voltage is applied while a DC voltage is applied, the multilayer ceramic capacitor vibrates due to a piezoelectric phenomenon. Therefore, when a multilayer ceramic capacitor is mounted on a mounting board and an AC voltage in the human audible range, such as 20 Hz to 20,000 Hz, is applied to the external electrodes, the multilayer ceramic capacitor undergoes expansion and contraction vibration, generating noise. This noise also resonates with the wiring mounting board, amplifying the sound and causing a noise phenomenon known as squealing, which can be unpleasant for humans. The technology described in Patent Document 1 discloses a multilayer ceramic capacitor that further includes first and second bumps to solve the problem of acoustic noise, and the first and second bumps described in Patent Document 1 have gaps provided in them to suppress the height of solder wetting.

[0003] Patent Application No. 2019-86320

[0004] However, the technology described in Patent Document 1 requires a process for forming a multilayer ceramic capacitor and a process for forming a first bump and a second bump, which causes problems such as the complexity of the manufacturing process and the resulting increase in manufacturing costs.

[0005] In consideration of the above problems, an object of the present invention is to provide a multilayer ceramic electronic component that sufficiently reduces the occurrence of acoustic noise while suppressing the complication of the manufacturing process and the resulting increase in manufacturing costs.

[0006] The multilayer ceramic electronic component of the present invention comprises a laminate including a plurality of laminated dielectric layers, the laminate having first and second main surfaces opposing each other in a height direction, first and second side surfaces opposing each other in a width direction perpendicular to the height direction, first end surfaces and second end surfaces opposing each other in a length direction perpendicular to the height direction and the width direction, first internal electrodes alternately laminated with the plurality of dielectric layers and exposed at the first end surfaces, and second internal electrodes alternately laminated with the plurality of dielectric layers and exposed at the second end surfaces, a first external electrode connected to the first internal electrodes, and a second external electrode connected to the second internal electrodes, the first external electrode having a first connection portion disposed on the first end surface, a first main surface band portion disposed on the first main surface, a third main surface band portion disposed on the second main surface, a first side surface band portion disposed on a part of the first side surface, and a front a third side surface band portion arranged on a portion of the second side surface and a first spacer portion arranged on the first main surface band portion, and the second external electrode has a second connection portion arranged on the second end face, a second main surface band portion arranged on the first main surface, a fourth main surface band portion arranged on the second main surface, a second side surface band portion arranged on a portion of the first side surface, a fourth side surface band portion arranged on a portion of the second side surface, and a second spacer portion arranged on the second main surface band portion, wherein the first spacer portion and the second spacer portion are made of a conductive material, and the electronic component has a first insulating layer continuously covering the first connection portion, the first side surface band portion, and the third side surface band portion, and a second insulating layer continuously covering the second connection portion, the second side surface band portion, and the fourth side surface band portion.

[0007] According to the present invention, it is possible to provide a multilayer ceramic electronic component that sufficiently reduces the occurrence of acoustic noise while suppressing the complication of the manufacturing process and the resulting increase in manufacturing costs.

[0008] FIG. 1 is a diagram showing a multilayer ceramic capacitor according to a first embodiment of the present invention. FIG. 2 is a cross-sectional view taken along line 201-201 of FIG. 1. FIG. 3 is a cross-sectional view taken along line 202-202 of FIG. 1. FIG. 4 is a cross-sectional view taken along line 203-203 of FIG. 1. FIG. 5 is a diagram showing another configuration of a multilayer ceramic capacitor. FIG. 6 is a diagram showing a multilayer ceramic capacitor according to a second embodiment of the present invention. FIG. 7 is a diagram showing a multilayer ceramic capacitor according to the second embodiment of the present invention. FIG. 8 is a diagram showing a modified external electrode and corresponds to FIG. 2. FIG. 9 is a diagram showing a modified external electrode and corresponds to FIG. 3. FIG. 10 is a diagram showing a modified external electrode and corresponds to FIG. 4. FIG. 11 is a diagram showing a state in which the multilayer ceramic capacitor is mounted on a mounting substrate.

[0009] First Embodiment A description will be given of an embodiment of the present invention with reference to the drawings. The following describes a multilayer ceramic electronic component, taking as an example a case where the multilayer ceramic electronic component is a multilayer ceramic capacitor 1. FIG. 1 is a perspective view showing the multilayer ceramic capacitor 1 according to the first embodiment of the present invention. FIG. 2 is a cross-sectional view taken along line 201-201 of FIG. 1.

[0010] (Multilayer ceramic capacitor) The multilayer ceramic capacitor 1 includes a laminate 2 and external electrodes. The external electrodes include a first external electrode 40 and a second external electrode 41. The external electrodes are covered with insulating layers. The first external electrode 40 is covered with a first insulating layer 110. The second external electrode 41 is covered with a second insulating layer 120. Because they are covered with insulating layers, the first external electrode 40 and the second external electrode 41 are not exposed on the surface of the multilayer ceramic capacitor 1 in FIG. 1 .

[0011] 2, the laminate 2 includes a plurality of laminated dielectric layers 20 and internal electrodes. The internal electrodes include a first internal electrode 30 and a second internal electrode 31.

[0012] The laminate 2 has a rectangular parallelepiped shape. In the rectangular parallelepiped, a line where two faces intersect is called a ridge line. In the rectangular parallelepiped, a portion where three surfaces intersect is called a corner.

[0013] The direction in which the dielectric layers and internal electrodes are stacked on top of each other is called the height direction 101, the direction perpendicular to the height direction and in which the first external electrode and the second external electrode face each other is called the length direction 100, and the direction perpendicular to the height direction 101 and the length direction 100 is called the width direction 102.

[0014] For each surface of the laminate 2, two surfaces facing each other in the height direction 101 are referred to as a first main surface 10 and a second main surface 11. Two surfaces facing each other in the width direction 102 are referred to as a first side surface 12 and a second side surface 13. Two surfaces facing each other in the length direction 100 are referred to as a first end surface 14 and a second end surface 15.

[0015] The internal electrodes include a first internal electrode 30 and a second internal electrode 31. The first internal electrode 30 is an internal electrode exposed at the first end face 14. The second internal electrode 31 is an internal electrode exposed at the second end face 15.

[0016] (Inner Layer Portion) A portion where a plurality of dielectric layers 20 and a plurality of internal electrodes are laminated is called an inner layer portion 60. The first internal electrode 30 and the second internal electrode 31 are disposed on different dielectric layers 20, respectively.

[0017] (Dielectric Layer) The dielectric layer 20 is made of a dielectric material. An example of the dielectric material is a dielectric ceramic containing components such as barium titanate, calcium titanate, strontium titanate, or calcium zirconate. The dielectric material has a dielectric ceramic as a main component and may contain a secondary component. Examples of the secondary component include a manganese compound, an iron compound, a chromium compound, a cobalt compound, and a nickel compound.

[0018] There are no particular limitations on the thickness of the dielectric layer 20. The region that forms the capacitance and is formed by the first internal electrode 30 and the second internal electrode 31 is called the effective region 62. An example of the thickness of the dielectric layer 20 in the effective region 62 is 0.3 μm or more and 2.0 μm or less.

[0019] There is no particular limitation on the number of the dielectric layers 20. For example, the number of the dielectric layers 20 in the effective region 62 is 1 to 6000.

[0020] (Outer Layer Portion) The portions of the inner layer portion 60 on both sides in the height direction 101 where no internal electrodes are formed and which are composed only of the dielectric layer 20 are called outer layer portions 61. The thickness of the outer layer portion 61 is not particularly limited. For example, the thickness of the outer layer portion 61 is 15 μm or more and 150 μm or less.

[0021] The thickness of the dielectric layer 20 in the outer layer portion 61 may be greater than the thickness of the dielectric layer 20 in the effective region 62. The material of the dielectric layer 20 in the outer layer portion 61 may be different from the material of the dielectric layer 20 in the inner layer portion 60.

[0022] (External Electrodes) The external electrodes include a first external electrode 40 and a second external electrode 41. The first external electrode 40 is an external electrode connected to the first internal electrode 30. The second external electrode 41 is an external electrode connected to the second internal electrode 31.

[0023] (Connections and bands) Regarding external electrodes, those arranged on the end faces are called connection parts. Those arranged on the side faces and on surfaces extending from the side faces in the length direction are called side band parts. Those arranged on the main faces and on surfaces extending from the main faces in both the length and width directions are called main face band parts.

[0024] The first external electrode 40 has a first connection portion 50 arranged on the first end face 14, a first main surface band portion 51 arranged on the first main surface 10, a third main surface band portion 52 arranged on the second main surface 11, a first side band portion 53 arranged on a portion of the first side surface 12, and a third side band portion 54 arranged on a portion of the second side surface 13.

[0025] The second external electrode 41 has a second connection portion 55 arranged on the second end face 15, a second main surface band portion 56 arranged on the first main surface 10, a fourth main surface band portion 57 arranged on the second main surface 11, a second side surface band portion 58 arranged on a portion of the first side surface 12, and a fourth side surface band portion 59 arranged on a portion of the second side surface 13.

[0026] (Base electrode layer) The external electrodes include a base electrode layer. The base electrode layer is a layer containing a conductive metal and glass. The base electrode layer included in the first external electrode 40 is called the first base electrode layer 42. The base electrode layer included in the second external electrode 41 is called the second base electrode layer 45.

[0027] (Baked Layer) The base electrode layer includes at least one selected from a baked layer, a conductive resin layer, a thin film layer, and the like. The baked layer preferably includes a metal component and either a glass component or a ceramic component, or both. Examples of the metal component include at least one selected from copper, nickel, silver, palladium, a silver-palladium alloy, and gold. Examples of the glass component include at least one selected from boron, silicon, barium, magnesium, aluminum, and lithium. The ceramic component may be the same type of ceramic material as the dielectric layer 20. Alternatively, the ceramic component may be a ceramic material different from that of the dielectric layer 20. Examples of the ceramic component include at least one selected from barium titanate, calcium titanate, barium calcium titanate, strontium titanate, and calcium zirconate.

[0028] The baked layer is formed by, for example, applying and baking a conductive paste containing glass and metal to the laminate 2. The baked layer may be formed by simultaneously baking a laminated chip having internal electrodes and a dielectric layer 20 and a conductive paste applied to the laminated chip. Alternatively, the baked layer may be formed by baking a laminated chip having internal electrodes and a dielectric layer 20 to obtain the laminate 2, and then applying and baking a conductive paste to the laminate 2.

[0029] When a laminated chip having internal electrodes and dielectric layer 20 and a conductive paste applied to the laminated chip are simultaneously fired, the fired layer is preferably formed by firing a material to which a ceramic material is added instead of a glass component. In this case, it is particularly preferable to use the same type of ceramic material as that of dielectric layer 20 as the added ceramic material. The fired layer may be a multi-layered layer.

[0030] The thickness in the length direction 100 of the first base electrode layer 42 located on the first end face 14 is preferably, for example, about 3 μm or more and 160 μm or less at the center in the height direction 101 and width direction 102 of the first base electrode layer 42. The thickness in the length direction 100 of the second base electrode layer 45 located on the second end face 15 is preferably, for example, about 3 μm or more and 160 μm or less at the center in the height direction 101 and width direction 102 of the second base electrode layer 45.

[0031] The external electrodes may include a plating layer in addition to the base electrode layer. A configuration in which the external electrodes include a plating layer will be described later.

[0032] (Spacer Portion) In the multilayer ceramic capacitor 1 of this embodiment, spacer portions made of conductive metal are provided as part of the external electrodes. The spacer portions include a first spacer portion 70 and a second spacer portion 71. The first main surface band portion 51 includes the first spacer portion 70. The second main surface band portion 56 includes the second spacer portion 71.

[0033] The spacer portions are part of the external electrode members. When the multilayer ceramic capacitor 1 is mounted on a mounting board or the like, the presence of the spacer portions makes it possible to increase the distance between the laminate and the mounting board.

[0034] (Spacer Portion Material) The spacer portion is made of a conductive material. Preferably, the spacer portion is made of metal plating. Whether the spacer portion is made of metal plating can be confirmed by the following method. The glass content of the first main surface band portion 51 and the second main surface band portion 56, as well as the first spacer portion 70 and the second spacer portion 71, is measured in a cross section at the center of the width direction 102, parallel to the length direction 100 and the height direction 101. If the glass content of the first spacer portion 70 and the second spacer portion 71 is found to be less than the glass content of the first main surface band portion 51 and the second main surface band portion 56, it can be determined that the spacer portion is made of metal plating.

[0035] The spacer portion is not limited to being made of plated metal, but may be made of, for example, a conductive paste, or a block formed of a conductive material.

[0036] (Shape of Spacer Portion) The shape of the spacer portion is not particularly limited. Examples of the shape of the spacer portion include a substantially rectangular parallelepiped shape, a cylindrical shape, and a three-dimensional shape with an H-shaped bottom.

[0037] (Spacer portion arrangement) The first spacer portion 70 is arranged at least on the first principal surface band portion 51, and covers a portion of the first base electrode layer 42 arranged on a portion of the first principal surface. The second spacer portion 71 is arranged at least on the second principal surface band portion 56, and covers a portion of the second base electrode layer 45 arranged on a portion of the first principal surface.

[0038] As a result, plating layers that serve as spacer portions are formed on the first principal surface band portion 51 and the second principal surface band portion 56. When the multilayer ceramic capacitor 1 is mounted on a mounting board or the like, the laminate and the mounting board can be separated by the thickness of the spacer portions, thereby reducing the height of solder wetting. As a result, the occurrence of squeal due to electrostriction can be reduced.

[0039] The first spacer portion 70 may extend from the first main surface band portion 51 to a portion of the first connecting portion 50 and cover the first underlying electrode layer 42. The second spacer portion 71 may extend from the second main surface band portion 56 to a portion of the second connecting portion 55 and cover the second underlying electrode layer 45.

[0040] In this case, the occurrence of the above-mentioned squealing noise can be reduced, and the bonding strength between the spacer portion and the base electrode can be increased.

[0041] Mounting of the multilayer ceramic capacitor 1 on a mounting substrate 200 will be described with reference to FIG. 11 . FIG. 11 is a diagram showing the multilayer ceramic capacitor 1 mounted on the mounting substrate 200. Pads 210 are formed on the mounting substrate 200. The multilayer ceramic capacitor 1 is mounted on the mounting substrate 200 by electrically connecting the first spacer portion 70 and the second spacer portion 71 to the pads 210. Solder 220 is used for mounting. During mounting, the solder wets and rises from the surface of the pad 210 in a height direction 101 (see arrow 103 in FIG. 11 ; the direction of arrow 103 is referred to as the wetting-up direction). In the example shown in FIG. 11 , the height of the solder wetting-up direction 103 at the connection portion and side band portion of the multilayer ceramic capacitor 1 can be reduced. As a result, the occurrence of acoustic noise due to electrostriction can be reduced.

[0042] Furthermore, in the multilayer ceramic capacitor 1 of this embodiment, the spacer portions are formed by metal plating, so the manufacturing process is not complicated, and therefore it is possible to suppress the increase in manufacturing costs that would otherwise be associated with a complicated manufacturing process.

[0043] (Ends of External Electrodes) The end portions of the external electrodes on the first main surface 10, the second main surface 11, the first side surface 12, and the second side surface 13 are referred to as the ends 48 of the external electrodes. Figure 2 shows examples of the ends 48 of the external electrodes, including the end 48 on the first main surface 10 of the first external electrode 40, the end 48 on the second main surface 11 of the first external electrode 40, the end 48 on the first main surface 10 of the first external electrode 40, and the end 48 on the second main surface 11 of the second external electrode 41. The spacer portion may or may not cover the ends 48 of the external electrodes.

[0044] (Thickness of spacer portion arranged at connecting portion) The thickness of the first spacer portion 70 arranged at the first connecting portion 50 may be smaller than the thickness of the first spacer portion 70 arranged at the first main surface band portion 51. The thickness of the second spacer portion 71 arranged at the second connecting portion 55 may be smaller than the thickness of the second spacer portion 71 arranged at the second main surface band portion 56. Even with this configuration, as described above, it is possible to reduce the occurrence of squeal due to the electrostriction phenomenon.

[0045] Preferably, the thickness of the first spacer portion 70 disposed on the first connecting portion 50 and the second spacer portion 71 disposed on the second connecting portion 55 may be 0 μm. In other words, the first spacer portion 70 may not be disposed on the first connecting portion 50, and the second spacer portion 71 may not be disposed on the second connecting portion 55.

[0046] Even in such a case, a plating layer is formed on the main surface band portion as a spacer portion. Therefore, during mounting, solder wets onto the spacer portion arranged on the main surface band portion, but the solder does not easily wet onto the connection portion. Therefore, in the multilayer ceramic capacitor 1 of this embodiment, solder does not easily wet onto the connection portion. As a result, it is possible to prevent the solder wet-up height in the height direction 101 during mounting from increasing, and the occurrence of squeal can be reduced.

[0047] The structure of the multilayer ceramic capacitor 1 as viewed from another direction will be described with reference to Figures 3 and 4. Figure 3 is a cross-sectional view taken along line 202-202 in Figure 1. Figure 4 is a cross-sectional view taken along line 203-203 in Figure 1.

[0048] As shown in Figure 3, the insulating layers cover the side band portions in addition to the connection portions. A first insulating layer 110 covers the first side band portion 53 and the third side band portion 54. A second insulating layer 120 covers the second side band portion 58 and the fourth side band portion 59. The insulating layers extend beyond the ends 48 of the external electrodes and contact the side surfaces.

[0049] 3 is a cross-sectional view taken at a height at which the second internal electrode 31 can be observed. In cross-sectional views taken at other heights, the first internal electrode 30 can be observed instead of the second internal electrode 31.

[0050] 4, a second spacer portion 71 is disposed on the second main surface band portion 56. A second insulating layer 120 is disposed on the second side surface band portion 58 and the fourth side surface band portion 59.

[0051] (Plating Material Constituting the Spacer Portion) A case where the spacer portion is formed of metal plating will be described. The metal plating may include at least one selected from, for example, copper, nickel, tin, silver, palladium, a silver-palladium alloy, and gold. The first spacer portion 70 and the second spacer portion 71 may each be formed of multiple layers.

[0052] Preferably, the first spacer portion 70 includes a first nickel plating layer 80 containing nickel and connected to the first main surface band portion 51, and a first tin plating layer 81 containing tin and covering the first nickel plating layer. Preferably, the second spacer portion 71 includes a second nickel plating layer 82 containing nickel and connected to the second main surface band portion 56, and a second tin plating layer 83 containing tin and covering the second nickel plating layer 82.

[0053] In this way, when the spacer portion includes a nickel plating layer and a tin plating layer, the nickel plating layer prevents the first base electrode layer 42 and the second base electrode layer 45 from being eroded by solder when mounting the multilayer ceramic capacitor 1.

[0054] The tin plating layer improves the wettability of solder when mounting the multilayer ceramic capacitor 1. The improved wettability of solder makes it easier to mount the multilayer ceramic capacitor 1.

[0055] Furthermore, since the spacer portion is formed from a plated layer, no additional process is required, which prevents the manufacturing process from becoming complicated and the resulting increase in manufacturing costs.

[0056] (Thickness of the spacer portion arranged on the main surface band portion) The thickness of the first spacer portion 70 and the second spacer portion 71 arranged on the main surface band portion may both be 5 μm or more and 25 μm or less. The thickness of the spacer portion can be detected by the following method. In a cross section parallel to the length direction 100 and the height direction 101 at the center of the width direction 102, the dimension in the height direction 101 of the region where the metal plating is formed is measured. This makes it possible to observe the thickness of the spacer portion.

[0057] By setting the thickness of the spacer portion within the above range, when mounting the multilayer ceramic capacitor 1 on a mounting substrate or the like, solder wets the spacer portion arranged in the main surface band portion, but the connection portion and side band portion are physically separated from the mounting substrate, making it difficult for the solder to wet. Therefore, in the multilayer ceramic capacitor 1 of this embodiment, solder does not wet the connection portion and side band portion easily, so the height of solder wetting in the height direction 101 during mounting can be prevented from increasing, and the occurrence of squeal can be reduced. If the thickness of the spacer portion is less than 5 μm, solder does not wet well, resulting in mounting defects. If the thickness of the spacer portion exceeds 25 μm, processing takes time, resulting in high processing costs.

[0058] When the first insulating layer 110 is formed on the first main surface band portion 51, the first spacer portion 70 may protrude from the first insulating layer 110 formed on the first main surface band portion 51. When the second insulating layer 120 is formed on the second main surface band portion 56, the second spacer portion 71 may protrude from the second insulating layer 120 formed on the second main surface band portion 56. In other words, in cross sections in the length direction and height direction, the thicknesses of the first spacer portion 70 and the second spacer portion 71 may be greater than the thicknesses of the first insulating layer 110 and the second insulating layer 120 formed on the band portions on the first main surface 10 and the second main surface 11.

[0059] When the spacer portions protrude from the insulating layer, solder can be easily applied to the first spacer portion 70 and the second spacer portion 71, even when the first insulating layer 110 is formed on the first main surface band portion 51 or when the second insulating layer 120 is formed on the second main surface band portion 56. As a result, the multilayer ceramic capacitor 1 can be easily mounted on a mounting board or the like.

[0060] When the first insulating layer 110 is formed on the first main surface band portion 51, the first spacer portion 70 and the first insulating layer 110 formed on the first main surface band portion 51 may be smooth. When the second insulating layer 120 is formed on the second main surface band portion 56, the second spacer portion 71 and the second insulating layer 120 formed on the second main surface band portion 56 may be smooth. In other words, the thicknesses of the first spacer portion 70 and the second spacer portion 71 may be equal to the thicknesses of the first insulating layer 110 and the second insulating layer 120 formed on the band portions of the first main surface 10 and the second main surface 11.

[0061] When the first insulating layer 110 is formed on the first main surface band portion 51, the first spacer portion 70 may be recessed further than the first insulating layer 110 formed on the first main surface band portion 51. When the second insulating layer 120 is formed on the second main surface band portion 56, the second spacer portion 71 may be recessed further than the second insulating layer 120 formed on the second main surface band portion 56. In other words, the thicknesses of the first spacer portion 70 and the second spacer portion 71 may be smaller than the thicknesses of the first insulating layer 110 and the second insulating layer 120 formed on the band portions of the first main surface 10 and the second main surface 11. When the spacer portion is recessed further than the insulating layer, the cost of plating can be reduced.

[0062] Preferably, the difference in dimension in the height direction 101 between the first spacer portion 70 and the first insulating layer 110 is −15 μm or more and 24 μm or less. Preferably, the difference in dimension in the height direction 101 between the second spacer portion 71 and the second insulating layer 120 is −15 μm or more and 24 μm or less. The difference in dimension can be observed as follows: In a cross section parallel to the length direction 100 and the height direction 101 at the center of the width direction 102, the maximum dimension in the height direction 101 of the region where the plated metal is formed, i.e., the thickness of the first spacer portion 70 and the second spacer portion 71, is measured. The first insulating layer 110 and the second insulating layer 120 are formed in the band portions of the first main surface 10 and the second main surface 11, and are closest to the first spacer portion 70 and the second spacer portion 71. The height direction 101 of the first insulating layer 110 and the second insulating layer 120, i.e., the thickness of the first insulating layer 110 and the second insulating layer 120, are measured. The difference between the thicknesses of the first insulating layer 110 and the second insulating layer 120 can be calculated by subtracting the thickness of the first spacer portion 70 and the second spacer portion 71 from the thickness of the first insulating layer 110 and the second insulating layer 120, respectively. In this way, the thickness difference between the first spacer portion 70 and the second spacer portion 71 and the insulating layer can be observed.

[0063] The above structure makes it easier to mount the multilayer ceramic capacitor 1 on a mounting substrate. If the difference in thickness between the spacer portion and the insulating layer is less than −15 μm, mounting becomes difficult, increasing the possibility that the multilayer ceramic capacitor 1 will come off the mounting substrate. If the difference in thickness between the spacer portion and the insulating layer exceeds 24 μm, the overall dimension of the multilayer ceramic capacitor in the lamination direction increases, causing interference with other components when mounted, resulting in poor mountability. In addition, the cost of plating increases.

[0064] (Thickness of Nickel Plating and Tin Plating) In this embodiment, the first spacer portion 70 and the second spacer portion 71 are formed of a nickel plating layer and a tin plating layer. Preferably, the thickness of the nickel plating layer of the first spacer portion 70 and the thickness of the nickel plating layer of the second spacer portion 71 may be thicker than the tin plating layer. The thickness of the nickel plating layer may be 10 times or more the thickness of the tin plating layer.

[0065] During mounting, the tin plating layer is corroded by solder, so if the nickel plating layer is thicker than the tin plating layer, the height of the multilayer ceramic capacitor 1 during mounting will be higher than if the nickel plating layer is thinner than the tin plating layer.

[0066] In this case, solder is less likely to wet onto the connection section and side band section, which helps reduce noise. Furthermore, because the spacer section is made of a plated layer, no additional process is required. As a result, the complexity of the manufacturing process and the resulting increase in manufacturing costs can be suppressed.

[0067] Preferably, the thickness of the nickel plating layer of the first spacer portion 70 may be thicker than the thickness of the first insulating layer 110 formed on the main surface band portion. Preferably, the thickness of the nickel plating layer of the second spacer portion 71 may be thicker than the thickness of the second insulating layer 120 formed on the main surface band portion.

[0068] During mounting, the tin-plated layer is eroded by solder. Because the nickel-plated layer is thicker than the insulating layer formed on the band portion of the main surface, the nickel-plated layer and the mounting board are securely connected during mounting, resulting in good electrical conductivity.

[0069] (Internal Electrodes) The internal electrodes will now be described. As shown in Fig. 3 , the internal electrodes extend in the length direction 100 and have a rectangular shape when viewed from above in the height direction 101. The first internal electrode 30 is extended to the first end surface 14 of the laminate 2. The second internal electrode 31 is extended to the second end surface 15 of the laminate 2. The second internal electrode 31 is shown in Fig. 3 .

[0070] The internal electrodes are composed of a first internal electrode 30 and a second internal electrode 31. The first internal electrode 30 and the second internal electrode 31 are disposed on different dielectric layers 20, respectively.

[0071] The internal electrodes are formed by sintering a conductive paste on the dielectric layers. The conductive paste contains a metal powder that serves as a conductor, an organic solvent, a binder, and a dispersant. The internal electrodes and the dielectric layers 20 are alternately stacked to form the inner layer portion 60.

[0072] The internal electrodes may be made of metals such as nickel, copper, silver, palladium, silver-palladium alloy, and gold. These metals may be compounds containing these metal elements or alloys with other metals.

[0073] The thickness of the internal electrodes is not particularly limited, but may be, for example, about 0.3 μm to 1.5 μm.

[0074] (Insulating Layer) The insulating layer will now be described. The first insulating layer 110 continuously covers the first connecting portion 50, the first side band portion 53, and the third side band portion 54. The second insulating layer 120 continuously covers the second connecting portion 55, the second side band portion 58, and the fourth side band portion 59. In other words, the first insulating layer 110 is disposed from the first connecting portion 50 to the first side band portion 53 and the third side band portion 54. The second insulating layer 120 is disposed from the second connecting portion 55 to the second side band portion 58 and the fourth side band portion 59.

[0075] By disposing an insulating layer on the connection portion, it is possible to suppress the height of solder wetting up at the connection portion during mounting, which contributes to reducing acoustic noise. Furthermore, by covering the side band portion with an insulating layer, it is possible to suppress solder wetting up onto the side band portion during mounting. Since it is possible to suppress solder wetting up on the side surface, it is possible to further reduce acoustic noise.

[0076] The first insulating layer 110 may or may not be in contact with the first spacer portion 70. The second insulating layer 120 may or may not be in contact with the second spacer portion 71.

[0077] The thickness of the first insulating layer 110 disposed in the connection portion and the thickness of the second insulating layer 120 disposed in the connection portion may be 1 μm or more and 20 μm or less. The thickness of the first insulating layer 110 disposed in the main surface band portion and the thickness of the second insulating layer 120 disposed in the main surface band portion may be 1 μm or more and 20 μm or less. The thickness of the first insulating layer 110 disposed in the side band portion and the thickness of the second insulating layer 120 disposed in the side band portion may be 1 μm or more and 20 μm or less.

[0078] The thickness of the insulating layer can be measured as follows: When measuring the thickness of the insulating layer disposed at the connection portion, a cross section parallel to the length direction 100 and the height direction 101 at the center of the width direction 102 is observed using a microscope, and the thickness of the insulating layer disposed at the connection portion at that time is measured in the length direction 100.

[0079] When measuring the thickness of the insulating layer arranged on the side band portion, a cross section parallel to the length direction 100 and width direction 102 at the center of the height direction 101 is observed using a microscope, and the thickness of the insulating layer arranged on the side band portion at that time is measured in the length direction 100.

[0080] When measuring the thickness of the insulating layer arranged in the main surface band portion, a cross section parallel to the length direction 100 and the height direction 101 at the center of the width direction 102 is observed using a microscope, and the thickness of the insulating layer arranged in the main surface band portion at that time is measured in the height direction 101.

[0081] The first insulating layer 110 may continuously cover the first connecting portion 50, the first side band portion 53, a portion of the first side surface 12 exposed on the surface of the multilayer ceramic capacitor 1, the third side band portion 54, and a portion of the second side surface 13 exposed on the surface of the multilayer ceramic capacitor 1. The second insulating layer 120 may continuously cover the second connecting portion 55, the second side band portion 58, a portion of the first side surface 12 exposed on the surface of the multilayer ceramic capacitor 1, the fourth side band portion 59, and a portion of the second side surface 13 exposed on the surface of the multilayer ceramic capacitor 1.

[0082] The portion of the insulating layer that covers the side surface exposed on the surface of the multilayer ceramic capacitor 1 is called an insulating layer side surface portion 130. As shown in Fig. 3, the insulating layer side surface portion 130 covers the end portion 48 of the external electrode.

[0083] Preferably, the first insulating layer 110 may entirely cover the first connecting portion 50, the first side band portion 53, and the third side band portion 54. Preferably, the second insulating layer may entirely cover the second connecting portion 55, the second side band portion 58, and the fourth side band portion 59.

[0084] (Another Form of Insulating Layer) Another form of insulating layer will be described with reference to Fig. 5. Fig. 5 is a diagram showing another configuration of the multilayer ceramic capacitor 1. Fig. 5 shows a cross section of the multilayer ceramic capacitor 1 parallel to the length direction 100 and the height direction 101.

[0085] 5 , the first insulating layer 110 may further cover the first main surface band portion 51, at least a portion of the first main surface 10, the third main surface band portion 52, and at least a portion of the second main surface 11. The second insulating layer 120 may further cover the second main surface band portion 56, at least a portion of the first main surface 10, the fourth main surface band portion 57, and at least a portion of the second main surface 11.

[0086] In other words, the first insulating layer 110 may continuously cover the first and third side face band portions, part or all of the first side face 12 and the second side face 13, as well as the first main surface band portion 51, at least a part of the first main surface 10 exposed on the surface of the multilayer ceramic capacitor 1, the third main surface band portion 52, and at least a part of the second main surface 11 exposed on the surface of the multilayer ceramic capacitor 1. The second insulating layer 120 may continuously cover the second and fourth side face band portions, part or all of the first side face 12 and the second side face 13, as well as the second main surface band portion 56, at least a part of the first main surface 10 exposed on the surface of the multilayer ceramic capacitor 1, the fourth main surface band portion 57, and at least a part of the second main surface 11 exposed on the surface of the multilayer ceramic capacitor 1.

[0087] In this case, the first insulating layer 110 may preferably entirely cover the first connecting portion 50, the first main surface band portion 51, and the third main surface band portion 52. The second insulating layer 120 may entirely cover the second connecting portion 55, the second main surface band portion 56, and the fourth main surface band portion 57.

[0088] With this insulating layer configuration, the first side band portion 53, the second side band portion 58, the third side band portion 54, and the fourth side band portion 59, as well as the first side surface 12 and the second side surface 13, are covered with the first or second insulating layer. This improves the adhesive strength between the side band portion and the laminate. As a result, peeling from the side band portion and moisture penetration can be suppressed.

[0089] Furthermore, when the insulating layer completely covers the side band portions and the connection portions, the side band portions and the connection portions are not exposed, so surface deterioration of the side band portions and the connection portions can be prevented.

[0090] When the insulating layer is further configured to continuously cover the main surface band portion and a portion of the main surface, the adhesive strength between not only the side band portion and the laminate 2 but also the main surface band portion and the laminate 2 is improved, thereby suppressing peeling from the side band portion and the main surface band portion and the intrusion of moisture. In other words, the adhesive strength between the first and second base electrode layers 42 and 45 and the laminate 2 is improved, suppressing peeling between the first and second base electrode layers 42 and 45 and the laminate 2 and the intrusion of moisture. Furthermore, when the main surface band portion, the side band portion, and the connecting portion are entirely covered, the first and second base electrode layers 42 and 45 are not exposed, so surface deterioration of the first and second base electrode layers 42 and 45 can be prevented.

[0091] The first insulating layer 110 and the second insulating layer 120 may be connected to each other via the first side surface 12 and the second side surface 13. Preferably, the first insulating layer 110 and the second insulating layer 120 may be connected to each other via the entire surfaces of the first side surface 12 and the second side surface 13 exposed in the multilayer ceramic capacitor 1. In other words, the first insulating layer 110 and the second insulating layer 120 may cover the side surfaces.

[0092] Because the first insulating layer 110 and the second insulating layer 120 are connected via the first side surface 12 and the second side surface 13, solder is reliably prevented from wetting onto the first connecting portion 50 and the second connecting portion 55, as well as the first side band portion 53, the second side band portion 58, the third side band portion 54, and the fourth side band portion 59 during mounting, thereby achieving the effect of reducing noise.

[0093] The first insulating layer 110 and the second insulating layer 120 may be connected via the first main surface 10 and the second main surface 11 and the first side surface 12 and the second side surface 13. More preferably, the first side surface 12 and the second side surface 13 exposed to the multilayer ceramic capacitor may be connected via the entire surfaces of the first main surface 10 and the second main surface 11 exposed to the multilayer ceramic capacitor.

[0094] The portion where the first insulating layer 110 and the second insulating layer 120 are connected via the first main surface 10 and the second main surface 11, or the first side surface 12 and the second side surface 13, is called an insulating layer connecting portion 131. Figure 5 shows the insulating layer connecting portion 131 on the first main surface 10 and the second main surface 11.

[0095] In this configuration, the first and second base electrode layers 42 and 45 are entirely covered with an insulating layer, which can suppress surface deterioration of the base electrode layers. Furthermore, the first and second main surfaces 10 and 11 and the first and second side surfaces 12 and 13 are entirely covered with an insulating layer, which significantly reduces peeling between the first and second base electrode layers 42 and 45 and the laminate 2, and also significantly reduces the number of paths for moisture to penetrate between the first and second base electrode layers 42 and 45 and the laminate 2, thereby significantly improving moisture resistance reliability.

[0096] (Material of the insulating layer) The material of the insulating layer will be described. The material of the first insulating layer 110 and the second insulating layer 120 is not particularly limited. The material of the insulating layer may be a synthetic resin. Examples of synthetic resins include thermosetting resins such as epoxy resin, polyimide resin, and phenolic resin, thermoplastic resins such as polyethylene resin and polyamide resin, and photocurable resins that undergo a polymerization reaction when exposed to light such as ultraviolet light or visible light to harden the resin.

[0097] More preferably, the material of the first insulating layer 110 and the second insulating layer 120 may be a synthetic resin such as the above containing an inorganic material such as alumina, silica, glass, or ceramic.

[0098] By incorporating alumina, silica, glass, or ceramic into the insulating layer, the amount of resin contained in the insulating layer is reduced, thereby suppressing water absorption. In addition, the residual stress generated in the insulating layer at the interface with the base body is alleviated, and the linear expansion coefficient is reduced, resulting in improved adhesion.

[0099] (Dimensions of Multilayer Ceramic Capacitor) There are no particular limitations on the dimensions of the multilayer ceramic capacitor 1. For example, the dimensions of the multilayer ceramic capacitor 1 can be approximately 0.1 mm or more and 2.5 mm or less in the height direction 101, approximately 0.1 mm or more and 3.2 mm or less in the length direction 100, and approximately 0.1 mm or more and 2.5 mm or less in the width direction 102.

[0100] (Manufacturing Method of Multilayer Ceramic Capacitor) The manufacturing method of the multilayer ceramic capacitor 1 will be described. (1) Sheet Preparation Step: First, a dielectric sheet and a conductive paste for the internal electrodes are prepared. The dielectric sheet and the conductive paste for the internal electrodes contain a binder and a solvent, and known organic binders and organic solvents can be used. (2) Printing Step: Next, the conductive paste for the internal electrodes is printed in a predetermined pattern on the dielectric sheet by, for example, screen printing or gravure printing, thereby forming an internal electrode pattern. (3) Stacking Step: Next, a predetermined number of dielectric sheets for the outer layers without an internal electrode pattern are stacked, and then dielectric sheets with internal electrodes are stacked on top of these, and a predetermined number of dielectric sheets for the outer layers are stacked on top of these to produce a laminate sheet. (4) Pressing Step: The resulting laminate sheet is pressed in the height direction 101 using a means such as a hydrostatic press to produce a laminate block. (5) Cutting Step: Next, the laminate block is cut to a predetermined size, and laminate chips are cut out. At this time, the corners and ridges of the laminated chip may be rounded by barrel polishing or the like. (6) Firing Step The laminated chip is then fired to produce the laminate 2. The firing temperature at this time depends on the materials of the dielectric and internal electrodes, but is preferably 900°C or higher and 1300°C or lower. (7) Base Electrode Layer Application Step A conductive paste for the external electrodes is applied to both end surfaces of the obtained laminate 2 and baked to form baked layers for the external electrodes. The baking temperature at this time is preferably 700°C or higher and 900°C or lower.

[0101] A method for manufacturing the spacer portion and the insulating layer will now be described. There are two patterns for manufacturing the spacer portion and the insulating layer. One pattern is a pattern in which the spacer portion is formed before the insulating layer. The other pattern is a pattern in which the spacer portion is formed after the insulating layer. Each method will be described below in order.

[0102] (Pattern in which the spacer portion is formed first) First, a pattern in which the spacer portion is formed before the insulating layer will be described. (8) Spacer portion formation process (plating process) Areas where no spacer portion is formed and the base electrode layer is exposed are sealed using adhesive tape or the like to prevent plating solution from entering between the adhesive tape and the base electrode layer. Then, nickel plating and tin plating are sequentially performed using nickel plating solution and tin plating solution to form spacer portions to a predetermined thickness. The thickness of the spacer portion can be adjusted appropriately by the immersion time in the nickel plating solution and the tin plating solution and the magnitude of the current. (9) Insulating layer formation process In the chip created by steps (1) to (8), an insulating layer material is applied to the insulating layer formation position. At this time, as already described, the main material of the insulating layer material is not particularly limited, but thermosetting resin, thermoplastic resin, photocurable resin, etc. may be used. In this embodiment, a thermosetting resin is used. The insulating layer material is applied to the base electrode layer where the insulating layer is to be formed and where the spacer portion is not formed, the exposed main surface and side surfaces of the laminate, and the boundary between them. Heat is then used to activate the polymerization reaction and harden the insulating layer material. While this manufacturing method was used in this embodiment, insulating layers can be formed in various positions by changing the position where adhesive tape is attached and the position where the insulating layer material is applied. The insulating layer material can also be changed. For example, the insulating layer material can be a liquid containing a monomer such as a thermosetting resin, thermoplastic resin, or photocurable resin as the main component, mixed with an inorganic material such as alumina, silica, glass, or ceramic. In this case, the resin hardening method, such as heat or light, can be changed as appropriate.

[0103] (Pattern in which the spacer portion is formed later) Next, a pattern in which the spacer portion is formed after the insulating layer will be described. (8) Insulating Layer Formation Process: The chip created by steps (1) to (7) is placed on an adhesive sheet, and an insulating layer material is applied to the chip. This prevents the insulating layer material from being applied to the area where the adhesive sheet and the chip are in contact, and allows the insulating layer material to be selectively applied to other areas. As already described, the main material of the insulating layer material is not particularly limited, but may be a thermosetting resin, a thermoplastic resin, a photocurable resin, or the like. In this embodiment, a thermosetting resin is used, and the insulating layer material is applied to the base electrode layer where the spacer portion is not formed, the main surface exposed on the laminate surface, the side surfaces, and the boundary between them, which are the insulating formation positions. The polymerization reaction is activated by heat, and the insulating layer material is hardened. The adhesive sheet attached to the chip is then peeled off.

[0104] In this embodiment, the manufacturing method described above was used, but by changing the position where the adhesive sheet and the chip contact and the application position of the insulating layer material, it is possible to form an insulating layer in various positions. The insulating layer material can also be changed. For example, the insulating layer material can be a liquid containing a mixture of a monomer such as a thermosetting resin, a thermoplastic resin, or a photocurable resin as the main component and an inorganic material such as alumina, silica, glass, or ceramic. In this case, the resin curing method, such as heat or light, can be changed as appropriate.

[0105] Another method is to adjust the position of the insulating layer using adhesive tape or the like. In the chips prepared by steps (1) to (7), the areas where the insulating layer is not to be formed are sealed using adhesive tape or adhesive sheets, and the insulating layer material is applied to the insulating layer formation areas. This allows the insulating layer material to be selectively applied to the areas where the insulating layer is to be formed. (9) Spacer Part Forming Process (Plating Process) In the chips on which the insulating layer is formed by step (8), nickel plating and tin plating are sequentially performed using a nickel plating solution and a tin plating solution to form spacers of a predetermined thickness in the exposed areas of the base electrode layer where no insulating layer is attached. The thickness of the spacers can be adjusted as needed by adjusting the immersion time in the nickel plating solution and the magnitude of the current.

[0106] Second Embodiment A multilayer ceramic capacitor 1 according to a second embodiment will be described with reference to Figures 6 and 7. The following description will focus on differences from the first embodiment. Figures 6 and 7 show cross sections of the multilayer ceramic capacitor 1 taken along a plane parallel to a length direction 100 and a height direction 101.

[0107] The multilayer ceramic capacitor 1 shown in Fig. 6 will be described. The ceramic capacitor 1 shown in Fig. 6 differs from the multilayer ceramic capacitor 1 shown in Fig. 5 in the arrangement of the spacer portions. In the multilayer ceramic capacitor 1 shown in Fig. 5, two spacer portions, a first spacer portion 70 and a second spacer portion 71, are arranged on the first main surface 10 side. In the multilayer ceramic capacitor 1 shown in Fig. 6, in addition to the two spacer portions on the first main surface 10 side, a third spacer portion 72 and a fourth spacer portion 73 are arranged on the second main surface 11 side.

[0108] 6, the first external electrode 40 has a first base electrode layer 42, a first spacer portion 70 made of plated metal and disposed on the first main surface band portion 51, and a third spacer portion 72 made of plated metal and disposed on the third main surface band portion 52. In the multilayer ceramic capacitor 1 shown in FIG. 6, the second external electrode 41 has a second base electrode layer 45, a second spacer portion 71 made of plated metal and disposed on the second main surface band portion 56, and a fourth spacer portion 73 made of plated metal and disposed on the fourth main surface band portion 57.

[0109] The multilayer ceramic capacitor 1 shown in Fig. 6 has the effect of facilitating mounting in addition to the effect of suppressing solder wetting that the multilayer ceramic capacitor 1 shown in Fig. 5 has. Spacer portions are arranged on two surfaces, the first main surface 10 side and the second main surface 11 side. This makes it easy to align the orientation of the multilayer ceramic capacitor 1 when mounting the multilayer ceramic capacitor 1 on a mounting board.

[0110] The multilayer ceramic capacitor 1 shown in FIG. 7 will be described. The multilayer ceramic capacitor 1 shown in FIG. 7 differs from the multilayer ceramic capacitor 1 shown in FIG. 6 in the arrangement of the insulating layers on the first main surface 10 side and the second main surface 11 side. In the multilayer ceramic capacitor 1 shown in FIG. 6, the first insulating layer 110 and the second insulating layer 120 are connected on the first main surface 10 and the second main surface 11. Insulating layer connecting portions 131 are provided on the first main surface 10 and the second main surface 11. In the multilayer ceramic capacitor 1 shown in FIG. 6, the main surfaces are covered with external electrodes or insulating layers.

[0111] 7, the first principal surface 10 and the second principal surface 11 have exposed portions that are not covered with an insulating layer. The portions of the insulating layer that cover the exposed principal surfaces on the surface of the multilayer ceramic capacitor 1 are called insulating layer principal surface portions 132. As shown in FIG. 3, the insulating layer principal surface portions 132 cover the ends 48 of the external electrodes.

[0112] As in the multilayer ceramic capacitor 1 shown in FIG. 7, by providing an area on the surface of the multilayer ceramic capacitor 1 where no insulating layer is provided, it is possible to reduce the cost related to the material of the insulating layer.

[0113] The shape, material, dimensions, etc. of the spacer portion of the second embodiment can be the same as those of the spacer portion of the first embodiment.

[0114] (Modifications of External Electrodes) Modifications of external electrodes will be described with reference to Figs. 8 to 10. Figs. 8 to 10 are diagrams showing modifications of external electrodes. Fig. 8 is a diagram corresponding to Fig. 2. Fig. 9 is a diagram corresponding to Fig. 3. Fig. 10 is a diagram corresponding to Fig. 4. In the description of the above embodiment, the external electrodes are configured by base electrodes. The external electrodes may include a plating layer in addition to the base electrode. Furthermore, the external electrodes may include multiple plating layers.

[0115] 8 to 10 , the first external electrode 40 includes a first plating layer 43 and a second plating layer 44, and the second external electrode 41 includes a third plating layer 46 and a fourth plating layer 47. In the first external electrode 40, the first base electrode layer 42, the first plating layer 43, and the second plating layer 44 are laminated in this order from the laminate 2. In the second external electrode 41, the second base electrode layer 45, the third plating layer 46, and the fourth plating layer 47 are laminated in this order from the laminate 2.

[0116] The first plating layer 43 and the third plating layer 46 may be nickel plating layers, and the second plating layer 44 and the fourth plating layer 47 may be tin plating layers.

[0117] By including a plating layer in the external electrodes, the surfaces of the external electrodes that are not covered with the insulating layer or the spacer portion can be prevented from deteriorating due to oxidation or corrosion.

[0118] The multilayer ceramic capacitor 1 of each embodiment achieves the following advantages. Generally, solder has good wettability to metals but relatively poor wettability to glass. Therefore, solder wets a plating layer better than a base electrode layer. In the present invention, by disposing a spacer portion on the main-surface band portion and configuring it with a plated metal, a plating layer is formed on the first main surface or the first and second main surfaces. Therefore, during mounting, solder wets onto the spacer portion disposed on the main-surface band portion, but the connection portion and side band portion are physically separated from the mounting surface, making it difficult for solder to wet onto them. Therefore, in the present invention, solder wets onto the connection portion and side band portion less easily, thereby preventing an increase in the height of solder wet-up in the vertical direction during mounting and reducing the occurrence of squeal noise. Furthermore, when the spacer portion is configured as a plating layer, no additional process is required, thereby preventing the manufacturing process from becoming complicated and the associated increase in manufacturing costs.

[0119] Furthermore, in the present invention, by disposing an insulating layer on the external electrodes, particularly on the connection portions of the base electrode layer and the side band portions, it is possible to more reliably prevent the solder from wetting up onto the connection portions of the base electrode layer and the side band portions during mounting. Therefore, in the present invention, it is possible to more reliably prevent the height of the solder wetting up onto the connection portions of the base electrode layer and the side band portions in the height direction from increasing, thereby reducing the occurrence of squealing.

[0120] Although the present invention has been described above as an embodiment, it is not limited to the above-described embodiment, and various changes, modifications, and combinations are possible.

[0121] In the above description, the multilayer ceramic electronic component is a multilayer ceramic capacitor. The multilayer ceramic electronic component is not limited to a multilayer ceramic capacitor. When a piezoelectric ceramic is used in the laminate, the multilayer ceramic electronic component functions as a ceramic piezoelectric element. An example of the piezoelectric ceramic material is a lead zirconate titanate-based ceramic material.

[0122] When a semiconducting ceramic is used in the laminate, the laminated ceramic electronic component functions as a thermistor element. An example of a semiconducting ceramic material is a spinel-based ceramic material.

[0123] When a magnetic ceramic is used in the laminate, the multilayer ceramic electronic component functions as an inductor element. When the multilayer ceramic electronic component functions as an inductor element, the internal electrodes become coil-shaped conductors. An example of a magnetic ceramic material is a ferrite ceramic material.

[0124] <1> A laminate including a plurality of dielectric layers stacked together, the laminate having first and second main surfaces opposing each other in a height direction, first and second side surfaces opposing each other in a width direction perpendicular to the height direction, first end surfaces and second end surfaces opposing each other in a length direction perpendicular to the height direction and the width direction, first internal electrodes stacked alternately with the plurality of dielectric layers and exposed at the first end surfaces, and second internal electrodes stacked alternately with the plurality of dielectric layers and exposed at the second end surfaces; a first external electrode connected to the first internal electrodes; and a second external electrode connected to the second internal electrodes, the first external electrode having a first connection portion arranged on the first end surface, a first main surface band portion arranged on the first main surface, a third main surface band portion arranged on the second main surface, a first side surface band portion arranged on a portion of the first side surface, a third side surface band portion arranged on a portion of the second side surface, and a first spacer portion arranged on the first main surface band portion, The second external electrode is a laminated ceramic electronic component having: a second connection portion arranged on the second end face; a second main surface band portion arranged on the first main surface; a fourth main surface band portion arranged on the second main surface; a second side surface band portion arranged on a portion of the first side surface; a fourth side surface band portion arranged on a portion of the second side surface; and a second spacer portion arranged on the second main surface band portion, wherein the first spacer portion and the second spacer portion are made of a conductive material; and the laminated ceramic electronic component has: a first insulating layer continuously covering the first connection portion, the first side surface band portion, and the third side surface band portion; and a second insulating layer continuously covering the second connection portion, the second side surface band portion, and the fourth side surface band portion.

[0125] <2> The multilayer ceramic electronic component according to <1>, wherein the dimension of the first spacer portion in the height direction is 5 μm or more and 25 μm or less, and the dimension of the second spacer portion in the height direction is 5 μm or more and 25 μm or less.

[0126] <3> The multilayer ceramic electronic component according to <1> or <2>, wherein the first insulating layer further covers the first main surface band portion, at least a portion of the first main surface, the third main surface band portion, and at least a portion of the second main surface, and the second insulating layer further covers the second main surface band portion, at least a portion of the first main surface, the fourth main surface band portion, and at least a portion of the second main surface.

[0127] <4> The multilayer ceramic electronic component according to any one of <1> to <3>, wherein a difference in dimension in the height direction between the first spacer portion and the first insulating layer is −15 μm or more and 24 μm or less, and a difference in dimension in the height direction between the second spacer portion and the second insulating layer is −15 μm or more and 24 μm or less.

[0128] <5> The multilayer ceramic electronic component according to any one of <1> to <4>, wherein the first insulating layer contains at least one of alumina, silica, glass, ceramic, and thermosetting resin, and the second insulating layer contains at least one of alumina, silica, glass, ceramic, and thermosetting resin.

[0129] <6> The multilayer ceramic electronic component according to any one of <1> to <5>, wherein the first spacer portion includes: a first nickel plating layer containing nickel and connected to the first main surface band portion; and a first tin plating layer containing tin and covering the first nickel plating layer; and the second spacer portion includes: a second nickel plating layer containing nickel and connected to the second main surface band portion; and a second tin plating layer containing tin and covering the second nickel plating layer.

[0130] <7> The multilayer ceramic electronic component according to any one of <1> to <6>, further comprising: a third spacer portion arranged on the third main surface band portion and made of a conductive material; and a fourth spacer portion arranged on the fourth main surface band portion and made of a conductive material.

[0131] <8> The multilayer ceramic electronic component according to <7>, wherein the dimension of the third spacer portion in the height direction is 5 μm or more and 25 μm or less, and the dimension of the fourth spacer portion in the height direction is 5 μm or more and 25 μm or less.

[0132] <9> The multilayer ceramic electronic component according to any one of <1> to <8>, wherein the first insulating layer further covers the first main surface band portion, at least a part of the first main surface, the third main surface band portion, and at least a part of the second main surface; and the second insulating layer further covers the second main surface band portion, at least a part of the first main surface, the fourth main surface band portion, and at least a part of the second main surface.

[0133] <10> The multilayer ceramic electronic component according to any one of <7> to <9>, wherein a difference in dimension in the height direction between the third spacer portion and the first insulating layer is −15 μm or more and 24 μm or less, and a difference in dimension in the height direction between the fourth spacer portion and the second insulating layer is −15 μm or more and 24 μm or less.

[0134] <11> The multilayer ceramic electronic component according to any one of <1> to <10>, wherein the first insulating layer contains at least one of alumina, silica, glass, ceramic, and thermosetting resin, and the second insulating layer contains at least one of alumina, silica, glass, ceramic, and thermosetting resin.

[0135] <12> The multilayer ceramic electronic component according to any one of <7> to <11>, wherein the third spacer portion has: a third nickel plating layer containing nickel as a plating metal and connected to the third main surface band portion; and a third tin plating layer containing tin as a plating metal and covering the third nickel plating layer; and the fourth spacer portion has: a fourth nickel plating layer containing nickel as a plating metal and connected to the fourth main surface band portion; and a fourth tin plating layer containing tin as a plating metal and covering the fourth nickel plating layer.

[0136] <13> The multilayer ceramic electronic component according to any one of <1> to <12>, wherein the first spacer portion and the second spacer portion are formed by metal plating.

[0137] <14> The multilayer ceramic electronic component according to any one of <7> to <13>, wherein the third spacer portion and the fourth spacer portion are formed by metal plating.

[0138] <15> The multilayer ceramic electronic component according to any one of <1> to <14>, wherein the first external electrode includes a first base electrode layer containing a conductive metal and glass, and the second external electrode includes a second base electrode layer containing a conductive metal and glass.

[0139] <16> The multilayer ceramic electronic component according to <15>, wherein the first external electrode includes a first plating layer and a second plating layer, the second external electrode includes a third plating layer and a fourth plating layer, the first base electrode layer, the first plating layer, and the second plating layer are stacked in this order on the laminate, the second base electrode layer, the third plating layer, and the fourth plating layer are stacked in this order on the laminate, the first plating layer and the third plating layer are nickel plating layers, and the second plating layer and the fourth plating layer are tin plating layers.

[0140] REFERENCE SIGNS LIST 1 Multilayer ceramic capacitor (multilayer ceramic electronic component) 40 First external electrode 41 Second external electrode 51 First main surface band portion 53 First side surface band portion 54 Third side surface band portion 55 Second connecting portion 56 Second main surface band portion 58 Second side surface band portion 59 Fourth side surface band portion 70 First spacer portion 71 Second spacer portion 110 First insulating layer 120 Second insulating layer

Claims

1. A laminated ceramic electronic component comprising a plurality of laminated dielectric layers, having a first main surface and a second main surface facing each other in a height direction, a first side surface and a second side surface facing each other in a width direction orthogonal to the height direction, a first end surface and a second end surface facing each other in a length direction orthogonal to the height direction and the width direction, a first internal electrode laminated alternately with the plurality of dielectric layers and exposed on the first end surface, and a second internal electrode laminated alternately with the plurality of dielectric layers and exposed on the second end surface; a first external electrode connected to the first internal electrode; and a second external electrode connected to the second internal electrode. The first external electrode has a first connection portion disposed on the first end surface, a first main surface band portion disposed on the first main surface, a third main surface band portion disposed on the second main surface, a first side surface band portion disposed on a part of the first side surface, a third side surface band portion disposed on a part of the second side surface, and a first spacer portion disposed on the first main surface band portion. The second external electrode has a second connection portion disposed on the second end surface, a second main surface band portion disposed on the first main surface, a fourth main surface band portion disposed on the second main surface, a second side surface band portion disposed on a part of the first side surface, a fourth side surface band portion disposed on a part of the second side surface, and a second spacer portion disposed on the second main surface band portion. The first spacer portion and the second spacer portion are made of a conductive material. The laminated ceramic electronic component further has a first insulating layer that continuously covers the first connection portion, the first side surface band portion, and the third side surface band portion, and a second insulating layer that continuously covers the second connection portion, the second side surface band portion, and the fourth side surface band portion.

2. The laminated ceramic electronic component according to claim 1, wherein the dimension of the first spacer portion in the height direction is 5 μm or more and 25 μm or less, and the dimension of the second spacer portion in the height direction is 5 μm or more and 25 μm or less.

3. The first insulating layer further covers the first main surface band portion, at least a part of the first main surface, the third main surface band portion, and at least a part of the second main surface. The second insulating layer further covers the second main surface band portion, at least a part of the first main surface, the fourth main surface band portion, and at least a part of the second main surface. The multilayer ceramic electronic component according to claim 1 or 2.

4. The difference in the dimension in the height direction between the first spacer portion and the first insulating layer is -15 μm or more and 24 μm or less. The difference in the dimension in the height direction between the second spacer portion and the second insulating layer is -15 μm or more and 24 μm or less. The multilayer ceramic electronic component according to any one of claims 1 to 3.

5. The first insulating layer contains at least one or more of alumina, silica, glass, ceramic, and thermosetting resin. The second insulating layer contains at least one or more of alumina, silica, glass, ceramic, and thermosetting resin. The multilayer ceramic electronic component according to any one of claims 1 to 4.

6. The first spacer portion includes a first nickel plating layer containing nickel and connected to the first main surface band portion, and a first tin plating layer containing tin and covering the first nickel plating layer. The second spacer portion includes a second nickel plating layer containing nickel and connected to the second main surface band portion, and a second tin plating layer containing tin and covering the second nickel plating layer. The multilayer ceramic electronic component according to any one of claims 1 to 5.

7. Further comprising a third spacer portion disposed on the third main surface band portion and made of a conductive material, and a fourth spacer portion disposed on the fourth main surface band portion and made of a conductive material. The multilayer ceramic electronic component according to any one of claims 1 to 6.

8. The dimension in the height direction of the third spacer portion is 5 μm or more and 25 μm or less. The dimension in the height direction of the fourth spacer portion is 5 μm or more and 25 μm or less. The multilayer ceramic electronic component according to claim 7.

9. The first insulating layer further covers the first main surface band portion, at least a part of the first main surface, the third main surface band portion, and at least a part of the second main surface. The second insulating layer further covers the second main surface band portion, at least a part of the first main surface, the fourth main surface band portion, and at least a part of the second main surface. The multilayer ceramic electronic component according to any one of claims 1 to 8.

10. The difference in the dimension in the height direction between the third spacer portion and the first insulating layer is -15 μm or more and 24 μm or less. The difference in the dimension in the height direction between the fourth spacer portion and the second insulating layer is -15 μm or more and 24 μm or less. The multilayer ceramic electronic component according to any one of claims 7 to 9.

11. The first insulating layer contains at least one of alumina, silica, glass, ceramic, and thermosetting resin. The second insulating layer contains at least one of alumina, silica, glass, ceramic, and thermosetting resin. The multilayer ceramic electronic component according to any one of claims 1 to 10.

12. The third spacer portion includes a third nickel plating layer containing nickel as a plating metal and connected to the third main surface band portion, and a third tin plating layer containing tin as a plating metal and covering the third nickel plating layer. The fourth spacer portion includes a fourth nickel plating layer containing nickel as a plating metal and connected to the fourth main surface band portion, and a fourth tin plating layer containing tin as a plating metal and covering the fourth nickel plating layer. The multilayer ceramic electronic component according to any one of claims 7 to 11.

13. The first spacer portion and the second spacer portion are formed of metal plating. The multilayer ceramic electronic component according to any one of claims 1 to 12.

14. The third spacer portion and the fourth spacer portion are formed of metal plating. The multilayer ceramic electronic component according to any one of claims 7 to 13.

15. The first external electrode includes a first base electrode layer containing a conductive metal and glass, and the second external electrode includes a second base electrode layer containing a conductive metal and glass. The multilayer ceramic electronic component according to any one of claims 1 to 14.

16. The first external electrode includes a first plating layer and a second plating layer, and the second external electrode includes a third plating layer and a fourth plating layer. The first base electrode layer, the first plating layer, and the second plating layer are laminated in this order from the laminate, and the second base electrode layer, the third plating layer, and the fourth plating layer are laminated in this order from the laminate. The first plating layer and the third plating layer are nickel plating layers, and the second plating layer and the fourth plating layer are tin plating layers. The multilayer ceramic electronic component according to claim 15.

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