Multilayer ceramic capacitor

Abstract

Provided is a multilayer ceramic capacitor capable of achieving miniaturization and thinning while suppressing dielectric breakdown in the vicinity of an outer layer part and reduction in capacitance.　A multilayer ceramic capacitor 1 comprising: an inner layer part 100 including a plurality of inner layer dielectric layers 20i and a plurality of inner electrode layers 30; and outer layer parts 200 sandwiching the inner layer part 100 in the lamination direction T, wherein, when a portion between an inner electrode layer 30 that is the first layer positioned at the center in the lamination direction T, and an inner electrode layer 30 that is the fifth layer from said inner electrode layer toward the corresponding outer layer part 200 is defined as a region A, and a portion between an inner electrode layer 30 that is the first layer on the side of the outermost layer part 200, and an inner electrode layer 30 that is the second layer from said inner electrode layer 30 toward the center in the lamination direction T is defined as a region B, the standard deviation of the ceramic grain diameter in the region A is larger than that in the region B.

Description

Multilayer ceramic capacitors

[0001] The present invention relates to a multilayer ceramic capacitor.

[0002] As electronic devices become smaller and thinner, there has been a demand for smaller and thinner multilayer ceramic capacitors to be mounted in the electronic devices. To achieve this, it is necessary to make the dielectric layers thinner.

[0003] However, thinning the dielectric layers increases the possibility of dielectric breakdown between the internal electrode layers that sandwich the dielectric layers. Also, excessively small dielectric particles that make up the dielectric layers may result in a decrease in the relative permittivity.

[0004] For this reason, there is known a capacitor, such as that disclosed in Patent Document 1, in which the average particle size of the dielectric particles in the portion of the multilayer ceramic capacitor that forms the capacitance is made smaller than the average particle size of the dielectric particles in other regions surrounding the portion that forms the capacitance, thereby suppressing the decrease in the dielectric constant and reducing the decrease in capacitance.

[0005] Japanese Patent Application Laid-Open No. 2019-179928

[0006] However, in the configuration described in Patent Document 1, the average particle size of the dielectric particles in the entire portion that forms the capacitance of the multilayer ceramic capacitor is manipulated, and this alone is insufficient to suppress dielectric breakdown near the outer layer portion where failure is likely to occur.

[0007] An object of the present invention is to provide a multilayer ceramic capacitor that can be made smaller and thinner while suppressing dielectric breakdown near the outer layer portions where failures are likely to occur and a decrease in capacitance.

[0008] The present inventors discovered that by adjusting the standard deviation of the ceramic grain diameter of the inner dielectric layers that constitute the inner layer portions of a multilayer ceramic capacitor, it is possible to suppress dielectric breakdown near the outer layer portions and a decrease in capacitance even when the inner dielectric layers are made thin, and have completed the present invention.

[0009] That is, the present invention provides a laminate including an inner layer portion including a plurality of inner dielectric layers and a plurality of internal electrode layers alternately stacked in a stacking direction, and outer layer portions sandwiching the inner layer portion from the stacking direction, the laminate having a first main surface and a second main surface opposing each other in the stacking direction, a first side surface and a second side surface opposing each other in a width direction perpendicular to the stacking direction, and a first end surface and a second end surface opposing each other in a length direction perpendicular to the stacking direction and the width direction; and a pair of external electrodes arranged at both ends in the length direction of the laminate so as to cover at least the first end surface and the second end surface, respectively, and connected to the internal electrode layers, wherein a region between an internal electrode layer located at the center in the stacking direction and an internal electrode layer that is a fifth layer from the first internal electrode layer toward the outer layer portion is defined as region A, When a region between the internal electrode layer located on the outermost layer side among the plurality of internal electrode layers and the internal electrode layer that is the second layer toward the center in the stacking direction, with the first internal electrode layer being the first layer, is defined as region B, the multilayer ceramic capacitor has a larger standard deviation of ceramic grain diameters of the internal dielectric layers in region A than the standard deviation of ceramic grain diameters of the internal dielectric layers in region B.

[0010] According to the present invention, it is possible to provide a multilayer ceramic capacitor that can suppress dielectric breakdown near the outer layer portions, where failures are likely to occur, and a decrease in capacitance, even when the inner dielectric layers are thin.

[0011] 1 is a perspective view showing a multilayer ceramic capacitor according to a first embodiment; FIG. 2 is a cross-sectional view (LT cross-section) of the multilayer ceramic capacitor shown in FIG. 1 taken along line II-II; FIG. 3 is a cross-sectional view (WT cross-section) of the multilayer ceramic capacitor shown in FIG. 1 taken along line III-III; FIG. 4 is a schematic view showing the structure of an inner layer portion of the multilayer ceramic capacitor shown in FIG. 1; FIG. 5 is a diagram showing the state of ceramic grains in each region ((a) region A, (b) region B); FIG. 6 is a perspective view showing a multilayer ceramic capacitor according to a second embodiment; FIG. 7 is a schematic view showing the structure of an inner layer portion of the multilayer ceramic capacitor shown in FIG.

[0012] Hereinafter, embodiments of the multilayer ceramic capacitor of the present invention will be described, but the present invention is not limited thereto. Furthermore, the drawings may be drawn in a simplified and schematic manner to explain the contents of the invention, and the dimensional ratios of the depicted components or between the components may not match the dimensional ratios of those components described in the specification. Furthermore, components described in the specification may be omitted in the drawings, or the number of components may be omitted.

[0013] (Multilayer Ceramic Capacitor) Fig. 1 is a perspective view showing a multilayer ceramic capacitor (first embodiment), Fig. 2 is a cross-sectional view of the multilayer ceramic capacitor shown in Fig. 1 taken along line II-II, and Fig. 3 is a cross-sectional view of the multilayer ceramic capacitor shown in Fig. 1 taken along line III-III. Fig. 4 is a schematic view showing the structure of an inner layer portion of the multilayer ceramic capacitor shown in Fig. 1. The multilayer ceramic capacitor 1 shown in Figs. 1 to 4 includes a laminate 10 and external electrodes 40. The external electrodes 40 include a first external electrode 41 and a second external electrode 42.

[0014] 1 to 3 show an XYZ Cartesian coordinate system. The X direction is the length direction L of the multilayer ceramic capacitor 1 and the laminate 10, the Y direction is the width direction W of the multilayer ceramic capacitor 1 and the laminate 10, and the Z direction is the lamination direction T of the multilayer ceramic capacitor 1 and the laminate 10. Therefore, the cross section shown in FIG. 2 is also referred to as an LT cross section, and the cross section shown in FIG. 3 is also referred to as a WT cross section.

[0015] The length direction L, width direction W, and stacking direction T do not necessarily have to be perpendicular to each other, and may intersect each other.

[0016] (Laminate) The laminate 10 has a substantially rectangular parallelepiped shape, and has a first main surface TS1 and a second main surface TS2 facing in the stacking direction T, a first side surface WS1 and a second side surface WS2 facing in the width direction W, and a first end surface LS1 and a second end surface LS2 facing in the length direction L. The surface of each surface may be uneven or may be roughened.

[0017] It is preferable that the corners and ridges of the laminate 10 are rounded. A corner is a portion where three surfaces of the laminate 10 intersect, and a ridge is a portion where two surfaces of the laminate 10 intersect.

[0018] 2 and 3 , the laminate 10 has a plurality of inner dielectric layers 20i and a plurality of internal electrode layers 30 stacked in a stacking direction T. The laminate 10 also has, in the stacking direction T, an inner layer portion 100, and a first outer layer portion 201 and a second outer layer portion 202 arranged to sandwich the inner layer portion 100.

[0019] The inner dielectric layer 20i constituting the inner layer portion 100 and the outer dielectric layer 20o constituting the outer layer portion 200 may have different component compositions because the inner layer portion 100 and the outer layer portion 200 are required to have different functions. For example, the inner dielectric layer 20i is required to have a high dielectric constant, while the outer dielectric layer 20o is required to have high moisture resistance, facing property, and strength. For this reason, the dielectric layer constituting the inner layer portion 100 will be referred to as the inner dielectric layer 20i, and the dielectric layer constituting the outer layer portion 200 will be referred to as the outer dielectric layer 20o. However, when there is no need to particularly distinguish between the inner dielectric layer 20i and the outer dielectric layer 20o, they will be collectively referred to as the dielectric layer 20.

[0020] (Inner Layer Portion) The inner layer portion 100 includes a plurality of inner dielectric layers 20i and a plurality of internal electrode layers 30. In the inner layer portion 100, the plurality of internal electrode layers 30 are arranged opposite each other with the inner dielectric layers 20i interposed therebetween. The inner layer portion 100 is a portion that generates electrostatic capacitance and essentially functions as a capacitor.

[0021] The material of the dielectric layer 20 is, for example, BaTiO ３ , CaTiO ３ , SrTiO ３ , or CaZrO ３ A dielectric ceramic containing, as a main component, a Mn compound, an Fe compound, a Cr compound, a Co compound, a Ni compound, or the like may be added as a secondary component to the material of the dielectric layer 20.

[0022] The thickness of the inner dielectric layer 20i is not particularly limited, but is preferably 0.30 μm or more and 0.45 μm or less, for example. By reducing the thickness of the inner dielectric layer 20i, the capacitance can be improved.

[0023] (Outer Layer Portions) The first outer layer portion 201 is disposed on the first main surface TS1 side of the laminate 10, and the second outer layer portion 202 is disposed on the second main surface TS2 side of the laminate 10. More specifically, the first outer layer portion 201 is disposed between the first main surface TS1 and an internal electrode layer 30 of the plurality of internal electrode layers 30 that is closest to the first main surface TS1, and the second outer layer portion 202 is disposed between the second main surface TS2 and an internal electrode layer 30 of the plurality of internal electrode layers 30 that is closest to the second main surface TS2. The first outer layer portion 201 and the second outer layer portion 202 do not include the internal electrode layer 30.

[0024] The outer layer portion 200 is formed of an insulating material. The first outer layer portion 201 and the second outer layer portion 202 can each be composed of multiple outer dielectric layers 20o, or may be composed of a single outer dielectric layer 20o. The outer dielectric layer 20o can be composed of the same type of dielectric material as the inner dielectric layer 20i, but may contain a different component from the inner dielectric layer 20i depending on the desired function. Furthermore, the outer layer portion 200 can be coated with a DLC film and can be formed of a different insulating material, such as an insulating resin.

[0025] The multiple internal electrode layers 30 include multiple first internal electrode layers 31 and multiple second internal electrode layers 32. The multiple first internal electrode layers 31 and the multiple second internal electrode layers 32 are alternately arranged in the stacking direction T of the laminate 10.

[0026] The first internal electrode layer 31 includes a first opposing electrode portion 311 and a first lead electrode portion 312 , and the second internal electrode layer 32 includes a second opposing electrode portion 321 and a second lead electrode portion 322 .

[0027] The first opposing electrode portion 311 and the second opposing electrode portion 321 face each other via the inner dielectric layer 20i in the stacking direction T of the laminate 10. The shapes of the first opposing electrode portion 311 and the second opposing electrode portion 321 are not particularly limited and may be, for example, approximately rectangular. The first opposing electrode portion 311 and the second opposing electrode portion 321 are portions that generate electrostatic capacitance and essentially function as a capacitor.

[0028] The first extraction electrode portion 312 extends from the first opposing electrode portion 311 toward the first end surface LS1 of the laminate 10 and is exposed at the first end surface LS1. The second extraction electrode portion 322 extends from the second opposing electrode portion 321 toward the second end surface LS2 of the laminate 10 and is exposed at the second end surface LS2. The lengths in the width direction W of the first opposing electrode portion 311 and the first extraction electrode portion 312 may be the same or different. Furthermore, the lengths in the width direction W of these portions may gradually change toward the exposed first end surface LS1. The lengths in the width direction W of the second opposing electrode portion 321 and the second extraction electrode portion 322 may be the same or different. Furthermore, the lengths in the width direction W of these portions may gradually change toward the exposed second end surface LS2.

[0029] As a result, the first internal electrode layer 31 is connected to the first external electrode 41, and a gap is provided between the first internal electrode layer 31 and the second end surface LS2 of the laminate 10, i.e., the second external electrode 42. In addition, the second internal electrode layer 32 is connected to the second external electrode 42, and a gap is provided between the second internal electrode layer 32 and the first end surface LS1 of the laminate 10, i.e., the first external electrode 41.

[0030] The first internal electrode layer 31 and the second internal electrode layer 32 contain metal Ni as a main component. The first internal electrode layer 31 and the second internal electrode layer 32 may contain, as a main component or as a component other than the main component, at least one selected from metals such as Cu, Ag, Pd, Sn, or Au, or alloys containing at least one of these metals, such as an Ag-Pd alloy. Furthermore, the first internal electrode layer 31 and the second internal electrode layer 32 may contain, as a component other than the main component, particles of a dielectric material having the same composition as the ceramic contained in the inner dielectric layer 20i. In this specification, the term "main component metal" refers to the metal component with the highest weight percentage.

[0031] The thickness of the first internal electrode layer 31 and the second internal electrode layer 32 is not particularly limited, but is preferably 0.30 μm or more and 0.40 μm or less, and more preferably 0.30 μm or more and 0.35 μm or less. The number of the first internal electrode layer 31 and the second internal electrode layer 32 is also not particularly limited.

[0032] The thicknesses of the inner dielectric layers 20i and the internal electrode layers 30 may be measured by, for example, observing the LT cross section of the laminate exposed by polishing near the center in the width direction with a scanning electron microscope. Each value may be an average value of measurements taken at multiple locations in the length direction, or may be an average value of measurements taken at multiple locations in the stacking direction.

[0033] As shown in Fig. 3, the laminate 10 has, in the width direction W, an electrode facing portion W30 where the internal electrode layers 30 face each other, and a first side gap WG1 and a second side gap WG2 arranged to sandwich the electrode facing portion W30. The first side gap WG1 is located between the electrode facing portion W30 and the first side surface WS1, and the second side gap WG2 is located between the electrode facing portion W30 and the second side surface WS2. More specifically, the first side gap WG1 is located between the end of the internal electrode layer 30 on the first side surface WS1 side and the first side surface WS1, and the second side gap WG2 is located between the end of the internal electrode layer 30 on the second side surface WS2 side and the second side surface WS2. The first side gap WG1 and the second side gap WG2 do not include the internal electrode layer 30, but only include the dielectric layer 20. The first side gap WG1 and the second side gap WG2 are also called W gaps.

[0034] The first side gap WG1 and the second side gap WG2 may have Si segregation, which can improve the flexural strength of the multilayer ceramic capacitor.

[0035] 2 , the laminate 10 has, in the longitudinal direction L, an electrode facing portion L30 where the first internal electrode layer 31 and the second internal electrode layer 32 of the internal electrode layer 30 face each other, a first end gap LG1, and a second end gap LG2. The first end gap LG1 is located between the electrode facing portion L30 and the first end face LS1, and the second end gap LG2 is located between the electrode facing portion L30 and the second end face LS2. More specifically, the first end gap LG1 is located between the end of the second internal electrode layer 32 on the first end face LS1 side and the first end face LS1, and the second end gap LG2 is located between the end of the first internal electrode layer 31 on the second end face LS2 side and the second end face LS2. The first end gap LG1 does not include the second internal electrode layer 32 but includes the first internal electrode layer 31 and the inner dielectric layer 20i, while the second end gap LG2 does not include the first internal electrode layer 31 but includes the second internal electrode layer 32 and the inner dielectric layer 20i. The first end gap LG1 is a portion that functions as a lead electrode portion to the first end surface LS1 of the first internal electrode layer 31, and the second end gap LG2 is a portion that functions as a lead electrode portion to the second end surface LS2 of the second internal electrode layer 32. The first end gap LG1 and the second end gap LG2 are also referred to as L gaps.

[0036] The electrode opposing portion L30 is located with the first opposing electrode portion 311 of the first internal electrode layer 31 and the second opposing electrode portion 321 of the second internal electrode layer 32. The first end gap portion LG1 is located with the first lead-out electrode portion 312 of the first internal electrode layer 31, and the second end gap portion LG2 is located with the second lead-out electrode portion 322 of the second internal electrode layer 32.

[0037] The thickness of the laminate 10 can be measured, for example, by observing an LT cross section near the center of the width of the laminate exposed by polishing, or a WT cross section near the center of the length of the laminate exposed by polishing, using a scanning electron microscope. Each value may also be the average of measurements taken at multiple locations in the length or width direction. Similarly, the length of the laminate 10 can be measured, for example, by observing an LT cross section near the center of the width of the laminate exposed by polishing, using a scanning electron microscope. Each value may also be the average of measurements taken at multiple locations in the stacking direction. Similarly, the width of the laminate 10 can be measured, for example, by observing a WT cross section near the center of the length of the laminate exposed by polishing, using a scanning electron microscope. Each value may also be the average of measurements taken at multiple locations in the stacking direction.

[0038] The external electrodes 40 include a first external electrode 41 and a second external electrode 42 .

[0039] The first external electrode 41 is disposed on the first end face LS1 of the laminate 10 and is connected to the first internal electrode layer 31. The first external electrode 41 may extend from the first end face LS1 to a portion of the first main surface TS1 and a portion of the second main surface TS2. Alternatively, the first external electrode 41 may extend from the first end face LS1 to a portion of the first side surface WS1 and a portion of the second side surface WS2.

[0040] The second external electrode 42 is disposed on the second end face LS2 of the laminate 10 and is connected to the second internal electrode layer 32. The second external electrode 42 may extend from the second end face LS2 to a portion of the first main face TS1 and a portion of the second main face TS2. The second external electrode 42 may also extend from the second end face LS2 to a portion of the first side face WS1 and a portion of the second side face WS2.

[0041] The first external electrode 41 has a first base electrode layer 415 and a first plating layer 416, and the second external electrode 42 has a second base electrode layer 425 and a second plating layer 426. The first external electrode 41 may be composed of only the first plating layer 416, and the second external electrode 42 may be composed of only the second plating layer 426.

[0042] The first base electrode layer 415 and the second base electrode layer 425 may be fired layers containing a metal and glass. The glass may be a glass component containing at least one selected from B, Si, Ba, Mg, Al, Li, etc. A specific example is borosilicate glass. The metal may contain Cu as a main component. The metal may contain at least one selected from metals such as Ni, Ag, Pd, or Au, or alloys such as Ag-Pd alloys, as a main component or as a component other than the main component.

[0043] The fired layer is a layer formed by applying a conductive paste containing metal and glass to the laminate by a dipping method and firing the layer. The fired layer may be fired after firing the internal electrode layer or simultaneously with firing the internal electrode layer. The fired layer may also be a multi-layer structure.

[0044] Alternatively, the first base electrode layer 415 and the second base electrode layer 425 may be resin layers containing conductive particles and a thermosetting resin. The resin layers may be formed on the fired layer described above, or may be formed directly on the laminate without forming a fired layer.

[0045] The resin layer is a layer formed by applying a conductive paste containing conductive particles and a thermosetting resin to the laminate by a coating method and then firing the layer. The resin layer may be fired after firing the internal electrode layer or simultaneously with firing the internal electrode layer. The resin layer may also be a multi-layered layer.

[0046] The thickness of each of the first base electrode layer 415 and the second base electrode layer 425 as a fired layer or a resin layer is not particularly limited, and may be 1 μm or more and 10 μm or less.

[0047] Alternatively, the first base electrode layer 415 and the second base electrode layer 425 may be thin film layers of 1 μm or less formed by a thin film forming method such as sputtering or vapor deposition, on which metal particles are deposited.

[0048] First plating layer 416 covers at least a portion of first base electrode layer 415, and second plating layer 426 covers at least a portion of second base electrode layer 425. First plating layer 416 and second plating layer 426 include, for example, at least one selected from metals such as Cu, Ni, Ag, Pd, and Au, and alloys such as Ag—Pd alloys.

[0049] The first plating layer 416 and the second plating layer 426 may each be formed of multiple layers. Preferably, they have a two-layer structure of Ni plating and Sn plating. The Ni plating layer can prevent the base electrode layer from being eroded by solder when mounting the ceramic electronic component, and the Sn plating layer improves the wettability of the solder when mounting the ceramic electronic component, facilitating mounting. The first plating layer 416 and the second plating layer 426 may each have a three-layer structure, for example, by stacking Sn plating, Ni plating, and Sn plating. The outermost layer may be Au plating.

[0050] The thickness of each of first plating layer 416 and second plating layer 426 is not particularly limited, and may be 1 μm or more and 10 μm or less.

[0051] (Ceramic Grain Diameter) The ceramic grain diameter D50 of the inner dielectric layer in region B is preferably 80 nm or more and 150 nm or less. This allows the number of ceramic grains contained in the inner dielectric layer 20i to be increased, increasing the number of interfaces between the ceramic grains and improving high-temperature reliability.

[0052] (Standard Deviation) When a region between the internal electrode layer 30 located at the center of the stacking direction T and the internal electrode layer 30 corresponding to the fifth layer toward the outer layer portion 200 side, with the internal electrode layer 30 being the first layer, among the plurality of stacked internal electrode layers 30, is defined as region A, and a region between the internal electrode layer 30 located closest to the outer layer portion 200 side and the internal electrode layer 30 corresponding to the second layer toward the center of the stacking direction T, with the internal electrode layer 30 being the first layer, among the plurality of internal electrode layers 30, is defined as region B, the standard deviation σ of the ceramic grain diameter of the internal dielectric layer 20i in region A is Ａis the standard deviation σ of the ceramic grain diameter of the inner dielectric layer 20i in the region B. Ｂ is larger than (Figure 5).

[0053] The standard deviation σ of the ceramic grain diameter is measured using an SEM on a WT cross section at the center of the length direction L of the multilayer ceramic capacitor 1 or on an LT cross section at the center of the width direction W of the multilayer ceramic capacitor 1, and the standard deviation σ in region A is calculated from the ceramic grain diameters of the inner dielectric layers 20i in region A and region B. Ａ and the standard deviation σ in region B Ｂ can be calculated.

[0054] Standard deviation σ of grain diameter of the inner dielectric layer 20i in region A Ａ is the standard deviation σ of the grain diameter of the inner dielectric layer 20i in the region B. Ｂ By making it larger than , the proportion of ceramic grains with large particle diameters in the inner dielectric layer 20i near the center of the stacking direction T of the multilayer ceramic capacitor can be increased, thereby improving the capacitance while maintaining high-temperature reliability.

[0055] On the other hand, since region B is an area where failures are likely to occur, the standard deviation σ Ｂ The standard deviation of area A is σ Ａ By making the ceramic grains smaller and reducing the variation in the ceramic grain diameter, the number of ceramic grains in region B can be increased, thereby improving the high-temperature reliability.

[0056] Standard deviation σ of ceramic grain diameter of the inner dielectric layer 20i in region A Ａ The standard deviation σ of the ceramic grain diameter of the inner dielectric layer 20i in the region B is preferably 20 nm or more and 120 nm or less. Ｂ The thickness of the inner dielectric layer 20i in the region B may be thinner than that of the inner dielectric layer 20i in the region A in the stacking direction.

[0057] The standard deviation σ of the ceramic grain diameter of the inner dielectric layer in the region A Ａ and the standard deviation σ of the ceramic grain diameter of the inner dielectric layer in the region B.Ｂ The ratio of (σ Ａ / σ Ｂ ) is preferably 1.1 or more and 3.0 or less.

[0058] Further, region B is defined as a region between the internal electrode layer 30 located closest to the outer layer portion 200 among the plurality of stacked internal electrode layers 30 and the internal electrode layer 30 corresponding to the tenth layer toward the center of the stacking direction T, with the internal electrode layer 30 being the first layer, and the standard deviation σ of the ceramic grain diameter of the internal dielectric layer 20i in region A Ａ is the standard deviation σ of the ceramic grain diameter of the inner dielectric layer 20i in the region B. Ｂ When the capacitance is made larger than 100 kJ / cm 2 , it is possible to more reliably improve the capacitance and the high-temperature reliability.

[0059] (Manufacturing Method) Next, an example of a manufacturing method for the above-mentioned multilayer ceramic capacitor 1 will be described. A dielectric sheet for the dielectric layers 20 and a conductive paste for the internal electrode layers 30 are prepared. The dielectric sheet and the conductive paste contain a binder and a solvent. Known materials can be used as the binder and the solvent.

[0060] Since the dielectric sheets must be formed separately for the position corresponding to region A and the position corresponding to region B, an inner layer dielectric paste for region A and an inner layer dielectric paste for region B are used. The inner layer dielectric paste for region A is formed by mixing and compounding material a and material b, which have different ceramic grain diameters. For example, the inner layer dielectric paste for region A contains 1 to 50 vol% of material b, which has a ceramic grain diameter 10 to 20 nm or more larger than that of material a. In this case, if too much material b is compounded, or if the ceramic grain diameter of material b is too large, the average ceramic grain diameter D50 of all the materials contained in the inner layer dielectric paste for region A becomes large, and high-temperature reliability cannot be sufficiently improved. The dielectric paste for region B is compounded with a material with smaller ceramic grain diameter variation than the material compounded in the inner layer dielectric paste for region A. Thereafter, the region A inner layer dielectric paste and the region B inner layer dielectric paste are printed on the PET film, respectively, to form the region A inner layer dielectric sheet and the region B inner layer dielectric sheet.

[0061] Next, a conductive paste is printed on the dielectric sheet in a predetermined pattern, for example, to form an internal electrode pattern on the dielectric sheet. The internal electrode pattern can be formed by screen printing, gravure printing, or the like.

[0062] Next, a predetermined number of dielectric sheets for the second outer layer portion 202, on which no internal electrode pattern is printed, are stacked. Dielectric sheets for the inner layer portion 100, on which internal electrode patterns are printed, are stacked in sequence on top of these. A predetermined number of dielectric sheets for the first outer layer portion 201, on which no internal electrode pattern is printed, are stacked on top of these. In this way, a laminated sheet is produced.

[0063] Next, the laminated sheet is pressed in the stacking direction using a means such as a hydrostatic press to produce a laminated block. Next, the laminated block is cut to a predetermined size, and laminated chips are cut out. At this time, the corners and ridges of the laminated chip are rounded by barrel polishing or the like. Note that the laminated chip may be cut so that the internal electrode patterns are exposed on both side surfaces in the width direction W, and a covering dielectric sheet that becomes the first side gap portion WG1 and the second side gap portion WG2 is attached to cover both side surfaces.

[0064] Next, the laminated chip is fired to produce the laminate 10. The firing temperature depends on the materials of the dielectric and the internal electrodes, but is preferably 900° C. or higher and 1400° C. or lower.

[0065] Next, the first end surface LS1 of the laminate 10 is immersed in a conductive paste, which is an electrode material for the base electrode layer, using a dipping method, to apply a conductive paste for the first base electrode layer 415 to the first end surface LS1. Similarly, the second end surface LS2 of the laminate 10 is immersed in a conductive paste, which is an electrode material for the base electrode layer, using a dipping method, to apply a conductive paste for the second base electrode layer 425 to the second end surface LS2. These conductive pastes are then fired to form the first base electrode layer 415 and the second base electrode layer 425, which are fired layers. The firing temperature is preferably 600°C or higher and 900°C or lower.

[0066] As described above, the first base electrode layer 415 and the second base electrode layer 425, which are resin layers, may be formed by applying a conductive paste containing conductive particles and a thermosetting resin by a coating method and then firing it, or the first base electrode layer 415 and the second base electrode layer 425, which are thin films, may be formed by a thin film formation method such as a sputtering method or a vapor deposition method.

[0067] Thereafter, a first plating layer 416 is formed on the surface of the first base electrode layer 415 to form the first external electrode 41, and a second plating layer 426 is formed on the surface of the second base electrode layer 425 to form the second external electrode 42. Through the above steps, the multilayer ceramic capacitor 1 is obtained.

[0068] The present invention is not limited to the shape of the multilayer ceramic capacitor 1, and can be widely used as long as it has an inner layer portion 100 formed by laminating inner dielectric layers 20i and internal electrode layers 30.

[0069] For example, as shown in FIG. 6, there is a multilayer ceramic capacitor 1A having external electrodes 40a and 40b on the first side surface WS1 and the second side surface WS2 of the laminate 10, respectively, and having external electrodes 40c and 40d on the first end surface LS1 and the second end surface LS2 of the laminate 10, respectively.

[0070] 7, the inner layer portion 100 includes a plurality of inner dielectric layers 20i and a plurality of internal electrode layers 30. The inner layer portion 100 includes the internal electrode layer 30 located closest to the first principal surface TS1 to the internal electrode layer 30 located closest to the second principal surface TS2 in the stacking direction T. In the inner layer portion 100, the plurality of internal electrode layers 30 are arranged opposite each other with the inner dielectric layer 20i interposed therebetween.

[0071] The multiple internal electrode layers 30 include multiple first internal electrode layers 31 and multiple second internal electrode layers 32. The multiple first internal electrode layers 31 are arranged on the multiple inner dielectric layers 20i. The multiple second internal electrode layers 32 are arranged on the multiple inner dielectric layers 20i. The multiple first internal electrode layers 31 and the multiple second internal electrode layers 32 are arranged alternately in the stacking direction T of the laminate 10, with the inner dielectric layers 20i interposed between them. The first internal electrode layers 31 and the second internal electrode layers 32 are arranged so as to sandwich the inner dielectric layers 20i therebetween.

[0072] The first internal electrode layer 31 is connected to the external electrodes 40a, 40b on the first side surface WS1 and the second side surface WS2 of the laminate 10, and the second internal electrode layer 32 is connected to the external electrodes 40c, 40d on the first end surface LS1 and the second end surface LS2 of the laminate 10.

[0073] The multilayer ceramic capacitor 1A can be used as a three-terminal capacitor by dividing the power supply line or signal line in the circuit, connecting the external electrode 40c to one end of the divided line, connecting the external electrode 40d to the other end of the divided line, and connecting the external electrodes 40a and 40b to ground. In this case, the second internal electrode layer 32 serves as a through electrode, and the first internal electrode layer 31 serves as a ground electrode.

[0074] 8, there is also a multilayer ceramic capacitor 1B having four external electrodes 40a, 40b, 40c, and 40d. The internal layer portion 100 includes a plurality of internal dielectric layers 20i and a plurality of internal electrode layers 30. The internal layer portion 100 includes, in the stacking direction T, the internal electrode layer 30 located closest to the first main surface TS1 to the internal electrode layer 30 located closest to the second main surface TS2. In the internal layer portion 100, the multiple internal electrode layers 30 are arranged opposite each other with the internal dielectric layer 20i interposed therebetween.

[0075] The multiple internal electrode layers 30 include multiple first internal electrode layers 31 and multiple second internal electrode layers 32. The multiple first internal electrode layers 31 are arranged on the multiple inner dielectric layers 20i. The multiple second internal electrode layers 32 are arranged on the multiple inner dielectric layers 20i. The multiple first internal electrode layers 31 and the multiple second internal electrode layers 32 are arranged alternately in the stacking direction T of the laminate 10, with the inner dielectric layers 20i interposed between them. The first internal electrode layers 31 and the second internal electrode layers 32 are arranged so as to sandwich the inner dielectric layers 20i therebetween.

[0076] The first internal electrode layer 31 has a first opposing electrode portion 311 opposing the second internal electrode layer 32, a first lead portion 312A extending from the first opposing electrode portion 311 to the first end face LS1 and the first side face WS1, and a second lead portion 312B extending from the first opposing electrode portion 311 to the second end face LS2 and the second side face WS2. The first lead portion 312A is exposed at the first end face LS1 and the first side face WS1. The second lead portion 312B is exposed at the second end face LS2 and the second side face WS2.

[0077] The second internal electrode layer 32 has a second opposing electrode portion 321 opposing the first internal electrode layer 31, a first lead portion 322A extending from the second opposing electrode portion 321 to the second end face LS2 and the first side face WS1, and a second lead portion 322B extending from the second opposing electrode portion 321 to the first end face LS1 and the second side face WS2. The first lead portion 322A is exposed at the second end face LS2 and the first side face WS1. The second lead portion 322B is exposed at the first end face LS1 and the second side face WS2.

[0078] In this embodiment, the first opposing electrode portion 311 and the second opposing electrode portion 321 face each other via the inner dielectric layer 20i, thereby forming capacitance and exhibiting the characteristics of a capacitor.

[0079] Although the embodiments of the present invention have been described above, the present invention is not limited to the embodiments and can be embodied in various forms without departing from the spirit of the present invention. The present invention includes the following combinations.

[0080] <1> A laminate including an inner layer portion including a plurality of inner dielectric layers and a plurality of internal electrode layers alternately stacked in a stacking direction, and outer layer portions sandwiching the inner layer portion from the stacking direction, the laminate having a first main surface and a second main surface opposing each other in the stacking direction, a first side surface and a second side surface opposing each other in a width direction perpendicular to the stacking direction, and a first end surface and a second end surface opposing each other in a length direction perpendicular to the stacking direction and the width direction; and a pair of external electrodes arranged at both ends in the length direction of the laminate so as to cover at least the first end surface and the second end surface, respectively, and connected to the internal electrode layers, wherein a region A is defined as a region between an internal electrode layer located at the center in the stacking direction and an internal electrode layer that is a fifth layer from the first internal electrode layer toward the outer layer portion, When a region between the inner electrode layer located at the outermost layer side among the plurality of inner electrode layers and the inner electrode layer located at the second layer toward the center in the stacking direction, with the inner electrode layer being the first layer, is defined as region B, the standard deviation σ of the ceramic grain diameter of the inner dielectric layer in region A is Ａis the standard deviation σ of the ceramic grain diameter of the inner dielectric layer in the region B Ｂ <2> When a region between an internal electrode layer located on the outermost layer side among the plurality of internal electrode layers and an internal electrode layer that is a tenth layer toward the center in the stacking direction, counting the internal electrode layer as the first layer, is defined as region B, the standard deviation σ of the ceramic grain diameter of the internal dielectric layer in region A is larger than Ａ is the standard deviation σ of the ceramic grain diameter of the inner dielectric layer in the region B Ｂ <3> The multilayer ceramic capacitor according to <1>, wherein the standard deviation σ of the ceramic grain diameter of the inner dielectric layer in the region A is greater than or equal to Ａ and the standard deviation σ of the ceramic grain diameter of the inner dielectric layer in the region B. Ｂ The ratio of (σ Ａ / σ Ｂ <4> The multilayer ceramic capacitor according to any one of <1> to <3>, wherein the ceramic grain diameter D50 of the inner dielectric layer in the region B is 80 nm or more and 150 nm or less. <5> The multilayer ceramic capacitor according to any one of <1> to <4>, wherein the thickness of the inner dielectric layer in the stacking direction is 0.30 μm or more and 0.45 μm or less.

[0081] REFERENCE SIGNS LIST 1 Multilayer ceramic capacitor 10 Laminate 20 Dielectric layer 30 Internal electrode layer 31 First internal electrode layer 311 First opposing electrode portion 312 First lead electrode portion 32 Second internal electrode layer 321 Second opposing electrode portion 322 Second lead electrode portion 40 External electrode 41 First external electrode 415 First base electrode layer 416 First plating layer 42 Second external electrode 425 Second base electrode layer 426 Second plating layer 100 Internal layer portion 200 External layer portion 201 First external layer portion 202 Second external layer portion G Ceramic grain L30 Electrode opposing portion LG1 First end gap portion LG2 Second end gap portion W30 Electrode opposing portion WG1 First side gap portion WG2 Second side gap portion L Length direction T Stacking direction W Width direction LS1 First end face LS2 Second end face TS1 First main surface TS2 Second main surface WS1 First side surface WS2 Second side surface

Claims

1. A laminate including an inner layer portion including a plurality of inner dielectric layers and a plurality of internal electrode layers alternately laminated in a stacking direction, and an outer layer portion sandwiching the inner layer portion from the stacking direction, the laminate having a first main surface and a second main surface opposing each other in the stacking direction, a first side surface and a second side surface opposing each other in a width direction orthogonal to the stacking direction, and a first end surface and a second end surface opposing each other in a length direction orthogonal to the stacking direction and the width direction; a pair of external electrodes disposed at both ends in the length direction of the laminate so as to cover at least the first end surface and the second end surface, respectively, and connected to the internal electrode layers; among the plurality of internal electrode layers, a region between the internal electrode layer located at the center in the stacking direction and the internal electrode layer corresponding to the fifth layer toward the outer layer portion side with the internal electrode layer as the first layer is defined as region A; among the plurality of internal electrode layers, when a region between the internal electrode layer located on the outermost layer portion side and the internal electrode layer corresponding to the second layer toward the center in the stacking direction with the internal electrode layer as the first layer is defined as region B, the standard deviation σ Ａ of the ceramic grain diameter of the inner dielectric layer in region A Ｂ is larger than the standard deviation σ of the ceramic grain diameter of the inner dielectric layer in region B, a multilayer ceramic capacitor.

2. When a region between the internal electrode layer located on the outermost layer side among the plurality of internal electrode layers and the internal electrode layer corresponding to the tenth layer toward the center in the stacking direction with the internal electrode layer as the first layer is defined as region B, the standard deviation σ of the ceramic grain diameter of the inner dielectric layer in the region A Ａ is larger than the standard deviation σ of the ceramic grain diameter of the inner dielectric layer in the region B Ｂ The multilayer ceramic capacitor according to claim 1.

3. The standard deviation σ of the ceramic grain diameter of the inner dielectric layer within the region A Ａ and the standard deviation σ of the ceramic grain diameter of the inner dielectric layer within the region B Ｂ and the ratio (σ Ａ / σ Ｂ ) is 1.1 or more and 3.0 or less. The multilayer ceramic capacitor according to claim 1 or 2.

4. The ceramic grain diameter D50 of the inner dielectric layer within the region B is 80 nm or more and 150 nm or less. The multilayer ceramic capacitor according to any one of claims 1 to 3.

5. The thickness of the inner dielectric layer in the stacking direction is 0.30 μm or more and 0.45 μm or less. The multilayer ceramic capacitor according to any one of claims 1 to 4.

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