Multilayer ceramic capacitor

Abstract

Provided is a multilayer ceramic capacitor the size and thickness of which can be reduced and the humidity resistance of which can be improved. This multilayer ceramic capacitor 1 comprises: a laminate 2 having two main surfaces facing each other in the lamination direction, two end surfaces facing each other in the vertical direction intersecting the lamination direction, and two lateral surfaces facing each other in the horizontal direction intersecting the lamination direction and the vertical direction; and an external electrode 3 disposed on an end surface of the laminate 2. The laminate 2 includes an inner layer 11 and an outer layer 12 disposed so as to sandwich the inner layer 11 in the lamination direction. The inner layer 11 includes an internal electrode 15 and an internal dielectric layer 14. The outer layer 12 and the internal dielectric layer 14 include: barium titanate as a main component; and Si as a sub-component. In a gap region D, which is between the internal electrode 15 and the area from an end surface to a lateral surface, the Si skew of the internal dielectric layer is larger than the Si skew of the outer layer 12.

Description

Multilayer ceramic capacitors

[0001] The present invention relates to a multilayer ceramic capacitor.

[0002] Multilayer ceramic capacitors generally have inner layer sections in which internal electrodes and dielectric layers are alternately stacked. Outer layer sections are arranged on both sides of the inner layer sections in the stacking direction, and gap sections that do not contribute to capacitance formation are provided on the outer periphery of the effective layers that contribute to capacitance formation in the inner layer sections, in a direction perpendicular to the stacking direction. These outer layer sections and gap sections contribute to reliability such as moisture resistance.

[0003] In recent years, there has been a demand for multilayer ceramic capacitors to be smaller and thinner, while at the same time increasing their capacitance. However, there is a limit to how much the inner layers can be miniaturized because they contribute to capacitance. Therefore, in order to achieve overall miniaturization and thinning, efforts are being made to further thin the outer layers and gap areas.

[0004] However, thinning the outer layer and gap portions may result in a decrease in reliability, so there is a conventional technique in which an insulating layer is disposed to cover the outside of the outer layer (see Patent Document 1).

[0005] Japanese Patent Application Laid-Open No. 2023-113923

[0006] However, when an insulating layer is disposed so as to cover the outside of the outer layer portion as in the above-mentioned conventional technology, an additional step of disposing the insulating layer is required, and the thickness of the laminate increases by the amount of the insulating layer.

[0007] An object of the present invention is to provide a multilayer ceramic capacitor that can be made smaller and thinner and that can have improved moisture resistance.

[0008] In order to solve the above problems, the present invention provides a multilayer ceramic capacitor comprising: a laminate having two main surfaces opposing each other in a stacking direction, two end surfaces opposing each other in a vertical direction intersecting the stacking direction, and two side surfaces opposing each other in a horizontal direction intersecting the stacking direction and the vertical direction; and external electrodes arranged on the end surfaces of the laminate, wherein the laminate comprises inner layer portions and outer layer portions arranged to sandwich the inner layer portions in the stacking direction, the inner layer portions comprising inner electrodes and inner dielectric layers, the outer layer portions and the inner dielectric layers containing barium titanate as a main component and Si as a minor component, and wherein the strain of Si in the inner dielectric layers in gap regions between the internal electrodes and the end faces or the side faces is greater than the strain of Si in the outer layer portions.

[0009] According to the present invention, it is possible to provide a multilayer ceramic capacitor that can be made smaller and thinner and that can have improved moisture resistance.

[0010] 1. A schematic perspective view of a multilayer ceramic capacitor. 2. A cross-sectional view taken along line II-II in Figure 1. 3. A cross-sectional view taken along line III-III in Figure 1. 4. A schematic diagram of a mapping image of Si by WDX, where (a) shows the outer layer and (b) shows the gap region. 5. A formula showing how to calculate the skewness.

[0011] A multilayer ceramic capacitor 1 according to an embodiment of the present invention will now be described. Fig. 1 is a schematic perspective view of the multilayer ceramic capacitor 1. Fig. 2 is a cross-sectional view taken along line II-II in Fig. 1. Fig. 3 is a cross-sectional view taken along line III-III in Fig. 1.

[0012] (Multilayer ceramic capacitor 1) The multilayer ceramic capacitor 1 has a substantially rectangular parallelepiped shape and includes a laminate 2 and a pair of external electrodes 3 provided on both ends of the laminate 2. The laminate 2 includes an inner layer portion 11 in which a plurality of internal dielectric layers 14 and a plurality of internal electrodes 15 are laminated, and an outer layer portion 12.

[0013] In the following description, the direction in which the internal dielectric layers 14 and the internal electrodes 15 are stacked will be referred to as the stacking direction T, and the direction in which the pair of external electrodes 3 are arranged will be referred to as the longitudinal direction L. The direction that intersects with the stacking direction T and with the stacking direction T will be referred to as the transverse direction W. In the embodiment, the transverse direction W is perpendicular to both the longitudinal direction L and the stacking direction T.

[0014] (Laminate 2) In the following description, of the six outer peripheral surfaces of the laminate 2 shown in FIG. 2, a pair of outer peripheral surfaces facing each other in the stacking direction T will be referred to as the first main surface A1 and the second main surface A2, and when there is no need to particularly distinguish between the first main surface A1 and the second main surface A2, they will be collectively referred to as the main surface A.

[0015] A pair of outer peripheral surfaces facing each other in the horizontal direction W of the laminate 2 are referred to as a first side surface B1 and a second side surface B2, and when there is no need to particularly distinguish between the first side surface B1 and the second side surface B2, they will be collectively referred to as side surfaces B. A pair of outer peripheral surfaces facing each other in the vertical direction L of the laminate 2 are referred to as a first end surface C1 and a second end surface C2, and when there is no need to particularly distinguish between the first end surface C1 and the second end surface C2, they will be collectively referred to as end surfaces C.

[0016] It is preferable that both or either of the first and second principal surfaces A1, A2 be flat. If the principal surface A is flat, the stress received from the nozzle when picking up the multilayer ceramic capacitor 1 can be dispersed by the flat principal surface A, thereby improving the strength of the multilayer ceramic capacitor 1 during mounting. However, this is not limiting, and both the first and second principal surfaces A1, A2 of the laminate 2 may be roughened.

[0017] The intersection of two of the first main surface A1, the second main surface A2, the first end surface C1, the second end surface C2, the first side surface B1, and the second side surface B2 is called a ridge, and the intersection of three of these surfaces is called a corner. The ridges and corners are preferably rounded, as this rounding can prevent chipping and cracking. When the ridges and corners are rounded, the main surface may be flat on the surfaces excluding the corners and ridges.

[0018] (Inner Layer Portion 11) The inner layer portion 11 includes inner electrodes 15 and inner dielectric layers 14 alternately stacked with the inner electrodes 15.

[0019] (Internal electrode 15) The internal electrode 15 includes a first internal electrode 15A having one end exposed on the first end face C1 and a second internal electrode 15B having one end exposed on the second end face C2. The first internal electrodes 15A and the second internal electrodes 15B are alternately stacked.

[0020] The thickness of the internal electrode 15 is preferably 0.25 μm or more and 0.6 μm or less. The internal electrode 15 may be made of, but is not limited to, an appropriate conductive material, such as a metal such as Ni, Cu, Ag, Pd, or Au, or an alloy containing at least one of these metals, such as an Ag-Pd alloy. Furthermore, if the internal electrode 15 contains Sn, the electric field concentration at the interface between the internal electrode 15 and the internal dielectric layer 14 can be alleviated, leading to improved high-temperature load reliability. In this case, Sn can be sufficiently effective even if it is contained in only one of the internal electrodes 15, either the first internal electrode 15A or the second internal electrode 15B.

[0021] The first internal electrode 15A has a first opposing portion 15Aa opposing the second internal electrode 15B and a first lead portion 15Ab extending from the first opposing portion 15Aa onto the first end face C1. The second internal electrode 15B has a second opposing portion 15Ba opposing the first internal electrode 15A and a second lead portion 15Bb extending from the second opposing portion 15Ba onto the second end face C2.

[0022] The first opposing portion 15Aa and the second opposing portion 15Ba face each other, and a capacitance is formed between the first opposing portion 15Aa and the second opposing portion 15Ba, thereby causing the multilayer ceramic capacitor 1 to exhibit capacitor characteristics.

[0023] In addition, when it is not necessary to distinguish between the first opposing portion 15Aa and the second opposing portion 15Ba, they will be collectively referred to as opposing portion 15a. In addition, when it is not necessary to distinguish between the first drawn-out portion 15Ab and the second drawn-out portion 15Bb, they will be collectively referred to as drawn-out portion 15b.

[0024] (Internal Dielectric Layer 14) The internal dielectric layer 14 contains barium titanate as a main component and Si as a secondary component. The thickness of the internal dielectric layer 14 in the stacking direction T is 0.45 μm or less.

[0025] (Ceramic Grains) The internal dielectric layers 14 constituting the inner layer portion 11 of the multilayer ceramic capacitor 1 contain ceramic grains. The ceramic grain diameter D50 of the internal dielectric layers 14 is preferably 0.15 μm or less. This allows the number of ceramic grains contained in the internal dielectric layers 14 to be increased, increasing the number of interfaces between the ceramic grains and improving high-temperature reliability.

[0026] 3, the region between the internal electrode 15 and the side surface B in the internal layer portion 11 is referred to as a side gap region D1. As shown in FIG. 2, the region between the first internal electrode 15A and the second end face C2 and the region between the second internal electrode 15B and the first end face C1, i.e., the region in the internal layer portion 11 where the lead portion 15b exists in the stacking direction T, is referred to as a lead region D2. The side gap region D1 and the lead region D2 are collectively referred to as the gap region D.

[0027] (Si Content) In this embodiment, the Si content of the internal dielectric layer 14 located in the side gap region D1 and near the center in the stacking direction T is preferably 0.2 at % (atomic percent) or more and 5.0 at % or less.

[0028] If the Si content in the dielectric ceramic in the side gap region D1 is less than 0.2 at %, sintering will be difficult. However, in the present application, the Si content in the dielectric ceramic in the side gap region D1 is 0.2 at % or more, which improves the sinterability of the internal dielectric layer 14. This reduces the possibility that moisture will penetrate from the first side surface B1 and the second side surface B2, which are not covered by the external electrode 3, and reach the internal electrode 15, thereby improving moisture resistance.

[0029] Furthermore, if the Si content in the dielectric ceramic in the side gap region D1 is more than 5.0 at %, the capacitance reduction due to the decrease in the dielectric constant becomes significant, which is not preferable. However, in the present application, the Si content in the dielectric ceramic in the side gap region D1 is 5.0 at % or less, so the problem of capacitance reduction due to the decrease in the dielectric constant is unlikely to occur.

[0030] In the embodiment, the Si content of the internal dielectric layer 14 located near the center in the stacking direction T in the side gap region D1 is set to 0.2 at% or more and 5.0 at% or less, but this is not limited to this. As long as the Si content of the internal dielectric layer 14 located at least near the center in the stacking direction T in the side gap region D1 is 0.2 at% or more and 5.0 at% or less, it is possible to reduce the possibility of moisture penetrating from the first side surface B1 and the second side surface B2 that are not covered by the external electrode 3 and reaching the internal electrode 15.

[0031] The Si content can be measured as follows. For example, in the case of the side gap region D1, in the cross section near the center in the vertical direction L shown in Figure 3, a region P is defined as a φ1 μm region located 5 μm outward in the horizontal direction W (toward the side surface B) from the end of the internal electrode 15 at a position approximately halfway in the stacking direction T. The Si content is calculated from the X-ray intensity spectrum detected by a WDX (wavelength dispersive X-ray fluorescence analyzer) within this region P.

[0032] 4A and 4B are schematic diagrams of Si mapping images by WDX, in which Fig. 4A shows the outer layer portion 12 and Fig. 4B shows the side gap region D1. In this embodiment, the Si content of the outer layer portion 12 is lower than the Si content of the side gap region D1.

[0033] (Outer layer portion 12) The laminate 2 has an inner layer portion 11 and two outer layer portions 12 arranged to sandwich the inner layer portion 11 in the stacking direction T. Of the two outer layer portions 12, the outer layer portion 12 on the first main surface A1 side is referred to as the first outer layer portion 12a, and the outer layer portion 12 on the second main surface A2 side is referred to as the second outer layer portion 12b. The first outer layer portion 12a and the second outer layer portion 12b are each formed from an insulating material.

[0034] In the embodiment, the outer layer portion 12 contains barium titanate as a main component and Si and Mn as secondary components.

[0035] (Strain) In the embodiment, the strain of Si contained in the outer layer portion 12 and the internal dielectric layer 14 in the side gap region D1 is preferably 0 or more and 0.5 or less. This improves moisture resistance without adversely affecting high-temperature reliability. The possibility that moisture penetrates from the outer layer portion 12, the first side surface B1, and the second side surface B2 and reaches the internal electrode 15 can be reduced, thereby improving moisture resistance.

[0036] (Definition of Skewness) The skewness of Si was calculated using the following method. First, the cross section of the multilayer ceramic capacitor 1 was polished to the position shown in FIG. 3, and the detected intensity of Si in each square was measured using WDX. More specifically, the observation field of view, 5 μm square, was divided into 38 × 38 squares, and the Si content was measured from the X-ray intensity spectrum in each square. Then, the calculation formula shown in FIG. 4 was used to calculate the skewness of Si. The calculation formula shown in FIG. 4 can also be calculated automatically. The calculation formula shown in FIG. 4 represents the degree to which the distribution is distorted from a normal distribution and is an index of left-right symmetry. In the calculation formula, n is the sampling size, x is the average value of each data xi (i: 1, 2, 3, ..., n), and s is the standard deviation.

[0037] (Skewness of outer layer portion 12) Furthermore, the skewness of Si contained in the internal dielectric layer 14 in the side gap region D1 is larger than the skewness of Si contained in the outer layer portion 12. That is, the grain size of Si contained in the internal dielectric layer 14 in the side gap region D1 varies more than the grain size of Si contained in the outer layer portion 12. In other words, the grain size of Si contained in the outer layer portion 12 is more uniform than the grain size of Si contained in the internal dielectric layer 14 in the side gap region D1. In other words, the Si contained in the internal dielectric layer 14 in the side gap region D1 has more significant segregation than the Si contained in the outer layer portion 12.

[0038] The strain of Si contained in the internal dielectric layer 14 in the side gap region D1 is preferably set to be 0.5% or more larger than the strain of Si contained in the outer layer portion 12. A larger strain of Si improves moisture resistance, and therefore the moisture resistance of the internal dielectric layer 14 can be improved.

[0039] 3, the internal electrodes 15 are not arranged in the side gap region D1. Therefore, the thickness of the side gap region D1 in the stacking direction T is thinner than that of the central facing region where the internal electrodes 15 and the internal dielectric layers 14 are alternately stacked by the amount of the internal electrodes 15. This results in a step being formed between the side gap region D1 and the facing region.

[0040] In the embodiment, the thickness of the internal dielectric layer 14 in the stacking direction T is 0.45 μm or less. When the thickness of each internal dielectric layer 14 is small in this way, the overall capacitance is improved.

[0041] However, when the internal dielectric layer 14 becomes relatively thinner than the internal electrode 15, the proportion of the internal electrode 15 in the overall thickness of the opposing portion in the stacking direction T increases. This increases the effect of the step caused by the presence or absence of the internal electrode 15 on the overall thickness of the laminate 2 in the stacking direction T. For this reason, when the laminate sheet is pressed in the stacking direction T, as described below, the density of the side gap region D1 at the step portion tends to decrease.

[0042] However, in the multilayer ceramic capacitor 1 of the embodiment, the strain of Si contained in the internal dielectric layer 14 in the side gap region D1 is larger than the strain of Si contained in the external layer portion 12. The larger the strain of Si, the better the moisture resistance, and therefore the moisture resistance of the internal dielectric layer 14 can be improved.

[0043] (Mn Content) Furthermore, in the embodiment, the Mn content contained in the outer layer portion 12 is greater than the Mn content of the internal dielectric layer 14 located in the side gap region D1 and near the center in the stacking direction T. This can further improve the high-temperature reliability of the outer layer portion 12. Increasing the Mn content contained in the outer layer portion 12 can improve the density of the outer layer portion and improve the moisture resistance reliability. Note that, since increasing the moisture resistance reliability of only the outer layer with Mn would relatively reduce the moisture resistance of the side gap region D1, the moisture resistance reliability of the gap region D1 is improved by the segregation of Si.

[0044] (External electrode 3) The external electrode 3 includes a first external electrode 3A and a second external electrode 3B. The first external electrode 3A is connected to the first internal electrode 15A and is disposed on the first end face C1. The first external electrode 3A also includes a folded portion extending to the main surface and part of the side face B. The second external electrode 3B is connected to the second internal electrode 15B and is disposed on the second end face C2. The second external electrode 3B also includes a folded portion extending to the main surface and part of the side face B. Hereinafter, unless it is necessary to distinguish between the first external electrode 3A and the second external electrode 3B, they will be collectively referred to as the external electrode 3.

[0045] The external electrode 3 includes a base electrode layer 31 and a plating layer 32 disposed on the base electrode layer 31. The base electrode layer 31 includes, for example, a metal and a glass component. The metal includes, for example, at least one selected from copper, nickel, silver, palladium, a silver-palladium alloy, gold, etc., and is copper in this embodiment. The glass component includes, for example, boron and silicon. The plating layer 32 may include a Ni (nickel) plating layer disposed on the base electrode layer 31 and a Sn (tin) plating layer disposed on the Ni plating layer.

[0046] (Method for manufacturing multilayer ceramic capacitor 1) (Method for adjusting the degree of distortion of Si) The degree of distortion of Si in the outer layer portion 12 and in the side gap region D1 can be made different by making a difference in the particle size of the Si-containing particles, for example, glass particles, contained in the dielectric paste for the outer layer portion and the dielectric paste for the internal dielectric layer.

[0047] Specifically, when the standard glass particles in the dielectric paste for the outer dielectric layer are set to 0.005 μm or more and 0.5 μm or less, glass particles having a particle size larger than that by about 1.0 μm are mixed into the dielectric paste for the inner dielectric layer at 0.01 vol% or more and 40 vol% or less. On the other hand, the glass particles in the dielectric paste for the outer layer portion are contained with a particle size of 0.005 μm or more and 0.5 μm or less.

[0048] Then, the conductive paste for the internal electrodes is printed in a predetermined pattern on the dielectric sheet prepared using the dielectric paste for the internal dielectric layers, to form an internal electrode pattern on the dielectric sheet. The internal electrode pattern can be formed by screen printing, gravure printing, or the like.

[0049] Next, a predetermined number of second outer layer dielectric sheets prepared using the outer layer dielectric paste are laminated. Then, dielectric sheets for inner layer portions, on which internal electrode patterns are printed, are laminated in order. Finally, a predetermined number of first outer layer dielectric sheets prepared using the outer layer dielectric paste are laminated on top of these. This completes the laminated sheet process.

[0050] Next, the laminated sheet is pressed in the lamination direction T by means of a hydrostatic press or the like to produce a laminated block.

[0051] Next, the laminated block is cut to a predetermined size to cut out laminated chips.

[0052] Next, the laminated chip is fired to produce the laminate 2. The firing temperature depends on the materials of the dielectric and the internal electrodes 15, but is preferably 900°C or higher and 1400°C or lower.

[0053] Next, the first end surface C1 of the laminate 2 is immersed in a conductive paste, which is an electrode material for the base electrode layer, using a dipping method, to apply the conductive paste for the base electrode layer 31 to the first end surface C1. Similarly, the second end surface C2 of the laminate 2 is immersed in a conductive paste, which is an electrode material for the base electrode layer, to apply the conductive paste for the base electrode layer 31 to the second end surface C2. The conductive paste is then fired to form the fired layer, the base electrode layer 31. The firing temperature is preferably 600°C or higher and 900°C or lower.

[0054] Thereafter, a plating layer 32 is formed on the surface of the base electrode layer 31 to form the external electrode 3. Through the above steps, the multilayer ceramic capacitor 1 of this embodiment is obtained.

[0055] Although the embodiments of the present invention have been described above, the present invention is not limited to the above-described embodiments and various modifications and variations are possible, such as those described below. Furthermore, although the above embodiments have been described with reference to a two-terminal multilayer ceramic capacitor, the present invention is not limited to this and can also be applied to a three-terminal multilayer ceramic capacitor.

[0056] <1> A multilayer ceramic capacitor comprising: a laminate having two main surfaces opposing each other in a stacking direction, two end faces opposing each other in a vertical direction intersecting the stacking direction, and two side surfaces opposing each other in a horizontal direction intersecting the stacking direction and the vertical direction; and external electrodes arranged on the end faces of the laminate, wherein the laminate comprises inner layer portions and outer layer portions arranged to sandwich the inner layer portions in the stacking direction, the inner layer portions comprising: inner electrodes; and inner dielectric layers, wherein the outer layer portions and the inner dielectric layers contain barium titanate as a main component and Si as a minor component, and wherein the strain of Si in the inner dielectric layers in gap regions between the internal electrodes and the end faces or the side faces is greater than the strain of Si in the outer layer portions.

[0057] <2> The multilayer ceramic capacitor according to <1>, wherein the strain of Si of the outer layer portion and the inner dielectric layer in the gap region is greater than 0 and not greater than 0.5.

[0058] <3> The multilayer ceramic capacitor according to <1> or <2>, wherein the strain of Si in the internal dielectric layer in the gap region is 0.5% or more greater than the strain of Si in the outer layer portion.

[0059] <4> The multilayer ceramic capacitor according to any one of <1> to <3>, wherein the Si content in the gap region near the center in the stacking direction is 0.2 atom % or more and 5.0 atom % or less.

[0060] <5> The multilayer ceramic capacitor according to any one of <1> to <4>, wherein the Mn content of the outer layer portion is greater than the Mn content of the gap region near the center in the lamination direction.

[0061] <6> The multilayer ceramic capacitor according to any one of <1> to <5>, wherein the ceramic grain diameter D50 of the internal dielectric layers is 0.15 μm or less.

[0062] <7> The multilayer ceramic capacitor according to any one of <1> to <6>, wherein the thickness of the internal dielectric layer in the lamination direction is 0.45 μm or less.

[0063] D1 Side gap region D2 Lead-out region 1 Multilayer ceramic capacitor 2 Laminated body 3 External electrode 3A First external electrode 3B Second external electrode 11 Inner layer portion 12 Outer layer portion 12a First outer layer portion 12b Second outer layer portion 14 Internal dielectric layer 15Bb Second lead-out portion 15 Internal electrode 15A First internal electrode 15Aa First opposing part 15Ab First drawer part 15B Second internal electrode 15Ba Second opposing part 15a Opposing part 15b Puller part 1

Claims

1. A laminate having two main surfaces facing each other in the stacking direction, two end surfaces facing each other in the longitudinal direction intersecting the stacking direction, and two side surfaces facing each other in the transverse direction intersecting the stacking direction and the longitudinal direction, and an external electrode disposed on the end surface of the laminate, wherein the laminate includes an inner layer portion and an outer layer portion disposed so as to sandwich the inner layer portion in the stacking direction, the inner layer portion includes an internal electrode and an internal dielectric layer, the outer layer portion and the internal dielectric layer contain barium titanate as a main component and Si as a sub-component, and the strain degree of Si in the internal dielectric layer in the gap region between the internal electrode and the end surface or the side surface is greater than the strain degree of Si in the outer layer portion. A multilayer ceramic capacitor.

2. The strain degree of Si in the outer layer portion and the internal dielectric layer in the gap region is greater than 0 and equal to or less than 0.

5. The multilayer ceramic capacitor according to claim 1.

3. The strain degree of Si in the internal dielectric layer in the gap region is 0.5% or more greater than the strain degree of Si in the particles including Si in the outer layer portion. The multilayer ceramic capacitor according to claim 1 or claim 2.

4. The Si content in the vicinity of the center in the stacking direction of the gap region is 0.2 atom% or more and 5.0 atom% or less. The multilayer ceramic capacitor according to any one of claims 1 to 3.

5. The Mn content in the outer layer portion is greater than the Mn content in the vicinity of the center in the stacking direction of the gap region. The multilayer ceramic capacitor according to any one of claims 1 to 4.

6. The ceramic grain diameter D50 of the internal dielectric layer is 0.15 μm or less. The multilayer ceramic capacitor according to any one of claims 1 to 5.

7. The thickness of the internal dielectric layer in the stacking direction is 0.45 μm or less. The multilayer ceramic capacitor according to any one of claims 1 to 6.

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