Display device

Abstract

This display device includes: a first substrate; a light-emitting diode that is disposed on a first surface of the first substrate and includes a gallium nitride layer; a first transistor that is disposed on the light-emitting diode and is electrically connected to the light-emitting diode; a second substrate that faces the first substrate; a data signal line that is disposed on the second substrate; a ground signal line that is disposed on the second substrate; a first conductor that is disposed on the data signal line and electrically connects the data signal line and the first transistor to each other; and a second conductor that is disposed on the ground signal line and electrically connects the ground wiring and the light-emitting diode to each other.

Description

display device

[0001] One embodiment of the present invention relates to a display device including a transistor using an oxide semiconductor and a light-emitting element using gallium nitride.

[0002] In recent years, display devices using gallium nitride (GaN) light-emitting elements in their display units have become known. For example, the light-emitting elements are light-emitting diodes (LEDs) or micro-LEDs. For example, the display device includes a sapphire substrate on which the light-emitting elements are formed and a backplane on which transistors including oxide semiconductors or low-temperature polysilicon are formed. A manufacturing method for the display device includes electrically connecting the light-emitting elements and the transistors by transferring the sapphire substrate to the backplane. The light-emitting elements of the display device manufactured in this manner can pass a current corresponding to a potential supplied to the transistors. As a result, the light-emitting elements emit light, and the display device can display an image on its display unit.

[0003] For example, Patent Documents 1 to 4 disclose display devices including transistors and light-emitting elements.

[0004] U.S. Patent No. 8,791,474 International Publication No. 2022 / 210402 International Publication No. 2023 / 074098 International Publication No. 2020 / 188851

[0005] For example, the manufacturing method of the display device includes transferring light-emitting elements and connecting them to transistors on a backplane. The electrical connection between the light-emitting elements and the transistors may be unstable, resulting in variations in contact resistance depending on the bonding between the light-emitting elements and the transistors. Furthermore, if the electrical connection between the light-emitting elements and the transistors is unstable or if the electrical characteristics of the transistors are unstable, the transistors may not be able to supply current to the light-emitting elements according to a predetermined potential. As a result, the light-emitting elements do not emit light at a predetermined brightness, and the display device cannot display an image according to a predetermined potential. Furthermore, if the electrical connection between the light-emitting elements and the transistors is unstable or if the electrical characteristics of the transistors are unstable, the long-term reliability of the transistors and the display device may become a problem.

[0006] An object of the present invention is to provide a display device which includes a transistor using an oxide semiconductor and a light-emitting element using gallium nitride and in which a decrease in long-term reliability can be suppressed.

[0007] A display device according to one embodiment of the present invention includes a first substrate, a light-emitting diode including a gallium nitride layer and disposed on a first surface of the first substrate, a first transistor disposed on the light-emitting diode and electrically connected to the light-emitting diode, a second substrate opposite the first substrate, a data signal line disposed on the second substrate, a ground wiring disposed on the second substrate, a first conductor disposed on the data signal line and electrically connecting the data signal line and the first transistor, and a second conductor disposed on the ground wiring and electrically connecting the ground wiring and the light-emitting diode.

[0008] 16 is a plan view showing a configuration of a display device according to a first embodiment of the present invention. FIG. 17 is a circuit diagram showing a circuit configuration of a pixel included in the display device according to the first embodiment of the present invention. FIG. 18 is a diagram showing a configuration of connections between the circuits of a pixel included in the display device according to the first embodiment of the present invention and each wiring. FIG. 19 is a schematic plan view showing an example of a pixel layout according to the first embodiment of the present invention. FIG. 19 is a cross-sectional view showing a cross-sectional structure taken along line A1-A2 of the display device shown in FIG. 1. FIG. 20 is a flowchart showing an example of a manufacturing method of the display device according to the first embodiment of the present invention. FIG. 21 is a cross-sectional view showing an example of a cross-sectional structure in a manufacturing process of the display device according to the first embodiment of the present invention. FIG. 22 is a cross-sectional view showing an example of a cross-sectional structure in a manufacturing process of the display device according to the first embodiment of the present invention. FIG. 23 is a cross-sectional view showing an example of a cross-sectional structure in a manufacturing process of the display device according to the first embodiment of the present invention. FIG. 24 is a cross-sectional view showing an example of a cross-sectional structure in a manufacturing process of the display device according to the first embodiment of the present invention. 23 is a cross-sectional view showing an example of a cross-sectional structure in a manufacturing process of the display device according to the first embodiment of the present invention. FIG. 24 is a cross-sectional view showing an example of a cross-sectional structure in a manufacturing process of the display device according to the first embodiment of the present invention. FIG. 25 is a cross-sectional view showing an example of a cross-sectional structure in a manufacturing process of the display device according to the first embodiment of the present invention. FIG. 26 is a plan view showing a configuration of a display device according to a second embodiment of the present invention. FIG. 27 is a cross-sectional view showing a cross-sectional structure along line B1-B2 of the display device shown in FIG. 22. FIG. 28 is a cross-sectional view showing a cross-sectional structure along line C1-C2 of the display device shown in FIG. 22. FIG. 29 is a flowchart showing an example of a manufacturing method of the display device according to the second embodiment of the present invention.FIG. 10 is a cross-sectional view showing an example of a cross-sectional structure in a manufacturing process of a display device according to a second embodiment of the present invention. FIG. 11 is a cross-sectional view showing an example of a cross-sectional structure in a manufacturing process of a display device according to a second embodiment of the present invention. FIG. 12 is a cross-sectional view showing an example of a cross-sectional structure in a manufacturing process of a display device according to a second embodiment of the present invention. FIG. 13 is a cross-sectional view showing an example of a cross-sectional structure in a manufacturing process of a display device according to a second embodiment of the present invention. FIG. 14 is a cross-sectional view showing an example of a cross-sectional structure in a manufacturing process of a display device according to a second embodiment of the present invention. FIG. 15 is a plan view showing a configuration of a protection circuit according to a second embodiment of the present invention.

[0009] Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, the present invention can be implemented in many different forms, and should not be construed as being limited to the description of the embodiments exemplified below. Furthermore, for clarity of explanation, the drawings may schematically depict the width, thickness, shape, configuration, etc. of each part compared to the actual form. However, these are merely examples and do not limit the interpretation of the present invention. Furthermore, in the embodiments of the present invention, elements similar to those described above with reference to the previous figures may be designated by the same reference numerals (or reference numerals with a, b, etc. suffixed thereto), and detailed descriptions may be omitted as appropriate. The letters "first" and "second" attached to each element are convenient labels used to distinguish each element and have no further meaning unless otherwise specified.

[0010] In the specification of this application, when a component or region is referred to as being "on (or under)" another component or region, unless otherwise specified, this includes not only the case where it is directly above (or directly under) the other component or region, but also the case where it is above (or under) the other component or region, i.e., the case where another component is included between the component or region and above (or under) the other component or region.

[0011] In the present specification, the D1 direction intersects the D2 direction, and the D3 direction intersects the D1 and D2 directions (D1D2 plane). The D1 direction is referred to as the first direction, the D2 direction is referred to as the second direction, and the D3 direction is referred to as the third direction. For example, the D1, D2, and D3 directions correspond to the X direction (x direction), the Y direction (y direction), and the Z direction (z direction). Note that even if the D3 direction deviates from perpendicular to the D1 and D2 directions within an error range, the D3 direction is still considered to be perpendicular to the D1 and D2 directions. In this case, it is referred to as, for example, approximately perpendicular.

[0012] In the present specification, when the terms "identical" and "matching" are used, the terms "identical" and "matching" may include a margin of error within the design range.

[0013] 1. First Embodiment The configuration of a display device 10 will be described with reference to FIGS.

[0014] [1-1. Overview of the Display Device 10] The overview of the display device 10 will be described with reference to Fig. 1. Fig. 1 is a schematic plan view showing the configuration of the display device 10.

[0015] The display device 10 includes at least a first substrate 101 (see FIG. 5), a second substrate 201, a flexible printed circuit board (FPC) 108, and a driver IC 106. The display device 10 also includes at least a display area 122 on a first surface 201a (see FIG. 5) of the second substrate 201 (see FIG. 5) and a peripheral area 121 surrounding the periphery of the display area 122. Note that, as will be described in detail later, the array substrate 100 (see FIG. 5) includes the first substrate 101, and the backplane 200 (see FIG. 5) includes the second substrate 201.

[0016] The second substrate 201 includes a first side 191, a second side 192 opposite to the first side, a third side 193, and a fourth side 194 opposite to the third side. The display area 122 and the peripheral area 121 are surrounded by the first side 191, the second side 192 opposite to the first side, the third side 193, and the fourth side 194 opposite to the third side 193 in a plan view.

[0017] A plurality of pixels 180 are arranged in the display region 122. The display region 122 is an area that overlaps with the plurality of pixels 180 in a planar view. The plurality of pixels 180 are arranged in a matrix in a first direction D1 and a second direction D2. The arrangement of the plurality of pixels 180 is not limited to a matrix. For example, the plurality of pixels 180 may be arranged in a staggered pattern. Each pixel 180 includes a pixel IC chip 181, the details of which will be described later.

[0018] The peripheral region 121 includes a plurality of scanning signal lines 129, a plurality of data signal lines 131, ground wiring 145, driving potential lines 147, and a terminal region 126. The peripheral region 121 is a region that overlaps in a plan view with the plurality of scanning signal lines 129, the plurality of data signal lines 131, the ground wiring 145, the driving potential lines 147, and the terminal region 126. The plurality of scanning signal lines 129, the plurality of data signal lines 131, the ground wiring 145, and the driving potential lines 147 are electrically connected to corresponding pixels 180 among the plurality of pixels 180.

[0019] The terminal region 126 is a region on the third side 193 side. A plurality of terminals 150 are arranged in the terminal region 126. The plurality of terminals 150 are electrically connected to the FPC 108, the plurality of scanning signal lines 129, the plurality of data signal lines 131, the ground wiring 145, and the driving potential line 147. The terminal region 126 is a region that overlaps in a plan view with the plurality of terminals 150 for connecting the plurality of scanning signal lines 129, the plurality of data signal lines 131, the ground wiring 145, and the driving potential line 147 to the FPC 108, the driver IC 106, and an external circuit (not shown). The plurality of terminals 150 are included in the second substrate 201 and overlap with the FPC 108.

[0020] As an example, the driver IC 106 is disposed on the FPC 108. The driver IC 106 supplies control signals for driving the plurality of pixels 180 to the plurality of pixels 180 via the FPC 108, the scanning signal lines 129, the data signal lines 131, the ground wiring 145, and the driving potential lines 147.

[0021] The ground wiring 145 is arranged to surround the display area 122. The ground wiring 145 includes a wiring electrically connected to the terminal 150 on the first side 191 side and extending in the D1 direction along the third side 193, a wiring extending in the D2 direction along the first side 191, a wiring extending in the D1 direction along the fourth side 194, a wiring extending in the D2 direction along the second side 192, and a wiring electrically connected to the terminal 150 on the second side 192 side and extending in the D1 direction along the third side 193. The ground wiring 145 further includes ground wirings 145a, 145b, and 145c electrically connected to the wiring extending in the D1 direction along the fourth side 194 and branching from the fourth side 194 side toward the third side 193 side along the D2 direction. For example, a constant potential such as a ground voltage, a ground voltage, a voltage VSS, or 0 V is supplied to the ground wiring 145. These voltages (potentials) are potentials that serve as references for each signal, and may be called reference voltages (potentials).

[0022] The driving potential line 147 includes a line electrically connected to the terminal 150 on the first side 191 side and extending in the D1 direction along the third side 193, and a line extending in the D2 direction along the first side 191. The driving potential line 147 also includes driving potential lines 147a, 147b, and 147c that are electrically connected to the line extending in the D2 direction along the first side 191 and branch off from the first side 191 toward the second side 192 along the D1 direction. The driving potential lines 147a, 147b, and 147c are each electrically connected to a plurality of pixel IC chips 181 arranged along the D1 direction. For example, a constant potential higher than the potential supplied to the ground wiring 145 is supplied to the driving potential line 147. The constant potential higher than the potential supplied to the ground wiring 145 is, for example, a voltage VDD or 30 V. The driving potential line 147 may be arranged to surround the display area 122 in the same manner as the ground line 145 .

[0023] The ground wiring 145 having the configuration described above can uniformly supply a constant potential such as a ground voltage to the plurality of pixel IC chips 181. Furthermore, the drive potential line 147 having the configuration described above can uniformly supply a constant potential such as a voltage VDD to the plurality of pixel IC chips 181. As a result, the display device 10 can display an image without unevenness in the display region 122.

[0024] [1-2. Configuration of pixel 180] The configuration of the pixel 180 will be described with reference to Figures 2 and 3. Figure 2 is a schematic circuit diagram showing the configuration of a pixel circuit 182 of a pixel 180 of the display device 10. Figure 3 is a schematic diagram showing the electrical connections between a pixel IC chip 181 including the pixel circuit 182 and a scanning signal line 129, a data signal line 131, a ground wiring 145, and a driving potential line 147. Configurations that are the same as or similar to those in Figure 1 will be described as necessary.

[0025] The pixel 180 includes a pixel IC chip 181 electrically connected to the scanning signal line 129 , the data signal line 131 , the ground wiring 145 and the driving potential line 147 .

[0026] The pixel IC chip 181 includes a first transistor 184a, a second transistor 184b, a third transistor 184c, a light-emitting diode 300, and a capacitor element 188. The pixel IC chip 181 also includes first connecting conductive layers 244a, 244b, 244c, and 244d. For example, the first connecting conductive layers 244a, 244b, 244c, and 244d connect the corresponding electrodes and wirings using solder or an anisotropic conductive film (ACF). For example, the first connecting conductive layer 244a is arranged between and connects the gate electrode 3G, source electrode 3S, and cathode 6F to the ground wiring 145a, the first connecting conductive layer 244b is arranged between and connects the drain electrode 2D and second electrode 8S to the driving potential line 147a, the first connecting conductive layer 244c is arranged between and connects the gate electrode 1G and the scanning signal line 129, and the first connecting conductive layer 244d is arranged between and connects the source electrode 1S and the data signal line 131.

[0027] In describing the first connecting conductive layers included in pixel 180, when the first connecting conductive layers are not to be distinguished, the first connecting conductive layers are described as first connecting conductive layers 244, and when the first connecting conductive layers are to be distinguished, the first connecting conductive layers are given individual symbols such as first connecting conductive layers 244a to 244d.

[0028] The first transistor 184a can function as a selection transistor. The conduction state of the first transistor 184a is controlled by a scanning signal line 129. The first transistor 184a includes a gate electrode 1G, a source electrode 1S, and a drain electrode 1D. The source electrode 1S is electrically connected to a data signal line 131, the drain electrode 1D is electrically connected to a gate electrode 2G of the second transistor 184b and a first electrode 8F of the capacitor 188, and the gate electrode 1G is electrically connected to the scanning signal line 129.

[0029] The second transistor 184b can function as a drive transistor. The second transistor 184b controls the light emission brightness of the light-emitting diode 300. The conduction state of the second transistor 184b is controlled by the first transistor 184a. The second transistor 184b includes a gate electrode 2G, a source electrode 2S, and a drain electrode 2D. The source electrode 2S is electrically connected to the drain electrode 3D of the third transistor 184c and the anode 6S of the light-emitting diode 300, the drain electrode 2D is electrically connected to the drive potential line 147 and the second electrode 8S of the capacitor element 188, and the gate electrode 2G is electrically connected to the drain electrode 1D and the first electrode 8F.

[0030] The third transistor 184c can function as a protection circuit for the light-emitting diode 300. The third transistor 184c includes a gate electrode 3G, a source electrode 3S, and a drain electrode 3D. The third transistor 184c is connected in parallel to the light-emitting diode 300. More specifically, the source electrode 3S is electrically connected to the gate electrode 3G, the cathode 6F of the light-emitting diode 300, and the ground wiring 145, and the drain electrode 3D is electrically connected to the anode 6S and the source electrode 2S. The gate electrode 3G is electrically connected to the source electrode 3S, and the third transistor 184c is a diode including a so-called diode connection. The conduction state of the third transistor 184c is controlled by the potential difference between the potential supplied to the drain electrode 3D and the potential supplied to the source electrode 3S. Because the source electrode 3S is electrically connected to the ground wiring 145, the potential supplied to the drain electrode 3D is basically equal to or higher than the potential supplied to the ground wiring 145. When the potential supplied to the drain electrode 3D is lower than the potential supplied to the ground wiring 145, the third transistor 184c is brought into a conductive state and functions as a protection circuit. In other words, when an overvoltage is applied between the anode 6S and cathode 6F of the light-emitting diode 300, the pixel 180 (pixel circuit 182) can cause the current flowing through the light-emitting diode 300 to flow to the ground wiring 145 via the third transistor 184c. As a result, the third transistor 184c can suppress the application of an overvoltage and the supply of an overcurrent to the light-emitting diode 300.

[0031] In describing the transistors included in pixel 180, when the transistors are not to be distinguished, the transistors are referred to as transistor 184, and when the transistors are to be distinguished, the transistors are referred to as first transistor 184a, second transistor 184b, and third transistor 184c.

[0032] The light-emitting diode 300 includes a cathode (n-type electrode) 6F and an anode (p-type electrode) 6S.

[0033] The capacitor 188 includes a first electrode 8F and a second electrode 8S. For example, the capacitor 188 can hold a charge corresponding to a potential corresponding to an image displayed by the pixel 180. Furthermore, for example, the capacitor 188 can hold a charge corresponding to the threshold voltage of the second transistor 184b and correct the threshold voltage of the second transistor 184b. As a result, the second transistor 184b can supply a stable current corresponding to the potential corresponding to the image to the light-emitting diode 300.

[0034] Any control signal is supplied from the driver IC 106 and an external circuit to the pixel circuits 182 of the plurality of pixels 180 of the display device 10 , and the display device 10 can display an image in the display area 122 .

[0035] In this specification and drawings, for convenience of explanation, the source and drain functions of the electrodes may be interchanged depending on the potential supplied to the source and drain electrodes of each transistor.

[0036] [1-3. Layout Example] An example of the layout of the third transistor 184c and the light-emitting diode 300 will be described with reference to Fig. 4. Fig. 4 is a schematic plan view showing an example of the layout of the third transistor 184c and the light-emitting diode 300. Configurations that are the same as or similar to those in Figs. 1 to 3 will be described as necessary.

[0037] The n-type electrode 350 (cathode 6F) of the light-emitting diode 300 is connected to the second connection conductive layer 370a, the conductive layer 152a, and the conductive connecting member 620a, and is connected to the first connection conductive layer 244a and the ground wiring 145a via the second connection conductive layer 370a, the conductive layer 152a, and the conductive connecting member 620a. The n-type electrode 350 (cathode 6F) is connected to the gate electrode 138a (gate electrode 3G) exposed from the opening 139 and the source electrode 3S exposed from the opening 140a via the second connection conductive layer 370a and the conductive layer 152a. The p-type electrode 360 ​​(anode 6S) of the light-emitting diode 300 is connected to the second connection conductive layer 370b and the conductive layer 152b, and is connected to the drain electrode 3D exposed from the opening 140b via the second connection conductive layer 370b and the conductive layer 152b.

[0038] That is, the third transistor 184c and the light-emitting diode 300 are provided on the same IC chip (pixel IC chip 181). Furthermore, as described in "1-2," the third transistor 184c functions as a protection circuit for the light-emitting diode 300. The display device 10 can have a configuration in which the light-emitting diode 300 and the third transistor 184c that protects the light-emitting diode 300 are integrally formed, rather than having the light-emitting diode 300 and the third transistor 184c that protects the light-emitting diode 300 individually. As a result, the electrical connection between the light-emitting diode 300 and the third transistor 184c can be more stable than if the light-emitting diode 300 and the third transistor 184c that protects the light-emitting diode 300 were individually provided. Therefore, the display device 10 can suppress variations in contact resistance between the light-emitting diode 300 and the third transistor 184c and stabilize the electrical characteristics of the light-emitting diode 300 and the third transistor 184c, thereby suppressing deterioration in the light-emitting characteristics, temperature characteristics, and the like of the pixel 180.

[0039] [1-4. Example of a Cross Section of a Pixel 180] An example of a cross section of a pixel 180 will be described with reference to Fig. 5. Fig. 5 is a cross-sectional view showing an example of the cross-sectional structure of a pixel 180 of the display device 10. Specifically, it is a cross-sectional view showing an example of the cross-sectional structure of the pixel 180 taken along line A1-A2 shown in Fig. 1. Configurations that are the same as or similar to those in Figs. 1 to 4 will be described as necessary.

[0040] The display device 10 includes an array substrate 100 and a backplane 200. The array substrate 100 includes a first substrate 101, an underlayer 110, a buffer layer 120, a light-emitting diode 300, an insulating layer 380, an insulating layer 117, an insulating layer 136, a second transistor 184b, an insulating layer 154, conductive layers 152a, 152b, and 152c, an insulating layer 118, an insulating layer 119, openings 619a and 619b, and a color conversion layer 115. The backplane 200 includes a second substrate 201, an underlayer 210, a plurality of terminals 150 (see FIG. 1 ), conductive layers 238a and 238b, first connecting conductive layers 244a and 244b, an insulating layer 240, and an insulating layer 246.

[0041] The first substrate 101 is a substrate (first support substrate) that supports the transistor 184 and the light-emitting diode 300. The first substrate 101 includes a first surface 101a and a second surface 101b facing the first surface 101a. The buffer layer 120, the light-emitting diode 300, the insulating layer 380, the insulating layer 117, the insulating layer 136, the second transistor 184b, the insulating layer 154, the conductive layers 152a, 152b, and 152c, the insulating layer 118, the insulating layer 119, and the openings 619a and 619b are disposed on the first surface 101a. The color conversion layer 115 is disposed on the second surface 101b.

[0042] The underlayer 110 is disposed on the first substrate 101. The buffer layer 120 is disposed on the underlayer 110.

[0043] The light emitting diode 300 is disposed on the buffer layer 120. The light emitting diode 300 includes a gallium nitride layer 310, an n-type semiconductor layer 320, a light emitting layer 330, a p-type semiconductor layer 340, an n-type electrode 350, and a p-type electrode 360.

[0044] The gallium nitride layer 310 is disposed on the buffer layer 120. The n-type semiconductor layer 320 is disposed on the gallium nitride layer 310. The light emitting layer 330 is disposed on the n-type semiconductor layer 320. The p-type semiconductor layer 340 is disposed on the light emitting layer 330. The n-type electrode 350 is disposed on the n-type semiconductor layer 320. The p-type electrode 360 ​​is disposed on the p-type semiconductor layer 340.

[0045] The insulating layer 116 is disposed so as to cover the light-emitting diode 300. Specifically, the insulating layer 116 is disposed on a part of the surface of the buffer layer 120, the side surfaces of the gallium nitride layer 310, the side surfaces and part of the surface of the n-type semiconductor layer 320, the side surfaces of the light-emitting layer 330, and the side surfaces and part of the surface of the p-type semiconductor layer 340.

[0046] The light-emitting diode 300 is a so-called micro LED or mini LED. However, the light-emitting diode 300 is not limited to the LED shown in the display device 10. The length of one side of a micro LED is 100 μm or less, and the length of one side of a mini LED is longer than 100 μm.

[0047] The insulating layer 380 is disposed so as to cover part of the surface of the buffer layer 120, the light-emitting diode 300, and the insulating layer 116. The insulating layer 117 is disposed on the insulating layer 380. The insulating layer 380 may be referred to as a first planarization film.

[0048] The second connection conductive layer 370a contacts the opening 372a (see FIG. 10 ) and the n-type electrode 350, and is electrically connected to the n-type electrode 350 via the opening 372a. The second connection conductive layer 370b contacts the opening 372b (see FIG. 10 ) and the p-type electrode 360, and is electrically connected to the p-type electrode 360 ​​via the opening 372b. Note that, because the openings 372a and 372b are formed in the insulating layers 117 and 380, the second connection conductive layer 370a contacts the insulating layers 117 and 380 that form the sidewalls of the opening 372a, and the second connection conductive layer 370b contacts the insulating layers 117 and 380 that form the sidewalls of the opening 372a.

[0049] The insulating layer 136 is disposed on the insulating layer 117. The insulating layer 136 is also disposed on the surfaces of the second connection conductive layers 370a and 370b. For example, the insulating layer 136 is an underlayer.

[0050] The transistor 184 is disposed over the insulating layer 136. The transistor 184 includes a conductive layer 138, a gate insulating layer 140, an oxide semiconductor layer 142, a source electrode 144a, and a drain electrode 144b. The transistor 184 shown in FIG. 5 is, for example, a second transistor 184b.

[0051] A conductive layer 138 is disposed on the insulating layer 136. The conductive layer 138 functions as a gate electrode. For example, the conductive layer 138 shown in FIG. 5 is a gate electrode 2G.

[0052] A gate insulating layer 140 is disposed on the conductive layer 138 and on the surface of the insulating layer 136 .

[0053] The oxide semiconductor layer 142 is disposed on the gate insulating layer 140. The oxide semiconductor layer 142 is used for the channel of the transistor 184.

[0054] The source electrode 144a and the drain electrode 144b are disposed on the oxide semiconductor layer 142 and the gate insulating layer 140, spaced apart from each other. The source electrode 144a and the drain electrode 144b are electrically connected to the oxide semiconductor layer 142. The source electrode 144a and the drain electrode 144b of the display device 10 are connected to the oxide semiconductor layer 142 by being in direct contact with the oxide semiconductor layer 142. Note that in the description of the source electrode, the drain electrode, and the wiring formed in the same layer as the source electrode and the drain electrode included in the pixel 180, when the source electrode, the drain electrode, and the wiring are not distinguished from each other, the source electrode, the drain electrode, and the wiring are referred to as the conductive layer 144, and when the source electrode, the drain electrode, and the wiring are distinguished from each other, the source electrode, the drain electrode, and the wiring are given individual reference symbols such as the source electrode 144a, the drain electrode 144b, etc.

[0055] The insulating layer 146 is disposed on the source electrode 144a and the drain electrode 144b, on part of the surface of the oxide semiconductor layer 142, and on part of the gate insulating layer 140. That is, the insulating layer 146 is disposed so as to cover the transistor 184. The insulating layer 154 is disposed on the insulating layer 146. That is, the insulating layer 154 is disposed so as to cover the transistor 184.

[0056] The conductive layer 152a is in contact with the opening 151a (see FIG. 13) and the second connection conductive layer 370a and is electrically connected to the second connection conductive layer 370a through the opening 151a. The conductive layer 152b is in contact with the opening 151b (see FIG. 13) and the second connection conductive layer 370b and is electrically connected to the second connection conductive layer 370b through the opening 151b. The conductive layer 152b is in contact with the opening 151d (see FIG. 13) and the source electrode 144a and is electrically connected to the source electrode 144a through the opening 151d. The conductive layer 152c is in contact with the opening 151c (see FIG. 13) and the drain electrode 144b and is electrically connected to the drain electrode 144b through the opening 151c. Note that since the openings 151a and 151b are formed in the insulating layer 136, the gate insulating layer 140, and the insulating layers 146 and 154, the conductive layers 152a and 152b are in contact with the insulating layer 136, the gate insulating layer 140, and the insulating layers 146 and 154, which form side walls of the openings 151a and 151b. Since the openings 151c and 151d are formed in the insulating layers 146 and 154, the conductive layers 152b and 152c are in contact with the insulating layers 146 and 154, which form side walls of the openings 151c and 151d.

[0057] The insulating layer 118 is disposed on the insulating layer 154 and the conductive layers 152a, 152b, and 152c. That is, the insulating layer 118 is disposed so as to cover the conductive layers 152a, 152b, and 152c. The insulating layer 119 is disposed on the insulating layer 118.

[0058] Openings 619a and 619b are formed in the insulating layers 118 and 119. A conductive connection member 620a is disposed in contact with the opening 619a and the conductive layer 152a, and is electrically connected to the conductive layer 152a. A conductive connection member 620b is disposed in contact with the opening 619b and the conductive layer 152c, and is electrically connected to the conductive layer 152c. The conductive connection members 620a and 620b may be referred to as conductors (a first conductor and a second conductor).

[0059] An adhesive resin material 610 is disposed on the buffer layer 120. The adhesive resin material 610 is formed so as to surround at least a portion of the periphery of the light-emitting diode 300 and the transistor 184 in a cross-sectional view.

[0060] The second substrate 201 is a substrate (second support substrate) that supports the plurality of terminals 150, the plurality of scanning signal lines 129, the plurality of data signal lines 131, the ground wiring 145, and the driving potential line 147. The second substrate 201 includes a first surface 201a and a second surface 201b facing the first surface 201a. The underlayer 210, the conductive layers 238a and 238b, the first connecting conductive layers 244a and 244b, the insulating layer 240, and the insulating layer 246 are disposed on the first surface 201a.

[0061] The underlayer 210 is disposed on the second substrate 201. The underlayer 210 can prevent the diffusion of impurities from the second substrate 201 or external impurities (e.g., moisture or sodium (Na)).

[0062] The conductive layers 238a and 238b are disposed on the base layer 210. The conductive layer 238a functions as the scanning signal line 129. The conductive layer 238b functions as the driving potential line 147a.

[0063] The insulating layer 240 is disposed on the conductive layers 238a and 238b. That is, the insulating layer 240 is disposed so as to cover the plurality of scanning signal lines 129 and the driving potential line 147a. An opening 243 is formed in the insulating layer 240.

[0064] The first connection conductive layer 244a is disposed on the insulating layer 240. The first connection conductive layer 244b is disposed on the conductive layer 238b in the opening 243 of the insulating layer 240 and is electrically connected to the conductive layer 238b. The first connection conductive layers 244a and 244b are formed on different layers in the same process. For example, as shown in FIG. 4, the first connection conductive layer 244a extends in the second direction D2 and branches out and extends in the first direction D1. Although not shown, the first connection conductive layer 244a is disposed so as to overlap the insulating layer 240. For example, the first connection conductive layer 244b extends in the first direction D1 and the second direction D2 as shown in FIG. 3. The first connection conductive layer 244b may be disposed so as to overlap the insulating layer 240.

[0065] An insulating layer 246 is disposed on the insulating layer 240 and the first connecting conductive layers 244a and 244b. As will be described in detail later, the insulating layer 246 is polished and planarized using chemical mechanical polishing (CMP). As a result, the insulating layer 246 is removed from above the first connecting conductive layers 244a and 244b, exposing a portion of the insulating layer 240 and the first connecting conductive layers 244a and 244b on the surface of the backplane.

[0066] For example, the plurality of terminals 150 are formed using the conductive layer 238 and the first connecting conductive layer 244. Furthermore, the insulating layer 240 on the first connecting conductive layer 244 is opened, and the insulating layer 246 on the first connecting conductive layer 244 is polished using CMP, so that the exposed surface of the first connecting conductive layer 244 is electrically connected to the FPC 300.

[0067] The first surface 101a of the array substrate 100 faces the first surface 201a of the backplane 200, and the array substrate 100 is bonded to the backplane 200. Specifically, the array substrate 100 and the backplane 200 are bonded together using an adhesive resin material 610. As a result, the array substrate 100 is electrically connected to the backplane 200 by conductive connecting members 620a and 620b. Specifically, the conductive layer 152a of the array substrate 100 is electrically connected to the first connecting conductive layer 244a of the backplane 200 via the conductive connecting member 620a, and the conductive layer 152c of the array substrate 100 is electrically connected to the first connecting conductive layer 244b of the backplane 200 via the conductive connecting member 620b. At this time, for example, the conductive layer 238b and the first connecting conductive layer 244b may overlap the second transistor 184b. The conductive layer 238b (the first connection conductive layer 244b) and the oxide semiconductor layer 142 can form a capacitor 188 with the insulating layers 119, 118, 154, and 146 interposed therebetween.

[0068] The light-emitting diode 300 and the plurality of transistors 184 for driving the light-emitting diode 300 of the display device 10 can be formed on the same first substrate 101. The light-emitting diode 300 and the second transistor 184b for driving the light-emitting diode 300 are electrically connected on the same first substrate 101. As a result, the display device 10 is formed by transferring a pixel IC chip 181 including a light-emitting diode and a transistor for driving the light-emitting diode to a backplane. That is, by using a stable array process for the connection portion between the drive transistor and the LED, which has a small contact area within the pixel IC chip, and using a transfer process for the connection portion between the backplane and the pixel IC chip, which has a large contact area, the contact resistance value between the light-emitting diode and the transistor can be stabilized. Therefore, because the current supplied to the light-emitting diode 300 by the second transistor 184b is stabilized, the display device 10 can suppress deterioration of the light-emitting characteristics and temperature characteristics of the pixel 180.

[0069] [1-5. Example of Manufacturing Method of Display Device 10] An example of a manufacturing method of the display device 10 will be described with reference to FIGS. 6 to 21. FIG. 6 is a flowchart showing an example of a manufacturing method of the light-emitting diodes 300 of the array substrate 100. FIGS. 7 to 10 are cross-sectional views showing an example of the cross-sectional structure in the manufacturing process of the array substrate 100. FIG. 11 is a flowchart showing an example of a manufacturing method of the transistors 184 of the array substrate 100. FIGS. 12 to 15 are cross-sectional views showing an example of the cross-sectional structure in the manufacturing process of the array substrate 100. FIG. 16 is a plan view showing an example of a manufacturing method of the array substrate 100. FIG. 17 is an enlarged view of the plane shown in FIG. 16. FIG. 18 is a flowchart showing an example of a manufacturing method of the backplane 200 and an example of a method of bonding the pixel IC chips 181 and the backplane 200. FIGS. 19 and 20 are cross-sectional views showing an example of the cross-sectional structure in the manufacturing process of the backplane 200. FIG. 21 is a cross-sectional view showing an example of the cross-sectional structure in the manufacturing process of the display device 10. Configurations that are the same as or similar to those in FIGS. 1 to 5 will be described as necessary.

[0070] 6 to 17, a method for manufacturing the array substrate 100 and the pixel IC chips 181 will be described. The method for manufacturing the array substrate 100 and the pixel IC chips 181 includes steps S110 to S380. The method for manufacturing the array substrate 100 and the pixel IC chips 181 uses a first substrate 101, such as a sapphire substrate or an amorphous glass substrate, as a support substrate.

[0071] Step S110 is a step of forming an underlayer 110 on the first surface 101a of the first substrate 101 so as to be in contact with the first surface 101a (see FIGS. 6 and 7). For example, the underlayer 110 is formed using sputtering. The underlayer 110 may be a single layer or a laminated layer. For example, the underlayer 110 may be a silicon nitride (SiNx) film as a single layer, or a laminated layer of a silicon oxide (SiOx) film and a silicon nitride (SiNx) film. The underlayer 110 can prevent impurities from the first substrate 101 or external impurities (e.g., moisture or sodium (Na)) from diffusing into layers laminated on the underlayer 110.

[0072] Step S120 is a step of forming a buffer layer 120 on the underlayer 110 so as to be in contact with the underlayer 110 (see FIGS. 6 and 7 ). For example, the buffer layer 120 is formed by sputtering. The buffer layer 120 may be a single layer or a multilayer. The buffer layer 120 may be c-axis oriented with respect to the first substrate 101. By providing the buffer layer 120, the crystallinity of the gallium nitride layer 310 of the light-emitting diode 300 can be improved. Light emitted from the light-emitting layer 330 of the light-emitting diode 300 passes through the buffer layer 120 and is emitted to the outside. Therefore, the buffer layer 120 has light-transmitting properties. For example, the buffer layer 120 can be a light-transmitting film such as an aluminum nitride (AlN) film.

[0073] Steps S130 to S200 are steps for forming the light emitting diode 300 (see FIGS. 6 and 7).

[0074] Step S130 is a step of forming a gallium nitride (GaN) film on the buffer layer 120 so as to be in contact with the buffer layer 120. Step S140 is a step of forming a silicon (Si)-doped gallium nitride film on the gallium nitride film so as to be in contact with the gallium nitride film. Step S150 is a step of forming a stacked film in which an indium gallium nitride (InGaN) film and a gallium nitride film are alternately stacked on the silicon-doped gallium nitride film so as to be in contact with the silicon-doped gallium nitride film. Step S160 is a step of forming a magnesium (Mg)-doped gallium nitride film on the stacked film in which an indium gallium nitride film and a gallium nitride film are alternately stacked. Steps S130 to S160 are steps of forming each film using sputtering.

[0075] Step S170 is a step of forming the gallium nitride layer 310, the n-type semiconductor layer 320, the light-emitting layer 330, and the p-type semiconductor layer 340 using photolithography and etching. The gallium nitride layer 310 includes the gallium nitride film deposited in step S130. Because the gallium nitride layer 310 is in contact with the buffer layer 120, the crystal growth of the gallium nitride layer 310 is controlled by the buffer layer 120. Specifically, the gallium nitride layer 310 includes a gallium nitride (GaN) film that is c-axis oriented with respect to the first substrate 101. The n-type semiconductor layer 320 includes a silicon-doped gallium nitride film deposited in step S140. A portion of the surface of the n-type semiconductor layer 320 is etched and exposed. The light-emitting layer 330 includes a stacked film formed in step S150 in which indium gallium nitride films and gallium nitride films are alternately stacked. The p-type semiconductor layer 340 includes the magnesium-doped gallium nitride film deposited in step S160.

[0076] Step S180 is a step of forming an insulating layer 116 so as to cover and contact a portion of the surface of the buffer layer 120, the side surfaces of the gallium nitride layer 310, a portion of the side surfaces and surfaces of the n-type semiconductor layer 320, the side surfaces of the light-emitting layer 330, and a portion of the side surfaces and surfaces of the p-type semiconductor layer 340 (see FIGS. 6 and 8 ). For example, the insulating layer 116 is formed by depositing an aluminum oxide (AlO) film using sputtering and then using photolithography and etching. Because the aluminum oxide (AlO) film has high resistance to hydrogen, water, and the like, the insulating layer 116 functions as a protective film that protects the light-emitting diode 300. Specifically, the insulating layer 116 can prevent hydrogen, water, and the like from penetrating the light-emitting diode 300 and from diffusing into the light-emitting diode 300. Furthermore, for example, when the insulating layer 116 is made of silicon nitride (SiN), whose refractive index is higher than that of a silicon oxide (SiOx) film, the insulating layer 116 can reflect light emitted from the light-emitting diode 300. As a result, the insulating layer 116 can suppress fluctuations in the electrical characteristics of the transistor 184 due to the light emitted from the light-emitting diode 300 .

[0077] Step S190 is a step of forming a p-type electrode 360 ​​on the p-type semiconductor layer 340. A specific example of step S190 is described below. Using photolithography and etching, a portion of the insulating layer 116 is opened to expose a portion of the p-type semiconductor layer 340. Furthermore, a metal film such as palladium (Pd) or gold (Au) or a laminated metal film such as a metal film stacked with nickel (Ni) and gold (Au) is formed on a portion of the p-type semiconductor layer 340 and on the insulating layer 116 using sputtering. Then, using photolithography and etching, the p-type electrode 360 ​​is formed on the p-type semiconductor layer 340. The p-type electrode 360 ​​includes a metal film such as palladium (Pd) or gold (Au) or a laminated metal film such as a metal film stacked with nickel (Ni) and gold (Au). The p-type electrode 360 ​​is electrically connected to the p-type semiconductor layer 340.

[0078] Step S200 is a step of forming an n-type electrode 350 on the n-type semiconductor layer 320. A specific example of step S200 is described below. Using photolithography and etching, a portion of the insulating layer 116 is opened to expose a portion of the n-type semiconductor layer 320. Furthermore, a metal film such as indium (In) or a laminated metal film such as a metal film formed by stacking titanium (Ti), aluminum titanium (AlTi), and gold (Au) is formed on the portion of the n-type semiconductor layer 320 and on the insulating layer 116 using sputtering. Then, using photolithography and etching, the n-type electrode 350 is formed on the n-type semiconductor layer 320. The n-type electrode 350 includes a metal film such as indium or a laminated metal film such as a metal film formed by stacking titanium, aluminum titanium, and gold. The n-type electrode 350 is electrically connected to the n-type semiconductor layer 320.

[0079] The n-type electrode 350 and the p-type electrode 360 ​​are insulated from each other by the insulating layer 116. In other words, the n-type electrode 350 and the p-type electrode 360 ​​are not short-circuited by the insulating layer 116.

[0080] The order of steps S200 and S190 may be reversed. Alternatively, after the p-type electrode 360 ​​and the n-type electrode 350 are formed by a manufacturing method similar to that of steps S190 and S200, the insulating layer 116 may be formed by a manufacturing method similar to that of step S180.

[0081] As described above, the light emitting diode 300 is formed.

[0082] Step S210 is a step of forming an insulating layer 380 so as to cover a portion of the surface of the buffer layer 120, the light-emitting diodes 300, and the insulating layer 116 (see FIGS. 6 and 9 ). Step S210 is also a step of forming an insulating layer 117 on the insulating layer 380 (see FIGS. 6 and 9 ). Specifically, the insulating layer 380 is formed so as to cover a portion of the surface of the buffer layer 120, the light-emitting diodes 300, and the insulating layer 116 using an apparatus (coating apparatus) that coats a film on a substrate surface, and the insulating layer 117 is formed on the insulating layer 380 using sputtering. The insulating layer 380 and the insulating layer 117 are formed using photolithography and etching. As a result, a groove 189 is formed around each of the plurality of light-emitting diodes 300. As will be described in detail later, the grooves 189 enable the plurality of light-emitting diodes 300 to be individually separated. For example, a spin coater or a slit coater can be used as the coating apparatus.

[0083] For example, the insulating layer 380 can be an organic insulating film such as an acrylic resin film or a polyimide resin film. Since the insulating layer 380 includes an organic insulating film, it can flatten unevenness due to the light-emitting diode 300 and the insulating layer 116. The insulating layer 380 may be a single layer or a multilayer. When the insulating layer 380 is a multilayer film, it may include not only an organic insulating film but also an inorganic insulating film such as a silicon oxide (SiOx) film or a silicon nitride (SiNx) film.

[0084] The insulating layer 117 is formed using the same material as the insulating layer 116. For example, the insulating layer 117 is formed using an aluminum oxide (AlO) film. Like the insulating layer 116, the insulating layer 117 can prevent hydrogen, water, and the like from entering the insulating layer 380 and the transistor 184 and from diffusing into the insulating layer 380 and the transistor 184. Furthermore, when the refractive index of the insulating layer 117 is higher than the refractive index of silicon oxide (SiOx), the insulating layer 117 can reflect the light emitted from the light-emitting diode 300, like the insulating layer 116. As a result, like the insulating layer 116, the insulating layer 117 can suppress fluctuations in the electrical characteristics of the transistor 184 due to the light emitted from the light-emitting diode 300.

[0085] Step S220 is a step of forming openings 372b and 372a using photolithography and etching (see FIGS. 6 and 10 ). Opening 372a exposes insulating layers 117 and 380 that form sidewalls of opening 372a and a portion of the surface of n-type electrode 350. Opening 372b exposes insulating layers 117 and 380 that form sidewalls of opening 372b and a portion of the surface of p-type electrode 360.

[0086] Step S230 is a step of depositing and forming second connection conductive layers 370a and 370b (see FIGS. 6 and 10 ). In step S230, a conductive film is formed by sputtering on the insulating layers 117 and 380 that form the sidewalls of the opening 372a, part of the surface of the n-type electrode 350, the insulating layers 117 and 380 that form the sidewalls of the opening 372b, and part of the surface of the p-type electrode 360. In step S230, the second connection conductive layer 370a is formed on the insulating layers 117 and 380 that form the sidewalls of the opening 372a and part of the surface of the n-type electrode 350, and the second connection conductive layer 370b is formed on the insulating layers 117 and 380 that form the sidewalls of the opening 372b and part of the surface of the p-type electrode 360 ​​using photolithography and etching. The conductive film includes the second connection conductive layers 370a and 370b. For example, the conductive film may be a laminated metal film of aluminum and titanium (Al / Ti film), etc. The second connection conductive layer 370 a is electrically connected to the n-type electrode 350, and the second connection conductive layer 370 b is electrically connected to the p-type electrode 360.

[0087] Step S240 is a step of forming an insulating layer 136 on the surfaces of the insulating layer 117 and the second connecting conductive layers 370 a and 370 b so as to be in contact with the insulating layer 117 and the second connecting conductive layers 370 a and 370 b (see FIGS. 11 and 12 ). For example, the insulating layer 136 can be formed in the same manner as the base layer 110 using the same material as the base layer 110.

[0088] Steps S250 to S310 are steps for forming the transistor 184 (see FIGS. 11 to 13).

[0089] Step S250 is a step of depositing a conductive layer 138 on the insulating layer 136 by sputtering so as to be in contact with the insulating layer 136. For example, the conductive layer 138 is formed using a metal film containing a common metal. For example, common metals include metal films containing aluminum (Al), titanium (Ti), chromium (Cr), cobalt (Co), nickel (Ni), molybdenum (Mo), hafnium (Hf), tantalum (Ta), tungsten (W), bismuth (Bi), silver (Ag), and copper (Cu), as well as alloys or compounds thereof. The conductive layer 138 may be a single layer or a multilayer.

[0090] Step S260 is a step of processing the conductive layer 138 formed in step S250 using photolithography and etching to form gate electrodes and wiring. The conductive layer 138 functions as gate electrodes 1G, 2G, and 3G. For example, the conductive layer 138 shown in FIG. 12 is gate electrode 2G.

[0091] Step S270 is a step of depositing a gate insulating layer 140 by sputtering on the conductive layer 138 and on the surface of the insulating layer 136 so as to be in contact with the conductive layer 138 and the insulating layer 136. For example, the gate insulating layer 140 may be made of silicon oxide (SiOx).

[0092] Step S280 is a step of depositing an oxide semiconductor layer 142 by sputtering over the gate insulating layer 140 so as to be in contact with the gate insulating layer 140. For example, the oxide semiconductor layer 142 can be formed using a metal oxide having semiconductor properties. Specifically, an oxide semiconductor containing indium, gallium (Ga), zinc (Zn), and oxygen (O), or an oxide semiconductor containing indium, tin (Sn), zinc, and oxygen can be used. Note that the oxide semiconductor layer 142 may be amorphous or crystalline. Alternatively, the oxide semiconductor layer 142 may be both amorphous and crystalline.

[0093] Step S290 is a step of processing the oxide semiconductor layer 142 formed in Step S280 by photolithography and etching to form the oxide semiconductor layer 142 used as the semiconductor layer of each of the plurality of transistors 184. The oxide semiconductor layer 142 functions as a channel of the transistor 184. For example, the oxide semiconductor layer 142 shown in FIG. 12 functions as a channel of the second transistor 184b.

[0094] Step S300 is a step of depositing the conductive layer 144 by sputtering over the oxide semiconductor layer 142 and over part of the gate insulating layer 140 so as to be in contact with the oxide semiconductor layer 142 and part of the gate insulating layer 140. For example, the conductive layer 144 can be formed in the same manner as the conductive layer 138 using the same material as the conductive layer 138.

[0095] For example, the conductive layer 144 has a stacked structure of a layer containing titanium and a layer containing aluminum. Specifically, the conductive layer 144 may have a three-layer structure (e.g., Ti / Al / Ti or TiN / Al / TiN) in which titanium or titanium nitride (TiN) and aluminum are stacked in this order. Alternatively, the conductive layer 144 may have a five-layer structure (e.g., TiN / Ti / Al / TiN / Ti) in which titanium or titanium nitride (TiN) and aluminum are stacked in this order. When the conductive layer 144 has a stacked structure of layers using titanium or titanium nitride, it is preferable to use a layer using titanium or titanium nitride as a layer in contact with the oxide semiconductor layer 142. Titanium and titanium nitride have high hydrogen absorbing properties, and the conductive layer 144 functions as a protective film to protect the oxide semiconductor layer 142. By using titanium and titanium nitride for the conductive layer 144, the conductive layer 138 can absorb hydrogen released from layers in contact with the conductive layer 138 during heat treatment in the manufacturing process of the display device 10, thereby suppressing the diffusion of hydrogen into the oxide semiconductor layer 142.

[0096] Step S310 is a step of processing the conductive layer 144 formed in step S300 by photolithography and etching to form a source electrode, a drain electrode, and a wiring. The conductive layer 144 functions as a source electrode, a drain electrode, or a wiring. For example, the conductive layer 144 shown in FIG. 12 is a source electrode 144a and a drain electrode 144b. The source electrode 144a and the drain electrode 144b are formed in the same layer and are disposed separately from each other over the oxide semiconductor layer 142 and part of the gate insulating layer 140.

[0097] As described above, the transistor 184 is formed.

[0098] Step S320 is a step of depositing an insulating layer 146 by sputtering over the conductive layer 144 and over a portion of the gate insulating layer 140 so as to be in contact with the conductive layer 144 and the gate insulating layer 140, and forming an insulating layer 154 on the insulating layer 146 so as to be in contact with the insulating layer 146. For example, the insulating layer 146 can be formed in the same manner as the gate insulating layer 140 using a material similar to that of the gate insulating layer 140. The insulating layer 154 can be formed in the same manner as the insulating layer 380 using a material similar to that of the insulating layer 380. Like the insulating layer 380, the insulating layer 154 can planarize unevenness due to the transistor 184 and the insulating layer 146.

[0099] Step S330 is a step of forming openings 151a to 151d using photolithography and etching. The opening 151a exposes the insulating layer 136, the gate insulating layer 140, the insulating layers 146 and 154, which form the sidewalls of the opening 151a, and a portion of the surface of the second connection conductive layer 370a. The opening 151b exposes the insulating layer 136, the gate insulating layer 140, the insulating layers 146 and 154, which form the sidewalls of the opening 151b, and a portion of the surface of the second connection conductive layer 370b. The opening 151c exposes the insulating layers 146 and 154, which form the sidewalls of the opening 151c, and a portion of the surface of the drain electrode 144b. The opening 151d exposes the insulating layers 146 and 154, which form the sidewalls of the opening 151d, and a portion of the surface of the source electrode 144a.

[0100] Step S340 is a step of depositing a conductive film to form bumps. Conductive layers 152a to 152c include the conductive film, with conductive layers 152a and 152c functioning as bumps and conductive layer 152b functioning as wiring. Specifically, step S340 uses sputtering and electrochemical plating (ECP) to deposit a conductive film on insulating layer 154, insulating layer 136 that forms the sidewall of opening 151a, gate insulating layer 140, insulating layers 146 and 154, and part of the surface of second connection conductive layer 370a. In step S340, a conductive film is formed by sputtering and electrochemical plating (ECP) on the insulating layer 136, the gate insulating layer 140, the insulating layers 146 and 154 that form the sidewalls of the opening 151b, and a portion of the surface of the second connection conductive layer 370b, on the insulating layers 146 and 154 that form the sidewalls of the opening 151c and a portion of the surface of the drain electrode 144b, and on the insulating layers 146 and 154 that form the sidewalls of the opening 151d and a portion of the surface of the source electrode 144a. In step S340, a conductive film is formed by photolithography and etching on the portion of the insulating layer 154, the insulating layer 136, the gate insulating layer 140, the insulating layers 146 and 154 that form the sidewalls of the opening 151a, and a portion of the surface of the second connection conductive layer 370a. In step S340, similar to the formation of the conductive layer 152a, the conductive layer 152b is formed on part of the insulating layer 154, the insulating layer 136 that forms the sidewall of the opening 151b, the gate insulating layer 140, the insulating layers 146 and 154, part of the surface of the second connection conductive layer 370b, the insulating layers 146 and 154 that form the sidewall of the opening 151d, and part of the surface of the source electrode 144a. In addition, the conductive layer 152c is formed on the insulating layers 146 and 154 that form the sidewall of the opening 151c, and part of the surface of the drain electrode 144b.

[0101] For example, the conductive film formed in step S340 may contain a hydrogen-storing metal. Examples of hydrogen-storing metals include copper, titanium, zirconium (Zr), palladium (Pd), magnesium (Mg), manganese (Mn), and alloys containing at least one of these metals. That is, the conductive layer 152 contains a hydrogen-storing metal. For example, a conductive layer containing at least one of the hydrogen-storing metals may be a conductive layer composed of manganese and copper. By using a conductive layer composed of a layer containing manganese and copper for the conductive layer 152, manganese oxide (MnO) is formed between the conductive layer 152 and the insulating layer in contact with the conductive layer 152. As a result, the display device 10 can suppress copper diffusion into the insulating layer in contact with the conductive layer 152 and absorb hydrogen released from the insulating layer in contact with the conductive layer 152, thereby suppressing deterioration in the electrical characteristics of the transistor 184 having the oxide semiconductor layer 142. Furthermore, since the conductive layer 152 is formed using ECP, it can be formed thicker than the conductive layers 138 and 144. Therefore, the resistance of the signal line, potential line, and wiring including the conductive layer 152 can be reduced.

[0102] Step S350 is a step of forming an insulating layer 118 so as to cover a portion of the surface of the insulating layer 154 and the conductive layers 152a-152c (see FIGS. 11 and 14). Step S350 is also a step of forming an insulating layer 119 on the insulating layer 118 (see FIGS. 11 and 14). Specifically, the insulating layer 118 is formed on the portion of the surface of the insulating layer 154 and the conductive layers 152a-152c by sputtering, and the insulating layer 119 is formed on the insulating layer 118 by using an apparatus (coating apparatus) that coats a film on a substrate surface. The insulating layers 118 and 119 are formed by photolithography and etching. As a result, similar to step S210, grooves 189 are formed around each of the plurality of light-emitting diodes 300.

[0103] For example, the insulating layer 118 is formed using a material similar to that of the insulating layer 116, and the insulating layer 119 is formed using a material similar to that of the insulating layer 380. For example, the insulating layer 118 is formed using an aluminum oxide (AlO) film. Like the insulating layer 116, the insulating layer 118 can prevent hydrogen, water, and the like from entering the insulating layer 154 and the transistor 184 and from diffusing into the insulating layer 154 and the transistor 184. As a result, like the insulating layer 116, the insulating layer 119 can suppress fluctuations in the electrical characteristics of the transistor 184 due to hydrogen, water, and the like. Similarly to the insulating layer 380, the insulating layer 119 can planarize unevenness due to the insulating layer 118 and the conductive layers 152a, 152b, and 152c.

[0104] Step S360 is a step of forming openings 619a and 619b using photolithography and etching. Opening 619a exposes insulating layers 118 and 119 that form sidewalls of opening 619a and a portion of the surface of conductive layer 152a. Opening 619b exposes insulating layers 118 and 119 that form sidewalls of opening 619b and a portion of the surface of conductive layer 152c. Also, similar to step S210, grooves 189 are formed around each of the plurality of light-emitting diodes 300.

[0105] Step S370 is a step of forming a color conversion layer 115 on the second surface 101b of the first substrate 101. Step S370 will be described here with reference to FIG. 11 and FIGS. 15 to 17. As shown in FIG. 16, the second surface 101b side of the array substrate 100 overlaps with the peripheral region 156 and the pixel chip region 185. The peripheral region 156 overlaps with and includes a plurality of alignment markers 157. The pixel chip region 185 overlaps with the bank region 155, a plurality of pixel IC chips 181, and grooves 189, and includes the bank region 155, a plurality of pixel IC chips 181, and grooves 189 (see FIG. 17). The bank region 155 includes a bank 155a. The plurality of alignment markers 157 are used when singulating the plurality of pixel IC chips 181. Specifically, step S370 involves applying acrylic resin using a coating device, and then forming a plurality of alignment markers 157 and banks 155a on the second surface 101b using photolithography and etching. Furthermore, for example, the color conversion layer 115 is applied using a coating device so as to overlap the pixel chip region 185 inside the bank 155a. The bank 155a has the function of preventing the color conversion layer 115 from leaking outside the bank 155a (peripheral region 156). In other words, the bank 155a can prevent the color conversion layer 115 from leaking outside the bank 155a.

[0106] For example, the color conversion layer 115 includes quantum dots. For example, the color conversion layer 115 may include quantum dots that convert blue light emitted by the light emitting diode 300 into red light, or may include quantum dots that convert blue light emitted by the light emitting diode 300 into green light, or may include both. Either the quantum dots that convert blue light into red light or the quantum dots that convert blue light into green light may be formed so as to be coated on each pixel 180.

[0107] As described above, the array substrate 100 is formed.

[0108] Step S380 is a step of singulating the array substrate 100 including a plurality of pixel IC chips 181 into individual pixel chip ICs 181. As a specific example, the array substrate 100 is singulated into individual pixel chip ICs 181 using a laser with reference to the alignment markers 157 (see FIG. 16 ). At this time, the laser singulates the array substrate 100 into individual pixel IC chips 181 along the grooves 189 with reference to the alignment markers 157. As shown in FIG. 17 , the array substrate 100 is singulated so that the length of the pixel IC chips 181 in the first direction D1 is length TW and the length of the pixel IC chips 181 in the second direction D2 is length TH.

[0109] As described above, the pixel IC chip 181 is formed.

[0110] 18 to 21, a method for manufacturing the backplane 200 and a method for bonding the pixel IC chip 181 to the backplane 200 will be described. The method for manufacturing the backplane 200 includes steps S400 to S460. The method for manufacturing the backplane 200 uses a second substrate 201, such as an amorphous glass substrate, as a support substrate.

[0111] Step S400 is a step of forming an underlayer 210 on the first surface 201a of the second substrate 201 so as to be in contact with the first surface 201a (see FIGS. 18 and 19 ). For example, the underlayer 210 can be formed in the same manner using the same material as the underlayer 110 in step S110. Like the underlayer 110, the underlayer 210 can prevent impurities from the second substrate 201 or external impurities (e.g., moisture or sodium (Na)) from diffusing into layers stacked on the underlayer 210.

[0112] Step S410 is a step of depositing a conductive film on the base layer 210 so as to be in contact with the base layer 210 (see FIGS. 18 and 19 ). Step S420 is a step of processing the conductive film deposited in step S410 using photolithography and etching to form a plurality of scanning signal lines 129, driving potential lines 147, and wiring (see FIGS. 18 and 19 ). For example, conductive layers 238a and 238b shown in FIG. 19 include a conductive film, and the conductive layer 238a functions as the scanning signal line 129, and the conductive layer 238b functions as the driving potential line 147a. For example, the conductive layers 238a and 238b can be deposited using the same material as the conductive layers 152a to 152c and formed in the same manner.

[0113] Step S430 is a step of depositing an insulating layer 240 by sputtering on the conductive layers 238a and 238b and on the surface of the base layer 210 so as to be in contact with the conductive layers 238a and 238b and the base layer 210 (see FIGS. 18 and 19 ). For example, the insulating layer 240 can be formed in the same manner as the gate insulating layer 140 and the insulating layer 146 using the same material as the gate insulating layer 140 and the insulating layer 146.

[0114] Step S440 is a step of forming an opening 243 using photolithography and etching (see FIGS. 18 and 19). The opening 243 exposes a part of the surface of the insulating layer 240 and the conductive layer 238b that will become the sidewall of the opening 243.

[0115] Step S450 is a step of depositing a conductive film so as to contact a portion of the surface of the insulating layer 240 and the conductive layer 238b (see FIGS. 18 and 20 ). Step S460 is a step of processing the conductive film deposited in step S450 using photolithography and etching to form a plurality of data signal lines 131, ground wiring 145, first connection conductive layer 244, and wiring (see FIGS. 18 and 20 ). For example, the first connection conductive layers 244a and 244b shown in FIG. 20 include a conductive film, and the first connection conductive layer 244a functions as the ground wiring 145a, while the first connection conductive layer 244b is electrically connected to the conductive layer 238b and functions as the drive potential line 147a. Although not shown, the first connection conductive layers 244c and 244d are formed in the same manner as the first connection conductive layers 244a and 244b by steps S450 and S460. The first connection conductive layer 244c (see FIG. 3) is electrically connected to the conductive layer 238a and functions as the scanning signal line 129. The first connection conductive layer 244d (see FIG. 3) functions as the data signal line 131. For example, the first connection conductive layer 244 can be formed in the same manner as the conductive layers 238a and 238b and the conductive layers 152a to 152c, using the same material. Although not shown, the first connection conductive layer 244c is electrically connected to the scanning signal line 129 via a conductive connection member 620 different from the conductive connection members 620a and 620b. The conductive connection member 620 electrically connecting the first connection conductive layer 244c and the scanning signal line 129 is sometimes called a conductor (third conductor).

[0116] For example, the data signal line 131 (first connecting conductive layer 244d) and the ground wiring 145a (first connecting conductive layer 244a) are formed using copper. The resistance values ​​of the data signal line 131 and the ground wiring 145a can be made smaller than the resistance values ​​of wiring formed using a material with a higher resistivity than copper. As a result, compared to wiring formed using a material with a higher resistivity than copper, the time constant of the signal supplied to the data signal line 131 is improved and the amount of charge supply of the potential supplied to the ground wiring 145a is increased.

[0117] As described above, the backplane 200 is formed.

[0118] Step S470 is a step of bonding the individual pixel IC chips 181 and the backplane 200 together.

[0119] Step S470 is a step of bonding the singulated pixel IC chip 181 and the backplane 200 (see FIGS. 18 and 21 ). An adhesive resin material 610 is formed on the buffer layer 120 using a coating device. The adhesive resin material 610 is then formed using photolithography and etching to surround at least a portion of the periphery of the light-emitting diode 300 and the transistor 184. Furthermore, conductive connecting members 620 a and 620 b are formed on the first connecting conductive layer 244 (here, the first connecting conductive layers 244 a and 244 b). For example, the conductive connecting members 620 a and 620 b may be solder or an anisotropic conductive film (ACF). Furthermore, the pixel IC chip 181 (the first surface 101 a of the array substrate 100) is disposed so as to face the first surface 201 a of the backplane 200, and the pixel IC chip 181 and the backplane 200 are bonded together with the adhesive resin material 610. At this time, conductive connecting members 620a and 620b contact openings 619a and 619b and are electrically connected to conductive layers 152a and 152c. That is, conductive connecting member 620a is electrically connected to light-emitting diode 300 through opening 619a, and conductive connecting member 620b is electrically connected to transistor 184 through opening 619b. Note that, for example, adhesive resin material 610 may be formed on second substrate 201 instead of first substrate 101, and conductive connecting members 620a and 620b may be formed on conductive layers 152a and 152c instead of first connecting conductive layer 244.

[0120] Steps S480 to S500 are steps for pressing the bonded pixel IC chip 181 and backplane 200 together and temporarily curing and fully curing the conductive connecting member 620. The manufacturing method for the display device 10 includes steps S490 and S500, but the manufacturing method for the display device 10 may involve only fully curing the conductive connecting member 620, rather than sequentially temporarily curing and fully curing the conductive connecting member 620 as in steps S490 and S500. By steps S480 to S500, the conductive layer 152a of the pixel IC chip 181 (array substrate 100) is electrically connected to the first connecting conductive layer 244a of the backplane 200 via the conductive connecting member 620a, and the conductive layer 152c of the pixel IC chip 181 (array substrate 100) is electrically connected to the first connecting conductive layer 244b of the backplane 200 via the conductive connecting member 620b.

[0121] As described above, the manufacturing method of the display device 10 can electrically connect the pixel IC chip 181 (first surface 101a of the array substrate 100) and the backplane 200. As a result, the pixel IC chip 181, which includes the light-emitting diode 300 and the first to third transistors 184a to 184c, is electrically connected to the data signal line 131, the scanning signal line 129, the ground wiring 145, and the drive potential line 147 included in the backplane 200.

[0122] When an LED chip is transferred to a backplane including a transistor for driving the LED, and the LED and the transistor are electrically connected, contact resistance may vary depending on the bonding between the LED chip and the transistor. Therefore, a display device in which the LED chip is transferred and connected to the transistor may suffer from degradation in pixel light-emitting characteristics, temperature characteristics, and the like. Meanwhile, the LED 300 and multiple transistors 184 for driving the LED 300 of the display device 10 can be formed on the same first substrate 101. The LED 300 and the pixel circuit 182 including the second transistor 184b for driving the LED 300 are electrically connected on the same first substrate 101. As a result, by transferring the pixel 180 including the LED and the transistor for driving the LED to the backplane as a single pixel IC chip 181, the display device 10 can be completed as a display device with stable contact resistance between the LED and the transistor. Since the current supplied to the light-emitting diode 300 by the second transistor 184 b is stabilized, the display device 10 can suppress deterioration of the light-emitting characteristics and temperature characteristics of the pixel 180 .

[0123] Furthermore, when multiple transistors for driving a light-emitting diode and the light-emitting diode are formed in the same process and arranged in the same layer, the electrical characteristics of the light-emitting diode depend on the electrical characteristics of the multiple transistors. That is, it is difficult to optimally adjust the electrical characteristics of the multiple transistors for driving the light-emitting diode and the light-emitting diode for each device. On the other hand, the multiple transistors 184 for driving the light-emitting diode 300 of the display device 10 are formed in a different process from the light-emitting diode 300 and arranged in a different layer. As a result, the configurations of the multiple transistors 184 and the light-emitting diode 300 can be individually optimized, and the electrical characteristics of the multiple transistors for driving the light-emitting diode and the light-emitting diode can be optimally adjusted for each device.

[0124] Furthermore, for example, because the plurality of transistors 184 include the oxide semiconductor layer 142, the off-state current and leakage current of the transistors 184 are smaller than the leakage current and off-state current of a transistor including amorphous silicon or polysilicon. Furthermore, the temperature characteristics of the off-state current of a transistor formed using an oxide semiconductor layer are superior to the temperature characteristics of the off-state current of a transistor formed using amorphous silicon or polysilicon. As a result, the display device 10 can suppress degradation of the electrical characteristics of the light-emitting diode 300 due to the leakage current of the transistor 184. Furthermore, the display device 10 can suppress degradation of the temperature characteristics due to the off-state current and leakage current of the transistor 184.

[0125] Furthermore, the display device 10 includes a protection circuit (third transistor 184c) for protecting the light-emitting diode 300 on the first substrate 101. Therefore, for example, there is no need to mount a protection circuit on a separate chip, and the light-emitting diode 300 is protected by the protection circuit formed on the first substrate 101, thereby ensuring, for example, ESD resistance.

[0126] As a result, the deterioration of the long-term reliability of the display device 10 is suppressed.

[0127] 2. Second Embodiment The configuration of a display device 20 will be described with reference to FIGS.

[0128] [2-1. Overview of Display Device 20] An overview of the display device 20 will be described with reference to Fig. 22. Fig. 22 is a schematic plan view showing the configuration of the display device 20. Configurations that are the same as or similar to those in Figs. 1 to 21 will be described as necessary.

[0129] Compared to the display device 10, the display device 20 includes at least a plurality of scanning signal line driving circuits 104, a plurality of pixels 180A, and a plurality of protection circuits 460. The display device 20 also includes a backplane 200A that is different from the backplane 200 of the display device 10. The display device 20 includes a plurality of scanning signal line driving circuits 104 and a plurality of protection circuits 460. The other configuration of the display device 20 is the same as that of the display device 20. Therefore, the configuration of the display device 20 will be described as necessary.

[0130] The display device 20 includes a plurality of pixel IC chips 181 and a backplane 200A electrically connected to the plurality of pixel IC chips 181.

[0131] The plurality of scanning signal line driver circuits 104 are arranged on the first substrate 101 and overlap with the peripheral region 121. One of the plurality of scanning signal line driver circuits 104 is arranged on the first side 191 side, and the other of the plurality of scanning signal line driver circuits 104 is arranged on the second side 192 side. The plurality of scanning signal line driver circuits 104 includes a plurality of transistors 484.

[0132] In describing the transistors included in pixel 180A, when the transistors are not to be distinguished, they are referred to as transistor 484, and when the transistors are to be distinguished, they are given individual reference symbols such as transistor 484a.

[0133] For example, some of the terminals 150 in the terminal region 126 are electrically connected to the scanning signal line driving circuit 104 on the first side 191 side using the connection wiring 141. For example, the driving potential line 147 is disposed between some of the terminals 150 in the terminal region 126 and the scanning signal line driving circuit 104 on the second side 192 side, and is electrically connected to some of the terminals 150 in the terminal region 126 and the scanning signal line driving circuit 104 on the second side 192 side. For example, the driving potential lines 147a, 147b, and 147c extend in the D1 direction from the scanning signal line driving circuit 104 on the first side 191 side and are connected to the plurality of pixels 180A arranged in the D1 direction. For example, a plurality of scanning signal lines including the scanning signal lines 129a, 129b, and 129c are electrically connected to the scanning signal line driving circuit 104 on the second side 192 side, extend in the D1 direction, and are connected to the plurality of pixels 180A arranged in the D1 direction. The electrical connections among the terminal 150, the connection wiring 141, the plurality of scanning signal line drive circuits 104, the drive potential lines 147, 147a, 147b, and 147c, and the scanning signal lines 129a, 129b, and 129c are not limited to the configuration shown in Fig. 22. For example, the scanning signal line drive circuit 104 on the first side 191 side and the scanning signal line drive circuit 104 on the second side 192 side may be symmetrically exchanged with respect to a virtual line parallel to the first direction D2, and the respective wirings may be exchanged. Furthermore, the drive potential lines 147, 147a, 147b, and 147c may be directly connected between the terminal 150 and each pixel 180A without being electrically connected to the scanning signal line drive circuit 104, as in the display device 20.

[0134] The pixel 180A includes a pixel IC chip 181. As will be described in detail later, the layered structure of the pixel 180A is different from the layered structure of the pixel 180. Specifically, the layered structure of the backplane 200A of the pixel 180A is different from the layered structure of the backplane 200 of the pixel 180.

[0135] Although details will be described later, the protection circuit 460 is disposed between the terminal 150 and each signal line. For example, the protection circuit 460 is electrically connected to the data signal line 131 and the terminal 150. Furthermore, for example, the protection circuit 460 is disposed between the connection wiring 141 and the terminal 150, and the protection circuit 460 is electrically connected to the connection wiring 141 and the terminal 150.

[0136] The second substrate 401 includes a first side 191, a second side 192 opposite to the first side, a third side 193, and a fourth side 194 opposite to the third side. The display area 122 and the peripheral area 121 are surrounded by the first side 191, the second side 192 opposite to the first side, the third side 193, and the fourth side 194 opposite to the third side 193 in a plan view.

[0137] As an example, the driver IC 106 is disposed on the FPC 108. The driver IC 106 supplies control signals for driving the plurality of pixels 180A to the plurality of pixels 180A via the FPC 108, the plurality of scanning signal line drive circuits 104, the plurality of connection wirings 141, the plurality of data signal lines 131, the ground wiring 145, and the drive potential line 147.

[0138] [2-2. Example of a Cross Section of the Display Device 20] An example of a cross section of the display device 20 will be described with reference to FIGS. 23 and 24. FIG. 23 is a cross-sectional view showing an example of the cross-sectional structure of a pixel 180A of the display device 20. Specifically, it is a cross-sectional view showing an example of the cross-sectional structure of the pixel 180A taken along line B1-B2 shown in FIG. 22. FIG. 24 is a cross-sectional view showing an example of the cross-sectional structure of a peripheral region 121 and a portion of the display region 122 of the display device 20. Specifically, it is a cross-sectional view showing an example of the cross-sectional structure of a peripheral region 121 and a portion of the display region 122 taken along line C1-C2 shown in FIG. Configurations that are the same as or similar to those in FIGS. 1 to 22 will be described as necessary.

[0139] The display device 20 includes an array substrate 100 (pixel IC chips 181) and a backplane 200 A. The array substrate 100 includes the same configuration as the array substrate 100 of the display device 20, and therefore a description thereof will be omitted here.

[0140] 23 and 24 , the backplane 200A includes a second substrate 401, a protective layer 417, a base layer 436, conductive layers 238a, 238b, and 438c, first connecting conductive layers 244a and 244b, a source electrode 444a, a drain electrode 444b, an oxide semiconductor layer 442, a gate insulating layer 440, an insulating layer 446, an insulating layer 454, and an insulating layer 456. Also, as shown in FIG. 24 , the backplane 200A includes a scanning signal line 129a and a transistor 484a. The transistor 484a includes at least the source electrode 444a, the drain electrode 444b, the oxide semiconductor layer 442, a portion of the gate insulating layer 440, and a portion of the insulating layer 446.

[0141] The second substrate 401 is a substrate (second support substrate) that supports the multiple terminals 150, the multiple scanning signal line driving circuits 104, the multiple scanning signal lines 129 including the scanning signal line 129a, the multiple data signal lines 131, the ground wiring 145, and the driving potential line 147. The second substrate 401 includes a first surface 401a and a second surface 401b facing the first surface 401a. The protective layer 417, the underlayer 436, the conductive layers 238a, 238b, and 438c, the first connecting conductive layers 244a and 244b, the source electrode 444a, the drain electrode 444b, the oxide semiconductor layer 442, the gate insulating layer 440, the insulating layer 446, the insulating layer 454, and the insulating layer 456 are disposed on the first surface 401a.

[0142] The protective layer 417 is disposed on the first surface 401 a of the second substrate 401. The protective layer 417 can prevent the diffusion of impurities from the second substrate 401 or external impurities (e.g., moisture or sodium (Na)).

[0143] The base layer 436 is disposed on the protective layer 417. Like the protective layer 417, the base layer 436 can prevent diffusion of impurities from the second substrate 401 or external impurities (for example, moisture or sodium (Na)).

[0144] The conductive layers 238a, 238b, and 438c are disposed on the base layer 436. The conductive layer 238a functions as the scanning signal line 129a. The conductive layer 238b functions as the driving potential line 147a. The conductive layer 438c functions as the gate electrode of the transistor 484a.

[0145] The gate insulating layer 440 is disposed on the conductive layers 238a, 238b, and 438c and on a portion of the base layer 436. That is, the gate insulating layer 440 is disposed so as to cover the plurality of scanning signal lines 129, the driving potential line 147a, and the gate electrode of the transistor 484a. The gate insulating layer 440 insulates the plurality of scanning signal lines 129, the driving potential line 147a, and the gate electrode of the transistor 484a from one another.

[0146] The oxide semiconductor layer 442 is disposed over the gate insulating layer 440. The oxide semiconductor layer 442 is used for channels of a plurality of transistors 484. The plurality of transistors 484 includes a transistor 484a.

[0147] The source electrode 444a and the drain electrode 444b are disposed on the oxide semiconductor layer 442 and the gate insulating layer 440. The source electrode 444a and the drain electrode 444b are electrically connected to the oxide semiconductor layer 442. The source electrode 444a and the drain electrode 444b of the display device 20 are connected to and in direct contact with the oxide semiconductor layer 442. Note that in the description of the source electrode, the drain electrode, and the wiring formed in the same layer as the source electrode and the drain electrode included in the pixel 180A, when the source electrode, the drain electrode, and the wiring are not distinguished from each other, the source electrode, the drain electrode, and the wiring are referred to as a conductive layer 444, and when the source electrode, the drain electrode, and the wiring are distinguished from each other, the source electrode, the drain electrode, and the wiring are given individual reference symbols such as the source electrode 444a, the drain electrode 444b, etc.

[0148] An insulating layer 454 is disposed on the insulating layer 446. An insulating layer 456 is disposed on the insulating layer 454. A portion of the insulating layer 456 is opened. Also, a portion of the insulating layer 454 and a portion of the insulating layer 456 are opened to expose the conductive layer 238b.

[0149] The first connection conductive layer 244a is disposed on the exposed portion of the insulating layer 456. The first connection conductive layer 244b is disposed on the exposed conductive layer 238b and electrically connected to the conductive layer 238b. The first connection conductive layers 244a and 244b are formed on different layers in the same process. For example, as shown in FIG. 4, the first connection conductive layer 244a extends in the second direction D2 and branches out and extends in the first direction D1. Although not shown, the first connection conductive layer 244a is disposed so as to overlap the gate insulating layer 440. For example, the first connection conductive layer 244b extends in the first direction D1 and the second direction D2 as shown in FIG. 3. The first connection conductive layer 244b may be disposed so as to overlap the gate insulating layer 440.

[0150] An adhesive resin material 610 is disposed on a portion of the insulating layer 456. The adhesive resin material 610 is formed so as to surround at least a portion of the periphery of the light-emitting diode 300 and the transistor 184, as in the cross-sectional view shown in FIG. 24 . Furthermore, for example, the adhesive resin material 610 is disposed on a portion of the insulating layer 456 so as to overlap with the display region 122 but not with the peripheral region 121, as in the cross-sectional view shown in FIG. 23 . Note that the adhesive resin material 610 may overlap with the peripheral region 121. Furthermore, in order to prevent damage to the display device 20, the peripheral region 121 of the display device 20 (the periphery of the adhesive resin material 610) may be sealed with a resin or the like.

[0151] The first surface 101a of the pixel IC chip 181 (array substrate 100) faces the first surface 401a of the backplane 200A, and the array substrate 100 is bonded to the backplane 200A. Specifically, the array substrate 100 and the backplane 200A are bonded together using an adhesive resin material 610. As a result, the array substrate 100 is electrically connected to the backplane 200A via conductive connecting members 620a and 620b. Specifically, the conductive layer 152a of the array substrate 100 is electrically connected to the first connecting conductive layer 244a of the backplane 200A via the conductive connecting member 620a, and the conductive layer 152c of the array substrate 100 is electrically connected to the first connecting conductive layer 244b of the backplane 200A via the conductive connecting member 620b. For example, the conductive layer 238b and the first connecting conductive layer 244b may overlap the second transistor 184b. The conductive layer 238b (the first connection conductive layer 244b) and the oxide semiconductor layer 142 can form a capacitor 188 with the insulating layers 119, 118, 154, and 146 interposed therebetween.

[0152] The display device 20 having the above-described configuration has the same effects as the display device 10. Furthermore, since the peripheral region 121 of the display device 20 includes the scanning signal line driving circuit 104, the display device 20 can reduce the step caused by the thickness of the peripheral region 121 and the thickness of the display region 122 more effectively than a display device that does not include the scanning signal line driving circuit 104.

[0153] [2-3. Example of a Manufacturing Method of the Display Device 20] An example of a manufacturing method of the display device 20 will be described with reference to Figures 25 to 30. Figure 25 is a flowchart showing an example of a manufacturing method of the backplane 200A and an example of a method of bonding the pixel IC chip 181 and the backplane 200A. Figures 26 to 30 are cross-sectional views showing an example of a cross-sectional structure in the manufacturing process of the backplane 200A. Configurations that are the same as or similar to those in Figures 1 to 24 will be explained as necessary. Furthermore, the manufacturing method of the array substrate 100 is the same as the manufacturing method of the array substrate 100 of the display device 10 explained in "1-5", and the manufacturing method of the array substrate 100 will be explained as necessary.

[0154] The method for manufacturing the backplane 200A includes steps S700 to S810. Similar to the method for manufacturing the backplane 200, the method for manufacturing the backplane 200A uses a second substrate 401 such as an amorphous glass substrate as a support substrate.

[0155] Step S700 is a step of forming a protective layer 417 on the first surface 401a of the second substrate 401 so as to be in contact with the first surface 401a (see FIGS. 25 and 26 ). For example, the protective layer 417 is formed on the first surface 401a using CVD, using a material similar to that of the insulating layer 117 in step S210. The protective layer 417 can prevent impurities from the second substrate 401 or external impurities (e.g., moisture or sodium (Na)) from diffusing into layers stacked on the base layer 436.

[0156] Step S710 is a step of forming an underlayer 436 on the protective layer 417 so as to be in contact with the protective layer 417 (see FIGS. 25, 26, and 27). For example, the underlayer 436 can be formed in the same manner using the same material as the underlayer 110 in step S110. Like the protective layer 417, the underlayer 436 can prevent impurities from the second substrate 401 or external impurities (e.g., moisture or sodium (Na)) from diffusing into layers stacked on the underlayer 436.

[0157] Step S720 is a step of depositing a conductive film on the base layer 436 so as to be in contact with the base layer 436 (see FIGS. 25, 26, and 27). Furthermore, step S730 is a step of processing the conductive film deposited in step S720 using photolithography and etching to form gate electrodes of multiple transistors, the scanning signal line 129a and the multiple scanning signal lines 129, the driving potential lines 147, 147a, 147b, and 147c, and various wirings. For example, the conductive layers 238a and 238b shown in FIG. 26 include conductive films, and the conductive layer 238a functions as the scanning signal line 129a, and the conductive layer 238b functions as the driving potential line 147a. Furthermore, the conductive layer 438c and the scanning signal line 129a shown in FIG. 27 include conductive films, and the conductive layer 438c functions as the gate electrode of the transistor 484a. For example, the conductive layers 238a and 238b, the conductive layer 438c, and the scanning signal line 129a are formed by sputtering using the same material as the conductive layer 138 formed in step S250, and are formed by photolithography and etching in the same manner as in step S260.

[0158] Step S740 is a step of depositing a gate insulating layer 440 by CVD over the conductive layers 238a and 238b, the conductive layer 438c and the scanning signal line 129a, and the surface of the base layer 436 so as to be in contact with the conductive layers 238a and 238b, the conductive layer 438c and the scanning signal line 129a, and the base layer 436 (see FIGS. 25, 26, and 27). For example, the gate insulating layer 440 can be deposited by CVD using the same material as the gate insulating layer 140.

[0159] Step S750 is a step of depositing an oxide semiconductor layer 442 by sputtering over the gate insulating layer 440 so as to be in contact with the gate insulating layer 440 (see FIGS. 25, 26, and 27). For example, the oxide semiconductor layer 442 is deposited over the gate insulating layer 440 using the same material as the oxide semiconductor layer 142.

[0160] In Step S760, the oxide semiconductor layer 442 formed in Step S750 is processed by photolithography and etching to form the oxide semiconductor layer 442 used as the semiconductor layer of each of the transistors 484 (see FIGS. 25, 26, and 27). Note that after Step S760, for example, an opening 441a is formed by photolithography and etching. The opening 441a exposes part of the surface of the gate insulating layer 440 and the scanning signal line 129a, which form the sidewall of the opening 441a.

[0161] Step S770 is a step of depositing a conductive layer 444 by sputtering over the oxide semiconductor layer 442, part of the surface of the scanning signal line 129a, the sidewall of the opening 441a, and part of the gate insulating layer 440, so as to be in contact with the oxide semiconductor layer 442, part of the surface of the scanning signal line 129a, the sidewall of the opening 441a, and part of the gate insulating layer 440. For example, the conductive layer 444 can be formed using a material similar to that of the conductive layer 144.

[0162] Step S780 is a step of processing the conductive layer 444 formed in step S770 by photolithography and etching to form a source electrode, a drain electrode, and a wiring (see FIGS. 25 and 29). The conductive layer 444 functions as a source electrode, a drain electrode, or a wiring. For example, the conductive layer 444 shown in FIG. 29 is a source electrode 444a and a drain electrode 444b.

[0163] Step S790 is a step of depositing an insulating layer 446 over the conductive layer 444, over part of the oxide semiconductor layer 442, and over part of the gate insulating layer 440 by CVD so as to be in contact with the conductive layer 444, part of the oxide semiconductor layer 442, and part of the gate insulating layer 440; depositing an insulating layer 454 over the insulating layer 446 so as to be in contact with the insulating layer 446; and depositing an insulating layer 456 over the insulating layer 454 so as to be in contact with the insulating layer 454 (see FIGS. 25 , 28 , and 29 ). For example, the insulating layer 446 can be formed using a material similar to that of the gate insulating layer 440. The insulating layer 454 can be formed using a material similar to that of the insulating layer 380. Like the insulating layer 380, the insulating layer 454 can planarize unevenness due to the transistor 484 and the insulating layer 446. The insulating layer 456 can be formed using a material similar to that of the insulating layer 117. Like the insulating layer 117, the insulating layer 456 can prevent external impurities (for example, moisture or sodium (Na)) from diffusing into layers below the insulating layer 456.

[0164] Step S800 is a step of forming openings 443a and 443b using photolithography and etching. The opening 443a exposes insulating layers 446, 454, and 456, which form the sidewalls of the opening 443a, and a portion of the surface of the conductive layer 238b. The opening 443b exposes insulating layers 456 and 454, which form the sidewalls of the opening 443b (see FIGS. 25 and 28).

[0165] Step S810 is a step of forming a conductive layer. Specifically, this is a step of depositing a conductive film so as to contact the insulating layers 446, 454, and 456 that form the sidewalls of the opening 443a, a portion of the surface of the conductive layer 238b, the insulating layer 456 that forms the sidewall of the opening 443b, and a portion of the surface of the insulating layer 454 (see FIGS. 25 and 30 ). For example, the conductive film is deposited on the insulating layers and the conductive layer using sputtering and ECP, as in step S340. Furthermore, for example, the deposited conductive layer is polished using CMP to be planarized until the surface of the insulating layer 456 is exposed. As a result, the first connection conductive layers 244a and 244b can be formed. 30 includes a conductive film, the first connection conductive layer 244a functions as a ground wiring 145a, and the first connection conductive layer 244b is electrically connected to the conductive layer 238b and functions as a driving potential line 147a. Although not shown, the first connection conductive layers 244c and 244d are formed in the same manner as the first connection conductive layers 244a and 244b. The first connection conductive layer 244c (see FIG. 3) is electrically connected to the conductive layer 238a and functions as a scanning signal line 129. The first connection conductive layer 244d (see FIG. 3) functions as a data signal line 131.

[0166] The conductive film formed in step S810 can be made of the same material as the conductive film formed in step S340. For example, the conductive film can be made of a conductive layer composed of manganese and copper. As a result, the display device 20 can suppress copper diffusion into the insulating layer in contact with the first connecting conductive layer 244 and absorb hydrogen released from the insulating layer in contact with the first connecting conductive layer, thereby suppressing degradation of the electrical characteristics of the transistor 484. Furthermore, because the first connecting conductive layer 244 is formed using ECP, it can be formed thicker than films and layers formed using sputtering or CVD. Therefore, the resistance values ​​of the data signal line 131 (first connecting conductive layer 244d) and the ground wiring 145a (first connecting conductive layer 244a) formed using the first connecting conductive layer 244 can be made even smaller than the resistance values ​​of wiring formed using a material with a higher resistivity than copper. As a result, compared to wiring formed using a material with a higher resistivity than copper, the time constant of the signal supplied to the data signal line 131 is improved and the amount of charge supplied to the ground wiring 145a is increased.

[0167] As described above, the backplane 200A is formed.

[0168] Steps S820 to S850 are the same as steps S450 to S500, and therefore, a description of steps S820 to S850 will be omitted here.

[0169] As described above, the manufacturing method of the display device 20 can electrically connect the pixel IC chip 181 (first surface 101a of the array substrate 100) and the backplane 200A. As a result, the pixel IC chip 181, which includes the light-emitting diode 300 and the first to third transistors 184a to 184c, is electrically connected to the data signal line 131, the scanning signal line 129, the ground wiring 145, and the drive potential line 147 included in the backplane 200A.

[0170] The manufacturing method of the display device 20 including the above-described configuration has the same effects as the manufacturing method of the display device 10. Furthermore, since the manufacturing method of the display device 20 includes forming the scanning signal line driving circuit 104 in the peripheral region 121, it is possible to reduce the number of components mounted on the display device 20 compared to when an IC chip including a scanning signal line driving circuit is mounted on the display device 20. As a result, the manufacturing method of the display device 20 is a manufacturing method that can reduce costs.

[0171] Furthermore, the transistor 484 included in the backplane 200A can be covered on the second substrate 401 side, the second substrate 401 side, and the third direction D3 side with insulating layers 471 and 456 using AlO. As a result, for example, it is possible to prevent impurities (e.g., moisture or sodium (Na)) from diffusing into the transistor 484. As a result, the manufacturing method of the display device 20 can suppress deterioration of the electrical characteristics of the transistor 484.

[0172] [2-4. Example of Protection Circuit 460] An example of the protection circuit 460 will be described with reference to Fig. 31. Fig. 31 is a plan view showing an example of the protection circuit 460. Configurations that are the same as or similar to those in Figs. 1 to 30 will be described as necessary.

[0173] The protection circuit 460 is electrically connected to the terminal 150 and the data signal line 131 connected to the terminal 150. The protection circuit 460 includes transistors 484b and 484c, and the conduction states of the transistors 484b and 484c are controlled by signals supplied to signal lines or wiring electrically connected to the protection circuit 460. The transistor 484b includes a gate electrode 4G, a source electrode 4S, and a drain electrode 4D. The transistor 484c includes a gate electrode 5G, a source electrode 5S, and a drain electrode 5D. The source electrode 4S is electrically connected to the drive potential line 147, and the drain electrode 4D is electrically connected to the gate electrode 4G, the data signal line 131, and the source electrode 5S. The drain electrode 5D is electrically connected to the gate electrode 5G and the ground wiring 145.

[0174] The drain electrode 4D is electrically connected to the gate electrode 4G and the data signal line 131. Therefore, when the potential supplied to the data signal line 131 is higher than the potential supplied to the driving potential line 147, the transistor 484b is brought into a conductive state and functions as a protection circuit. In other words, when an overvoltage is supplied to the data signal line 131 via the terminal 150, a current can be made to flow from the drain electrode 4D to the driving potential line 147 via the transistor 484b. As a result, the transistor 484b can suppress the application of an overvoltage and the supply of an overcurrent to the data signal line 131.

[0175] Furthermore, the drain electrode 5D is electrically connected to the gate electrode 5G and the ground wiring 145. Therefore, when the potential supplied to the source electrode 5S is lower than the potential supplied to the ground wiring 145, the transistor 484c is brought into a conductive state and functions as a protection circuit. In other words, when an overvoltage is supplied to the data signal line 131 via the terminal 150, a current can be passed from the ground wiring 145 to the source electrode 5S via the transistor 484c. As a result, the transistor 484c can suppress the application of an overvoltage and the supply of an overcurrent to the data signal line 131.

[0176] Like the transistor 484a and the plurality of transistors 184, the transistors 484b and 484c include an oxide semiconductor layer 442 and are formed over the second substrate 401. As a result, the leakage current and off-state current of the transistors 484b and 484c are smaller than those of a transistor containing amorphous silicon or polysilicon. Therefore, the leakage current and off-state current of the protection circuit 460 are small, which can efficiently prevent application of an overvoltage and supply of an overcurrent to the data signal line 131. Furthermore, the protection circuit 460 can prevent deterioration of electrical characteristics due to leakage current and off-state current. Furthermore, the temperature characteristics of the off-state current of a transistor formed using an oxide semiconductor layer are superior to those of a transistor formed using amorphous silicon or polysilicon. Therefore, the display device 20 includes a protection circuit using a transistor with excellent temperature characteristics, which can prevent deterioration of long-term reliability.

[0177] The above-described embodiments of the present invention or parts of the embodiments can be combined as appropriate as long as they are not mutually inconsistent.

[0178] Even if there are other effects and advantages different from those brought about by the aspects of each of the above-mentioned embodiments, those that are clear from the description in this specification or that can be easily predicted by a person skilled in the art are naturally understood to be brought about by the present invention.

[0179] 1D: drain electrode, 1G: gate electrode, 1S: source electrode, 2D: drain electrode, 2G: gate electrode, 2S: source electrode, 3D: drain electrode, 3G: gate electrode, 3S: source electrode, 4D: drain electrode, 4G: gate electrode, 4S: source electrode, 5D: drain electrode, 5G: gate electrode, 5S: source electrode, 6F: cathode (n-type electrode), 6S: anode (p-type electrode), 8F: first electrode, 8S: second electrode, 10: display device, 20: display device, 100: array substrate, 101: first substrate, 101a: first surface, 101b: second surface, 104: scanning signal line driver driving circuit, 106: driver IC, 108: flexible printed circuit board (FPC), 110: underlayer, 111: crystalline polysilicon, 115: color conversion layer, 116: insulating layer, 117: insulating layer, 118: insulating layer, 119: insulating layer, 120: buffer layer, 121: peripheral region, 122: display region, 126: terminal region, 129: scanning signal line, 129a: scanning signal line, 129b: scanning signal line, 129c: scanning signal line, 131: data signal line, 136: insulating layer, 138: conductive layer, 138a: gate electrode, 139: opening, 140: gate insulating layer, 140a: opening, 1 40b: opening, 141: connection wiring, 142: oxide semiconductor layer, 144: conductive layer, 144a: source electrode, 144b: drain electrode, 145: ground wiring, 145a: ground wiring, 145b: ground wiring, 145c: ground wiring, 146: insulating layer, 147: driving potential line, 147a: driving potential line, 147b: driving potential line, 147c: driving potential line, 150: terminal, 151a: opening, 151b: opening, 151c: opening, 151d: opening, 152: conductive layer, 152a: conductive layer, 152b: conductive layer, 152c: conductive layer, 154: insulating layer, 155: barrier bank region, 155a: bank, 156: peripheral region, 157: alignment marker, 180: pixel, 180A: pixel, 181: pixel IC chip, 182: pixel circuit, 184: transistor, 184a: first transistor, 184b: second transistor, 184c: third transistor, 185: pixel chip region, 188: capacitance element, 189: groove, 191: first side, 192: second side, 193: third side, 194: fourth side, 200: backplane, 200A: backplane, 201: second substrate, 201a: first surface, 201b: second surface,210: Underlayer, 238: Conductive layer, 238a: Conductive layer, 238b: Conductive layer, 240: Insulating layer, 243: Opening, 244: First connecting conductive layer, 244a: First connecting conductive layer, 244b: First connecting conductive layer, 244c: First connecting conductive layer, 244d: First connecting conductive layer, 245b: First connecting conductive layer, 246: Insulating layer, 300: Light-emitting diode, 310: Gallium nitride layer, 320: N-type semiconductor layer, 330: Light-emitting layer, 340: P-type semiconductor layer, 350: N-type electrode, 360: P-type electrode, 370a: Second connecting conductive layer, 370b: Second connecting conductive layer, 372a: Opening, 372b: Opening, 380: Insulating layer, 401: second substrate, 401a: first surface, 401b: second surface, 417: protective layer, 436: base layer, 438c: conductive layer, 440: gate insulating layer, 441a: opening, 442: oxide semiconductor layer, 443a: opening, 443b: opening, 444: conductive layer, 444a: source electrode, 444b: drain electrode, 446: insulating layer, 454: insulating layer, 456: insulating layer, 460: protection circuit, 471: insulating layer, 484: transistor, 484a: transistor, 484b: transistor, 484c: transistor, 610: adhesive resin material, 619a: opening, 619b: opening, 620: conductive connecting member, 620a: conductive connecting member,

Claims

1. A first substrate, a light-emitting diode disposed on a first surface of the first substrate and including a gallium nitride layer, a first transistor disposed on the light-emitting diode and electrically connected to the light-emitting diode, a second substrate facing the first substrate, a data signal line disposed on the second substrate, a ground wiring disposed on the second substrate, a first conductor disposed on the data signal line and electrically connecting the data signal line and the first transistor, and a second conductor disposed on the ground wiring and electrically connecting the ground wiring and the light-emitting diode. A display device comprising.

2. The display device according to claim 1, wherein the first substrate is a sapphire substrate or an amorphous glass substrate, and the second substrate is an amorphous glass substrate.

3. The display device according to claim 1, wherein the first transistor includes an oxide semiconductor layer.

4. The display device according to claim 1, wherein the data signal line is disposed in the same layer as the ground wiring.

5. The display device further includes a second transistor and a third transistor, the second transistor is electrically connected to the data signal line and the first transistor, and the third transistor is electrically connected to the first transistor and the ground wiring and is connected in parallel to the light-emitting diode. The display device according to claim 4.

6. The display device further includes a scanning signal line and a third conductor, the scanning signal line is disposed between the second substrate and the same layer, and is electrically connected to the first transistor via the third conductor. The display device according to claim 4.

7. The display device according to claim 6, wherein the data signal line, the ground wiring, and the scanning signal line include a conductive layer containing copper and manganese.

8. The display device further includes a first planarization film, and the first planarization film is disposed between the light-emitting diode and the first transistor. The display device according to claim 3.

9. The display device further includes a first insulating layer, a second insulating layer, and a third insulating layer, wherein the first insulating layer is disposed to cover the light-emitting diode, the second insulating layer is disposed to contact the first planarization film, the third insulating layer is disposed on the first transistor, and the display device according to claim 8, wherein the first insulating layer, the second insulating layer, and the third insulating layer contain aluminum oxide.

10. The first transistor includes a source electrode, a gate electrode, and a drain electrode, wherein the source electrode and the drain electrode are spaced apart from each other in the same layer and disposed to contact the oxide semiconductor layer, and the display device according to claim 9, wherein the source electrode and the drain electrode include a conductive layer containing titanium.

11. The display device further includes a second planarization film, wherein the second planarization film is disposed on the first transistor and includes a first opening and a second opening, wherein the first conductor is disposed in the first opening and electrically connected to the first transistor, and the second conductor is disposed in the second opening and electrically connected to the light-emitting diode. The display device according to claim 1.

12. The display device further includes a color conversion layer configured to be capable of converting the color of light emitted by the light-emitting diode into a color different from the color, wherein the first substrate includes a second surface opposite to the first surface, and the color conversion layer is disposed on the second surface. The display device according to claim 1.

13. The display device further includes a driver IC, wherein the driver IC is electrically connected to the data signal line, the ground wiring, and the scanning signal line and configured to be capable of controlling the light-emitting diode. The display device according to claim 6.

14. The display device further includes a driving circuit disposed on the second substrate, wherein the driving circuit is electrically connected to the scanning signal line. The display device according to claim 6.

15. The driving circuit includes a plurality of transistors different from the first transistor, wherein the plurality of transistors include an oxide semiconductor layer. The display device according to claim 14.

16. The display device further includes a protection circuit disposed on the second substrate, the protection circuit being electrically connected to the data signal line and including a transistor different from the first transistor and the plurality of transistors, the transistor different from the first transistor and the plurality of transistors including an oxide semiconductor layer, the display device according to claim 15.

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