Light detection device

Abstract

[Problem] To avoid an adverse effect due to dielectric absorption charge. [Solution] This light detection device comprises a photoelectric conversion element, a floating diffusion region that holds a charge photoelectrically converted by the photoelectric conversion element, a first capacitor that holds a charge corresponding to the held charge of the floating diffusion region, and a charge cancellation part that cancels the dielectric absorption charge discharged from the first capacitor after charge held by the first capacitor is discharged.

Description

Photodetector

[0001] The present disclosure relates to a light detection device.

[0002] To expand the dynamic range of a photodetector, an overflow driving method is known in which charge overflowing from a photodiode (PD) (hereinafter referred to as overflow charge) is stored in a floating diffusion (FD) and read out, thereby detecting charge exceeding the storage capacity of the PD. Another proposed method expands the dynamic range by directly or indirectly connecting multiple capacitors for holding the overflow charge to the FD and sequentially reading out the charge held in each capacitor as signals with different gains, thereby increasing the sensitivity on the high-illuminance side without reducing the sensitivity on the low-illuminance side (see Patent Document 1).

[0003] Japanese Patent Application Laid-Open No. 2006-245522

[0004] Capacitors that hold overflowing charges are required to have a high capacitance, and for this reason, capacitors with a high dielectric constant MIM (Metal Insulator Metal) structure using high-k materials are sometimes used.

[0005] However, high-dielectric-constant films have a problem in that dielectric absorption charges are generated after the electric charge is discharged. The dielectric absorption charges may cause afterimages in captured images, which may degrade the image quality of the captured images.

[0006] Therefore, the present disclosure provides a photodetector that can avoid the adverse effects of dielectrically absorbed charges.

[0007] In order to solve the above problems, the present disclosure provides a photodetector device comprising: a photoelectric conversion element; a floating diffusion region that holds charges photoelectrically converted by the photoelectric conversion element; a first capacitor that holds charges corresponding to the charges held in the floating diffusion region; and a charge cancellation section that cancels out dielectric absorption charges discharged from the first capacitor after the charges held in the first capacitor are discharged.

[0008] The image sensor may include a signal processing unit that generates an image for each frame based on pixel signals photoelectrically converted by a plurality of the photoelectric conversion elements, and the charge cancellation unit may include: a second capacitor that has a capacitance corresponding to the capacitance of the first capacitor and is connected to the first capacitor; and a switching circuit that alternately switches the connection between the first capacitor and the second capacitor for each frame, thereby canceling out the dielectric absorption charge discharged from the first capacitor with the dielectric absorption charge discharged from the second capacitor.

[0009] The switching circuit may alternately switch, for each frame, between connecting the upper electrode of the first capacitor to the upper electrode of the second capacitor and connecting the lower electrode of the first capacitor to the lower electrode of the second capacitor, or connecting the upper electrode of the first capacitor to the lower electrode of the second capacitor and connecting the lower electrode of the first capacitor to the upper electrode of the second capacitor.

[0010] The second capacitor may have a capacitance equal to or less than that of the first capacitor.

[0011] The first capacitor and the second capacitor may have the same structure made of the same material and may be arranged in the same layer.

[0012] The first capacitor and the second capacitor may each include a high-k film disposed between two electrodes.

[0013] The semiconductor device may comprise a first substrate on which the plurality of photoelectric conversion elements are arranged, and a second substrate stacked on the first substrate and on which the signal processing unit is arranged, wherein the first capacitor, the second capacitor, and the switching circuit may each be arranged on the first substrate or the second substrate.

[0014] The semiconductor device may comprise a first substrate on which the plurality of photoelectric conversion elements are arranged, a second substrate stacked on the first substrate and on which the signal processing unit is arranged, and a third substrate stacked between the first substrate and the second substrate and on which the first capacitor and the second capacitor are arranged, and the switching circuit may be arranged on the first substrate, the second substrate, or the third substrate.

[0015] The floating diffusion region has a first floating diffusion region and a second floating diffusion region, and further includes a first transistor that transfers charges photoelectrically converted by the photoelectric conversion element to the first floating diffusion region, and a second transistor that transfers at least a portion of the charges held in the first floating diffusion region directly or indirectly to the second floating diffusion region, and the first capacitor and the second capacitor may hold at least a portion of the charges held in the second floating diffusion region.

[0016] The pixel circuit may include a pixel circuit that reads out a pixel signal at a signal level based on the amount of charge in the first floating diffusion region, the second floating diffusion region, the first capacitor, and the second capacitor that is held in accordance with the charge overflowing due to photoelectric conversion of the photoelectric conversion element, and then reads out a pixel signal at a reset level in a state in which the charge held in the first floating diffusion region, the second floating diffusion region, the first capacitor, and the second capacitor has been discharged.

[0017] The pixel circuit may read a pixel signal at a reset level in a state where charge in the first floating diffusion region has been drained or in a state where charge overflowing from the photoelectric conversion element is held in the first floating diffusion region, and then read a pixel signal at a signal level in a state where charge corresponding to the amount of light incident on the photoelectric conversion element has been transferred to the first floating diffusion region.

[0018] The floating diffusion region may have a third floating diffusion region, and may further include a third transistor that transfers at least a portion of the charge held in the first floating diffusion region to the third floating diffusion region, and the second transistor may transfer at least a portion of the charge held in the third floating diffusion region to the second floating diffusion region.

[0019] The semiconductor device may further include a third capacitor for retaining at least a portion of the charge retained in the third floating diffusion region.

[0020] After reading out a pixel signal of a reset level in a state in which the charges in the first floating diffusion region, the third floating diffusion region, and the third capacitor that are held in accordance with the amount of light incident on the photoelectric conversion element have been drained, or in a state in which the charges overflowing from the photoelectric conversion element are held in at least one of the first floating diffusion region, the third floating diffusion region, and the third capacitor, a pixel signal of a signal level based on the charges held in at least one of the first floating diffusion region, the third floating diffusion region, and the third capacitor may be read out in a state in which charges corresponding to the amount of light incident on the photoelectric conversion element are held in at least one of the first floating diffusion region, the third floating diffusion region, and the third capacitor.

[0021] The capacitance of the second capacitor may be equal to or less than the sum of the capacitance of the first capacitor and the capacitance of the third capacitor.

[0022] The first capacitor, the second capacitor, and the third capacitor may be made of the same material, have the same structure, and be arranged in the same layer, and the third capacitor may have a high-k film arranged between two electrodes.

[0023] The charges held in the first floating diffusion region and the second floating diffusion region may be discharged via the switching circuit or by turning on a fourth reset transistor.

[0024] The image sensor may further include a fifth transistor that transfers the charge photoelectrically converted by the photoelectric conversion element to the first capacitor and the second capacitor.

[0025] the floating diffusion region has a first floating diffusion region and a second floating diffusion region, and further comprises: a first transistor that transfers charge photoelectrically converted by the photoelectric conversion element to the first floating diffusion region; a first source follower circuit that generates a voltage according to charge held in the first floating diffusion region; a first voltage holding unit that holds a reset level voltage generated by the first source follower circuit in a state where the charge held in the first floating diffusion region is discharged; and a second voltage holding unit that holds a signal level voltage generated by the first source follower circuit in a state where charge according to the amount of light incident on the photoelectric conversion element is held in the first floating diffusion region; the charge cancellation unit has a first cancellation unit connected to the first voltage holding unit and a second cancellation unit connected to the second voltage holding unit; and the first capacitor has: a fourth capacitor that is provided in the first voltage holding unit and holds charge according to the reset level voltage; and a fifth capacitor that is provided in the second voltage holding unit and holds charge according to the signal level voltage. The first cancellation unit may cancel out the dielectric absorption charge discharged from the fourth capacitor, and the second cancellation unit may cancel out the dielectric absorption charge discharged from the fifth capacitor.

[0026] the pixel circuit may include: a second source follower circuit that generates a pixel signal having a signal level corresponding to a voltage held in the first voltage holding unit or the second voltage holding unit; and a signal processing unit that generates an image for each frame based on the pixel signals photoelectrically converted by the plurality of photoelectric conversion elements, wherein the first cancellation unit may include: a sixth capacitor having a capacitance corresponding to a capacitance of the fourth capacitor and connected to the fourth capacitor; and a first switching circuit that alternately switches the connection between the fourth capacitor and the sixth capacitor for each frame to cancel out the dielectric absorption charge discharged from the fourth capacitor with the dielectric absorption charge discharged from the sixth capacitor; and the second cancellation unit may include: a seventh capacitor having a capacitance corresponding to a capacitance of the fifth capacitor and connected to the fifth capacitor; and a second switching circuit that alternately switches the connection between the fifth capacitor and the seventh capacitor for each frame to cancel out the dielectric absorption charge discharged from the fifth capacitor with the dielectric absorption charge discharged from the seventh capacitor.

[0027] 10 is a block diagram of an electronic device according to a first embodiment of the present disclosure; FIG. 11 is a block diagram of a photodetector according to a first embodiment of the present disclosure; FIG. 12 is a diagram showing a layered structure of a photodetector according to a first embodiment of the present disclosure; FIG. 13 is a circuit diagram of a pixel and a pixel circuit according to a first embodiment of the present disclosure; FIG. 14 is a diagram showing a charging period of a capacitor in a dielectric absorption phenomenon; FIG. 15 is a diagram showing a discharging period of a capacitor in a dielectric absorption phenomenon; FIG. 16 is a diagram showing a floating period of a capacitor in a dielectric absorption phenomenon; FIG. 17 is a graph showing a voltage fluctuation of a capacitor due to a dielectric absorption phenomenon; FIG. 18 is an equivalent circuit diagram of a capacitor in which a dielectric absorption phenomenon occurs; FIG. 19 is a diagram showing the operation of a switching transistor for each frame; FIG. 19 is a diagram showing the operation of a charge cancellation unit in an odd-numbered frame; FIG. 20 is a diagram showing the operation of a charge cancellation unit in an even-numbered frame; FIG. 21 is a graph explaining cancellation of dielectric absorption charge by a charge cancellation unit; FIG. 22 is a plan view of a pixel and a pixel circuit according to a first embodiment of the present disclosure; FIG. 23 is a cross-sectional view of FIG. 20; FIG. 21 is a cross-sectional view of a photodetector according to a first embodiment of the present disclosure; FIG. 22 is a timing chart showing the operation of a pixel according to a first embodiment of the present disclosure; FIG. 23 is a potential diagram of a pixel in a first period; FIG. 24 is a potential diagram of a pixel in a second period; FIG. 25 is a potential diagram of a pixel in a third period; and FIG. 26 is a potential diagram of a pixel in a fourth period. FIG. 10 is a potential diagram of a pixel in a fifth period. FIG. 11 is a potential diagram of a pixel in a sixth period. FIG. 12 is a circuit diagram of a pixel and a pixel circuit according to a comparative example. FIG. 13 is a circuit diagram of a pixel and a pixel circuit according to a second embodiment of the present disclosure. FIG. 14 is a plan view of a pixel and a pixel circuit according to a third embodiment of the present disclosure. FIG. 15 is a circuit diagram of a pixel and a pixel circuit according to a third embodiment of the present disclosure. FIG. 16 is a plan view of a pixel and a pixel circuit according to a fourth embodiment of the present disclosure. FIG. 17 is a circuit diagram of a pixel and a pixel circuit according to a fifth embodiment of the present disclosure. FIG. 18 is a cross-sectional view of a photodetector according to a sixth embodiment of the present disclosure. FIG. 19 is a circuit diagram of a pixel and a pixel circuit according to a sixth embodiment of the present disclosure. FIG. 19 is a plan view of a pixel and a pixel circuit according to a sixth embodiment of the present disclosure. FIG. 19 is a circuit diagram of a pixel and a pixel circuit according to a seventh embodiment of the present disclosure. FIG. 19 is a block diagram showing an example of a schematic configuration of a vehicle control system.FIG. 2 is an explanatory diagram showing an example of the installation positions of an outside-vehicle information detection unit and an imaging unit.

[0028] Hereinafter, an embodiment of a photodetector will be described with reference to the drawings. The following description will focus on the main components of the photodetector, but the photodetector may include components and functions that are not shown or described. The following description does not exclude components and functions that are not shown or described.

[0029] 1 is a block diagram of an electronic device 1 according to a first embodiment of the present disclosure. The electronic device 1 captures image data and includes a light detection device 10, a processing unit 2, a recording unit 3, and a control unit 4. The electronic device 1 can be applied to, for example, an in-vehicle camera, a smartphone, or a camera mounted on an industrial robot, but the specific use and configuration of the electronic device 1 are arbitrary.

[0030] The photodetector 10 is, for example, a CMOS (Complementary Metal-Oxide-Semiconductor) image sensor, and performs photoelectric conversion on incident light to capture image data. The image data output from the photodetector 10 is input to the processing unit 2 and the recording unit 3 via a transmission line L1. The electronic device 1 also has an imaging lens 5 that focuses the incident light and guides it to the photodetector 10.

[0031] The processing unit 2 performs predetermined image processing such as image recognition, tracking, analysis, etc. on the image data. The image data that has been subjected to image processing by the processing unit 2 is output to the recording unit 3, for example.

[0032] The recording unit 3 records the image data output from the light detection device 10 or the processing unit 2. The recording unit 3 may be disposed in a server connected via a network. In the electronic device 1 according to this embodiment, at least one of the processing unit 2 and the recording unit 3 shown in FIG. 1 may be omitted.

[0033] The control unit 4 instructs the photodetector 10 to generate image data via a control line L2.

[0034] 2 is a block diagram of the photodetector 10 according to the first embodiment of the present disclosure. The photodetector 10 includes a pixel array unit 11, a row driver unit 12, a signal processor 13, and a timing controller 14.

[0035] The pixel array unit 11 has a plurality of pixels 20 arranged in a first direction X and a second direction Y. In this specification, the left-right (horizontal) direction in Fig. 2 is referred to as the first direction X, and the up-down (vertical) direction in Fig. 2 is referred to as the second direction Y. Furthermore, a group of pixels 20 arranged in the first direction X is referred to as a pixel row, and a group of pixels 20 arranged in the second direction Y is referred to as a pixel column.

[0036] Each pixel 20 has a photoelectric conversion element that generates a charge corresponding to the amount of incident light. A pixel circuit (not shown in Fig. 2) connected to the pixel 20 generates a pixel signal Vimg based on the charge of the photoelectric conversion element.

[0037] The row driver 12 is composed of a shift register, an address decoder, etc. The row driver 12 drives each pixel 20 in the pixel array unit 11 either all at once or on a pixel row basis. The row driver 12 discharges electric charges and reads signals from each pixel 20 and pixel circuit.

[0038] In the charge draining process, unnecessary charges are drained (reset) from the photoelectric conversion elements of the pixels 20. This allows the photoelectric conversion elements in the pixels 20 to start a new exposure. In this specification, the operation of discarding the charges of the photoelectric conversion elements and starting a new exposure (starting the accumulation of charges) is also referred to as an electronic shutter operation.

[0039] The photodetector 10 may perform a global shutter operation in which exposure is started simultaneously for all pixels. The global shutter operation has the advantage that the exposure timing for each pixel is not shifted, and therefore distortion due to a shift in exposure timing does not occur in the captured image.

[0040] In signal readout, a pixel signal Vimg based on the charge accumulated in the photoelectric conversion element in the pixel 20 is read out from the pixel circuit. The pixel signal Vimg is a signal that corresponds to the amount of light incident on the pixel 20 during the period from the electronic shutter operation to the signal readout.

[0041] The signal processing unit 13 generates an image for each frame based on the pixel signal Vimg. Specifically, the pixel signal Vimg output from each pixel 20 and pixel circuit in the pixel array unit 11 is supplied to the signal processing unit 13 via a vertical signal line. The signal processing unit 13 performs predetermined signal processing on the pixel signal Vimg to generate an image. Examples of predetermined signal processing include analog-to-digital conversion of the pixel signal Vimg, CDS (Correlated Double Sampling) processing, and DDS (Double Data Sampling) processing. The photodetector 10 can generate multiple consecutive images using multiple consecutive frames. Details of frames will be described later.

[0042] The timing control unit 14 is configured by a timing generator that generates various timing signals, etc. Based on the various timing signals, the timing control unit 14 controls the read and sweep timing of the row drive unit 12, and controls the drive of the signal processing unit 13, etc.

[0043] The photodetector 10 is configured by stacking, for example, two semiconductor substrates (hereinafter simply referred to as substrates). FIG. 3 is a diagram showing the stacked structure of the photodetector 10 according to the first embodiment of the present disclosure. The photodetector 10 is configured by stacking a pixel substrate (first substrate) b1 and a logic substrate (second substrate) b2 in this order. These substrates are bonded together by vias or the like. Note that these substrates may be bonded together by Cu-Cu bonding or bumps in addition to vias.

[0044] The pixel substrate b1 has arranged thereon, for example, a plurality of pixels 20 and pixel circuits in the pixel array unit 11. The logic substrate b2 has arranged thereon, for example, a row driver 12, a signal processor 13, and a timing controller 14.

[0045] 3 shows an example in which two substrates are stacked, but the number of stacked substrates is arbitrary, and the circuits and the like arranged on each substrate may vary depending on the number of stacked substrates. For example, the photodetector 10 may be configured such that a second pixel substrate is stacked and a part of the pixel substrate b1 (e.g., the pixel circuit) is arranged on the second pixel substrate. Furthermore, the row driver 12, the signal processor 13, and the timing controller 14 may be distributed and arranged on two or more logic substrates. Furthermore, the photodetector 10 may be configured using a single flat substrate.

[0046] 4 is a circuit diagram of a pixel 20 and a pixel circuit 21 according to the first embodiment of the present disclosure. The pixel 20 includes, for example, a photoelectric conversion element PD and a transfer transistor (first transistor) TG. The pixel circuit 21 includes, for example, a first conversion efficiency transistor (third transistor) FDG, a second conversion efficiency transistor (second transistor) FCG, a reset transistor RST, an amplification transistor AMP, a selection transistor SEL, a first capacitor MIMA, a floating diffusion region (first floating diffusion region) FD1, a floating diffusion region (third floating diffusion region) FD2, and a floating diffusion region (second floating diffusion region) FD3. In this specification, the pixel 20 and the pixel circuit 21 may be collectively referred to simply as the pixel 20.

[0047] In this specification, an example will be described in which the transfer transistor TG, the first conversion efficiency transistor FDG, the second conversion efficiency transistor FCG, the reset transistor RST, the amplification transistor AMP, and the selection transistor SEL are configured with, for example, NMOS (N-channel Metal-Oxide-Semiconductor) transistors. However, the conductivity type of each transistor illustrated here is arbitrary. Any of the above transistors may be configured with, for example, PMOS (P-channel Metal-Oxide-Semiconductor) transistors.

[0048] The photoelectric conversion element PD is, for example, a photodiode, and generates charges according to the amount of light incident on the photoelectric conversion element PD. The photoelectric conversion element PD has an anode and a cathode. Either the anode or the cathode (for example, the cathode) is connected to the source of the transfer transistor TG, and the other (for example, the anode) is grounded. In this specification, an example will be described in which electrons generated by the photoelectric conversion element PD through photoelectric conversion are transferred from the cathode.

[0049] The transfer transistor TG transfers the charges photoelectrically converted by the photoelectric conversion element PD to the floating diffusion region FD1. The drain of the transfer transistor TG is connected to the floating diffusion region FD1.

[0050] The floating diffusion regions FD1, FD2, and FD3 hold charges photoelectrically converted by the photoelectric conversion element PD. The transfer transistor TG, the first conversion efficiency transistor FDG, and the second conversion efficiency transistor FCG switch whether or not to transfer charges to the floating diffusion regions FD1, FD2, and FD3, respectively.

[0051] During the exposure period, charge overflowing from the photoelectric conversion element PD (overflow charge) passes under the gate of the transfer transistor TG and is accumulated in the floating diffusion region FD1. Charge overflowing from the floating diffusion region FD1 passes under the gate of the first conversion efficiency transistor FDG and is accumulated in the floating diffusion region FD2. Charge overflowing from the floating diffusion region FD2 passes under the gate of the second conversion efficiency transistor FCG and is accumulated in the floating diffusion region FD3. The first conversion efficiency transistor FDG switches whether or not to read charge from the floating diffusion region FD2 when the pixel circuit 21 outputs the pixel signal Vimg. The source of the first conversion efficiency transistor FDG is connected to the floating diffusion region FD1. The drain of the first conversion efficiency transistor FDG is connected to the floating diffusion region FD2. The first conversion efficiency transistor FDG is used to read out the overflow charge accumulated in the floating diffusion region FD2 under high illuminance conditions.

[0052] The second conversion efficiency transistor FCG switches whether or not to read charge from the floating diffusion region FD3 when the pixel circuit 21 outputs the pixel signal Vimg. The source of the second conversion efficiency transistor FCG is connected to the floating diffusion region FD2. The drain of the second conversion efficiency transistor FCG is connected to the floating diffusion region FD3. The second conversion efficiency transistor FCG is used to read out overflow charge accumulated in the floating diffusion region FD3 at higher illuminance.

[0053] The first capacitor MIMA holds charge corresponding to the charge held in the floating diffusion region FD3. One end of the first capacitor MIMA is connected to the floating diffusion region FD3. The other end of the first capacitor MIMA is connected to the node of the power supply voltage MIMVDD. The first capacitor MIMA has, for example, a high-dielectric-constant MIM structure. The detailed structure of the first capacitor MIMA will be described later. By holding charge in the first capacitor MIMA, the floating diffusion region FD3 can hold more charge (for example, 100 times or more charge) than the floating diffusion regions FD1 and FD2.

[0054] The amplifier transistor AMP and the select transistor SEL constitute a first source follower circuit 23 that generates a voltage corresponding to the charge held in the floating diffusion region FD1. The gate of the amplifier transistor AMP is connected to the floating diffusion region FD1 and is used as the input section of the first source follower circuit 23. The drain of the amplifier transistor AMP is connected to the node of the power supply voltage VDD. The source of the amplifier transistor AMP is connected to the drain of the select transistor SEL.

[0055] The selection transistor SEL controls the reading of signals from the pixels 20. When the selection transistor SEL is turned on, a pixel signal Vimg having a voltage level corresponding to the voltage of the floating diffusion region FD1 is output from the source of the selection transistor SEL to the vertical signal line VSL. The pixel signal Vimg on the vertical signal line VSL is input to, for example, the signal processing unit 13 in the subsequent stage.

[0056] The reset transistor RST controls the discharge of charges from the pixel 20. The source of the reset transistor RST is connected to the floating diffusion region FD3. The drain of the reset transistor RST is connected to the node of the power supply voltage VDD. When the reset transistor RST is turned on, the charges in the photoelectric conversion element PD, the floating diffusion regions FD1, FD2, and FD3, and the first capacitor MIMA are discharged to the node of the power supply voltage VDD.

[0057] The pixel circuit 21 outputs a pixel signal Vimg for each frame based on the charge photoelectrically converted by the photoelectric conversion element PD. After the pixel signal Vimg is output, the pixel circuit 21 performs a reset operation to discharge the charge from the photoelectric conversion element PD, the floating diffusion regions FD1, FD2, and FD3, and the first capacitor MIMA. As a result, each pixel circuit 21 outputs a pixel signal Vimg for each frame that corresponds to the amount of charge photoelectrically converted during the exposure period.

[0058] 4 can accumulate overflow charge from the photoelectric conversion element PD in the floating diffusion regions FD1 to FD3 and the first capacitor MIMA. In this specification, the pixel 20 employing a drive method in which the overflow charge from the photoelectric conversion element PD is used to generate a pixel signal is referred to as a lateral overflow integration capacitor (LOFIC) driven pixel.

[0059] 2 inputs predetermined signals to the gates of the transfer transistor TG, reset transistor RST, and selection transistor SEL. As a result, the transfer transistor TG, reset transistor RST, and selection transistor SEL are switched on or off at timing specified by the row driver 12. Similarly, the row driver 12 applies predetermined voltages to the gates of the first conversion efficiency transistor FDG and the second conversion efficiency transistor FCG. As a result, the potentials of the first conversion efficiency transistor FDG and the second conversion efficiency transistor FCG are controlled by the row driver 12.

[0060] Furthermore, the pixel 20 according to the first embodiment of the present disclosure includes a charge cancellation unit 22, as shown in FIG. 4 . The charge cancellation unit 22 is connected to a first capacitor MIMA. The charge cancellation unit 22 cancels out dielectric absorption charges discharged from the first capacitor MIMA. The dielectric absorption charges are charges released due to the dielectric absorption phenomenon described below. The charge cancellation unit 22 includes switching transistors MT1, MT2, MT3, and MT4, and a second capacitor MIMB. The switching transistors MT1, MT2, MT3, and MT4 are configured, for example, by NMOS transistors.

[0061] The second capacitor MIMB has a capacitance corresponding to the capacitance of the first capacitor MIMA.

[0062] The second capacitor MIMB has a lower electrode and an upper electrode. For the sake of distinction, the upper electrode is drawn with a thicker line than the lower electrode in Figure 4. Similarly, the first capacitor MIMA has a lower electrode and an upper electrode drawn with a thicker line than the lower electrode.

[0063] The switching transistor MT1 switches whether the upper electrode of the first capacitor MIMA and the lower electrode of the second capacitor MIMB are connected. The drain of the switching transistor MT1 is connected to the upper electrode of the first capacitor MIMA and the node of the power supply voltage MIMVDD. The source of the switching transistor MT1 is connected to the lower electrode of the second capacitor MIMB.

[0064] The switching transistor MT2 switches whether the upper electrode of the first capacitor MIMA and the upper electrode of the second capacitor MIMB are connected. The drain of the switching transistor MT2 is connected to the upper electrode of the first capacitor MIMA and the node of the power supply voltage MIMVDD. The source of the switching transistor MT2 is connected to the upper electrode of the second capacitor MIMB.

[0065] The switching transistor MT3 switches whether the lower electrode of the first capacitor MIMA and the upper electrode of the second capacitor MIMB are connected. The drain of the switching transistor MT3 is connected to the lower electrode of the first capacitor MIMA and the floating diffusion region FD3. The source of the switching transistor MT3 is connected to the upper electrode of the second capacitor MIMB.

[0066] The switching transistor MT4 switches whether the lower electrode of the first capacitor MIMA and the lower electrode of the second capacitor MIMB are connected. The drain of the switching transistor MT4 is connected to the lower electrode of the first capacitor MIMA and the floating diffusion region FD3. The source of the switching transistor MT4 is connected to the lower electrode of the second capacitor MIMB.

[0067] The second capacitor MIMB is connected to the first capacitor MIMA by one of the switching transistors MT1 to MT4. More specifically, the connection between the first capacitor MIMA and the second capacitor MIMB is switched by switching the switching transistors MT1 to MT4 on or off. Specifically, the first capacitor MIMA and the second capacitor MIMB are always connected in parallel, but the orientation of the second capacitor MIMB connected to the first capacitor MIMA alternates every frame. In this specification, the switching transistors MT1 to MT4 that switch the orientation of the second capacitor MIMB may be referred to as a switching circuit.

[0068] 5A to 5C, 6A and 6B are diagrams illustrating the dielectric absorption phenomenon. 5A to 5C show a capacitor MIM in which the dielectric absorption phenomenon occurs. FIG. 5A shows a charging period PR_1 of the capacitor MIM. The capacitor MIM in FIG. 5A is charged by applying a voltage Vo between the upper electrode and the lower electrode. At this time, the capacitor MIM is charged by a voltage V ０ When a voltage is applied, the internal dipoles are oriented.

[0069] FIG. 5B illustrates the discharge period PR_2 of the capacitor MIM. In FIG. 5B, one end of the capacitor MIM is shorted to the other end. This causes the capacitor MIM to discharge. At this time, the dipole orientation within the capacitor MIM is relaxed, releasing charge. When the orientation of all dipoles within the capacitor MIM is relaxed, the capacitor MIM is completely discharged. However, the relaxation of some dipoles within the capacitor MIM may be delayed, preventing the capacitor MIM from being completely discharged during the discharge period PR_2. The dielectric absorption phenomenon refers to the phenomenon in which the capacitor MIM continues to retain some charge even after the discharge period PR_2. The partial charge retained by the capacitor MIM after the discharge period PR_2 is called the dielectric absorption charge.

[0070] 5C is a diagram showing a floating period PR_3 of the capacitor MIM. In FIG. 5C, the voltage Vo is not applied to the capacitor MIM, and the capacitor MIM is in a floating state. If the capacitor MIM is discharged, no charge is normally released from the capacitor MIM during the floating period PR_3. However, if the relaxation of some dipoles in the capacitor MIM is delayed, the dipoles of the capacitor MIM are relaxed over time. As a result, dielectric absorption charges are released from the capacitor MIM during the floating period PR_3, and a voltage Vf due to the dielectric absorption charges is generated between the upper and lower electrodes of the capacitor MIM.

[0071] 6A is a graph showing voltage fluctuations of capacitor MIM due to the dielectric absorption phenomenon. The vertical axis of FIG. 6A represents the voltage V between the upper and lower electrodes of capacitor MIM, and the horizontal axis represents time t. Time t in FIG. 6A is divided into three periods: a charging period PR_1, a discharging period PR_2, and a floating period PR_3. During the charging period PR_1, the voltage V of capacitor MIM is equal to the applied voltage Vo.

[0072] Subsequently, the capacitor MIM is discharged during the discharge period PR_2, causing the voltage V of the capacitor MIM to temporarily become 0V.

[0073] However, if dielectric absorption occurs in the capacitor MIM, the dielectric absorption charge is gradually released from the capacitor MIM during the floating period PR_3, and the voltage of the capacitor MIM increases over time. The voltage V of the capacitor MIM increases from 0 V to a voltage Vf.

[0074] 6B is an equivalent circuit diagram of the capacitor MIM in which the dielectric absorption phenomenon occurs. The capacitor MIM is equivalent to a capacitor C ０ and capacitor C ０ A capacitor C connected in parallel with ＤＡ and resistor R ＤＡ and the capacitor C ＤＡ is the resistance R ＤＡ is connected in series with

[0075] Capacitor C ０ is rapidly discharged during the discharge period PR_2. However, the capacitor C ＤＡ is the resistance R ＤＡ Therefore, the capacitor C ０ The discharge of the capacitor C in FIG. ０ corresponds to the dielectric absorption charge. In FIG. 6B, the capacitor C ＤＡ A voltage Vf is generated according to the charge stored in the capacitor.

[0076] 4 has a high-dielectric-constant film made of a high-k material, and thus, like the capacitor MIM of FIGS. 5A to 5C, the dielectric absorption phenomenon may occur. Due to the dielectric absorption phenomenon, the first capacitor MIMA of FIG. 4 may not be able to completely discharge the stored charge within one frame period, and dielectric absorption charge may occur within the next frame period. When the voltage of the floating diffusion region FD3 changes due to the dielectric absorption charge generated in the previous frame, the pixel signal Vimg changes due to that voltage, and an afterimage occurs in the image output by the signal processing unit 13.

[0077] The charge cancellation unit 22 according to the first embodiment of the present disclosure is characterized in that it cancels out the dielectric absorption charge of the first capacitor MIMB by providing the second capacitor MIMB in which the dielectric absorption phenomenon occurs and a switching circuit that switches the connection between the first capacitor MIMA and the second capacitor MIMB, thereby preventing the pixel signal Vimg from being affected by the dielectric absorption charge.

[0078] 7, 8A, and 8B are diagrams showing the operation of the charge cancellation unit 22 to cancel out the dielectric absorption charge. FIG. 7 is a diagram showing the operation of the switching transistors MT1 to MT4 of the charge cancellation unit 22 for each frame. FIG. 7 shows the operation of the switching transistors MT1 to MT4 from the Nth frame to the N+5th frame. N is any natural number. In this specification, an example where N=1 will be described. That is, the Nth, N+2th, and N+4th frames are odd-numbered frames, and the N+1st, N+3rd, and N+5th frames are even-numbered frames.

[0079] 7, in odd-numbered frames, the switching transistors MT1 and MT3 are turned off, and the switching transistors MT2 and MT4 are turned on.

[0080] 8A is a diagram showing the operation of the charge cancellation unit 22 in an odd-numbered frame. In FIG. 8A, for example, a low-level OFF signal is input to the gates of the switching transistors MT1 and MT3. Also, for example, a high-level ON signal is input to the gates of the switching transistors MT2 and MT4.

[0081] 8A, when the switching transistor MT2 is turned on, the upper electrode of the second capacitor MIMB is connected to the upper electrode of the first capacitor MIMA and the node of the power supply voltage MIMVDD, and when the switching transistor MT4 is turned on, the lower electrode of the second capacitor MIMB is connected to the lower electrode of the first capacitor MIMA and the floating diffusion region FD3.

[0082] As shown in FIG. 7, in even-numbered frames, the switching transistors MT1 and MT3 are turned on, and the switching transistors MT2 and MT4 are turned off.

[0083] 8B is a diagram showing the operation of the charge cancellation unit 22 in an even-numbered frame. In FIG. 8B, when the switching transistor MT1 is turned on, the lower electrode of the second capacitor MIMB is connected to the upper electrode of the first capacitor MIMA and the node of the power supply voltage MIMVDD. When the switching transistor MT3 is turned on, the upper electrode of the second capacitor MIMB is connected to the lower electrode of the first capacitor MIMA and the floating diffusion region FD3.

[0084] 7, the charge cancellation unit 22 alternately repeats the operations of FIG. 8A and FIG. 8B for each frame. That is, the switching circuit of the charge cancellation unit 22 alternately switches between connecting the upper electrode of the first capacitor MIMA to the upper electrode of the second capacitor MIMB and connecting the lower electrode of the first capacitor MIMA to the lower electrode of the second capacitor MIMB, or connecting the upper electrode of the first capacitor MIMA to the lower electrode of the second capacitor MIMB and connecting the lower electrode of the first capacitor MIMA to the upper electrode of the second capacitor MIMB.

[0085] The first capacitor MIMA and the second capacitor MIMB are connected in parallel between the floating diffusion region FD3 and the node of the power supply voltage MIMVDD in both even-numbered and odd-numbered frames. The second capacitor MIMB switches between connecting one of its upper and lower electrodes to the floating diffusion region FD3 and connecting the other to the node of the power supply voltage MIMVDD for each frame. The first capacitor MIMA has its upper electrode connected to the node of the power supply voltage MIMVDD and its lower electrode connected to the floating diffusion region FD3, regardless of the frame. Note that the switching operation of the switching transistors MT1 to MT3 in even-numbered and odd-numbered frames may be reversed from that shown in FIG. 7. In this case, the even-numbered frames are represented by the circuit of FIG. 8A, and the odd-numbered frames are represented by the circuit of FIG. 8B.

[0086] The pixel circuit 21 accumulates electric charges in the first capacitor MIMA and the second capacitor MIMB for each frame. However, the direction of the electric charges accumulated in the second capacitor MIMB switches for each frame. The first capacitor MIMA and the second capacitor MIMB retain (store) a portion of the electric charges held in the floating diffusion region FD3 for each frame.

[0087] After outputting the pixel signal Vimg, the pixel circuit 21 turns on the reset transistor RST to drain the charge from the first capacitor MIMA and the second capacitor MIMB. In odd-numbered frames, the accumulated charge (e.g., electrons) is drained from the bottom electrodes of the first capacitor MIMA and the second capacitor MIMB. However, as described above, due to the dielectric absorption phenomenon occurring in the first capacitor MIMA and the second capacitor MIMB, the accumulated charge is not completely drained during the on-period of the reset transistor RST.

[0088] In the next frame (even-numbered frame) of FIG. 8A , as shown in FIG. 8B , the lower electrode of the first capacitor MIMA and the lower electrode of the second capacitor MIMB are connected to the floating diffusion region FD3. As described above, in FIG. 8B , the lower electrode of the first capacitor MIMA discharges dielectric absorption charges (e.g., electrons), which tend to lower the voltage of the lower electrode of the first capacitor MIMA, i.e., the floating diffusion region FD3. In contrast, the lower electrode of the second capacitor MIMB is connected to the upper electrode of the first capacitor MIMA, and the dielectric absorption charges (e.g., electrons) discharged from the lower electrode of the second capacitor MIMB tend to lower the voltage of the upper electrode of the first capacitor MIMA. Therefore, the voltage change between the upper and lower electrodes of the first capacitor MIMA is canceled out, suppressing the voltage change in the floating diffusion region FD3.

[0089] Similarly, in even-numbered frames, the first capacitor MIMA and the second capacitor MIMB are connected in parallel and retain (store) a portion of the charge held in the floating diffusion region FD3. When the reset transistor RST is turned on, the stored charge (e.g., electrons) is discharged from the lower electrode of the first capacitor MIMA and the upper electrode of the second capacitor MIMB. As described above, during the on-period of the reset transistor RST, the stored charge in the first capacitor MIMA and the second capacitor MIMB is not completely discharged. In the next frame (an odd-numbered frame), as shown in FIG. 8A , the connection between the upper and lower electrodes of the second capacitor MIMB is reversed from the previous frame. As described above, the dielectric absorption charge discharged from the lower electrode of the first capacitor MIMA and the dielectric absorption charge discharged from the upper electrode of the second capacitor MIMB cancel out the voltage change in the lower electrode of the first capacitor MIMA, thereby suppressing the voltage change in the floating diffusion region FD3.

[0090] As described above, the switching circuit of the charge cancellation unit 22 alternately switches the connection between the first capacitor MIMA and the second capacitor MIMB for each frame, thereby canceling out the dielectric absorption charge discharged from the first capacitor MIMA with the dielectric absorption charge discharged from the second capacitor MIMB.

[0091] 9 is a graph illustrating the cancellation of dielectrically absorbed charge by the charge cancellation unit 22. The vertical axis of FIG. 9 represents the amount of dielectrically absorbed charge, and the horizontal axis represents time. FIG. 9 shows a case where the amount of dielectrically absorbed charge discharged from the lower electrode of the first capacitor MIMA and the amount of dielectrically absorbed charge discharged from the lower electrode of the second capacitor MIMB are approximately the same. In this case, the dielectrically absorbed charge of the first capacitor MIMA is completely canceled out, and no voltage change occurs in the floating diffusion region FD3.

[0092] A dielectric absorption charge corresponding to the capacitance of the first capacitor MIMA is generated in the first capacitor MIMA, and a dielectric absorption charge corresponding to the capacitance of the second capacitor MIMB is generated in the second capacitor MIMB.

[0093] If the amount of dielectric absorption charge discharged by the second capacitor MIMB exceeds the amount of dielectric absorption charge discharged by the first capacitor MIMA, the dielectric absorption charge not only cancels out the dielectric absorption charge of the first capacitor MIMA but also unnecessarily increases the voltage of the floating diffusion region FD3. This may result in black spots in the image output by the signal processing unit 13. To prevent this, it is desirable to set the capacitance of the second capacitor MIMB equal to or less than the capacitance of the first capacitor MIMA.

[0094] On the other hand, if the amount of dielectric absorption charge discharged by the second capacitor MIMB is significantly less than that discharged by the first capacitor MIMA, the dielectric absorption charge cannot be completely offset by the first capacitor MIMA, resulting in some image lag. Therefore, it is desirable to form the second capacitor MIMB from the same material and have the same structure as the first capacitor.

[0095] If the dielectric absorption charges of the first capacitor MIMA and the second capacitor MIMB are not equal, black spots or afterimages will occur in the captured image, but by providing the charge cancellation section 22, the image quality of the captured image can be reliably improved.

[0096] FIG. 10 is a plan view of a pixel 20 and a pixel circuit 21 according to the first embodiment of the present disclosure, showing a pixel region for one pixel. FIG. 10 illustrates a planar structure of a stacked chip viewed from above (e.g., from the back surface side). FIG. 10 illustrates a layout for multiple layers stacked together. An amplifier transistor AMP and a select transistor SEL constituting a first source follower circuit 23 are arranged on the left side of the pixel region. A charge cancellation unit 22 is arranged on the right side of the pixel region. In the center of the pixel region, from top to bottom, a floating diffusion region FD3, a second conversion efficiency transistor FCG, a floating diffusion region FD2, a first conversion efficiency transistor FDG, a floating diffusion region FD1, a transfer transistor TG, a ground voltage Vss, and a photoelectric conversion element PD are arranged.

[0097] The charge cancellation unit 22 is arranged in this order from the top of the pixel area: the upper electrode MIMB_Upper of the second capacitor MIMB, a switching transistor MT3, the lower electrode MIMA_Lower and floating diffusion region FD3 of the first capacitor MIMA, a switching transistor MT4, the lower electrode MIMB_Lower of the second capacitor MIMB, a switching transistor MT1, the upper electrode MIMA_Upper and power supply voltage MIMVDD of the first capacitor MIMA, a switching transistor MT2, and the upper electrode MIMB_Upper of the second capacitor MIMB.

[0098] FIG. 11A is a cross-sectional view taken along line A-A' in FIG. 10. FIG. 11A shows the cross-sectional structure of a pixel substrate (first substrate) b1. As can be seen from FIG. 11A, the photodetector 10 according to the first embodiment is a back-illuminated type, with the lower end of FIG. 11A corresponding to the back surface. The pixel 20 receives incident light from below in FIG. 11A. In the pixel 20, a first region Ly1, a second region Ly2, a third region Ly3, and a fourth region Ly4 are arranged in this order from the light incident surface side. A photoelectric conversion element PD is arranged in the first region Ly1. In the second region Ly2, switching transistors MT3, MT4, MT1, and MT2 are arranged in this order from the left side of FIG. 11A. Furthermore, a floating diffusion region FD3 is arranged in the second region Ly2. In addition to the above, the second region Ly2 also includes various transistors and floating diffusion regions FD1 and FD2 shown in FIG. 10, but these are not shown in FIG. 11A. In the third region Ly3, any number of wiring layers are arranged. The wiring layers are made of, for example, copper. In the fourth region Ly4, from the left side of FIG. 11A, a first capacitor MIMA and a second capacitor MIMB are arranged in this order.

[0099] The first capacitor MIMA and the second capacitor MIMB have an MIM structure in which upper and lower electrodes having comb-shaped cross sections are opposed to each other, with an insulating film Fa made of a high-k material disposed between them. The first capacitor MIMA has an upper electrode MIMA_Upper disposed on the upper side of FIG. 11A and a lower electrode MIMA_Lower disposed on the lower side of FIG. 11A. The upper electrode MIMA_Upper and the lower electrode MIMA_Lower are connected to the corresponding switching transistors MT1 to MT4 via wiring layers. Meanwhile, the upper electrode MIMA_Upper and the lower electrode MIMA_Lower are made of, for example, titanium. The insulating film Fa disposed between the upper electrode MIMA_Upper and the lower electrode MIMA_Lower is made of a high-k material (for example, hafnium).

[0100] The cross-sectional shapes of the first capacitor MIMA and the second capacitor MIMB are arbitrary, and do not necessarily have to be the MIM structure shown in FIG. 11A.

[0101] The second capacitor MIMB is formed in the same process as the first capacitor MIMA and is disposed in the same layer. The second capacitor MIMB is made of the same material and has the same structure as the first capacitor MIMA. Specifically, the second capacitor MIMB has an upper electrode MIMB_Upper made of the same material as the upper electrode MIMA_Upper, a lower electrode MIMB_Lower made of the same material as the lower electrode MIMA_Lower, and an insulating film Fb made of the same material as the insulating film Fa.

[0102] The first capacitor MIMA and the second capacitor MIMB have a high-dielectric constant high-k film (insulating films Fa and Fb) between the upper electrode and the lower electrode. In this case, there is a risk of dielectric absorption charge being generated, but by providing a charge cancellation section 22, the dielectric absorption charge can be canceled out.

[0103] A structure in which an insulating film is sandwiched between two metal electrodes is also called an MIM structure. The first capacitor MIMA and the second capacitor MIMB in Fig. 11A are configured with an MIM structure. However, the first capacitor MIMA and the second capacitor MIMB may also be configured with, for example, a metal-oxide-metal (MOM) structure.

[0104] 11B is a cross-sectional view of the photodetector 10 having the stacked structure shown in FIG. 3. As shown in FIG. 11B, the photodetector 10 according to the first embodiment is a stacked chip in which a pixel substrate b1 and a logic substrate b2 are stacked. The upper end of FIG. 11B is the light incident surface, which corresponds to the back surface. A plurality of pixels 20 are arranged on the pixel substrate b1. The plurality of pixels 20 in FIG. 11B receive incident light from above in FIG. 11B. An on-chip lens 40 that focuses the incident light is arranged on the light incident surface side of each of the plurality of pixels 20. The pixel substrate b1 and the logic substrate b2 are stacked in this order from the light incident surface side. Each of the plurality of pixels 20 has a capacitor MIM on the bonding surface side with the logic substrate b2.

[0105] The capacitor MIM in Fig. 11B includes the first capacitor MIMA or the second capacitor MIMB in Fig. 11A. Figs. 11A and 11B show an example in which the first capacitor MIMA, the second capacitor MIMB, and the switching circuits MT1 to MT4 are arranged on the pixel substrate b1. However, this is not limiting, and at least one of the first capacitor MIMA, the second capacitor MIMB, or the switching circuits may be arranged on the logic substrate b2.

[0106] The operation of the photodetector 10 according to the first embodiment of the present disclosure will be described below. Fig. 12 is a timing chart showing the operation of the pixel 20 according to the first embodiment of the present disclosure. Fig. 12 shows the waveforms of the RST signal input to the gate of the reset transistor RST, the FCG signal input to the gate of the second conversion efficiency transistor FCG, the FDG signal input to the gate of the first conversion efficiency transistor FDG, and the TG signal input to the gate of the transfer transistor TG. Fig. 12 shows the readout operation of the pixel signal Vimg after the exposure period.

[0107] The photodetector 10 repeatedly performs an operation of outputting pixel signals photoelectrically converted by each pixel 20 to the vertical signal line VSL for each frame. Each pixel 20 switches its photoelectric conversion efficiency according to the illuminance of incident light to generate pixel signals of a signal level and a reset level.

[0108] Each pixel 20 determines whether the illuminance is low, medium, or high based on the reset level voltage of the floating diffusion region FD1 (or FD2). When the illuminance is determined to be low, each pixel 20 selects a high conversion gain (HCG) photoelectric conversion efficiency to generate a pixel signal, when the illuminance is determined to be medium, each pixel 20 selects a middle conversion gain (MCG) photoelectric conversion efficiency to generate a pixel signal, and when the illuminance is determined to be high, each pixel 20 selects a low conversion gain (LCG) photoelectric conversion efficiency to generate a pixel signal.

[0109] More specifically, when it is determined that the illuminance is low, each pixel 20 generates a pixel signal of the HCG reset level (R) with the first conversion efficiency transistor FDG and the second conversion efficiency transistor FCG turned off (times t2 to t3), and also generates a pixel signal of the HCG signal level (D) corresponding to the charge held in the floating diffusion region FD1 transferred from the photoelectric conversion element PD via the transfer transistor TG (times t4 to t5), and outputs these pixel signals to the vertical signal line VSL. The signal processing unit 13 performs CDS based on these signals.

[0110] On the other hand, when the illuminance is determined to be medium, each pixel 20 generates a pixel signal of the MCG reset level (R) with the first conversion efficiency transistor FDG turned on and the second conversion efficiency transistor FCG turned off (times t1 to t2), and also generates a pixel signal of the MCG signal level (D) corresponding to the charges held in the floating diffusion regions FD1 and FD2 with both the transfer transistor TG and the first conversion efficiency transistor FDG turned on (times t6 to t7), and outputs these pixel signals to the vertical signal line VSL. The signal processing unit 13 performs CDS based on these signals.

[0111] As described above, when the illuminance is low or medium, each pixel 20 reads out a pixel signal at a reset level in which the charges in the floating diffusion regions FD1 and FD2 have been drained due to resetting immediately before the exposure period, or in which the charges overflowing from the photoelectric conversion element PD are held in the floating diffusion regions FD1 and FD2, and then reads out a pixel signal at a signal level in which charges corresponding to the amount of light incident on the photoelectric conversion element PD have been transferred to the floating diffusion regions FD1 and FD2.

[0112] 13A to 13F are potential diagrams of the pixel 20 at times t1 to t11 in FIG. 12 when the illuminance is determined to be high. The horizontal direction in FIGS. 13A to 13F indicates the location from the photoelectric conversion element PD to the power supply voltage VDD node, and the vertical direction indicates the magnitude of the potential. The voltage level decreases toward the top of the vertical direction, and increases toward the bottom.

[0113] 13A is a potential diagram of pixel 20 from time t1 to time t2 in FIG. 12. Between times t1 and t2, the first conversion efficiency transistor FDG is turned on, and the transfer transistor TG, reset transistor RST, and second conversion efficiency transistor FCG are turned off. Due to high illuminance, overflow charge from the photoelectric conversion element PD leaks into the floating diffusion region FD1, the overflow charge from the floating diffusion region FD1 leaks into the floating diffusion region FD2, and the overflow charge from the floating diffusion region FD2 is held in the floating diffusion region FD3. As a result, the floating diffusion regions FD1 to FD3 have approximately the same voltage level.

[0114] As described above, after the reset transistor RST is switched from on to off, the dielectric absorption charge corresponding to the accumulated charge in the first capacitor MIMA and the second capacitor MIMB in the previous frame is gradually discharged from the first capacitor MIMA and the second capacitor MIMB.

[0115] 4, a first capacitor MIMA and a second capacitor MIMB having large capacitances are connected to the floating diffusion region FD3, and any charge that cannot be held in the floating diffusion region FD3 is held (accumulated) in the first capacitor MIMA and the second capacitor MIMB. In this way, when the illuminance is so high that the amount of light photoelectrically converted by the photoelectric conversion element PD cannot be accumulated in the photoelectric conversion element PD, the overflow charge from the photoelectric conversion element PD is transferred in the following order: floating diffusion region FD1, floating diffusion region FD2, floating diffusion region FD3, and two capacitors (i.e., the first capacitor MIMA and the second capacitor MIMB).

[0116] Fig. 13B is a potential diagram of the pixel 20 from time t2 to t3 in Fig. 12. From time t2 to t3, the first conversion efficiency transistor FDG transitions from on to off. In this state, the potentials of the floating diffusion regions FD1 to FD3 are the same as those in Fig. 13A.

[0117] 13C is a potential diagram of pixel 20 from time t4 to t5 in FIG. 12. Because transfer transistor TG is temporarily turned on immediately before time t3 to t4, the accumulated charge in photoelectric conversion element PD is transferred to floating diffusion region FD1, the charge that overflows from floating diffusion region FD1 leaks into floating diffusion region FD2, and the charge that overflows from floating diffusion region FD2 is held in floating diffusion region FD3. As a result, floating diffusion regions FD1 to FD3 have approximately the same voltage level.

[0118] 13D is a potential diagram of pixel 20 from time t6 to t7. Because transfer transistor TG is temporarily turned on immediately before time t5 to t6, most of the accumulated charge remaining in photoelectric conversion element PD is transferred to floating diffusion region FD1, and the charge overflowing from floating diffusion region FD1 leaks out to floating diffusion regions FD2 and FD3 in that order. Furthermore, from time t5 to t11, first conversion efficiency transistor FDG is turned on. As a result, floating diffusion regions FD1 to FD3 have approximately the same voltage level.

[0119] FIG. 13E is a potential diagram of pixel 20 from time t8 to t9 in FIG. 12. The transfer transistor TG is temporarily turned on immediately before this from time t7 to t8, completely discharging any accumulated charge remaining in the photoelectric conversion element PD. Furthermore, from time t7 to t11, the second conversion efficiency transistor FCG is turned on. This causes the floating diffusion regions FD1 to FD3 to have the same voltage level. A pixel signal is read out from time t7 to t8. This pixel signal has a signal level corresponding to the charge held in the floating diffusion regions FD1, FD2, and FD3, the first capacitor MIMA, and the second capacitor MIMB. This pixel signal readout is the readout of the signal level (D) of the LCG.

[0120] Figure 13F is a potential diagram of pixel 20 from time t10 to t11 in Figure 12. The reset transistor RST turns on immediately before this, from time t9 to t10. This causes the charges held in the floating diffusion regions FD1 to FD3 to be discharged to the power supply voltage node. A pixel signal is read out from time t10 to t11. This reading of pixel signal g is the reading of the reset level (R) of the LCG.

[0121] The signal processing unit 13 calculates the difference between the pixel signal Vimg at the LCG signal level and the pixel signal Vimg at the LCG reset level. This makes it possible to read out the pixel signal that has undergone DDS. In DDS driving, noise components due to dielectric absorption charges cannot be canceled out by the pixel signal Vimg at the reset level. Therefore, by providing the charge cancellation unit 22 described above to cancel out the dielectric absorption charges, the LCG signal level can be read out with high accuracy.

[0122] 12 constitutes one frame. As described above, in one frame, pixel signals Vimg of signal levels and reset levels are read out for each of the HCG, MCG, and LCG. The signal processing unit 13 can generate an image for each frame based on these pixel signals Vimg input for each frame.

[0123] 14 is a circuit diagram of a pixel 100 and a pixel circuit 101 according to a comparative example. The pixel 100 of FIG. 14 differs from the pixel 20 of FIG. 4 in that it does not have a charge cancellation unit 22. Therefore, the pixel 100 of FIG. 14 cannot cancel the dielectric absorption charge of the first capacitor MIMA. Therefore, an afterimage occurs in an image output based on a pixel signal of the pixel 100 according to the comparative example.

[0124] In contrast, the pixel 20 according to the first embodiment of the present disclosure can cancel out the dielectric absorption charge of the first capacitor MIMA using the charge cancellation unit 22, thereby suppressing the occurrence of afterimages.

[0125] The pixel 20 according to the first embodiment of the present disclosure requires the addition of a second capacitor MIMB and switching circuits MT1 to MT4 compared to the pixel 100 according to the comparative example. In this embodiment, a portion of the charge held in the floating diffusion region FD3 can be distributed and held in the first capacitor MIMA and the second capacitor MIMB, so the total area of ​​the capacitor MIM connected to the floating diffusion region FD3 is the same between this embodiment and the comparative example. Therefore, essentially, only new space is required for the switching circuits MT1 to MT4, and the photodetector according to this embodiment can be realized with approximately the same size as the comparative example.

[0126] As described above, the pixel 20 according to the first embodiment of the present disclosure includes a charge cancellation unit 22 for canceling out the dielectric absorption charge of the first capacitor MIMA. The charge cancellation unit 22 includes a second capacitor MIMB having a capacitance corresponding to that of the first capacitor MIMA. The charge cancellation unit 22 alternately connects the upper electrode and the lower electrode of the second capacitor MIMB to the floating diffusion region FD3 for each frame, thereby suppressing voltage fluctuations in the floating diffusion region FD3 due to the dielectric absorption charge of the first capacitor MIMA. As a result, according to the first embodiment of the present disclosure, it is possible to prevent the occurrence of afterimages due to dielectric absorption, and to output captured images of higher image quality.

[0127] Inductively absorbed charges are likely to occur in capacitors with high dielectric constants that use high-k materials. In this embodiment, there is a risk of dielectrically absorbed charges occurring in the large-capacity first capacitor MIMA connected to the floating diffusion region FD3 used in high-illumination situations. Therefore, in this embodiment, a charge cancellation unit 22 is connected to the first capacitor MIMA. This makes it possible to prevent afterimages from occurring in high-illumination situations.

[0128] Second Embodiment Fig. 15 is a circuit diagram of a pixel 20a and a pixel circuit 21a according to a second embodiment of the present disclosure. Fig. 16 is a plan view of the pixel 20a and the pixel circuit 21a according to the second embodiment of the present disclosure.

[0129] 15 and 16 differs from the pixel 20 of FIG. 4 in that it includes a third capacitor MIMC connected to the floating diffusion region FD2. The third capacitor MIMC holds at least a portion of the charge stored in the floating diffusion region FD2. As shown in FIG. 16, the third capacitor MIMC is formed in an MIM structure directly below the floating diffusion region FD2, which is disposed between the first conversion efficiency transistor FDG and the second conversion efficiency transistor FCG.

[0130] The third capacitor MIMC is made of the same material and structure as the first capacitor MIMA and the second capacitor MIMB, and is arranged in the same layer. The third capacitor MIMC also has a high-k film arranged between the upper electrode and the lower electrode, and has a high-dielectric-constant MIM structure similar to the first capacitor MIMA and the second capacitor MIMB.

[0131] Like the first capacitor MIMA, the third capacitor MIMC cannot discharge all of the stored charge during the on-period of the reset transistor RST, but rather gradually discharges the dielectric absorption charge after the reset transistor RST transitions from on to off. The charge cancellation unit 22 in FIG. 15 cancels out the dielectric absorption charge of not only the first capacitor MIMA but also the third capacitor MIMC. More specifically, the second capacitor MIMB included in the charge cancellation unit 22 in FIG. 15 generates a dielectric absorption charge sufficient to cancel out the dielectric absorption charge of the first capacitor MIMA and the dielectric absorption charge of the third capacitor MIMC. Therefore, the capacitance of the second capacitor MIMB in FIG. 15 is set to be equal to or less than the sum of the capacitances of the first capacitor MIMA and the third capacitor MIMC.

[0132] The operation of the pixel 20a according to the second embodiment of the present disclosure is similar to the operation shown in FIG. 12 . Note that in the second embodiment, from time t1 to t2 in FIG. 12 , a pixel signal Vimg is output at a reset level in a state in which the charges in the floating diffusion regions FD1 and FD2 and the third capacitor MIMC have been drained, or in a state in which the charges accumulated in the photoelectric conversion element PD have not been transferred to the floating diffusion regions FD1 and FD2. Also in the second embodiment, from time t6 to t7 in FIG. 12 , a pixel signal Vimg is output at a signal level based on the charges held in the floating diffusion regions FD1 and FD2 and the third capacitor MIMC in a state in which the charges held in the photoelectric conversion element PD are held in the floating diffusion regions FD1 and FD2 and the third capacitor MIMC. Also in the second embodiment, from time t8 to t9 and from time t10 to t11 in FIG. 12 , the pixel signal Vimg is output taking into account the charges held in the third capacitor MIMC.

[0133] As described above, the dielectric absorption charge of the third capacitor MIMC is cancelled out by the dielectric absorption charge of the second capacitor MIMB, so there is no need to provide a dedicated charge cancellation section 22 for the third capacitor MIMC.

[0134] In the pixel 20a according to the second embodiment of the present disclosure, the third capacitor MIMC is also connected to the floating diffusion region FD2, so that the amount of charge that can be held when the first conversion efficiency transistor FDG is turned on can be increased, enabling imaging at higher illuminance levels and expanding the dynamic range.

[0135] Third Embodiment Fig. 17 is a circuit diagram of a pixel 20b and a pixel circuit 21b according to a third embodiment of the present disclosure. Fig. 18 is a plan view of the pixel 20b and the pixel circuit 21b according to the third embodiment of the present disclosure.

[0136] The pixel 20b in Figures 17 and 18 has a photoelectric conversion element PD and a transfer transistor (first transistor) TG, a first conversion efficiency transistor (second transistor) FDG, a reset transistor RST, an amplification transistor AMP, a selection transistor SEL, a first capacitor MIMA, a floating diffusion region (first floating diffusion region) FD1, and a floating diffusion region (second floating diffusion region) FD2.

[0137] 4 in that pixel 20b does not have a second conversion efficiency transistor FCG and a floating diffusion region FD3. A first capacitor MIMA and a charge cancellation unit 22 are connected to the floating diffusion region FD2. The first conversion efficiency transistor FDG transfers at least a portion of the charge stored in the floating diffusion region FD1 directly to the floating diffusion region FD2.

[0138] The operation of pixel 20b according to the third embodiment of the present disclosure is the same as that shown in FIG. 12 . Note that, because pixel 20b does not have an MCG state, the operations at times t1 to t2 and t6 to t7 are omitted. Furthermore, at times t10 to t11 in FIG. 12 , a pixel signal Vimg is output in a state in which the charges in floating diffusion regions FD1 and FD2, first capacitor MIMA, and second capacitor MIMB are discharged. Furthermore, at times t8 to t9 in FIG. 12 , a pixel signal Vimg is output at a signal level based on the charges retained in floating diffusion regions FD1 and FD2, first capacitor MIMA, and second capacitor MIMB in a state in which the charges accumulated in photoelectric conversion element PD are retained in floating diffusion regions FD1 and FD2, first capacitor MIMA, and second capacitor MIMB.

[0139] In this way, in the first and second embodiments, the photoelectric conversion efficiency is switched between three stages to output a plurality of pixel signals, whereas in the third embodiment, the photoelectric conversion efficiency can be switched between two stages to output a plurality of pixel signals, thereby simplifying the readout control of the pixel signals.

[0140] The dielectric absorption charge cancellation technique according to the first embodiment of the present disclosure can also be applied to pixels with two-stage conversion efficiency.

[0141] 19 is a circuit diagram of a pixel 20c and a pixel circuit 21c according to a fourth embodiment of the present disclosure. FIG. 20 is a plan view of the pixel 20c and the pixel circuit 21c according to the fourth embodiment of the present disclosure.

[0142] 19 and 20 differs from the pixel 20 of FIG. 4 in that it does not have a reset transistor RST. By turning on the reset transistor RST, the pixel 20 of FIG. 4 discharges the charges in the photoelectric conversion element PD and the floating diffusion regions FD1 to FD3 to the node of the power supply voltage VDD. In contrast, the pixel 20c of FIG. 19 discharges the charges in the photoelectric conversion element PD and the floating diffusion regions FD1 to FD3 to the node of the power supply voltage MIMVDD via the charge cancellation unit 22.

[0143] For example, by turning on the switching transistors MT2 and MT3 of the charge cancellation unit 22, the cathode of the photoelectric conversion element PD and the floating diffusion regions FD1 to FD3 can be electrically connected to the power supply voltage MIMVDD node, thereby discharging the accumulated (stored) charge.

[0144] As described above, even if the reset transistor RST is omitted, the pixel 20c according to the fourth embodiment of the present disclosure can achieve the same operation as that shown in Fig. 12. Fig. 20 shows a configuration in which the reset transistor RST is omitted from the pixel 20a in Fig. 4, but it can also be applied to a configuration in which the reset transistor RST is omitted from the pixel 20a in Fig. 15 or the pixel 20b in Fig. 17.

[0145] 21 is a circuit diagram of a pixel 20d and a pixel circuit 21d according to a fifth embodiment of the present disclosure. The pixel 20d of FIG. 21 differs from the pixel 20 of FIG. 4 in that it includes an overflow transistor (fifth transistor) OFG. The overflow transistor OFG has a drain connected to a floating diffusion region FD3 and a source connected to the cathode (or anode) of the photoelectric conversion element PD. In addition, the source of the reset transistor RST of the pixel 20d is connected to the floating diffusion region FD2.

[0146] The overflow transistor OFG can transfer the charge photoelectrically converted by the photoelectric conversion element PD to the floating diffusion region FD3, the first capacitor MIMA, and the second capacitor MIMB. As a result, the pixel 20d in Fig. 21 can transfer the overflow charge of the photoelectric conversion element PD to the first capacitor MIMA and the second capacitor MIMB without passing through the floating diffusion regions FD1 and FD2.

[0147] In pixel 20d, the accumulated charge of the photoelectric conversion element PD is transferred directly to the floating diffusion region FD3 via the overflow transistor OFG, so that the dark current components accumulated in the floating diffusion regions FD1 and FD2 are no longer transferred to the floating diffusion region FD3.

[0148] Sixth Embodiment As shown in FIG. 11B, the first capacitor MIMA and the charge cancellation unit 22 can be disposed on, for example, the pixel substrate b1, but the location of the first capacitor MIMA and the charge cancellation unit 22 is not limited to the pixel substrate b1.

[0149] Fig. 22 is a cross-sectional view of a photodetector 10a according to a sixth embodiment of the present disclosure. The photodetector 10a in Fig. 22 includes an intermediate substrate (third substrate) b3 stacked between a pixel substrate b1 and a logic substrate b2. The pixel 20e and pixel circuit 21e in Fig. 22 are disposed on both the pixel substrate b1 and the intermediate substrate b3. The first capacitor MIMA, the second capacitor MIMB, and the capacitor MIM corresponding to the switching circuit are disposed on the intermediate substrate b3.

[0150] Fig. 23 is a circuit diagram of a pixel 20e and a pixel circuit 21e according to a sixth embodiment of the present disclosure. As shown in Fig. 23, a first capacitor MIMA and a charge cancellation unit 22 are arranged on an intermediate substrate b3. The circuit configurations of the pixel 20e and the pixel circuit 21e are the same as those in Fig. 4. The switching circuit (switching transistors MT1 to MT4) in Fig. 23 may be arranged on the pixel substrate b1 or the logic substrate b2.

[0151] FIG. 24 is a plan view of a pixel 20e and a pixel circuit 21e according to a sixth embodiment of the present disclosure. FIG. 24 illustrates the planar configurations of the pixel substrate b1 and the intermediate substrate b3, overlapping each other. The pixel substrate b1 and the intermediate substrate b3 are connected by a floating diffusion region FD3. A ground voltage Vss is disposed in the center of the intermediate substrate b3. A ring-shaped charge cancellation unit 22 is also disposed surrounding the ground voltage Vss. Specifically, from the bottom left of the intermediate substrate b3, the upper electrode MIMB_Upper of the second capacitor MIMB, the switching transistor MT3, the lower electrode MIMA_Lower and floating diffusion region FD3 of the first capacitor MIMA, the switching transistor MT4, the lower electrode MIMB_Lower of the second capacitor MIMB, the switching transistor MT1, the upper electrode MIMA_Upper and power supply voltage MIMVDD of the first capacitor MIMA, and the switching transistor MT2 are disposed clockwise.

[0152] On the pixel substrate b1, there are arranged, clockwise from the bottom left, a ground voltage Vss, a vertical signal line VSL, a selection transistor SEL, an amplification transistor AMP, a power supply voltage VDD, a reset transistor RST, a floating diffusion region FD3, a second conversion efficiency transistor FCG, a floating diffusion region FD2, and a first conversion efficiency transistor FDG. Further, from the first conversion efficiency transistor FDG towards the center, there are arranged a floating diffusion region FD1 and a transfer transistor TG.

[0153] A photodetector 10a according to a sixth embodiment of the present disclosure can operate in the same manner as the photodetector 10 shown in FIG. 11B. Furthermore, the photodetector 10a can reduce the area of ​​the pixel 20e by arranging the first capacitor MIMA and the charge cancellation unit 22 on the intermediate substrate b3. This allows the photodetector 10a to be easily miniaturized and downsized. The sixth embodiment of the present disclosure can be applied to any of the first to fifth embodiments.

[0154] Seventh Embodiment In the first to sixth embodiments, an example is shown in which the charge cancellation unit 22 is applied to a pixel 20 driven by LOFIC. The charge cancellation unit 22 is applicable to various pixels in which a capacitor that generates dielectric absorption charge holds charge generated by photoelectric conversion. FIG. 25 is a circuit diagram of a pixel 20f and a pixel circuit 21f according to a seventh embodiment of the present disclosure. The pixel 20f is a global shutter pixel, and includes a fourth capacitor MIMEa for a reset level and a fifth capacitor MIMEb for a signal level, as well as a first cancellation unit 62a and a second cancellation unit 62b connected to the fourth capacitor MIMEa and the fifth capacitor MIMEb, respectively.

[0155] The pixel 20f has a pixel main section 51 and a signal holding section 52. The pixel main section 51 has a photoelectric conversion element PD, a transfer transistor TG, a conversion efficiency transistor DCG, a reset transistor RST, a floating diffusion region (first floating diffusion region) FD1, a first amplification transistor AMPa, and a current source 53. The current source 53 has transistors 53a and 53b connected in series between the source of the first amplification transistor AMPa and a ground node. A control signal PC is input to the gate of the transistor 53a. A selection signal SELa is input to the gate of the transistor 53b (first selection transistor SELa). The conversion efficiency transistor DCG, the first amplification transistor AMPa, and the first selection transistor SELa correspond to the first conversion efficiency transistor FDG, the amplification transistor AMP, and the selection transistor SEL in FIG. 4, respectively.

[0156] The first amplification transistor AMPa constitutes a first source follower circuit 23. The first source follower circuit 23 generates a voltage corresponding to the charge held in the floating diffusion region FD1. A voltage corresponding to the charge photoelectrically converted by the photoelectric conversion element PD is output from the source of the first amplification transistor AMPa and input to the signal holding unit 52. The pixel main unit 51 sequentially outputs a voltage Vp corresponding to the reset level and a voltage Vd corresponding to the signal level for each frame.

[0157] The signal holding unit 52 has a first voltage holding unit 61a, a second voltage holding unit 61b, a first cancellation unit 62a, a second cancellation unit 62b, a second amplification transistor AMPb, a second selection transistor SELb, a third selection transistor SELc, and a floating diffusion region (second floating diffusion region) FD2.

[0158] The first voltage holding unit 61a holds a reset level voltage Vp. The first voltage holding unit 61a has a fourth capacitor MIMEa and a switching transistor SMPa. The fourth capacitor MIMEa holds a charge corresponding to the reset level voltage Vp. The switching transistor SMPa controls charging and discharging of the fourth capacitor MIMEa. The drain of the switching transistor SMPa is connected to one end of the fourth capacitor MIMEa. The source of the switching transistor SMPa is connected to the floating diffusion region FD2.

[0159] The second voltage holding unit 61b holds a signal level voltage Vd. The second voltage holding unit 61b has a fifth capacitor MIMEb and a switching transistor SMPb. The fifth capacitor MIMEb holds a charge corresponding to the signal level voltage Vd. The switching transistor SMPb switches whether or not to transfer charge to the fifth capacitor MIMEb. The drain of the switching transistor SMPb is connected to one end of the fifth capacitor MIMEb. The source of the switching transistor SMPb is connected to the floating diffusion region FD2.

[0160] The first cancellation unit 62a is connected to the first voltage holding unit 61a. The first cancellation unit 62a cancels out the dielectric absorption charge discharged from the fourth capacitor MIMEa. The first cancellation unit 62a corresponds to the charge cancellation unit 22 in FIG. 4 and has a circuit configuration similar to that of the charge cancellation unit 22. Specifically, the first cancellation unit 62a includes switching transistors (switching circuits) MT1, MT2, MT3, and MT4, switching transistors (first switching circuits) MT1a, MT2a, MT3a, and MT4a corresponding to the second capacitor MIMB, and a sixth capacitor MIMFa.

[0161] The fourth capacitor MIMEa corresponds to the first capacitor MIMA in FIG. 4. The sixth capacitor MIMFa has a capacitance corresponding to the fourth capacitor MIMEa. More specifically, the fourth capacitor MIMEa and the sixth capacitor MIMFa are formed in the same process, have the same structure using the same material, and are arranged in the same layer. The sixth capacitor MIMFa has a capacitance equal to or less than the capacitance of the fourth capacitor MIMEa.

[0162] The second cancellation unit 62b is connected to the second voltage holding unit 61b. The second cancellation unit 62b cancels out the dielectric absorption charge discharged from the fifth capacitor MIMEb. Similar to the first cancellation unit 62a, the second cancellation unit 62b has switching transistors (second switching circuits) MT1b, MT2b, MT3b, MT4b corresponding to the switching transistors (switching circuits) MT1, MT2, MT3, MT4 and the second capacitor MIMB of the charge cancellation unit 22, and a seventh capacitor MIMFb.

[0163] The fifth capacitor MIMEb corresponds to the first capacitor MIMA in FIG. 4. The seventh capacitor MIMFb has a capacitance corresponding to the fifth capacitor MIMEb. More specifically, the fifth capacitor MIMEb and the seventh capacitor MIMFb are formed in the same process, have the same structure using the same material, and are arranged in the same layer. The seventh capacitor MIMFb has a capacitance equal to or less than the capacitance of the fifth capacitor MIMEb.

[0164] The fourth capacitor MIMEa, the fifth capacitor MIMEb, the sixth capacitor MIMFa, and the seventh capacitor MIMFb each have, for example, an MIM structure in which a high-k film is disposed between two electrodes.

[0165] The second select transistor SELb switches whether or not to transfer the voltages Vp and Vd generated by the first source follower circuit 23 to the signal holding unit 52. The drain of the second select transistor SELb is connected to the source of the first amplification transistor AMPa and the drain of the first select transistor SELa. The source of the second select transistor SELb is connected to the floating diffusion region FD2.

[0166] The second amplification transistor AMPb constitutes a second source follower circuit 63. The gate of the second amplification transistor AMPb has the same voltage as the floating diffusion region FD2 and is used as the input section of the second source follower circuit 63. The drain of the second amplification transistor AMPb is connected to the node of the power supply voltage VDD. The source of the second amplification transistor AMPb is connected to the drain of the third selection transistor SELc.

[0167] The third selection transistor SELc switches whether or not the pixel signals Vimgd and Vimgp are output from the pixel 20f. The pixel signals Vimgd and Vimgp are output from the source of the selection transistor SEL to the vertical signal line VSL.

[0168] The pixel main section 51 is disposed, for example, on the first pixel substrate b1a. The signal holding section 52 is disposed, for example, on the second pixel substrate b1b. The first pixel substrate b1a, the second pixel substrate b1b, and the logic substrate b2 are stacked in this order. The pixel main section and the signal holding section may be disposed on the same pixel substrate (for example, pixel substrate b1). Alternatively, they may be disposed separately on three or more pixel substrates.

[0169] The pixel 20f can adjust the timing of outputting the pixel signals Vimgd and Vimgp because it can hold the voltages Vp and Vd in the signal holding unit 52. The pixel 20f is particularly used for a global shutter operation.

[0170] 4, pixel 20f generates charge by exposure to light, reads out the generated charge, and discharges the generated charge for each frame. Furthermore, pixel 20f outputs pixel signals Vimgd and Vimgp for each frame. The signal processing unit 13 can generate an image for each frame based on these pixel signals input for each frame.

[0171] The pixel 20f discharges the charges held in the fourth capacitor MIMEa, the fifth capacitor MIMEb, the sixth capacitor MIMFa, and the seventh capacitor MIMFb every frame. The first cancellation unit 62a cancels out the dielectric absorption charge of the fourth capacitor MIMEa by alternately connecting the upper electrode and the lower electrode of the sixth capacitor MIMFa to the floating diffusion region FD2 every frame. The second cancellation unit 62b cancels out the dielectric absorption charge of the fifth capacitor MIMEb by alternately connecting the upper electrode and the lower electrode of the seventh capacitor MIMFb to the floating diffusion region FD2 every frame.

[0172] The pixel 20f may be provided with two first voltage holding units 61a for storing the pixel signal Vimgd separately as an HCG signal and an LCG signal. Alternatively, three or more first voltage holding units 61a may be provided for storing an MCG signal or the like. In this case, each of the multiple first voltage holding units 61a is connected to one first cancellation unit 62a. Similarly, the pixel 20f may be provided with multiple second voltage holding units 61b and multiple second cancellation units 62b.

[0173] The pixel 20 in Fig. 4 stores charges transferred from the photoelectric conversion element PD in each capacitor. The pixel 20 in Fig. 4 is called a charge domain driven pixel. In contrast, the pixel 20f in Fig. 25 stores a voltage generated by a first source follower circuit 23 based on charges generated by the photoelectric conversion element PD in each capacitor. The pixel 20f in Fig. 25 is called a voltage domain driven pixel or a VDGS (Voltage Domain Global Shutter) pixel.

[0174] As described above, the photodetector according to the seventh embodiment of the present disclosure includes global shutter pixels 20f, each of which includes a fourth capacitor MIMEa that holds a charge corresponding to a reset level voltage and a fifth capacitor MIMEb that holds a charge corresponding to a signal level voltage. If the fourth capacitor MIMEa and the fifth capacitor MIMEb are formed from a high-k material with a high dielectric constant, there is a risk of dielectric absorption charge being generated. Therefore, in this embodiment, similar to the first to sixth embodiments, a first cancellation unit 62a for canceling the dielectric absorption charge of the fourth capacitor MIMEa and a second cancellation unit 62b for canceling the dielectric absorption charge of the fifth capacitor MIMEb are provided. This prevents image lag due to dielectric absorption charge from occurring in a captured image generated by a pixel signal output from the pixel 20f, thereby improving the image quality of the captured image.

[0175] (Application Examples) The technology according to the present disclosure can be applied to various products. For example, the technology according to the present disclosure may be realized as a device mounted on any type of moving body, such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, personal mobility, an airplane, a drone, a ship, a robot, construction machinery, or agricultural machinery (tractor).

[0176] 26 is a block diagram showing a schematic configuration example of a vehicle control system 7000, which is an example of a mobile object control system to which the technology according to the present disclosure can be applied. The vehicle control system 7000 includes a plurality of electronic control units connected via a communication network 7010. In the example shown in FIG. 26 , the vehicle control system 7000 includes a drive system control unit 7100, a body system control unit 7200, a battery control unit 7300, an outside-vehicle information detection unit 7400, an inside-vehicle information detection unit 7500, and an integrated control unit 7600. The communication network 7010 connecting these multiple control units may be an in-vehicle communication network conforming to any standard, such as a Controller Area Network (CAN), a Local Interconnect Network (LIN), a Local Area Network (LAN), or FlexRay (registered trademark).

[0177] Each control unit includes a microcomputer that performs arithmetic processing according to various programs, a memory unit that stores the programs executed by the microcomputer or parameters used in various calculations, and a drive circuit that drives various controlled devices. Each control unit includes a network I / F for communicating with other control units via a communication network 7010, and a communication I / F for communicating with devices or sensors inside and outside the vehicle via wired or wireless communication. Figure 26 illustrates the functional configuration of the integrated control unit 7600, including a microcomputer 7610, a general-purpose communication I / F 7620, a dedicated communication I / F 7630, a positioning unit 7640, a beacon receiving unit 7650, an in-vehicle device I / F 7660, an audio / video output unit 7670, an in-vehicle network I / F 7680, and a memory unit 7690. The other control units also include a microcomputer, a communication I / F, a memory unit, and the like.

[0178] The drivetrain control unit 7100 controls the operation of devices related to the drivetrain of the vehicle in accordance with various programs. For example, the drivetrain control unit 7100 functions as a control device for a drive force generating device for generating drive force for the vehicle, such as an internal combustion engine or a drive motor, a drive force transmission mechanism for transmitting drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, and a braking device for generating braking force for the vehicle. The drivetrain control unit 7100 may also function as a control device for an ABS (Antilock Brake System) or an ESC (Electronic Stability Control), etc.

[0179] A vehicle state detection unit 7110 is connected to the drivetrain control unit 7100. The vehicle state detection unit 7110 includes at least one of a gyro sensor that detects the angular velocity of the axial rotational motion of the vehicle body, an acceleration sensor that detects the acceleration of the vehicle, or a sensor that detects the amount of operation of the accelerator pedal, the amount of operation of the brake pedal, the steering angle of the steering wheel, the engine rotation speed, the rotation speed of the wheels, etc. The drivetrain control unit 7100 performs arithmetic processing using signals input from the vehicle state detection unit 7110, and controls the internal combustion engine, the drive motor, the electric power steering device, the brake device, etc.

[0180] The body system control unit 7200 controls the operation of various devices equipped in the vehicle body according to various programs. For example, the body system control unit 7200 functions as a control device for a keyless entry system, a smart key system, a power window device, or various lamps such as headlamps, backup lamps, brake lamps, turn signals, and fog lamps. In this case, radio waves transmitted from a portable device that serves as a key or signals from various switches can be input to the body system control unit 7200. The body system control unit 7200 receives these radio waves or signals and controls the vehicle's door lock device, power window device, lamps, etc.

[0181] The battery control unit 7300 controls the secondary battery 7310, which is the power supply source for the drive motor, in accordance with various programs. For example, information such as battery temperature, battery output voltage, or remaining battery capacity is input to the battery control unit 7300 from a battery device equipped with the secondary battery 7310. The battery control unit 7300 performs arithmetic processing using these signals, and controls the temperature regulation of the secondary battery 7310 or a cooling device or the like equipped in the battery device.

[0182] The outside vehicle information detection unit 7400 detects information outside the vehicle equipped with the vehicle control system 7000. For example, at least one of an imaging unit 7410 and an outside vehicle information detection unit 7420 is connected to the outside vehicle information detection unit 7400. The imaging unit 7410 includes at least one of a time-of-flight (ToF) camera, a stereo camera, a monocular camera, an infrared camera, and other cameras. The outside vehicle information detection unit 7420 includes at least one of an environmental sensor for detecting the current weather or climate, or a surrounding information detection sensor for detecting other vehicles, obstacles, pedestrians, etc. around the vehicle equipped with the vehicle control system 7000.

[0183] The environmental sensor may be, for example, at least one of a raindrop sensor that detects rain, a fog sensor that detects fog, a sunshine sensor that detects the degree of sunshine, and a snow sensor that detects snowfall. The surrounding information detection sensor may be at least one of an ultrasonic sensor, a radar device, and a LIDAR (Light Detection and Ranging, Laser Imaging Detection and Ranging) device. The imaging unit 7410 and the outside vehicle information detection unit 7420 may each be provided as an independent sensor or device, or may be provided as a device in which multiple sensors or devices are integrated.

[0184] 27 shows an example of the installation positions of the imaging unit 7410 and the vehicle exterior information detection unit 7420. The imaging units 7910, 7912, 7914, 7916, and 7918 are provided, for example, at least one of the front nose, side mirrors, rear bumper, back door, and upper part of the windshield inside the vehicle cabin of the vehicle 7900. The imaging unit 7910 provided on the front nose and the imaging unit 7918 provided on the upper part of the windshield inside the vehicle cabin mainly acquire images of the front of the vehicle 7900. The imaging units 7912 and 7914 provided on the side mirrors mainly acquire images of the sides of the vehicle 7900. The imaging unit 7916 provided on the rear bumper or back door mainly acquires images of the rear of the vehicle 7900. The imaging unit 7918 provided on the upper part of the windshield inside the vehicle cabin is mainly used to detect leading vehicles, pedestrians, obstacles, traffic lights, traffic signs, lanes, etc.

[0185] 27 shows an example of the imaging ranges of the imaging units 7910, 7912, 7914, and 7916. Imaging range a indicates the imaging range of the imaging unit 7910 provided on the front nose, imaging ranges b and c indicate the imaging ranges of the imaging units 7912 and 7914 provided on the side mirrors, respectively, and imaging range d indicates the imaging range of the imaging unit 7916 provided on the rear bumper or back door. For example, by overlaying the image data captured by the imaging units 7910, 7912, 7914, and 7916, a bird's-eye view image of the vehicle 7900 viewed from above can be obtained.

[0186] The outside vehicle information detection units 7920, 7922, 7924, 7926, 7928, and 7930 provided on the front, rear, sides, corners, and above the windshield inside the vehicle cabin of the vehicle 7900 may be, for example, ultrasonic sensors or radar devices. The outside vehicle information detection units 7920, 7926, and 7930 provided on the front nose, rear bumper, back door, and above the windshield inside the vehicle cabin of the vehicle 7900 may be, for example, LIDAR devices. These outside vehicle information detection units 7920 to 7930 are mainly used to detect preceding vehicles, pedestrians, obstacles, etc.

[0187] Returning to FIG. 26 , the explanation will be continued. The outside-vehicle information detection unit 7400 causes the imaging unit 7410 to capture an image outside the vehicle and receives the captured image data. The outside-vehicle information detection unit 7400 also receives detection information from the connected outside-vehicle information detection unit 7420. If the outside-vehicle information detection unit 7420 is an ultrasonic sensor, a radar device, or a LIDAR device, the outside-vehicle information detection unit 7400 emits ultrasonic waves or electromagnetic waves and receives information on the received reflected waves. Based on the received information, the outside-vehicle information detection unit 7400 may perform object detection processing or distance detection processing for people, vehicles, obstacles, signs, or text on the road surface. Based on the received information, the outside-vehicle information detection unit 7400 may also perform environment recognition processing for recognizing rainfall, fog, road conditions, etc. Based on the received information, the outside-vehicle information detection unit 7400 may also calculate the distance to an object outside the vehicle.

[0188] The outside vehicle information detection unit 7400 may also perform image recognition processing or distance detection processing to recognize people, vehicles, obstacles, signs, or characters on the road surface based on the received image data. The outside vehicle information detection unit 7400 may perform processing such as distortion correction or alignment on the received image data, and may also generate an overhead image or a panoramic image by combining image data captured by different image capturing units 7410. The outside vehicle information detection unit 7400 may also perform viewpoint conversion processing using image data captured by different image capturing units 7410.

[0189] The interior information detection unit 7500 detects information inside the vehicle. A driver state detection unit 7510 that detects the driver's state is connected to the interior information detection unit 7500, for example. The driver state detection unit 7510 may include a camera that captures an image of the driver, a biosensor that detects the driver's biometric information, or a microphone that collects sound from within the vehicle cabin. The biosensor is provided, for example, on the seat or steering wheel, and detects the biometric information of a passenger sitting in the seat or the driver gripping the steering wheel. The interior information detection unit 7500 may calculate the driver's level of fatigue or concentration based on the detection information input from the driver state detection unit 7510, or may determine whether the driver is dozing off. The interior information detection unit 7500 may perform processing such as noise canceling on the collected audio signal.

[0190] The integrated control unit 7600 controls the overall operation of the vehicle control system 7000 according to various programs. An input unit 7800 is connected to the integrated control unit 7600. The input unit 7800 may be implemented by a device that can be operated by a passenger, such as a touch panel, a button, a microphone, a switch, or a lever. Data obtained by voice recognition of a voice input through a microphone may be input to the integrated control unit 7600. The input unit 7800 may be, for example, a remote control device using infrared or other radio waves, or an externally connected device such as a mobile phone or a personal digital assistant (PDA) that can operate the vehicle control system 7000. The input unit 7800 may be, for example, a camera, in which case the passenger can input information using gestures. Alternatively, data obtained by detecting the movement of a wearable device worn by the passenger may be input. Furthermore, the input unit 7800 may include, for example, an input control circuit that generates an input signal based on information input by the passenger using the input unit 7800 and outputs the input signal to the integrated control unit 7600. Passengers and the like operate this input unit 7800 to input various data to the vehicle control system 7000 and to instruct processing operations.

[0191] The storage unit 7690 may include a ROM (Read Only Memory) that stores various programs executed by the microcomputer, and a RAM (Random Access Memory) that stores various parameters, calculation results, sensor values, etc. The storage unit 7690 may also be realized by a magnetic storage device such as an HDD (Hard Disc Drive), a semiconductor storage device, an optical storage device, a magneto-optical storage device, or the like.

[0192] The general-purpose communication I / F 7620 is a general-purpose communication I / F that mediates communication with various devices present in the external environment 7750. The general-purpose communication I / F 7620 may implement a cellular communication protocol such as GSM (Global System of Mobile communications), WiMAX (registered trademark), LTE (Long Term Evolution), or LTE-Advanced (LTE-A), or other wireless communication protocols such as a wireless LAN (also referred to as Wi-Fi (registered trademark)) or Bluetooth (registered trademark). The general-purpose communication I / F 7620 may connect to a device (e.g., an application server or a control server) present on an external network (e.g., the Internet, a cloud network, or an operator-specific network) via, for example, a base station or an access point. In addition, the general-purpose communication I / F 7620 may connect to a terminal located near the vehicle (e.g., a terminal of a driver, pedestrian, or store, or an MTC (Machine Type Communication) terminal) using, for example, P2P (Peer To Peer) technology.

[0193] The dedicated communication I / F 7630 is a communication I / F that supports a communication protocol designed for use in vehicles. The dedicated communication I / F 7630 may implement a standard protocol such as WAVE (Wireless Access in Vehicle Environment), which is a combination of a lower layer IEEE 802.11p and an upper layer IEEE 1609, DSRC (Dedicated Short Range Communications), or a cellular communication protocol. The dedicated communication I / F 7630 typically performs V2X communication, which is a concept including one or more of vehicle-to-vehicle communication, vehicle-to-infrastructure communication, vehicle-to-home communication, and vehicle-to-pedestrian communication.

[0194] The positioning unit 7640 performs positioning by receiving, for example, GNSS signals from GNSS (Global Navigation Satellite System) satellites (for example, GPS signals from GPS (Global Positioning System) satellites), and generates position information including the latitude, longitude, and altitude of the vehicle. Note that the positioning unit 7640 may identify the current position by exchanging signals with a wireless access point, or may obtain position information from a terminal such as a mobile phone, PHS, or smartphone that has a positioning function.

[0195] The beacon receiving unit 7650 receives, for example, radio waves or electromagnetic waves transmitted from radio stations or the like installed on the road, and acquires information such as the current location, congestion, road closures, required travel time, etc. The function of the beacon receiving unit 7650 may be included in the dedicated communication I / F 7630 described above.

[0196] The in-vehicle device I / F 7660 is a communication interface that mediates connections between the microcomputer 7610 and various in-vehicle devices 7760 present in the vehicle. The in-vehicle device I / F 7660 may establish wireless connections using wireless communication protocols such as wireless LAN, Bluetooth (registered trademark), NFC (Near Field Communication), or WUSB (Wireless USB). Furthermore, the in-vehicle device I / F 7660 may establish a wired connection such as USB (Universal Serial Bus), HDMI (High-Definition Multimedia Interface), or MHL (Mobile High-Definition Link) via a connection terminal (and a cable, if necessary) not shown. The in-vehicle device 7760 may include, for example, at least one of a mobile device or a wearable device owned by a passenger, or an information device carried into or attached to the vehicle. The in-vehicle device 7760 may also include a navigation device that searches for a route to an arbitrary destination. The in-vehicle device I / F 7660 exchanges control signals or data signals with these in-vehicle devices 7760.

[0197] The in-vehicle network I / F 7680 is an interface that mediates communication between the microcomputer 7610 and the communication network 7010. The in-vehicle network I / F 7680 transmits and receives signals in accordance with a predetermined protocol supported by the communication network 7010.

[0198] The microcomputer 7610 of the integrated control unit 7600 controls the vehicle control system 7000 in accordance with various programs based on information acquired via at least one of the general-purpose communication I / F 7620, the dedicated communication I / F 7630, the positioning unit 7640, the beacon receiving unit 7650, the in-vehicle device I / F 7660, and the in-vehicle network I / F 7680. For example, the microcomputer 7610 may calculate control target values ​​for the driving force generating device, the steering mechanism, or the braking device based on the acquired information inside and outside the vehicle, and output control commands to the drivetrain control unit 7100. For example, the microcomputer 7610 may perform cooperative control aimed at realizing functions of an Advanced Driver Assistance System (ADAS), including vehicle collision avoidance or impact mitigation, following driving based on the following distance, vehicle speed maintenance driving, vehicle collision warning, vehicle lane departure warning, etc. In addition, the microcomputer 7610 may perform cooperative control for the purpose of autonomous driving, in which the vehicle travels autonomously without relying on driver operation, by controlling a driving force generating device, a steering mechanism, a braking device, etc. based on information acquired about the vehicle's surroundings.

[0199] The microcomputer 7610 may generate three-dimensional distance information between the vehicle and objects such as surrounding structures and people, and create local map information including information about the vicinity of the vehicle's current location, based on information acquired via at least one of the general-purpose communication I / F 7620, the dedicated communication I / F 7630, the positioning unit 7640, the beacon receiving unit 7650, the in-vehicle device I / F 7660, and the in-vehicle network I / F 7680. Furthermore, the microcomputer 7610 may predict dangers, such as a vehicle collision, the approach of a pedestrian, or entry into a closed road, based on the acquired information, and generate a warning signal. The warning signal may be, for example, a signal for generating a warning sound or turning on a warning lamp.

[0200] The audio / image output unit 7670 transmits at least one audio and / or image output signal to an output device capable of visually or audibly notifying vehicle occupants or the outside of the vehicle of information. In the example of FIG. 26 , an audio speaker 7710, a display unit 7720, and an instrument panel 7730 are illustrated as examples of the output devices. The display unit 7720 may include, for example, at least one of an on-board display and a head-up display. The display unit 7720 may have an AR (Augmented Reality) display function. The output device may also be other devices, such as headphones, a wearable device such as an eyeglass-type display worn by the occupant, a projector, or a lamp. When the output device is a display device, the display device visually displays results obtained by various processes performed by the microcomputer 7610 or information received from other control units in various formats, such as text, images, tables, and graphs. When the output device is an audio output device, the audio output device converts audio signals, such as reproduced audio data or acoustic data, into analog signals and audibly outputs the analog signals.

[0201] In the example shown in FIG. 26 , at least two control units connected via the communication network 7010 may be integrated into a single control unit. Alternatively, each control unit may be composed of multiple control units. Furthermore, the vehicle control system 7000 may include another control unit not shown. In the above description, some or all of the functions performed by one of the control units may be assigned to another control unit. In other words, as long as information is transmitted and received via the communication network 7010, predetermined arithmetic processing may be performed by one of the control units. Similarly, a sensor or device connected to one of the control units may be connected to another control unit, and multiple control units may transmit and receive detection information to and from each other via the communication network 7010.

[0202] In the vehicle control system 7000 described above, the photodetector 10 according to the present embodiment described with reference to Fig. 2 can be applied to the image capturing unit 7410 of the application example shown in Fig. 26. This allows the image capturing unit 7410 to output higher quality images.

[0203] The present technology may be configured as follows: (1) A photodetector comprising: a photoelectric conversion element; a floating diffusion region that holds charge photoelectrically converted by the photoelectric conversion element; a first capacitor that holds charge corresponding to the charge held in the floating diffusion region; and a charge cancellation unit that cancels out dielectric absorption charge discharged from the first capacitor after discharging the charge held in the first capacitor. (2) The photodetector according to (1), comprising: a signal processing unit that generates an image for each frame based on pixel signals photoelectrically converted by a plurality of the photoelectric conversion elements, the charge cancellation unit including: a second capacitor that has a capacitance corresponding to the capacitance of the first capacitor and is connected to the first capacitor; and a switching circuit that alternately switches the connection between the first capacitor and the second capacitor for each frame, thereby canceling out the dielectric absorption charge discharged from the first capacitor with the dielectric absorption charge discharged from the second capacitor. (3) The photodetector according to (2), wherein the switching circuit alternately switches, for each frame, between connecting the upper electrode of the first capacitor to the upper electrode of the second capacitor and connecting the lower electrode of the first capacitor to the lower electrode of the second capacitor, or connecting the upper electrode of the first capacitor to the lower electrode of the second capacitor and connecting the lower electrode of the first capacitor to the upper electrode of the second capacitor. (4) The photodetector according to (2) or (3), wherein the second capacitor has a capacitance equal to or less than that of the first capacitor. (5) The photodetector according to any one of (2) to (4), wherein the first capacitor and the second capacitor have the same structure made of the same material and are arranged in the same layer. (6) The photodetector according to any one of (2) to (5), wherein the first capacitor and the second capacitor each have a high-k film arranged between two electrodes. (7) A photodetector device according to any one of (2) to (6), comprising: a first substrate on which the plurality of photoelectric conversion elements are arranged; and a second substrate stacked on the first substrate and on which the signal processing unit is arranged, wherein the first capacitor, the second capacitor, and the switching circuit are each arranged on the first substrate or the second substrate.(8) The photodetector according to any one of (2) to (6), comprising: a first substrate on which the plurality of photoelectric conversion elements are arranged, a second substrate stacked on the first substrate and on which the signal processing unit is arranged, and a third substrate stacked between the first and second substrates and on which the first capacitor and the second capacitor are arranged, wherein the switching circuit is arranged on the first substrate, the second substrate, or the third substrate. (9) The photodetector according to any one of (2) to (8), wherein the floating diffusion region has a first floating diffusion region and a second floating diffusion region, and further comprising: a first transistor that transfers charges photoelectrically converted by the photoelectric conversion elements to the first floating diffusion region, and a second transistor that transfers at least a portion of the charges held in the first floating diffusion region to the second floating diffusion region, (10) The photodetector according to (9), comprising a pixel circuit that reads out a pixel signal of a signal level based on the amount of charge in the first floating diffusion region, the second floating diffusion region, the first capacitor, and the second capacitor that is held in accordance with the charge overflowing due to photoelectric conversion of the photoelectric conversion element, and then reads out a pixel signal of a reset level in a state in which the charge held in the first floating diffusion region, the second floating diffusion region, the first capacitor, and the second capacitor has been drained. (11) The photodetector according to (10), wherein the pixel circuit reads out a pixel signal of a signal level in a state in which charge corresponding to the amount of light incident on the photoelectric conversion element has been transferred to the first floating diffusion region, and then reads out a pixel signal of a reset level in a state in which the charge in the first floating diffusion region has been drained or in a state in which the charge overflowing from the photoelectric conversion element is held in the first floating diffusion region. (12) The photodetector device according to any one of (9) to (11), wherein the floating diffusion region has a third floating diffusion region, and further comprises a third transistor that transfers at least a portion of the charge held in the first floating diffusion region to the third floating diffusion region, and the second transistor transfers at least a portion of the charge held in the third floating diffusion region to the second floating diffusion region.(13) The photodetector according to (12), further comprising a third capacitor that holds at least a portion of the charge held in the third floating diffusion region. (14) The photodetector according to (13), further comprising: a pixel signal at a signal level based on the charge held in at least one of the first floating diffusion region, the third floating diffusion region, and the third capacitor, in a state where charge corresponding to the amount of light incident on the photoelectric conversion element is held in at least one of the first floating diffusion region, the third floating diffusion region, and the third capacitor, after reading out a pixel signal at a reset level in a state where charge held in the first floating diffusion region, the third floating diffusion region, and the third capacitor in accordance with the amount of light incident on the photoelectric conversion element is drained, or in a state where charge overflowing from the photoelectric conversion element is held in at least one of the first floating diffusion region, the third floating diffusion region, and the third capacitor. (15) The photodetector according to (13) or (14), wherein the capacitance of the second capacitor is equal to or less than the sum of the capacitance of the first capacitor and the capacitance of the third capacitor. (16) The photodetector according to any one of (13) to (15), wherein the first capacitor, the second capacitor, and the third capacitor are made of the same material, have the same structure, and are arranged in the same layer, and the third capacitor has a high-k film arranged between two electrodes. (17) The photodetector according to any one of (9) to (16), wherein charges held in the first floating diffusion region and the second floating diffusion region are discharged via the switching circuit or by turning on a fourth reset transistor. (18) The photodetector according to any one of (2) to (17), further comprising a fifth transistor that transfers charges photoelectrically converted by the photoelectric conversion element to the first capacitor and the second capacitor.(19) The floating diffusion region has a first floating diffusion region and a second floating diffusion region, and further comprises: a first transistor that transfers charge photoelectrically converted by the photoelectric conversion element to the first floating diffusion region; a first source follower circuit that generates a voltage according to charge held in the first floating diffusion region; a first voltage holding unit that holds a reset level voltage generated by the first source follower circuit in a state where the charge held in the first floating diffusion region is discharged; and a second voltage holding unit that holds a signal level voltage generated by the first source follower circuit in a state where charge according to the amount of light incident on the photoelectric conversion element is held in the first floating diffusion region; the charge cancellation unit has a first cancellation unit connected to the first voltage holding unit and a second cancellation unit connected to the second voltage holding unit; and the first capacitor has: a fourth capacitor provided in the first voltage holding unit that holds charge according to the reset level voltage; and a fifth capacitor provided in the second voltage holding unit that holds charge according to the signal level voltage. The photodetector according to (1), wherein the first cancellation unit cancels out the dielectric absorption charge discharged from the fourth capacitor, and the second cancellation unit cancels out the dielectric absorption charge discharged from the fifth capacitor.(20) The photodetector according to (19), further comprising: a second source follower circuit that generates a pixel signal at a signal level corresponding to a voltage held in the first voltage holding unit or the second voltage holding unit; and a signal processing unit that generates an image for each frame based on the pixel signals photoelectrically converted by the plurality of photoelectric conversion elements, wherein the first cancellation unit comprises: a sixth capacitor having a capacitance corresponding to a capacitance of the fourth capacitor and connected to the fourth capacitor; and a first switching circuit that alternately switches the connection between the fourth capacitor and the sixth capacitor for each frame to cancel out the dielectric absorption charge discharged from the fourth capacitor with the dielectric absorption charge discharged from the sixth capacitor; and the second cancellation unit comprises: a seventh capacitor having a capacitance corresponding to a capacitance of the fifth capacitor and connected to the fifth capacitor; and a second switching circuit that alternately switches the connection between the fifth capacitor and the seventh capacitor for each frame to cancel out the dielectric absorption charge discharged from the fifth capacitor with the dielectric absorption charge discharged from the seventh capacitor.

[0204] The aspects of the present disclosure are not limited to the individual embodiments described above, but include various modifications that may be conceived by those skilled in the art, and the effects of the present disclosure are not limited to the above-described contents. In other words, various additions, modifications, and partial deletions are possible within the scope of the conceptual idea and spirit of the present disclosure, which is derived from the contents defined in the claims and their equivalents.

[0205] REFERENCE SIGNS LIST 1 Electronic device, 2 Processing unit, 3 Recording unit, 4 Control unit, 5 Imaging lens, 10, 10a Photodetector, 11 Pixel array unit, 12 Row driver unit, 13 Signal processing unit, 14 Timing control unit, 20, 20a, 20b, 20c, 20d, 20e, 20f, 100 Pixel, 21, 21a, 21b, 21c, 21d, 21e, 21f, 101 Pixel circuit, 22 Charge cancellation unit, 23 First source follower circuit, 40 On-chip lens, 51 Pixel main unit, 52 Signal holding unit, 61a First voltage holding unit, 61b Second voltage holding unit, 62a First cancellation unit, 62b Second cancellation unit, 63 Second source follower circuit

Claims

1. A photodetection device comprising: a photoelectric conversion element; a floating diffusion region that holds charges photoelectrically converted by the photoelectric conversion element; a first capacitor that holds charges corresponding to the charges held in the floating diffusion region; and a charge cancellation unit that cancels dielectric absorption charges discharged from the first capacitor after discharging the charges held in the first capacitor.

2. The photodetection device according to claim 1, further comprising a signal processing unit that generates an image for each frame based on pixel signals photoelectrically converted by a plurality of the photoelectric conversion elements, wherein the charge cancellation unit includes: a second capacitor having a capacitance corresponding to the capacitance of the first capacitor and connected to the first capacitor; and a switching circuit that alternately switches the connection between the first capacitor and the second capacitor for each frame to cancel the dielectric absorption charges discharged from the first capacitor with the dielectric absorption charges discharged from the second capacitor.

3. The photodetection device according to claim 2, wherein the switching circuit alternately switches, for each frame, to connect the upper electrode of the first capacitor to the upper electrode of the second capacitor and connect the lower electrode of the first capacitor to the lower electrode of the second capacitor, or to connect the upper electrode of the first capacitor to the lower electrode of the second capacitor and connect the lower electrode of the first capacitor to the upper electrode of the second capacitor.

4. The photodetection device according to claim 2, wherein the second capacitor has a capacitance equal to or less than the capacitance of the first capacitor.

5. The photodetection device according to claim 2, wherein the first capacitor and the second capacitor have the same structure made of the same material and are arranged in the same layer.

6. The photodetection device according to claim 2, wherein the first capacitor and the second capacitor each have a High-k film disposed between two electrodes.

7. The photodetection device according to claim 2, further comprising: a first substrate on which the plurality of photoelectric conversion elements are arranged; and a second substrate laminated on the first substrate and on which the signal processing unit is arranged, wherein each of the first capacitor, the second capacitor, and the switching circuit is arranged on the first substrate or the second substrate.

8. A first substrate on which the plurality of photoelectric conversion elements are arranged, a second substrate laminated on the first substrate and on which the signal processing unit is arranged, and a third substrate laminated between the first substrate and the second substrate and on which the first capacitor and the second capacitor are arranged, wherein the switching circuit is arranged on the first substrate, the second substrate, or the third substrate. The photodetection device according to claim 2.

9. The floating diffusion region has a first floating diffusion region and a second floating diffusion region, and further includes a first transistor that transfers the charge photoelectrically converted by the photoelectric conversion element to the first floating diffusion region, and a second transistor that transfers at least a part of the holding charge of the first floating diffusion region directly or indirectly to the second floating diffusion region. The first capacitor and the second capacitor hold at least a part of the holding charge of the second floating diffusion region. The photodetection device according to claim 2.

10. A pixel circuit that reads out a pixel signal of a signal level based on the charge amounts of the first floating diffusion region, the second floating diffusion region, the first capacitor, and the second capacitor held in response to the charge overflowing due to the photoelectric conversion of the photoelectric conversion element, and then reads out a pixel signal of a reset level in a state where the holding charges of the first floating diffusion region, the second floating diffusion region, the first capacitor, and the second capacitor are discharged. The photodetection device according to claim 9.

11. The pixel circuit reads out a pixel signal of a signal level in a state where the charge of the first floating diffusion region is transferred according to the amount of incident light to the photoelectric conversion element after reading out a pixel signal of a reset level in a state where the charge of the first floating diffusion region is discharged or in a state where the charge overflowing from the photoelectric conversion element is held in the first floating diffusion region. The photodetection device according to claim 10.

12. The floating diffusion region has a third floating diffusion region, and further includes a third transistor that transfers at least a part of the holding charge of the first floating diffusion region to the third floating diffusion region. The second transistor transfers at least a part of the holding charge of the third floating diffusion region to the second floating diffusion region. The photodetection device according to claim 9.

13. The photodetection device according to claim 12, further comprising a third capacitor that holds at least a part of the holding charge of the third floating diffusion region.

14. After reading out the pixel signal of the reset level in a state where the charges in the first floating diffusion region, the third floating diffusion region, and the third capacitor held according to the amount of incident light on the photoelectric conversion element are discharged, or in a state where the charges overflowing from the photoelectric conversion element are held in at least one of the first floating diffusion region, the third floating diffusion region, or the third capacitor, the charge corresponding to the amount of incident light on the photoelectric conversion element is held in at least one of the first floating diffusion region, the third floating diffusion region, or the third capacitor, and the pixel signal of the signal level based on the holding charge of at least one of the first floating diffusion region, the third floating diffusion region, or the third capacitor is read out. The photodetection device according to claim 13.

15. The capacitance of the second capacitor is less than or equal to the sum of the capacitance of the first capacitor and the capacitance of the third capacitor. The photodetection device according to claim 13.

16. The first capacitor, the second capacitor, and the third capacitor are formed of the same material with the same structure and are arranged in the same layer. The third capacitor has a High-k film disposed between two electrodes. The photodetection device according to claim 13.

17. Discharging the holding charges in the first floating diffusion region and the second floating diffusion region is performed via the switching circuit or by turning on a fourth transistor for reset. The photodetection device according to claim 9.

18. The photodetection device according to claim 2, further comprising a fifth transistor that transfers the charges photoelectrically converted by the photoelectric conversion element to the first capacitor and the second capacitor.

19. The floating diffusion region has a first floating diffusion region and a second floating diffusion region, and includes a first transistor that transfers the charges photoelectrically converted by the photoelectric conversion element to the first floating diffusion region, a first source follower circuit that generates a voltage corresponding to the held charges in the first floating diffusion region, a first voltage holding unit that holds the voltage at the reset level generated by the first source follower circuit in a state where the held charges in the first floating diffusion region are discharged, and a second voltage holding unit that holds the voltage at the signal level generated by the first source follower circuit in a state where the charges corresponding to the amount of incident light on the photoelectric conversion element are held in the first floating diffusion region. The charge cancellation unit includes a first cancellation unit connected to the first voltage holding unit and a second cancellation unit connected to the second voltage holding unit. The first capacitor includes a fourth capacitor provided in the first voltage holding unit and holding charges corresponding to the voltage at the reset level, and a fifth capacitor provided in the second voltage holding unit and holding charges corresponding to the voltage at the signal level. The first cancellation unit cancels the dielectric absorption charges discharged from the fourth capacitor, and the second cancellation unit cancels the dielectric absorption charges discharged from the fifth capacitor. The photodetection device according to claim 1.

20. A second source follower circuit that generates a pixel signal having a signal level corresponding to the voltage held in the first voltage holding unit or the second voltage holding unit, and a signal processing unit that generates an image for each frame based on the pixel signals photoelectrically converted by the plurality of photoelectric conversion elements. The first canceling unit includes a sixth capacitor having a capacitance corresponding to the capacitance of the fourth capacitor and connected to the fourth capacitor, and a first switching circuit that alternately switches the connection between the fourth capacitor and the sixth capacitor for each frame to cancel the dielectric absorption charge discharged from the fourth capacitor with the dielectric absorption charge discharged from the sixth capacitor. The second canceling unit includes a seventh capacitor having a capacitance corresponding to the capacitance of the fifth capacitor and connected to the fifth capacitor, and a second switching circuit that alternately switches the connection between the fifth capacitor and the seventh capacitor for each frame to cancel the dielectric absorption charge discharged from the fifth capacitor with the dielectric absorption charge discharged from the seventh capacitor. The optical detection device according to claim 19.

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