Carrier structure and method for manufacturing electronic device

Abstract

A carrier structure (1000) comprises: a substrate (102); an insulating layer (103, 106) formed above the substrate (102); first wiring (1041) formed above the insulating layer (103, 106); second wiring (1042) formed above the insulating layer (103, 106); a first terminal pad (101C) electrically connected to the first wiring (1041); a second terminal pad (101A) electrically connected to the second wiring (1042); and a functional element unit (170) including a functional element (111), a first electrode (112), a second electrode (113), and an insulating member (161) that covers the functional element (111), and joined to the first wiring (1041) and the second wiring (1042) such that a gap (109) is provided between the functional element unit and the insulating layer (103, 106).

Description

Carrier structure and method for manufacturing electronic device

[0001] The present disclosure relates to a carrier structure and a method for manufacturing an electronic device.

[0002] A technique for manufacturing an electronic device has been proposed (see, for example, Patent Document 1) in which a composite integrated film formed on a growth substrate is peeled off from the growth substrate using a transfer stamp and attached (i.e., transferred) to a device substrate (i.e., a mounting substrate). Here, the composite integrated film is a functional element unit having functional elements such as light-emitting elements. The electronic device is a device having a device substrate and a functional element unit bonded thereto.

[0003] Japanese Patent Application Laid-Open No. 2022-79295

[0004] However, when a defective portion is found in a functional element in a functional element unit provided on a device substrate by a function test, a complicated process is required to remove the functional element unit from the device substrate.

[0005] An object of the present disclosure is to provide a carrier structure that enables functional testing of functional elements, and a method for manufacturing an electronic device that uses a functional element unit peeled from the carrier structure.

[0006] The carrier structure of the present disclosure comprises a substrate, an insulating layer formed above the substrate, a first wiring formed above the insulating layer, a second wiring formed above the insulating layer and separated from the first wiring, a first terminal pad electrically connected to the first wiring, a second terminal pad electrically connected to the second wiring, a functional element, a first electrode electrically connected to the functional element, a second electrode electrically connected to the functional element, and an insulating member covering the functional element, the functional element unit being joined to the first wiring and the second wiring so as to provide a gap between the first wiring and the second wiring, and characterized in that the first electrode is electrically joined to the first wiring and the second electrode is electrically joined to the second wiring.

[0007] The method for manufacturing an electronic device according to the present disclosure is characterized by comprising the steps of: preparing a carrier structure including a substrate, an insulating layer formed above the substrate, a first wiring formed above the insulating layer, a second wiring formed above the insulating layer and separated from the first wiring, a first terminal pad electrically connected to the first wiring, a second terminal pad electrically connected to the second wiring, a functional element unit including a functional element, a first electrode electrically connected to the functional element, a second electrode electrically connected to the functional element, and an insulating member covering the functional element, wherein the first electrode is electrically connected to the first wiring and the second electrode is electrically connected to the second wiring; inspecting the functional element unit using the first terminal pad and the second terminal pad; peeling the functional element unit from the first wiring and the second wiring; and attaching the peeled functional element unit to a device substrate.

[0008] According to the carrier structure of the present disclosure, functional tests can be performed on functional elements before they are transferred to a device substrate, thereby preventing functional element units in which defects are found from being transferred to a device substrate.

[0009] According to the electronic device manufacturing method disclosed herein, functional element units are peeled off from a carrier structure that enables functional testing of the functional elements and are transferred to a device substrate, thereby preventing functional element units in which defects are found from being transferred to the device substrate.

[0010] 1A is a schematic cross-sectional view showing a composite integrated film as a functional element unit formed on a sacrificial layer, and FIG. 1B is a schematic cross-sectional view showing a peeling process of the composite integrated film. FIG. 1A is a schematic cross-sectional view showing a transfer process of the composite integrated film to a carrier substrate, and FIG. 1B is a schematic cross-sectional view showing a carrier structure according to the first embodiment. FIG. 1B is a schematic perspective view showing a portion of the carrier structure according to the first embodiment. FIG. 1A is a schematic cross-sectional view showing a state in which the composite integrated film has been peeled off and lifted from the carrier substrate. FIG. 1B is a schematic cross-sectional view showing a transfer process in which the composite integrated film peeled off from the carrier substrate is attached to a device substrate, and FIG. 1B is a schematic cross-sectional view showing an electronic device having a device substrate and the composite integrated film. FIG. 1A and FIG. 1B are a schematic cross-sectional view and a schematic plan view showing a conductive pattern and terminal pads as wiring layers of the carrier substrate. FIG. 1C is a schematic plan view showing a state in which a test device is placed on the terminal pads of the carrier substrate. FIG. 1C is a schematic perspective view, a schematic side view, and a schematic plan view showing a carrier substrate formation process (part 1). 13A, 13B, and 13C are schematic perspective views, side views, and plan views illustrating a carrier substrate forming step (part 2). (A), (B), and (C) are schematic perspective views, side views, and plan views illustrating a carrier substrate forming step (part 3). (A), (B), and (C) are schematic perspective views, side views, and plan views illustrating a carrier substrate forming step (part 4). (A), (B), and (C) are schematic perspective views, side views, and plan views illustrating a carrier substrate forming step (part 5). (A), (B), and (C) are schematic perspective views, side views, and plan views illustrating a carrier substrate forming step (part 6). (A), (B), and (C) are schematic perspective views showing a modified example of the carrier substrate of FIG. 13A. (A), (B), and (C) are schematic perspective views, side views, and plan views illustrating a carrier substrate forming step (part 7). 15A and 15B are schematic perspective views showing a modified example of the carrier substrate of Fig. 15A, and Fig. 15A, 15B, and 15C are schematic perspective, side, and plan views showing a portion of a carrier structure including a carrier substrate and a composite integration film.18(B) are a schematic perspective view and a schematic cross-sectional view showing a portion of a carrier structure including a carrier substrate and a composite integration film. (A) and (B) are schematic cross-sectional views showing a modified example of the carrier structure of FIG. 18(B). (A), (B), and (C) are schematic cross-sectional views showing a composite integration film forming process (part 1). (A), (B), and (C) are schematic cross-sectional views showing a composite integration film forming process (part 2). (A), (B), and (C) are schematic cross-sectional views showing a composite integration film forming process (part 3). (A), (B), and (C) are schematic cross-sectional views showing a composite integration film forming process (part 4). (A), (B), and (C) are schematic cross-sectional views showing a composite integration film forming process (part 5). A schematic plan view showing a composite integration film forming process (part 5). (A), (B), and (C) are schematic cross-sectional views showing a composite integration film forming process (part 6). 1A is a schematic plan view showing a composite integrated film forming step (part 6), and (B) and (C) are schematic plan views showing modified examples of the composite integrated film forming step (part 6). (A), (B), and (C) are schematic cross-sectional views showing a composite integrated film forming step (part 7). (A) and (B) are schematic cross-sectional views showing a composite integrated film transferring step. (A) and (B) are schematic perspective views showing a composite integrated film replacing step. (A) is a schematic perspective view showing a portion of an electronic device according to embodiment 1. (A) is a flowchart showing a method for manufacturing an electronic device according to embodiment 1. (A), (B), and (C) are schematic cross-sectional views showing a functional element forming step, a peeling step, and a transferring step in embodiment 2. (A) and (B) are schematic cross-sectional views showing a carrier structure forming step according to embodiment 2. (A) and (B) are schematic perspective views showing a portion of a carrier structure according to embodiment 2. (A) and (B) are schematic cross-sectional views showing a method for manufacturing an electronic device according to embodiment 2. (A) is a schematic plan view showing wiring and terminal pads of a carrier substrate. 1A, 1B, and 1C are a schematic perspective view, a schematic side view, and a schematic plan view showing a carrier substrate forming step (part 1), and a schematic perspective view, a schematic side view, and a schematic plan view showing a carrier substrate forming step (part 2).(A), (B), and (C) are schematic perspective views, schematic side views, and schematic plan views showing a carrier substrate formation process (part 3). (A), (B), and (C) are schematic perspective views, schematic side views, and schematic plan views showing a carrier substrate formation process (part 4). (A), (B), and (C) are schematic perspective views, schematic side views, and schematic plan views showing another carrier substrate formation process (part 4a). (A), (B), and (C) are schematic perspective views, schematic side views, and schematic plan views showing a carrier substrate formation process (part 5). (A), (B), and (C) are schematic perspective views, schematic side views, and schematic plan views showing another carrier substrate formation process (part 5a). (A), (B), and (C) are schematic perspective views, schematic side views, and schematic plan views showing a carrier substrate formation process (part 6). 53 。 54 (A), (B), and (C) are a schematic perspective view, a schematic side view, and a schematic plan view showing another step (part 6a) of forming a carrier substrate. 55 (A), (B), and (C) are a schematic cross-sectional view showing another step (part 6) of forming a carrier substrate. 56 (A), (B), and (C) are a schematic cross-sectional view showing another step (part 1) of transferring a functional element. 57 (A), (B), and (C) are a schematic cross-sectional view showing another step (part 2) of transferring a functional element. 58 (A), (B), and (C) are a schematic plan view showing another step (part 3) of transferring a functional element. 59 (A), (B), and (C) are a schematic cross-sectional view showing another step (part 1) of forming a carrier structure. 59 (A), (B), (C), and (D) are a schematic cross-sectional view, a schematic plan view, a schematic cross-sectional view, and a schematic perspective view showing another step (part 2) of forming a carrier structure. 59 (A), (B), (C), and (D) are a schematic cross-sectional view, a schematic plan view, a schematic cross-sectional view, and a schematic perspective view showing another step (part 3) of forming a carrier structure. Fig. 1 is a schematic cross-sectional view showing a carrier structure according to embodiment 2. (A), (B), (C), and (D) are a schematic cross-sectional view, a schematic plan view, a schematic cross-sectional view, and a schematic perspective view showing the carrier structure. Fig. 2 is a schematic cross-sectional view showing another example of the carrier structure according to embodiment 2. (A), (B), and (C) are schematic perspective views showing another example of the carrier structure. Fig. 3 is a schematic perspective view showing a part of an electronic device according to embodiment 2. Fig. 4 is a flowchart showing a method for manufacturing an electronic device according to embodiment 2.1A and 1B are schematic cross-sectional views showing steps (1 and 2) of forming a carrier structure according to embodiment 3. 1A is a schematic cross-sectional view showing a composite integrated film according to embodiment 3, and 1B is a schematic cross-sectional view showing an electronic device according to embodiment 3.

[0011] Hereinafter, a carrier structure according to an embodiment and a method for manufacturing an electronic device according to an embodiment will be described with reference to the drawings. The following embodiments are merely examples, and the embodiments can be appropriately combined and modified.

[0012] In the figures, components having the same or similar functions are given the same reference numerals. The figures also show coordinate axes of an XYZ Cartesian coordinate system to facilitate understanding of the relationships between the figures. The X and Y axes are coordinate axes in the direction along the flat bottom surface of the composite integrated film as a functional element unit (i.e., the horizontal direction). The Z axis is the coordinate axis in the height direction (i.e., the thickness direction) of the composite integrated film.

[0013] The carrier structure according to the embodiment is an intermediate structure having a composite integration film as a composite integration film and a carrier substrate that temporarily supports one or more composite integration films. The carrier substrate has a substrate, wiring, and terminal pads, and a testing device performs a functional test of the composite integration film via the carrier substrate. The carrier structure according to the embodiment is also configured such that a partial gap is provided between the carrier substrate and the composite integration film, and the presence of the gap makes it easy to peel the composite integration film from the carrier substrate.

[0014] The transfer device can hold the composite integrated film using a movable transfer stamp. The transfer device peels off the composite integrated film that has passed the functional test using the carrier substrate (i.e., no defects have been found) from the carrier substrate and attaches the peeled carrier substrate to a device substrate as a mounting substrate. In this way, by using the carrier structure according to the embodiment, a functional test of the composite integrated film can be performed before the composite integrated film is transferred to the device substrate, thereby preventing a composite integrated film in which a defect has been found from being transferred to the device substrate.

[0015] The transfer device can peel and remove from the carrier substrate any composite buildup film that has failed the functional test using the carrier substrate (i.e., any defective portion has been found), and apply another composite buildup film to the area on the carrier substrate from which the failed composite buildup film was peeled off. In other words, the transfer device can replace the defective composite buildup film on the carrier substrate with a new composite buildup film.

[0016] In the electronic device manufacturing method according to the embodiment, a transfer device performs a process (i.e., a transfer process) in which a composite integrated film supported on a carrier substrate so as to have a partial void thereon is peeled from the carrier substrate and attached to a device substrate serving as a mounting substrate. This process produces an electronic device having a composite integrated film and a device substrate supporting the composite integrated film. According to the electronic device manufacturing method according to the embodiment, the carrier structure is used, so that a composite integrated film containing a defect can be prevented from being transferred to the device substrate.

[0017] {1} Embodiment 1 {1-1} Overview of Embodiment 1 The method for manufacturing an electronic device according to embodiment 1 includes: (11) a step of forming a carrier substrate as a laminated substrate; (12) a step of transferring functional elements formed on a growth substrate onto another substrate to form a composite integrated film as a functional element unit (FIGS. 1(A) and (B)); (13) a step of transferring one or more composite integrated films onto a carrier substrate to form a carrier structure (FIGS. 2(A) and (B), FIG. 3); (14) a step of performing a functional test on the functional elements of the composite integrated film on the carrier substrate (FIGS. 3, 4); and (15) a step of transferring the composite integrated film from the carrier substrate onto a device substrate (FIG. 5).

[0018] 1A is a schematic cross-sectional view showing a composite integrated film 170 as a functional element unit formed on the upper surface of a sacrificial layer 152 on a substrate 153. FIG. 1B is a schematic cross-sectional view showing a peeling process in which the composite integrated film 170 is held by a movable transfer stamp 500 of a transfer device (not shown) and peeled off from the substrate 153.

[0019] As shown in FIG. 1A or 1B , the composite integrated film 170 includes, for example, a support layer 151 made of an insulating material, a light-emitting diode (LED) as a functional element 111 formed thereon, a cathode electrode wiring 112 as a first electrode electrically connected to the functional element 111, an anode electrode wiring 113 as a second electrode electrically connected to the LED (functional element 111), and a transparent protective layer 161 as an insulating material covering the LED (functional element 111). In the examples of FIGS. 1A and 1B , an insulating layer 114 is provided between the anode electrode wiring 113 and a portion of the functional element 111. The functional element is not limited to a light-emitting element such as an LED. The functional element may also be an electronic element (or semiconductor element) such as a light-receiving element, a piezoelectric element, or a metal-oxide semiconductor field-effect transistor (MOSFET). Furthermore, the wiring designated by 112 may be an anode electrode wiring, and the wiring designated by 113 may be a cathode electrode wiring.

[0020] Fig. 2A is a schematic cross-sectional view showing a transfer process of the composite integrated film 170 onto the carrier substrate 200. Fig. 2B is a schematic cross-sectional view showing the carrier structure 1000 according to the first embodiment.

[0021] As shown in FIG. 2A , the composite integrated film 170 attracted by the movable transfer stamp 500 of the transfer device is carried onto the carrier substrate 200 and attached to the bonding surface 1041 a, which is the upper surface (i.e., flat surface) of the first wiring 1041 and the bonding surface 1042 a, which is the upper surface (i.e., flat surface) of the second wiring 1042 of the carrier substrate 200. The bonding surfaces 1041 a and 1042 a may be subjected to a planarization process (e.g., CMP) to form flat surfaces. As a result, as shown in FIG. 2B , the lower surface of the composite integrated film 170 facing the carrier substrate 200 becomes a flat surface 180, and the composite integrated film 170 is bonded to the bonding surfaces 1041 a and 1042 a so as to provide a gap 109 between the flat surface 180 and the insulating layer 106. This bonding is between flat surfaces, and does not require the use of an adhesive or the like. The carrier structure 1000 is configured such that a gap 109 is partially provided between the carrier substrate 200 and the composite integration film 170, and the presence of the gap 109 makes it easy to peel the composite integration film 170 from the carrier substrate 200. In other words, the carrier structure 1000 includes the substrate 102, an insulating layer 103 (106) formed above the substrate 102 (e.g., on the substrate 102 or on the substrate 102 via another layer), a first wiring 1041 formed above the insulating layer 103 (106) (e.g., on the insulating layer 103 or on the insulating layer 103 via another layer), a second wiring 1042 formed above the insulating layer 103 (106), and a second wiring 1043 formed above the first wiring 1044. The insulating layer 103 (106) has an opening penetrating from the surface facing the composite integrated film 170 to the surface facing the substrate 102, and at least one of the first wiring 1041 and the second wiring 1042 is electrically connected to either the first electrode 112 or the second electrode 113 through the opening.2B shows an example in which the first electrode 112 and the first wiring 1041 are electrically connected through an opening in the insulating layer 103 (106), and the second electrode 113 and the second wiring 1042 are electrically connected through an opening in the insulating layer 103 (106). However, one of the electrical connection between the first electrode 112 and the first wiring 1041 and the electrical connection between the second electrode 113 and the second wiring 1042 may be formed by a wiring that does not pass through the opening in the insulating layer 103 (106) (for example, a wiring that passes through the surface and side surface of the insulating layer 103 (106)). The first height of the portion of the first wiring 1041 that protrudes from the insulating layer 103 (106) at the portion where it joins the first electrode 112 toward the functional element unit 170 is substantially equal to the second height of the portion of the second wiring 1042 that protrudes from the insulating layer 103 (106) at the portion where it joins the second electrode 113 toward the functional element unit 170.

[0022] FIG. 3 is a schematic perspective view showing a part of the carrier structure 1000 according to the first embodiment.

[0023] As shown in FIG. 3 , a plurality of composite integrated films 170 are disposed on a carrier substrate 200. The composite integrated film 170 in FIG. 3 has LED elements of three colors, RGB. However, the number of composite integrated films 170 on the carrier substrate 200 may be one or more. The carrier substrate 200 also includes a first terminal pad 101C electrically connected to a first wiring 1041 and a second terminal pad 101A electrically connected to a second wiring 1042. The first terminal pad 101C for the cathode electrode and the second terminal pad 101A for the anode electrode are provided at positions (e.g., exposed) that can be contacted by probes of a test device that performs a functional test, for example. One or both of the first terminal pad 101C and the second terminal pad 101A for the anode electrode may be provided at a position different from that shown in FIG. 3, such as on the side (the surface facing horizontally in FIG. 3) or the bottom (the surface facing downward in FIG. 3) of the carrier substrate 200.

[0024] Fig. 4 is a schematic perspective view showing the composite integrated film 170 peeled and lifted from the carrier substrate 200. Fig. 5A is a schematic cross-sectional view showing a transfer process in which a movable transfer stamp 510 of a transfer device is used to attach the composite integrated film 170 peeled from the carrier substrate 200 to a device substrate 300. Fig. 5B is a schematic cross-sectional view showing an electronic device 10 having a device substrate 300 and one or more composite integrated films 170.

[0025] In the first embodiment, as shown in Figure 4 and Figures 5(A) and (B), the composite integrated film 170 that has passed the functional test using the carrier substrate 200 (i.e., no defects have been found) is peeled from the carrier substrate 200 by a movable transfer stamp 510 of a transfer device, and the peeled composite integrated film 170 is attached to a device substrate 300 as a mounting substrate, thereby manufacturing the electronic device 10. This eliminates the need for a process of peeling and removing the composite integrated film 170 that has defects from the electronic device 10. Note that the transfer stamp 510 may be the same as the transfer stamp 500 shown in Figure 1(B).

[0026] 1-2 Details of First Embodiment <Carrier Substrate 200> FIGS. 6A and 6B are a schematic cross-sectional view and a schematic plan view showing the first terminal pad 101C and the second terminal pad 101A for the anode electrode, which are part of the carrier substrate 200 shown in FIG. 3. FIG. 7 is a schematic plan view showing a state in which a test device 700 for a functional test is placed on the first terminal pad 101C and the second terminal pad 101A for the anode electrode of the carrier substrate 200. In FIGS. 6A and 6B, 102 denotes an insulating substrate, and the first terminal pad 101C and the second terminal pad 101A for the anode electrode are electrode layers. The substrate 102 is formed of an insulating material such as glass or silicon. A conductive pattern 101 is formed on the substrate 102. The conductive pattern 101 is formed of a metal (e.g., gold (Au), aluminum (Al), etc.). The second terminal pad 101A is a conductive pattern for the anode electrode and is part of the conductive pattern 101. The first terminal pad 101C is a conductive pattern for the cathode electrode and is part of the conductive pattern 101. The region 900 is a region where the first terminal pad 101C serving as a test pad with which a probe of a test device or the like comes into contact and the second terminal pad 101A for the anode electrode are exposed. In the region 900, the test pads are exposed without being subjected to lamination processing of an insulating layer. The shape, number, and position of the test pads provided on the carrier substrate 200 are not limited to the example shown in the figure, and they may be provided on the side surface, back surface, etc. of the carrier substrate 200.

[0027] 8A, 8B, and 8C are a schematic perspective view, a schematic side view, and a schematic plan view showing a first step of forming a carrier substrate 200, which is a laminated substrate. 8A, 8B, and 8C show the structure of a portion 800 in FIG. 6. 8A, 8B, and 8C show examples of a substrate 102 and conductive patterns 101 formed thereon. The shape, arrangement, number, and the like of the conductive patterns 101 are not limited to the illustrated example, and various modifications are possible.

[0028] 9A, 9B, and 9C are a schematic perspective view, a schematic side view, and a schematic plan view showing a second step of forming a carrier substrate 200. FIGS. 9A, 9B, and 9C show the structure of portion 800 in FIG. 6. FIGS. 9A, 9B, and 9C show an example in which a conductive pattern 101 formed on a substrate 102 is covered with an insulating layer 103. The insulating layer 103 is made of a polymer compound such as polyimide (PI), or other resin.

[0029] 10A, 10B, and 10C are a schematic perspective view, a schematic side view, and a schematic plan view showing a third step of forming a carrier substrate 200. Figures 10A, 10B, and 10C show the structure of portion 800 in Figure 6. Figures 10A, 10B, and 10C show an example in which an opening 105 is formed in an insulating layer 103 covering a conductive pattern 101, exposing the conductive pattern 101 as an underlying wiring.

[0030] 11A, 11B, and 11C are a schematic perspective view, a schematic side view, and a schematic plan view showing a fourth step of forming the carrier substrate 200. Figures 11A, 11B, and 11C show the structure of the portion 800 in Figure 6. Figures 11A, 11B, and 11C show an example in which wiring (e.g., a first wiring 1041 and a second wiring 1042) is formed as an electrode layer that is connected to the conductive pattern 101 and extends onto the upper surface of the insulating layer 103 through the opening 105.

[0031] 12A, 12B, and 12C are a schematic perspective view, a schematic side view, and a schematic plan view showing a fifth step of forming a carrier substrate 200. Figures 12A, 12B, and 12C show the structure of portion 800 in Figure 6. Figures 12A, 12B, and 12C show an example in which part of the wiring (e.g., the first wiring 1041 and the second wiring 1042) serving as an electrode layer is covered with an insulating layer 106.

[0032] 13A, 13B, and 13C are a schematic perspective view, a schematic side view, and a schematic plan view showing a sixth step of forming a carrier substrate 200. Figures 13A, 13B, and 13C show the structure of portion 800 in Figure 6. Figures 13A, 13B, and 13C show a step of forming an opening 107 in an insulating layer 106 that covers a portion of the wiring serving as an electrode layer (e.g., the first wiring 1041 and the second wiring 1042) to expose the wiring serving as an electrode layer (e.g., the first wiring 1041 and the second wiring 1042).

[0033] 14A, 14B, and 14C are schematic perspective views showing modified examples of the sixth step of forming the carrier substrate 200 in Fig. 13A. As shown in Fig. 14A, 14B, and 14C, the shape, size, position, and number of the openings 107 formed in the insulating layer 106 that covers part of the wiring (e.g., the first wiring 1041 and the second wiring 1042) as the electrode layer are not limited to the example in Fig. 13A, and various modifications are possible.

[0034] 15A, 15B, and 15C are schematic perspective views, schematic side views, and schematic plan views showing a seventh step of forming a carrier substrate 200. Figures 15A, 15B, and 15C show the structure of portion 800 in Figure 6. Figures 15A, 15B, and 15C show an example in which openings 107 are provided in an insulating layer 106 that covers part of the wiring (e.g., the first wiring 1041 and the second wiring 1042) serving as electrode layers, and conductive pads (e.g., bonding surfaces 1041a, 1042a) serving as electrode layers are formed, connected to the wiring (e.g., the first wiring 1041 and the second wiring 1042) and extending onto the upper surface of the insulating layer 106 through the openings 107. The bonding surfaces 1041a and 1042a are formed of a metal such as Au, molybdenum (Mo), or titanium (Ti), and the upper surfaces of the bonding surfaces 1041a and 1042a are smoothed to a surface roughness of, for example, 10 nm or less.

[0035] Regarding surface roughness, JIS_B_0601 specifies "arithmetic mean roughness Ra," "maximum height difference Ry," "root mean square roughness Rq," and "n-point average roughness Rz." In this application, "n-point average roughness Rz" is used as the surface roughness of each surface. For example, an atomic force microscope (AFM) is used to measure a 5 μm×5 μm area of ​​the surface to be measured, and the calculated value of n-point average roughness is obtained. Specifically, from a planar image of the surface to be measured obtained by AFM, the height of the profile curve element in the reference length (Rt ｉ ) is calculated as the average value of the n-point average roughness Rz by the following formula (1): where n is a positive integer, and i is an integer between 1 and n.

[0036]

[0037] As a measuring instrument, for example, an AFM "L-trace II" manufactured by Hitachi High-Tech Fielding Corporation can be used, and as a measurement condition (measurement mode), for example, the "tapping AFM mode" of the "L-trace II" manufactured by Hitachi High-Tech Fielding Corporation can be used.

[0038] The measurement range is a 5 μm × 5 μm range of the surface to be measured, the resolution is 512 pixels × 51 pixels, and the scanning speed is 1 μm / s. From the planar image obtained by AFM, a step profile with a reference length of 5 μm is obtained in an arbitrary horizontal direction (the same direction as the probe scanning direction), and the n-point average roughness Rz is calculated.

[0039] 16(A) and 16(B) are schematic perspective views showing a modified example of the seventh step of forming the carrier substrate 200 in Fig. 15(A). As shown in Fig. 16(A) and 16(B), the shape, size, position, and number of the bonding surfaces 1041a and 1042a are not limited to the example in Fig. 15(A), and various modifications are possible.

[0040] 17(A), (B), and (C) are a schematic perspective view, a schematic cross-sectional view, and a schematic plan view showing a part of a carrier structure 1000 including a carrier substrate 200 and one or more composite integration films 170. Figures 17(A), (B), and (C) show the structure of part 800 of Figure 6. As shown in Figures 17(A), (B), and (C), the shape of the carrier structure 1000 and the positions and number of the composite integration films 170 are not limited to the examples of Figures 17(A), (B), and (C), and various modifications are possible.

[0041] 18A and 18B are a schematic perspective view and a schematic cross-sectional view showing a portion of a carrier structure 1000 including a carrier substrate 200 and a composite integration film 170. Figures 18A and 18B show the structure of portion 800 of Figure 6. As shown in Figures 18A and 18B, the composite integration film 170 is bonded onto bonding surfaces 1041a, 1042a so that a gap 109 is formed.

[0042] As shown in Figure 18 (B), when the areas of the bonding surfaces 1041a, 1042a and the opening 107 are the same, it is possible to flatten the bonding surfaces 1041a, 1042a, making it easy to attach a composite integrated film 170 to the bonding surfaces 1041a, 1042a to perform a functional test and to peel it off again after the functional test.

[0043] The bonding surfaces 1041a and 1042a may be made of either an inorganic or organic material, but forming the bonding surfaces 1041a and 1042a from an organic material such as PI improves peelability. When the areas of the bonding surfaces 1041a and 1042a are large, it is desirable to use an organic material such as PI for the retention layer 151.

[0044] 19(A) is a schematic perspective view showing a modified example of the carrier structure of FIG. 18(B). In FIG. 19(A), the opening 107 is positioned so as not to overlap the bonding surface. The opening 107 in the surface of the insulating layer 106 facing the composite integrated film 170 is formed at a position so as not to overlap either the cathode electrode wiring 112 (122, 132) as the first electrode or the anode electrode wiring 113 (123, 133) as the second electrode in a direction perpendicular to the surface of the insulating layer 106 facing the composite integrated film 170 (i.e., the vertical direction in FIG. 19(A)). At least one of the first wiring 1041 and the second wiring 1042 includes bonding surfaces 1041a, 1042a extending on the surface of the insulating layer 106 facing the composite integrated film 170. That is, at least one of the first wiring 1041 and the second wiring 1042 is wider than the entire surface of this bonding surface.

[0045] As shown in FIG. 19A, by arranging the opening 107 at a position offset from the bonding surfaces 1041a and 1042a of the functional layers, it becomes easy to ensure the flatness of the bonding surfaces 1041a and 1042a.

[0046] 19(B) is a schematic cross-sectional view showing a modified example of the carrier structure of FIG. 18(B). FIG. 19(B) shows an example in which the opening 107 is smaller than the bonding surface. The size of the opening 107 on the surface of the insulating layer 106 facing the composite integrated film 170 is smaller than the bonding surface 112a of the cathode electrode wiring 112 (122, 132) and the bonding surface 113a of the anode electrode wiring 113 (123, 133), which will be described later. Furthermore, at least one of the first wiring 1041 and the second wiring 1042 includes bonding surfaces 1041a, 1042a extending on the surface of the insulating layer 106 facing the composite integrated film 170. That is, at least one of the first wiring 1041 and the second wiring 1042 is wider than the entire surface of this bonding surface.

[0047] 19(B), by making the opening 107 smaller than the bonding surfaces 1041a and 1042a, the peripheral edges of the bonding surfaces 1041a and 1042a can be easily kept flat, making it easier to perform a functional test by attaching a composite integrated film 170 to the upper parts of the bonding surfaces 1041a and 1042a. Furthermore, a configuration in which the diameter of the opening 107 is one-third of the diameter of the bonding surfaces 1041a and 1042a can be used as a common electrode is also possible. Furthermore, the configurations of FIGS. 19(A) and 19(B) may be combined. That is, the opening 107 may be formed at a position where it does not overlap with either the cathode electrode wiring 112 (122, 132) or the anode electrode wiring 113 (123, 133), and the opening 107 may be formed to be smaller than the size of the bonding surface 112a (122a, 132a), which is the flat surface of the cathode electrode wiring 112 (122, 132), and the bonding surface 113a (123a, 133a), which is the flat surface of the anode electrode wiring 113 (123, 133).

[0048] <Composite integrated film 170> Figures 20(A), (B), and (C) are schematic cross-sectional views showing a first step in forming the composite integrated film 170. Figures 20(A), (B), and (C) show steps for forming the functional elements 111, 121, and 131 that constitute the composite integrated film 170 by growth (e.g., epitaxial growth) on the growth substrates 110, 120, and 130 (135), respectively. In Figures 20(A), (B), and (C), the functional elements 111, 121, and 131 are LEDs having a PN junction between a P layer and an N layer.

[0049] The functional element in Figure 20 (A) is a light-emitting element formed by patterning a substrate on which a functional element 111, which is a green (G) light-emitting diode (LED) made of gallium nitride (GaN) or indium gallium nitride, is epitaxially grown on a growth substrate 110 such as a sapphire substrate or a silicon (Si) substrate.

[0050] The functional element in Figure 20 (B) is a light-emitting element formed by patterning a substrate on which a functional element 121, which is a blue (B) LED made of GaN or InGaN, is epitaxially grown on a growth substrate 120 such as a sapphire substrate or a Si substrate.

[0051] The functional element in FIG. 20(C) is a light-emitting element formed by forming a sacrificial layer 135 made of a material such as aluminum arsenide (AlAs) (e.g., aluminum gallium arsenide (AlGaAs)) on a gallium arsenide (GaAs) growth substrate 130, and then patterning a substrate on which a functional element 131, which is a red (R) LED made of GaAs, is epitaxially grown.

[0052] 21A, 21B, and 21C are schematic cross-sectional views showing a second step in forming the composite integrated film 170. FIGS. 21A, 21B, and 21C show the lift-off process in which the functional elements 111, 121, and 131 constituting the composite integrated film 170 are peeled off from the growth substrates 110, 120, and 130 (135) using a movable transfer stamp (not shown) of a transfer device. Laser lift-off can be used in FIGS. 21A and 21B. In FIG. 21C, the sacrificial layer 135 is etched with an etching solution to separate the functional element 131.

[0053] 22A, 22B, and 22C are schematic cross-sectional views illustrating the third step of forming a composite integrated film 170. As shown in 22A, 22B, and 22C, the laminated substrate is a multilayer substrate formed by stacking a base layer (substrate 153), a sacrificial layer 152 formed thereon, and a retaining layer 151 formed thereon. The functional elements 111 and 121 are formed, for example, of GaN, and their undersides are polished by chemical mechanical polishing (CMP) or the like to a surface roughness of 10 nm or less. The GaAs red LEDs have a surface roughness of 10 nm or less due to sacrificial layer etching. The functional elements, which are LED elements, are transferred in parallel to the retaining layer 151. The retaining layer 151 is made of an insulating material, such as an organic material such as PI, or an inorganic material such as silicon nitride (SiN). 22A, 22B, and 22C, functional elements 111, 121, and 131 that have been patterned into the shape of light-emitting elements and then separated are transferred onto the holding layer 151. Note that the functional elements 111, 121, and 131 may be patterned after being transferred.

[0054] 23A, 23B, and 23C are schematic cross-sectional views showing a fourth step in forming a composite integrated film 170. As shown in 23A, 23B, and 23C, functional elements 111, 121, and 131, which are light-emitting elements of three colors, R, G, and B, are transferred onto a retaining layer 151 (i.e., onto the same substrate).

[0055] 24(A), (B), and (C) are schematic cross-sectional views showing a fifth step of forming the composite integrated film 170. Fig. 25 is a schematic plan view showing a fifth step of forming the composite integrated film 170. As shown in Figs. 24(A), (B), and (C) and 25, openings 151a for wiring the functional elements 111, 121, and 131 are opened in the retention layer 151. The openings 151a and 151b are formed to a depth at which the sacrificial layer 152 is exposed.

[0056] 26A, 26B, and 26C are schematic cross-sectional views showing a sixth step of forming a composite integrated film 170. The support layer 151 has openings 151a and 151b that penetrate from a surface 155 on the composite integrated film 170 side to a surface 156 on the substrate 153 side. Cathode electrode wirings 112, 122, and 132 as first electrodes penetrate through the openings 151a, and anode electrode wirings 113, 123, and 133 as second electrodes penetrate through the openings 151b. Insulating layers 114, 124, and 134 are provided below the anode electrode wirings 113, 123, and 133. The cathode electrode wirings 112, 122, and 132 and the anode electrode wirings 113, 123, and 133 are formed of a transparent conductive film such as indium tin oxide (ITO) or a metal. 26(A), (B), and (C) have a holding layer 151, functional elements 111, 121, and 131 as functional elements formed on the holding layer 151, openings 151a formed in the holding layer 151, cathode electrode wirings 112, 122, and 132 as first electrodes that pass through the openings 151a connected to the functional elements 111, 121, and 131, and anode electrode wirings 113, 123, and 133 as second electrodes that pass through the openings 151b connected to the functional elements 111, 121, and 131.

[0057] The lower surface of the composite integrated film 170 is composed of the lower surface of the retaining layer 151 (i.e., flat surface 151c), the lower surfaces of the cathode electrode wirings 112, 122, and 132 exposed through the openings 151a of the retaining layer 151 (i.e., flat bonding surfaces 112a, 122a, and 132a), and the lower surfaces of the anode electrode wirings 113, 123, and 133 exposed through the openings 151a of the retaining layer 151 (i.e., flat bonding surfaces 113a, 123a, and 133a), forming a flat surface 180. The surface roughness (Rz) of the surface composed of the lower surface of the retaining layer 151, the cathode electrode wirings 112, 122, and 132 exposed through the openings 151a of the retaining layer 151, and the anode electrode wirings 113, 123, and 133 exposed through the openings 151b of the retaining layer 151 is preferably 10 nm or less. In addition, the film step caused by the surface consisting of the underside of the retaining layer 151, the cathode electrode wiring 112, 122, 132 exposed through the opening 151a of the retaining layer 151, and the anode electrode wiring 113, 123, 133 exposed through the opening 151b of the retaining layer 151 is 1 / 1000 or less of the shortest side on the XY plane in the outer shape of the composite integrated film 170, i.e., the shorter of the distance which is the length of the side along the X direction and the distance which is the length of the side along the Y direction.

[0058] 27(A) is a schematic plan view showing a sixth step of forming the composite integrated film 170. Figures 27(B) and 27(C) are schematic plan views showing modified examples of the sixth step of forming the composite integrated film 170. As described above, the arrangement, shape, size, and number of the lower surface of the support layer 151, the cathode electrode wiring 112, 122, 132, and the anode electrode wiring 113, 123, 133 are not limited to the illustrated example, and various modifications are possible. In Figures 27(B) and 27(C), either the anode side wiring layer or the cathode side wiring is used as a shared wiring.

[0059] 28(A), (B), and (C) are schematic cross-sectional views showing a seventh step of forming a composite integrated film 170. In Fig. 28(A), (B), and (C), a protective layer 161 made of a transparent insulating material is formed so as to cover the upper part of the structure of Fig. 26(A), (B), and (C).

[0060] 29A is a diagram showing a process of etching the sacrificial layer 152 of FIGS. 28A, 28B, and 28C to separate the composite integrated film 170 from the substrate 153 using a transfer stamp 500. The composite integrated film 170 forms a flat surface 180. The surface roughness (Rz) of the flat surface 180 is preferably 10 nm or less.

[0061] 29(B) shows a process of bonding the composite integrated film 170 to the bonding surfaces 1041a, 1042a of the carrier substrate 200 using a transfer stamp 500. The bonding surfaces 1041a, 1042a, which are conductive pads, are formed of metal such as Au, Mo, or Ti and have a surface roughness Rz of 10 nm or less. Therefore, the bonding surfaces 1041a, 1042a are bonded by intermolecular forces to the cathode electrode wirings 112, 122, 132 and the anode electrode wirings 113, 123, 133, which are made of a transparent conductive film such as ITO or a metal, and the bonding surfaces 1041a, 1042a, thereby achieving electrical connection. Furthermore, the bonding surfaces 1041a, 1042a can be bonded by intermolecular forces to the cathode electrode wirings 112, 122, 132 and the anode electrode wirings 113, 123, 133, thereby providing physical and electrical connection. In other words, simply by attaching the composite integrated film 170 to the bonding surfaces 1041 a, 1042 a of the carrier substrate 200, which is a laminate substrate, the two can be electrically connected without performing an annealing process or the like to improve contact. As described above, the composite integrated film 170 is supported on the carrier substrate 200 in an electrically conductive state by being bonded to the bonding surfaces 1041 a, 1042 a, and is supported in a partially spaced state so as to have a gap 109 between the composite integrated film 170 and the insulating layer 106 of the carrier substrate 200. This allows the composite integrated film 170 to be easily peeled off from the carrier substrate 200, and after a functional test (e.g., a light emission test for an LED) is completed, the composite integrated film 170 can be transferred to a device substrate, which is a transfer destination substrate, separate from the carrier substrate 200.

[0062] In addition, the area of ​​the portion of composite integrated film 170 in embodiment 1 that is bonded to bonding surfaces 1041a, 1042a is 90% or less of the area of ​​composite integrated film 170. In other words, the area of ​​the gap between composite integrated film 170 and insulating layer 106 of carrier substrate 200 is greater than 10% of the area of ​​the underside of composite integrated film 170.

[0063] 30A and 30B are schematic perspective views showing a process of replacing the composite integration film 170 on the carrier substrate 200 with another composite integration film 170a. The composite integration film 170 can be subjected to a functional test using a test device while it is bonded to the carrier substrate 200.

[0064] The transfer device peels off the composite integrated film 170 that has passed the functional test using the carrier substrate 200 (i.e., no defects have been found) from the carrier substrate, and attaches the peeled carrier substrate 170 onto the device substrate 300, which serves as a mounting substrate. In this way, by using the carrier structure 1000 according to the first embodiment, a functional test of the composite integrated film 170 can be performed before it is transferred to the device substrate 300, so that a composite integrated film 170 in which a defect has been found can be prevented from being transferred to the device substrate.

[0065] The transfer device can peel and remove a composite accumulation film 170 that has failed the functional test using the carrier substrate (i.e., a defective portion has been found) from the carrier substrate 200, as shown in Fig. 30(A), and then attach another composite accumulation film 170a to the area on the carrier substrate 200 from which the failed composite accumulation film 170 has been peeled, as shown in Fig. 30(B). In other words, the transfer device can replace the defective composite accumulation film 170 on the carrier substrate 200 with a new composite accumulation film 170a.

[0066] 31 is a schematic perspective view showing a part of the electronic device 10 according to embodiment 1. In the above description, defective composite integrated films 170 on the carrier substrate 200 are replaced and all are transferred to the final substrate as non-defective products, but the electronic device may also be manufactured by marking the defective elements, recording the defective locations as data, and transferring non-defective composite integrated films 170 onto the device substrate 300.

[0067] 32 is a flowchart showing a method for manufacturing the electronic device 10 according to embodiment 1. When manufacturing the electronic device, first, a carrier substrate 200, which is a laminated substrate and has wiring, is formed (step ST11). Then, the functional elements 111, 121, and 131 formed on the growth substrate are transferred onto another laminated substrate (composed of the substrate 153, etc.) to form a composite integrated film 170 (step ST12).

[0068] Next, one or more composite integrated films 170 are transferred onto a carrier substrate 200 to form a carrier structure 1000 (step ST13).

[0069] Next, a function test is performed on the functional elements 111, 121, and 131 of the composite integrated film 170 on the carrier substrate 200 (step ST14). If any composite integrated film 170 fails, it is replaced with another composite integrated film 170a (step ST15), as shown in Figures 30(A) and (B). A carrier structure 1000 that does not contain any defective products is formed by steps ST11 to ST15.

[0070] Next, the composite integrated film 170 on the carrier substrate 200 of the carrier structure 1000 is transferred onto the device substrate 300 (step ST16). Through steps ST11 to ST16, an electronic device 10 containing no defective products is formed.

[0071] <<1-4>> Effects of the First Embodiment As described above, by stacking a large number of composite integrated films 170 on the carrier substrate 200, it is possible to perform a function test before bonding on the device substrate 300, which was previously not possible before bonding on the device substrate 300. As a result, by removing or recording defective elements, it is possible to prevent the defective elements from being transferred to the device substrate 300, which is the final substrate.

[0072] {2} Embodiment 2 {2-1} Overview of Embodiment 2 The method for manufacturing an electronic device according to embodiment 2 includes the steps of: (21) forming a laminated substrate having a flat surface; (22) forming one or more functional elements formed on a growth substrate; (23) transferring one or more functional elements onto the flat surface of the laminated substrate; (24) forming a composite integrated film as a functional element unit from a portion of the laminated substrate and the functional elements, and forming a carrier substrate from a portion of the laminated substrate; (25) performing a functional test of the functional elements of the composite integrated film on the carrier substrate; and (26) transferring the composite integrated film from the carrier substrate onto a device substrate.

[0073] 33A, 33B, and 33C are schematic cross-sectional views showing the steps of forming, peeling, and transferring a functional element 3111 according to the second embodiment. As shown in FIG. 33A, a functional element 3111 such as an LED is formed on a growth substrate 3110 by, for example, epitaxial growth. Next, as shown in FIG. 33B, the functional element 3111 is peeled off from the growth substrate 3110 using a transfer stamp. As shown in FIG. 33C, the functional element 3111 is attached to a holding layer 2151 of a laminated substrate. The laminated substrate of FIG. 33C includes an insulating substrate 2102, a conductive pattern 2101 formed thereon as a wiring layer, an insulating layer 2103 covering the conductive pattern 2101, an insulating layer 2106 formed thereon, and a holding layer 2151 formed thereon. The substrate 2102, the conductive pattern 2101, the insulating layer 2103, the insulating layer 2106, and the holding layer 2151 are formed of the same materials as the substrate 102, the conductive pattern 101, the insulating layer 103, the insulating layer 106, and the holding layer 251 in the first embodiment.

[0074] 34(A) and (B) are schematic cross-sectional views showing the process of forming the carrier structure 2000 according to the second embodiment. Fig. 34(A) shows a structure having a transparent insulating film 3161 covering the composite integrated film 2170 serving as the functional element unit of Fig. 33(C). Fig. 34(B) shows a structure in which the insulating layer 2106 of Fig. 34(A) has been removed by etching. By removing the insulating layer 2106, the carrier substrate 2200 and the composite integrated film 2170 supported thereon are formed.

[0075] FIG. 35 is a schematic perspective view showing a part of a carrier structure 2000 according to the second embodiment.

[0076] As shown in FIG. 35 , a plurality of composite integrated films 2170 are disposed on a carrier substrate 2200. The composite integrated film 2170 in FIG. 35 has LED elements of three colors (RGB). However, the number of composite integrated films 2170 on the carrier substrate 2200 may be one or more. The carrier substrate 2200 also includes a first terminal pad 2101C electrically connected to a first wiring 21041 and a second terminal pad 2101A electrically connected to a second wiring 21042. The first terminal pad 2101C for the cathode electrode and the second terminal pad 2101A for the anode electrode are provided in positions (e.g., exposed) that can be contacted by probes of a test device that performs a functional test, for example. One or both of the first terminal pad 2101C and the second terminal pad 2101A may be provided at a position different from that shown in FIG. 35, such as on the side (sideways in FIG. 35) or bottom (downward in FIG. 35) of the carrier substrate 2200.

[0077] 36(A) is a schematic cross-sectional view showing a transfer process in which a composite integrated film 2170 peeled from a carrier substrate 2200 is attached to a device substrate 300 using a movable transfer stamp 510 of a transfer device. The lower surface of the composite integrated film 2170 forms a flat surface 3180. The surface roughness (Rz) of the flat surface 3180 is preferably 10 nm or less. FIG. 36(B) is a schematic cross-sectional view showing an electronic device 20 having a device substrate 300 and one or more composite integrated films 2170.

[0078] 36(A) and 36(B), the composite integrated film 2170 that has passed the functional test using the carrier substrate 2200 (i.e., no defective portions have been found) is peeled from the carrier substrate 2200 by the movable transfer stamp 510 of the transfer device, and the peeled composite integrated film 2170 is attached to the device substrate 300 as the mounting substrate, thereby manufacturing the electronic device 20. This eliminates the need for a process of peeling and removing the composite integrated film 2170 that has defective portions from the electronic device 20.

[0079] <2-2> Details of Embodiment 2 <Carrier Substrate 2200> Fig. 37 is a schematic plan view showing a first terminal pad 2101C and a second terminal pad 2101A, which are part of the carrier substrate 2200 shown in Fig. 35. In Fig. 37, 2102 is an insulating substrate, and the first terminal pad 2101C and the second terminal pad 2101A are electrode layers. The substrate 2102 is formed of an insulating material such as glass or silicon. A conductive pattern 2101 is formed on the substrate 2102. The conductive pattern 2101 is formed of a metal (e.g., Au, Al, etc.). The second terminal pad 2101A is a conductive pattern for an anode electrode and is part of the conductive pattern 2101. The first terminal pad 2101C is a conductive pattern for a cathode electrode and is part of the conductive pattern 2101. Region 900 is an area where first terminal pads 2101C and second terminal pads 2101A are exposed as test pads that come into contact with probes of a test device, etc. In region 900, the test pads are exposed without laminating an insulating layer. The shape, number, and position of the test pads provided on carrier substrate 2200 are not limited to the example shown in the figure, and they may be provided on the side or back surface of carrier substrate 2200, etc.

[0080] 38(A), (B), and (C) are a schematic perspective view, a schematic side view, and a schematic plan view showing a process (part 1) for forming a carrier substrate 2200, which is a laminated substrate. Figures 38(A), (B), and (C) show the structure of portion 800 in Figure 37. Figures 38(A), (B), and (C) show examples of a substrate 2102 and conductive patterns 2101 formed thereon. The shape, arrangement, number, and the like of the conductive patterns 2101 are not limited to the illustrated example, and various modifications are possible.

[0081] 39(A), (B), and (C) are a schematic perspective view, a schematic side view, and a schematic plan view showing a second step of forming a carrier substrate 2200. Figures 39(A), (B), and (C) show the structure of portion 800 in FIG. 37. Figures 39(A), (B), and (C) show an example in which a conductive pattern 2101 formed on a substrate 2102 is covered with an insulating layer 2103. The insulating layer 2103 is formed of a polymer compound such as polyimide (PI), or other resin.

[0082] 40(A), (B), and (C) are a schematic perspective view, a schematic side view, and a schematic plan view showing a third step of forming a carrier substrate 2200. Figures 40(A), (B), and (C) show the structure of portion 800 in Figure 37. Figures 40(A), (B), and (C) show an example in which an opening 2105 is formed in an insulating layer 2103 covering a conductive pattern 2101, exposing the conductive pattern 2101 as an underlying wiring.

[0083] 41(A), (B), and (C) are a schematic perspective view, a schematic side view, and a schematic plan view showing a fourth step of forming a carrier substrate 2200. Figures 41(A), (B), and (C) show the structure of portion 800 in Figure 37. Figures 41(A), (B), and (C) show an example in which wiring (e.g., first wiring 21041 and second wiring 21042) is formed as an electrode layer that is connected to the conductive pattern 2101 and extends onto the upper surface of the insulating layer 2103 through the opening 2105.

[0084] 42(A), (B), and (C) are schematic perspective views, schematic side views, and schematic plan views showing another example of the step (part 4a) of forming a carrier substrate 2200. FIGS. 42(A), (B), and (C) show the structure of portion 800 of FIG. 6. FIGS. 42(A), (B), and (C) show an example in which wiring (e.g., first wiring 21041 and second wiring 21042) is formed as an electrode layer connected to the conductive pattern 2101 and extending onto the upper surface of the insulating layer 2103 through the opening 2105. The wiring (e.g., first wiring 21041 and second wiring 21042) is formed narrower than those shown in FIGS. 41(A), (B), and (C).

[0085] 43(A), (B), and (C) are a schematic perspective view, a schematic side view, and a schematic plan view showing the fifth step of forming a carrier substrate 2200. Figures 43(A), (B), and (C) show the structure of portion 800 in Figure 6. Figures 43(A), (B), and (C) show an example in which part of the wiring (e.g., the first wiring 21041 and the second wiring 21042) serving as the electrode layers in Figures 41(A), (B), and (C) is covered with an insulating layer 2106.

[0086] 44(A), (B), and (C) are a schematic perspective view, a schematic side view, and a schematic plan view showing another example of the step (part 5a) of forming a carrier substrate 2200. Figures 44(A), (B), and (C) show the structure of portion 800 in FIG. 37. Figures 44(A), (B), and (C) show a step of providing an insulating layer 2106 that covers a portion of the wiring (e.g., the first wiring 21041 and the second wiring 21042) serving as the electrode layer in FIGS. 42(A), (B), and (C).

[0087] 45(A), (B), and (C) are schematic perspective views, side views, and plan views illustrating the sixth step of forming a carrier substrate 2200. FIGS. 45(A), (B), and (C) show the structure of portion 800 in FIG. 37 . FIGS. 45(A), (B), and (C) show a planarization process such as CMP performed on the upper surface of the insulating layer 2106 covering a portion of the wiring (e.g., the first wiring 21041 and the second wiring 21042) serving as the electrode layer in FIGS. 43(A), (B), and (C). The wiring (e.g., the first wiring 21041 and the second wiring 21042) is formed of a metal such as Au, Mo, or Ti. The surface of the insulating layer 2106 is polished by CMP, and the insulating layer 2106 is smoothed to a surface roughness of 10 nm or less on the same surface while the conductive layer that will become the terminal portion is exposed.

[0088] 46(A), (B), and (C) are schematic perspective views, schematic side views, and schematic plan views showing another example of the carrier substrate 2200 formation step (part 6a). FIGS. 46(A), (B), and (C) show the structure of portion 800 of FIG. 37. FIGS. 46(A), (B), and (C) show a planarization process such as CMP on the upper surface of the insulating layer 2106 covering a portion of the wiring (e.g., the first wiring 21041 and the second wiring 21042) serving as the electrode layer in FIGS. 44(A), (B), and (C). The surface of the insulating layer 2106 is polished by CMP, and the insulating layer 2106 is smoothed to a surface roughness of 10 nm or less on the same surface while the conductive layer that will become the terminal portion is exposed.

[0089] Fig. 47 is a schematic cross-sectional view showing a carrier substrate forming step (part 7) and a laminated substrate produced by the steps shown in Figs.

[0090] <Composite integrated film 2170> Figures 48(A), (B), and (C) are schematic cross-sectional views showing a first step in forming functional elements 3111, 3121, and 313. Figures 48(A), (B), and (C) show steps in which functional elements 3111, 3121, and 3131 that constitute composite integrated film 2170 are formed by growing (e.g., epitaxially growing) them on growth substrates 3110, 3120, and 3130 (3135), respectively. In Figures 48(A), (B), and (C), functional elements 3111, 3121, and 3131 are LEDs having a PN junction between a P-type semiconductor layer (P layer) and an N-type semiconductor layer (N layer).

[0091] The materials of the functional elements 3111, 3121, 3131 and growth substrates 3110, 3120, 3130 (3135) in Figures 48(A), (B), and (C) are the same as the materials of the functional elements 111, 121, 131 and growth substrates 110, 120, 130 (135) in Figures 20(A), (B), and (C).

[0092] 49(A), (B), and (C) are schematic cross-sectional views showing the transfer process (part 1) of functional elements 3111, 3121, and 3131. FIGS. 49(A), (B), and (C) show the process of lifting off functional elements 3111, 3121, and 3131 constituting composite integrated film 2170 from growth substrates 3110, 3120, and 3130 (3135) using a movable transfer stamp (not shown) of a transfer device. Laser lift-off can be used in FIGS. 49(A) and (B). In FIG. 49(C), functional element 3131 is separated by etching sacrificial layer 3135 with an etching solution.

[0093] FIG. 50 is a schematic cross-sectional view showing the transfer process (part 2) of functional elements 3111, 3121, and 3131. As shown in FIG. 50, the laminated substrate includes an insulating substrate 2102, an insulating layer 2103 formed thereon, an insulating layer 2103 covering a conductive pattern 2101 as a wiring layer, an insulating layer 2106 formed thereon, and a retaining layer 2151 formed thereon. The functional elements 3111 and 3121 are formed, for example, of GaN, and their undersides are polished by chemical mechanical polishing (CMP) or the like to a surface roughness of 10 nm or less. The functional element 3131 is a GaAs red LED, and its underside is stripped by sacrificial layer etching to a surface roughness of 10 nm or less. LED functional elements are transferred in parallel to the retaining layer 2151. The retaining layer 2151 is made of an insulating material, and is composed of an organic material such as PI or an inorganic material such as silicon nitride (SiN). 50, functional elements 3111, 3121, and 3131 that have been patterned into the shape of light-emitting elements and then separated are transferred onto the holding layer 2151. Note that the functional elements 3111, 3121, and 3131 may be patterned after being transferred.

[0094] Fig. 51 is a schematic plan view showing a third step of transferring functional elements 3111, 3121, and 3131. As shown in Fig. 51, the functional elements 3111, 3121, and 3131 are bonded onto a support layer 2151 of a laminated substrate.

[0095] FIG. 52 is a schematic cross-sectional view showing a first step in forming the carrier structure 2000. As shown in FIG. 52, the laminated substrate includes a substrate 2102, a conductive pattern 2101 formed thereon, an insulating layer 2103 covering the conductive pattern 2101, an insulating layer 2106 formed thereon, and a retention layer 2151 formed thereon. The functional elements 3111 and 3121 are formed of, for example, GaN, and their lower surfaces are polished by chemical mechanical polishing (CMP) or the like to a surface roughness of 10 nm or less. The functional element 3131 is a GaAs red LED, and its lower surface is stripped by sacrificial layer etching to a surface roughness of 10 nm or less. The insulating layers 2103 and 2106 are formed above the laminated substrate.

[0096] FIG. 53 is a schematic cross-sectional view showing a second step of forming the carrier structure 2000. FIG. 54 is a schematic plan view showing the structure of FIG. 53. The support layer 2151 has openings 2151a and 2151b that penetrate from the surface facing the composite integrated film 2170 to the surface facing the substrate 2102. Cathode electrode wirings 3112, 3122, and 3132 as first electrodes penetrate through the openings 2151a, and anode electrode wirings 3113, 3123, and 3133 as second electrodes penetrate through the openings 2151b. Insulating layers 3114, 3124, and 3134 are provided below the anode electrode wirings 3113, 3123, and 3133. The cathode electrode wirings 3112, 3122, and 3132 and the anode electrode wirings 3113, 3123, and 3133 are formed of a transparent conductive film such as indium tin oxide (ITO) or a metal.

[0097] 55(A), (B), (C), and (D) are schematic cross-sectional views, schematic plan views, schematic cross-sectional views, and schematic perspective views showing another process for forming the carrier structure 2000. FIGS. 55(A), (B), (C), and (D) show the structure of portion 800 of FIG. 37. In this example, each composite integration film 2170 includes six functional elements. As shown in FIGS. 55(A), (B), (C), and (D), various modifications are possible to the shape of the carrier structure 2000 and the position, shape, and number of the composite integration films 2170.

[0098] 56(A), (B), (C), and (D) are schematic cross-sectional views, schematic plan views, schematic cross-sectional views, and schematic perspective views showing another process for forming the carrier structure 2000. FIGS. 56(A), (B), (C), and (D) show the structure of portion 800 of FIG. 37. In this example, each composite integration film 2170 includes three functional elements. As shown in FIGS. 56(A), (B), (C), and (D), various modifications are possible to the shape of the carrier structure 2000 and the position, shape, and number of the composite integration films 2170.

[0099] FIG. 57 is a schematic cross-sectional view showing a carrier structure 2000 according to embodiment 2. In FIG. 57, the insulating layer 2106 in the structure of FIG. 53 has been etched to form a void 109. As shown in FIG. 57, the flat lower surface 2172 (flat surface) of the composite integration film 2170 is bonded to flat bonding surfaces 21041a and 21042a so as to provide a void 109 between the insulating layer 2103 and the lower surface 2172. This bonding is between flat surfaces, and no adhesive or the like is required. The carrier structure 2000 is configured so that a void 109 is partially provided between the carrier substrate 2200 and the composite integration film 2170. The presence of the void 109 makes it easy to peel the composite integration film 170 from the carrier substrate 200.

[0100] 58(A), (B), (C), and (D) are schematic cross-sectional, plan, cross-sectional, and perspective views of a carrier structure 2000. The carrier structure 2000 comprises a carrier substrate 2200 and one or more composite integration films 2170 bonded thereon.

[0101] Fig. 59 is a schematic cross-sectional view showing another example of the carrier structure 2000 according to embodiment 2. In Fig. 59, the bonding surfaces 21041a and 21042a have upper surfaces that are narrower than the cathode electrode wiring 3112. The wiring (for example, the first wiring 21041 and the second wiring 21042) is formed to be narrower than those shown in Figs.

[0102] 57, the width (X-direction width) of the bonding surface 3112a, which is the flat surface of the cathode electrode wiring 3112 exposed from the lower surface 2172 of the composite integrated film 2170, and the width (X-direction width) of the bonding surface 21041a of the first wiring 21041 in contact therewith are the same or approximately the same, but as shown in Fig. 59, the width (X-direction width) of the bonding surface 21041a may be formed to be narrower than the width (X-direction width) of the bonding surface 3112a of the cathode electrode wiring 3112. Similarly, the width (X-direction width) of the bonding surface 3112a of the cathode electrode wiring 3112 and the width (X-direction width) of the bonding surface 21041a in contact therewith may be formed to be the same or approximately the same. Furthermore, the width (width in the X direction) of the bonding surface 21042a of the second wiring 21042 may be formed narrower than the width (width in the X direction) of the bonding surface 3113a, which is the flat surface of the anode electrode wiring 3113 exposed from the lower surface 2172 of the composite integrated film 2170. In other words, one or both of the bonding surface 21041a of the first wiring 21041 and the bonding surface 21042a of the second wiring 21042 may be made narrower than the bonding surface 3112a of the cathode electrode wiring 3112 and the bonding surface 3113a of the anode electrode wiring 3113, respectively.

[0103] 60(A), (B), and (C) are schematic perspective views showing other examples of the carrier structure 2000. Each of Fig. 60(A), (B), and (C) shows different shapes of the bonding surfaces 21041a and 21042a. The ease of peeling can be adjusted by devising the shape of the contact surfaces of the bonding surfaces 21041a and 21042a with the composite integrated film 2170.

[0104] 61 is a diagram showing a portion of an electronic device 20 formed by transferring a composite integrated film 2170 on a carrier structure 2000 onto a device substrate 3310 as a target substrate using a transfer stamp. Although an LED display is shown as the electronic device 20, the electronic device 20 may be other electronic elements such as a light-receiving element, a piezoelectric element, or a MOSFET.

[0105] 62 is a flowchart showing a method for manufacturing the electronic device 20 according to embodiment 2. When manufacturing the electronic device 20, first, a laminated substrate having a flat surface is formed (step ST21). Then, the functional elements 3111, 3121, and 3131 formed on the growth substrate are transferred onto the laminated substrate to form a composite integrated film 2170 (step ST22).

[0106] Next, the functional elements 3111, 3121, and 3131 are transferred onto the flat surface of the laminated substrate (step ST23).

[0107] Next, a composite integrated film 2170 is formed from a part of the laminated substrate and the functional elements 3111, 3121, and 3131, and a carrier substrate 2200 is formed from a part of the laminated substrate (step ST24).

[0108] Next, a function test is performed on the functional elements 3111, 3121, and 3131 of the composite integrated film 2170 on the carrier substrate 2200 (step ST25). If any composite integrated film 2170 fails, the failed composite integrated film 2170 is replaced with another composite integrated film (step ST26). By steps ST21 to ST26, a carrier structure 2000 that does not contain any defective products is formed.

[0109] Next, the composite integrated film 2170 on the carrier substrate 2200 of the carrier structure 2000 is transferred onto the device substrate 300 (step ST27). Through steps ST21 to ST27, an electronic device 20 containing no defective products is formed.

[0110] <<2-4>> Effects of the Second Embodiment As described above, according to the second embodiment, by stacking a large number of composite integrated films 170 on the carrier substrate 200, it is possible to perform a function test before bonding on the device substrate 300, which was previously not possible before bonding on the device substrate 300. As a result, by removing defective elements or recording identifying information of defective elements, it is possible to prevent the transfer of defective elements to the device substrate 300, which is the final substrate.

[0111] Furthermore, according to the second embodiment, the laminated substrate (the laminated substrate including the substrate 153) used in the first embodiment is not used, so that the manufacturing process can be simplified.

[0112] Except for the above, the second embodiment is the same as the first embodiment.

[0113] <3> Third Embodiment In the third embodiment, the composite integrated film 170 is formed using the method described in the first embodiment, and the carrier substrate 2200 is formed using the method described in the second embodiment.

[0114] Fig. 63(A) is a schematic cross-sectional view showing a first step of forming a carrier structure 3000 according to the third embodiment. Fig. 63(B) is a schematic cross-sectional view showing a second step of forming a carrier structure 3000. Fig. 64(A) is a schematic cross-sectional view showing a third step of forming a carrier structure 3000. Fig. 64(B) is a schematic cross-sectional view showing an electronic device 30 according to the third embodiment.

[0115] First, prepare the composite integrated film 170 formed by the method described in embodiment 1 and the laminated substrate formed by the method described in embodiment 2. The laminated substrate is a structure that will become the carrier substrate 2200.

[0116] 63(A) and (B), the composite integrated film 170 formed by the method described in embodiment 1 is placed on and bonded to the flat upper surface of the laminated substrate formed by the method described in embodiment 2. This bonding is by intermolecular force.

[0117] Next, the insulating layer 2106 is etched to form the carrier structure 2000 shown in Fig. 64(A). The composite integrated film 170 is subjected to a functional test in the state shown in Fig. 64(A).

[0118] If the function test fails, the composite integrated film 170 of FIG. 64(A) can be replaced.

[0119] According to embodiment 3, as shown in Figures 63 (A) and (B), the composite integrated film 170 can be transferred onto a flat surface consisting of the joining surfaces 21041a, 21042a and the upper surface of the insulating layer 2106.Therefore, compared to the case where the composite integrated film 170 is transferred onto the joining surfaces 1041a, 1042a as shown in Figures 2 (A) and (B), it is possible to reduce the local force applied to the composite integrated film 170 during transfer and to alleviate the stress generated during transfer.

[0120] Other than the above, the third embodiment is the same as the first or second embodiment.

[0121] <4> Modifications In the above embodiments 1 to 3, examples have been described in which the composite integrated film 170, 2170 includes three RGB LEDs as functional elements, but each composite integrated film 170, 2170 may be formed to include one LED. Furthermore, the greater the number of functional elements included in each composite integrated film 170, 2170, the more improved the production efficiency, but the lower the yield of each composite integrated film 170, 2170.

[0122] In the above-described first to third embodiments, the composite integrated films 170 and 2170 have been described as examples in which LEDs are used as functional elements, but the functional elements may be various electronic elements (semiconductor devices) such as light-receiving elements, piezoelectric elements, MOSFETs, etc. Therefore, the electronic devices are not limited to displays, and may also be sensor devices, integrated circuits (ICs), or integrated devices that combine various electronic elements.

[0123] In the above embodiments 1 to 3, a configuration has been described in which the first wiring 1041, 21041 and the second wiring 1042, 21042 are joined to the insulating member (retaining layer 151, 2151) of the composite integrated film 170, 2170 and the cathode electrode wiring 112, 122, 132, 3112, 3122, 3132 and the anode electrode wiring 113, 123, 133, 3113, 3123, 3133, but the first wiring 1041, 21041 and the second wiring 1042, 21042 may be joined only to the cathode electrode wiring 112, 122, 132, 3112, 3122, 3132 and the anode electrode wiring 113, 123, 133, 3113, 3123, 3133, respectively.

[0124] Various aspects of the present disclosure are summarized below as appendices. (Appendix 1) A carrier structure comprising: a substrate, an insulating layer formed above the substrate, a first wiring formed above the insulating layer, a second wiring formed above the insulating layer and separated from the first wiring, a first terminal pad electrically connected to the first wiring, a second terminal pad electrically connected to the second wiring, and a functional element unit including a functional element, a first electrode electrically connected to the functional element, a second electrode electrically connected to the functional element, and an insulating member covering the functional element, the functional element unit being joined to the first wiring and the second wiring so as to provide a gap between the first electrode and the second wiring, wherein the first electrode is electrically joined to the first wiring, and the second electrode is electrically joined to the second wiring. (Supplementary Note 2) The carrier structure according to Supplementary Note 1, characterized in that the insulating layer has an opening penetrating from the surface facing the functional element unit to the surface facing the substrate, and at least one of the first wiring or the second wiring is electrically connected to either the first electrode or the second electrode through the opening. (Supplementary Note 3) The carrier structure according to Supplementary Note 2, characterized in that the size of the opening in the surface of the insulating layer facing the functional element unit is formed smaller than the size of a flat surface of the first electrode facing the insulating layer, and is formed smaller than the size of a flat surface of the second electrode facing the insulating layer, and at least one of the first wiring and the second wiring includes a bonding surface extending on the surface of the insulating layer facing the functional element unit. (Supplementary Note 4) The carrier structure according to Supplementary Note 2 or 3, characterized in that the opening in the surface of the insulating layer facing the functional element unit side is formed at a position that does not overlap with either the first electrode or the second electrode in a direction perpendicular to the surface facing the functional element unit side, and at least one of the first wiring and the second wiring includes a bonding surface that extends on the surface of the insulating layer facing the functional element unit side. (Supplementary Note 5) The carrier structure according to any one of Supplementary Notes 1 to 4, characterized in that the first wiring is bonded to the first electrode and the insulating member, and the second wiring is bonded to the second electrode and the insulating member.(Appendix 6) The carrier structure according to any one of Appendices 1 to 5, wherein the first wiring and the second wiring are made of an inorganic material, and the insulating member is made of an organic material. (Appendix 7) The carrier structure according to any one of Appendices 1 to 6, wherein a first height of a portion of the first wiring that is bonded to the first electrode and that protrudes from the insulating layer toward the functional element unit is substantially equal to a second height of a portion of the second wiring that is bonded to the second electrode and that protrudes from the insulating layer toward the functional element unit. (Appendix 8) The carrier structure according to any one of Appendices 1 to 7, wherein a plurality of the first wirings and the second wirings are formed on the insulating layer, and the carrier structure has a plurality of the functional element units bonded to the first wirings and the second wirings. (Appendix 9) The carrier structure described in any one of Appendices 1 to 6, characterized in that the functional element unit has a flat surface on the insulating layer side that is composed of the insulating member, the first electrode, and the second electrode, and the area where the first wiring and the second wiring contact the flat surface of the functional element unit is 90% or less of the area of ​​the flat surface. (Supplementary Note 10) A method for manufacturing an electronic device, comprising: a step of preparing a carrier structure including: a substrate; an insulating layer formed above the substrate; a first wiring formed above the insulating layer; a second wiring formed above the insulating layer and separated from the first wiring; a first terminal pad electrically connected to the first wiring; a second terminal pad electrically connected to the second wiring; a functional element unit including a functional element, a first electrode electrically connected to the functional element, a second electrode electrically connected to the functional element, and an insulating member covering the functional element, wherein the first electrode is electrically connected to the first wiring and the second electrode is electrically connected to the second wiring; a step of inspecting the functional element unit using the first terminal pad and the second terminal pad; a step of peeling the functional element unit from the first wiring and the second wiring; and a step of attaching the peeled functional element unit to a device substrate.(Supplementary Note 11) The method for manufacturing an electronic device according to Supplementary Note 10, further comprising the steps of: if an abnormality is found in the functional element unit in the step of inspecting the functional element unit, peeling the abnormal functional element unit from the first wiring and the second wiring, and bonding a functional element unit different from the peeled functional element unit to the first wiring and the second wiring. (Supplementary Note 12) The method for manufacturing an electronic device according to Supplementary Note 10 or 11, characterized in that the functional element unit is bonded to the first wiring and the second wiring so as to provide a gap between the functional element unit and the insulating layer.

[0125] 10, 20, 30 Electronic device, 1000, 2000, 3000 Carrier structure, 101, 2101 Conductive pattern, 101C, 2101C First terminal pad, 101A, 2101A Second terminal pad, 102, 2102 Substrate, 103, 106, 2103, 2106 Insulating layer, 1041, 21041 First wiring, 1041a, 21041a Bonding surface of first wiring, 1042, 21042 Second wiring, 1042a, 21042a Bonding surface of second wiring, 105, 107, 2105 Opening, 109 Air gap, 111, 121, 131, 3111, 3121, 3131 Functional element, 112, 122, 132, 3112, 3122, 3132 Cathode electrode wiring (first electrode), 112a, 122a, 132a, 3112a Bonding surface of cathode electrode wiring, 113, 123, 133, 3113, 3123, 3133 Anode electrode wiring (second electrode), 113a, 123a, 133a, 3113a Bonding surface of anode electrode wiring, 114, 124, 134, 3114, 3124, 3134 Insulating film, 151, 2151 Holding layer (insulating member), 152 Sacrificial layer, 153 Substrate, 151a, 151b, 2151a, 2151b Opening, 161, 3161 Insulating member, 170, 2170 Composite integrated film (functional element unit), 180, 3180 flat surface, 200, 2200 carrier substrate, 500, 510 transfer stamp.

Claims

1. A carrier structure comprising a substrate, an insulating layer formed above the substrate, a first wiring formed above the insulating layer, a second wiring formed above the insulating layer and separated from the first wiring, a first terminal pad electrically connected to the first wiring, a second terminal pad electrically connected to the second wiring, a functional element, a first electrode electrically connected to the functional element, a second electrode electrically connected to the functional element, and an insulating member covering the functional element, and a functional element unit joined to the first wiring and the second wiring such that a gap is provided between the insulating layer, wherein the first electrode is electrically joined to the first wiring, and the second electrode is electrically joined to the second wiring.

2. The carrier structure according to claim 1, wherein the insulating layer has an opening penetrating from the surface on the functional element unit side to the surface on the substrate side, and at least one of the first wiring and the second wiring is electrically connected to either the first electrode or the second electrode through the opening.

3. The carrier structure according to claim 2, wherein the size of the opening on the surface of the insulating layer on the functional element unit side is formed smaller than the size of the flat surface of the first electrode on the insulating layer side and smaller than the size of the flat surface of the second electrode on the insulating layer side, and at least one of the first wiring and the second wiring includes a bonding surface extending on the surface of the insulating layer on the functional element unit side.

4. The carrier structure according to claim 2 or 3, wherein the opening on the surface of the insulating layer on the functional element unit side is formed at a position that does not overlap with either the first electrode or the second electrode in a direction orthogonal to the surface on the functional element unit side, and at least one of the first wiring and the second wiring includes a bonding surface extending on the surface of the insulating layer on the functional element unit side.

5. The carrier structure according to any one of claims 1 to 3, wherein the first wiring is joined to the first electrode and the insulating member, and the second wiring is joined to the second electrode and the insulating member.

6. The carrier structure according to claim 5, wherein the first wiring and the second wiring are inorganic substances, and the insulating member is an organic substance.

7. The carrier structure according to any one of claims 1 to 3, wherein a first height of a portion protruding from the insulating layer toward the functional element unit at a portion where the first wiring is joined to the first electrode is substantially equal to a second height of a portion protruding from the insulating layer toward the functional element unit at a portion where the second wiring is joined to the second electrode.

8. The carrier structure according to any one of claims 1 to 3, wherein a plurality of the first wirings and the second wirings are formed on the insulating layer, and the carrier structure has a plurality of functional element units joined to the first wirings and the second wirings.

9. The carrier structure according to any one of claims 1 to 3, wherein the functional element unit has a flat surface formed of the insulating member, the first electrode, and the second electrode on the insulating layer side, and an area where the first wiring and the second wiring are in contact with the flat surface of the functional element unit is 90% or less of the area of the flat surface.

10. A method of manufacturing an electronic device, the method including: preparing a carrier structure including a substrate, an insulating layer formed above the substrate, a first wiring formed above the insulating layer, a second wiring formed above the insulating layer and separated from the first wiring, a first terminal pad electrically connected to the first wiring, a second terminal pad electrically connected to the second wiring, a functional element, a first electrode electrically connected to the functional element, a second electrode electrically connected to the functional element, and a functional element unit including an insulating member covering the functional element, wherein the first electrode is electrically connected to the first wiring and the second electrode is electrically connected to the second wiring; inspecting the functional element unit using the first terminal pad and the second terminal pad; peeling the functional element unit from the first wiring and the second wiring; and attaching the peeled functional element unit to a device substrate.

11. In the step of inspecting the functional element unit, if there is an abnormality in the functional element unit, the functional element unit with the abnormality is peeled off from the first wiring and the second wiring, and a functional element unit different from the peeled functional element unit is joined to the first wiring and the second wiring. The method for manufacturing an electronic device according to claim 10, further comprising the step of:

12. The method for manufacturing an electronic device according to claim 10 or 11, wherein the functional element unit is joined to the first wiring and the second wiring such that a gap is provided between the functional element unit and the insulating layer.

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