Wiring board and semiconductor device

Abstract

This wiring board comprises: a first base material including an organic material; a second base material mainly made of an inorganic material and joined to the first base material; and first wiring positioned at least inside the first base material. The first wiring is provided with a first via conductor penetrating at least a part of the first base material, a first wiring layer electrically connected to the first via conductor, and a first alloy layer positioned at the boundary surface between the first via conductor and the first wiring layer. The first via conductor contains a first metal and a second metal different from the first metal. The first wiring layer contains a third metal. The first alloy layer contains an alloy of the second metal and the third metal.

Description

Wiring board and semiconductor device

[0001] The present disclosure relates to a wiring substrate and a semiconductor device.

[0002] Conventionally, in a wiring board having wiring including a plurality of via conductors penetrating a substrate and a wiring layer electrically connecting the plurality of via conductors, a technique for connecting the via conductors and the wiring layer by changing the metal composition has been known (see, for example, Patent Documents 1 and 2).

[0003] Patent No. 3634984 Patent No. 3187373

[0004] The wiring board of the present disclosure comprises a first substrate containing an organic material, a second substrate primarily composed of an inorganic material and bonded to the first substrate, and a first wiring located at least inside the first substrate, wherein the first wiring comprises a first via conductor penetrating at least a portion of the first substrate, a first wiring layer electrically connected to the first via conductor, and a first alloy layer located at the interface between the first via conductor and the first wiring layer, wherein the first via conductor contains a first metal and a second metal different from the first metal, the first wiring layer contains a third metal, and the first alloy layer contains an alloy of the second metal and the third metal.

[0005] FIG. 1 is a perspective view showing an example of the configuration of a semiconductor device according to an embodiment. FIG. 2 is a cross-sectional view showing an example of the configuration of a wiring board according to an embodiment. FIG. 3 is a cross-sectional view showing an example of the configuration of a first wiring in the wiring board according to an embodiment. FIG. 4 is an explanatory diagram of the aspect of metal composition in a cross section taken along line A-A in FIG. 3. FIG. 5 is a cross-sectional view showing an example of the configuration of a joint between a first wiring and a connection conductor in the wiring board according to an embodiment. FIG. 6 is a cross-sectional view showing an example of the configuration of a wiring board according to a comparative example.

[0006] Hereinafter, embodiments for carrying out a wiring board and a semiconductor device according to the present disclosure (hereinafter referred to as "embodiments") will be described in detail with reference to the drawings. Note that the present disclosure is not limited to these embodiments. Furthermore, the embodiments can be appropriately combined as long as the processing content is not contradictory. Furthermore, the same components in the following embodiments will be assigned the same reference numerals, and redundant explanations will be omitted.

[0007] In addition, in the drawings referred to below, to make the explanation easier to understand, an orthogonal coordinate system may be shown in which the X-axis direction, Y-axis direction, and Z-axis direction, which are perpendicular to each other, are defined, and the Z-axis direction is the thickness direction of the wiring board.

[0008] <Semiconductor Device> FIG. 1 is a perspective view showing an example of the configuration of a semiconductor device 100 according to the embodiment. As shown in FIG. 1, the semiconductor device 100 according to the embodiment includes a wiring substrate 110 and a semiconductor element 120. The wiring substrate 110 includes a first substrate and a second substrate. The wiring substrate 110 is a laminate of the first substrate 10 and the second substrate 20. The first substrate 10 includes an organic material. The organic material may be an organic resin. The second substrate 20 is mainly composed of an inorganic material. The inorganic material may be ceramic. The detailed configuration of the wiring substrate 110 will be described later using FIG. 2 and the like.

[0009] The semiconductor element 120 is mounted on the wiring substrate 110. In the example shown in Fig. 1, the semiconductor element 120 is located on a first surface 11 (described later) of a first base material 10 of the wiring substrate 110.

[0010] <Wiring Board> Fig. 2 is a cross-sectional view showing an example of the configuration of a wiring board 110 according to an embodiment. Note that Fig. 2 shows a cross section of the wiring board 110 taken along a plane including the X-axis and Z-axis shown in Fig. 1. As shown in Fig. 2, the wiring board 110 includes a first substrate 10, a second substrate 20, a first wiring 30, and a second wiring 40.

[0011] <Substrate> The first substrate 10 includes an organic material. The organic material may be an organic resin. The organic resin may be, for example, an epoxy resin, an acrylic resin, a polycarbonate resin, a polyimide resin, an olefin resin, or a polyphenylene resin.

[0012] The organic resin may be, for example, polytetrafluoroethylene (PTFE), other fluororesins, or polyphenylene ether resins. The first substrate 10 may contain components other than the organic resin. Examples of components other than the organic resin contained in the first substrate 10 include inorganic materials such as silica and rubber materials. The content of the inorganic material, such as silica, in the first substrate 10, in terms of mass %, may be greater than the content of the organic resin in the first substrate 10. More specifically, the content of the inorganic material, such as silica, in the first substrate 10 may be 50 mass % or more of the first substrate 10, and the content of the organic resin in the first substrate 10 may be 50 mass % or less of the first substrate 10. The content of the organic resin in the first substrate 10 may be 10 mass % or more and 30 mass % or less of the first substrate 10.

[0013] The first substrate 10 has a first surface 11 and a second surface 12 located opposite the first surface 11. The first substrate 10 may be a plate-like body having the first surface 11 and the second surface 12 as main surfaces.

[0014] The first substrate 10 may have multiple organic resin layers 13. The multiple organic resin layers 13 may be stacked along the thickness direction of the first substrate 10. By configuring the first substrate 10 using multiple organic resin layers 13, it is possible to obtain a first substrate 10 having a first wiring layer 32 (described later) therein. A wiring board 110 having such a first substrate 10 has a high degree of design freedom. Note that the organic resin layer 13 refers to a layer containing an organic resin, and includes not only a layer composed only of an organic resin, but also a layer in which an inorganic material such as silica is contained in the organic resin. Furthermore, the content of the organic resin in the organic resin layer 13 in terms of mass % may be smaller than the content of the inorganic material in the organic resin layer 13 in terms of mass %.

[0015] 2, the first base material 10 has two organic resin layers 13, but the number of organic resin layers 13 is not limited to two. The number of organic resin layers 13 may be three or more.

[0016] The second substrate 20 contains ceramic as an inorganic material. Examples of the ceramic include ceramics primarily composed of at least one selected from the group consisting of aluminum oxide, silicon oxide, zirconium oxide, silicon carbide, silicon nitride, and aluminum nitride, and ceramics primarily composed of composite oxides such as mullite, zircon, steatite, enstatite, glass ceramics, and glass. The second substrate 20 may be high-temperature co-fired ceramic (HTCC) or low-temperature co-fired ceramic (LTCC).

[0017] In addition to ceramic, the second substrate 20 contains a silica component such as glass.

[0018] The second substrate 20 has a third surface 21 and a fourth surface (not shown) located opposite the third surface 21. The second substrate 20 may be a plate-like body having the third surface 21 and the fourth surface (not shown) as main surfaces.

[0019] The second substrate 20 may have a plurality of ceramic layers 23. In this case, the plurality of ceramic layers 23 may be stacked along the thickness direction of the second substrate 20. By configuring the second substrate 20 using a plurality of ceramic layers 23 in this manner, it is possible to obtain a second substrate 20 having a second wiring layer 42 (described later) therein. A wiring board 110 having such a second substrate 20 has a high degree of freedom in design.

[0020] Furthermore, by configuring the second substrate 20 using a plurality of ceramic layers 23, it is possible to manufacture the second substrate 20 while checking for each layer whether the first wiring 30 described below is properly formed. This makes it possible to improve the yield of the second substrate 20.

[0021] The number of ceramic layers 23 is not limited. For example, the number of ceramic layers 23 may be two, or may be three or more. Furthermore, the second substrate 20 does not necessarily have to have a multi-layer structure. In other words, the second substrate 20 may be a single layer.

[0022] Ceramics have higher rigidity than organic materials. Therefore, the wiring substrate 110 formed of the second substrate 20 mainly composed of ceramic and the first substrate 10 containing an organic material can have improved rigidity compared to a wiring substrate made of only organic materials. This makes it easy to ensure the rigidity of the wiring substrate 110, for example, even if the wiring substrate 110 is made thin, without adding a reinforcing member or the like.

[0023] Furthermore, by combining the second substrate 20 mainly composed of ceramic with the first substrate 10 containing an organic material, it is possible to increase rigidity while achieving finer wiring and narrower pitches. For example, since warping of the substrate becomes more likely as the substrate becomes larger, a configuration of the wiring substrate 110 in which the second substrate 20 compensates for the low rigidity of the first substrate 10 is useful for increasing the size of the substrate.

[0024] <Wiring> As shown in Fig. 2, the first wiring 30 is located at least inside the first substrate 10. The first wiring 30 extends from one of the first surface 11 and the second surface 12 to the other. Note that "extending" here does not necessarily mean extending the shortest distance. The first wiring 30 may be electrically connected to the second wiring 40 (described later) at the interface, which is the joining surface between the first substrate 10 and the second substrate 20.

[0025] The first wiring 30 may be, for example, a metal conductor containing copper. The first wiring 30 includes a first via conductor 31, a first wiring layer 32, and a first alloy layer 33 (see FIG. 3 ). There may be a plurality of first via conductors 31. The first via conductor 31 penetrates at least a portion of the first substrate 10. The first via conductor 31 penetrates one or more organic resin layers 13.

[0026] The first wiring layer 32 is located between adjacent organic resin layers 13. The first wiring layer 32 electrically connects the plurality of first via conductors 31 to each other. The first wiring 30 may include a wiring layer located on the first surface 11 of the first substrate 10. The first wiring layer 32 may contain, for example, copper (Cu), and more specifically, the first wiring layer 32 may be made of copper foil. That is, the first wiring layer 32 may be 70% or more copper by weight of the entire first wiring layer 32.

[0027] The first alloy layer 33 is located at the interface between the first via conductor 31 and the first wiring layer 32. The first alloy layer 33 may be located at the interface with the first via conductor 31 of the first wiring layer 32, which is connected to the second wiring 40 at the interface between the first substrate 10 and the second substrate 20.

[0028] The second wiring 40 is located inside the second substrate 20. The second wiring 40 is electrically connected to the first wiring 30. The second wiring 40 extends from one of the third surface 21 and the fourth surface (not shown) to the other. Note that "extending" here does not necessarily mean extending the shortest distance. The second wiring 40 may have, for example, a wiring layer in the middle that forms the portion that extends along the third surface 21.

[0029] The second wiring 40 may be, for example, a metal conductor containing tungsten. The second wiring 40 may also be a metal conductor containing copper, silver, or molybdenum. The second wiring 40 includes a second via conductor 41, a second wiring layer 42, and a second alloy layer 43 (see FIG. 3 ). The second via conductor 41 penetrates at least a portion of the second substrate 20. The second via conductor 41 penetrates one or more ceramic layers 23.

[0030] The second wiring layer 42 is located inside the second substrate 20. The second wiring layer 42 may be located between adjacent ceramic layers 23. As shown in FIG. 2 , the second wiring layer 42 may be located between the first substrate 10 and the second substrate 20 and include a connection conductor 421 that electrically connects the first wiring 30 and the second wiring 40. In this case, the connection conductor 421 may be a conductor that contains a silica component. A wiring board 110 including such a connection conductor 421 has a high degree of freedom in design.

[0031] For example, the connection conductor 421 may have a width greater than that of the first via conductor 31 that is in direct contact with the connection conductor 421 in the direction along the first surface 11. This facilitates alignment of the connection conductor 421 with the first via conductor 31, thereby improving the yield of the wiring substrate 110. The connection conductor 421 may also be bonded to the second substrate 20 via a silica component. The silica component is contained in the connection conductor 421 and the second substrate 20. This allows the connection conductor 421 to be firmly bonded to the second substrate 20, which also contains the silica component, via the silica component. Note that the connection conductor 421 may have a width greater than that of at least one of the lands located within the first substrate 10 and the second substrate 20 in the direction along the first surface 11.

[0032] Furthermore, for example, the first substrate 10 may be bonded to the connecting conductor 421 and the second substrate 20 by an anchor effect. The anchor effect may be caused by, for example, a silica component contained in the second substrate 20 and the connecting conductor 421.

[0033] In this way, the first substrate 10 is joined to the connecting conductor 421 and the second substrate 20 by the anchor effect, which makes it difficult for the second substrate 20, the connecting conductor 421, and the first substrate 10 to shift in the direction along the third surface 21 of the second substrate 20. This stabilizes the physical connection between the first wiring 30 and the second wiring 40.

[0034] The second via conductors 41 may be present at multiple positions in the thickness direction of the second substrate 20. The second wiring layer 42 electrically connects at least two of the multiple second via conductors 41. The second wiring layer 42 electrically connects the multiple second via conductors 41 to each other. The second wiring layer 42 may be a so-called land. Note that the second wiring 40 may include a wiring layer located on a fourth surface of the second substrate 20 opposite the third surface 21 in the thickness direction.

[0035] 5 , the second alloy layer 43 is located at the interface between the first via conductor 31 and the second wiring layer 42. The connecting conductor 421 may be defined as a portion including the second alloy layer 43 and the second wiring layer 42. The second alloy layer 43 contains a silica component. In this way, the inclusion of the silica component in the second alloy layer 43 can improve the bonding of the wiring to the second substrate 20, which is primarily composed of ceramic.

[0036] Furthermore, second via conductor 41 contains a silica component. In this way, the silica component in second via conductor 41 has an anchor effect, which can further enhance the bonding of second via conductor 41 to second substrate 20, which is mainly composed of ceramic.

[0037] Because the wiring substrate 110 has the second wiring 40 on the second base material 20, the degree of freedom in wiring design is higher compared to conventional wiring substrates in which only the substrate containing an organic resin has wiring. On the other hand, when a configuration is adopted in which wiring is provided on both the first base material 10 and the second base material 20, it is desirable to bond the first base material 10 and the second base material 20 more firmly so that misalignment of the first wiring 30 and the second wiring 40 does not occur.

[0038] In the example shown in FIG. 2, the second wiring 40 includes the second wiring layer 42, but the second wiring 40 does not necessarily have to include the second wiring layer 42.

[0039] Of the first wiring 30 and the second wiring 40, only the second wiring 40 may contain a silica component. In this case, the second wiring 40 is firmly bonded to the second substrate 20, which also contains a silica component, via the silica component. Specifically, the silica component contained in the second wiring 40 is integrated with the silica component contained in the second substrate 20 by firing. The integrated silica component hardens while entering the gaps between the multiple metal particles that make up the second wiring 40, thereby generating an anchor effect. The second wiring 40 is firmly bonded to the second substrate 20 due to this anchor effect. This can increase the rigidity of the second substrate 20.

[0040] Furthermore, when the second wiring 40 contains a silica component, it is possible to make the shrinkage rates of the second base material 20 and the second wiring 40 closer to each other in the firing step during the manufacture of the wiring substrate 110. This makes it possible to make the positional deviation of the second wiring 40 less likely to occur.

[0041] The second wiring 40 may be formed by printing a conductive paste containing a metal component such as copper or tungsten and a silica component on a green sheet, which is the raw material of the ceramic layer 23, and firing the green sheet at the same time. The second wiring 40 may also be plated. Specifically, the conductive paste may be a paste containing at least one of copper, tungsten, and molybdenum and silicon dioxide (SiO ２ The silicon dioxide may be present in a state of being contained in silica, or in a state of being contained in borosilicate glass. The conductor paste may contain only silica as a material containing silicon dioxide, or may contain both silica and borosilicate glass.

[0042] On the other hand, the first wiring 30 may be formed by copper plating or copper foil transfer, whereby, of the first wiring 30 and the second wiring 40, only the second wiring 40 can be configured to contain a silica component.

[0043] Fig. 3 is a cross-sectional view showing an example of the configuration of the first wiring 30 in the wiring substrate 110 according to the embodiment. Fig. 4 is an explanatory diagram of the metal composition in the cross section taken along line A-A in Fig. 3. Fig. 3 shows the junction between the first via conductor 31 and the first wiring layer 32 in the first wiring 30.

[0044] As shown in FIGS. 3 and 4 , when the first via conductor 31 and the first wiring layer 32 are joined, the first via conductor 31 contains a first metal and a second metal. The first metal may be copper (Cu). The second metal is a metal different from the first metal. The second metal may be tin (Sn). The first wiring layer 32 contains a third metal. The third metal may be the same metal as the first metal. The third metal may be copper (Cu). Here, the weight percentage of the first metal contained in the first via conductor 31 may be smaller than the weight percentage of the second metal contained in the first via conductor 31. More specifically, the weight percentage of copper as the first metal contained in the first via conductor 31 may be 15% or more and 45% or less. In this case, the weight percentage of tin as the second metal contained in the first via conductor 31 may be 35% or more and 55% or less.

[0045] Furthermore, the first via conductors 31 may contain 1% to 10% by weight of resin. This configuration can impart fluidity to the first via conductors 31. Furthermore, it can improve the bonding strength between the first via conductors 31 and the first substrate 10, which contains a resin as an organic material. The resin contained in the first via conductors 31 and the resin contained in the first substrate 10 may be the same or different. Furthermore, the weight percentage of the resin contained in the first substrate 10 may be greater than the weight percentage of the resin contained in the first via conductors 31. The resin contained in the first via conductors 31 may be an epoxy resin.

[0046] Furthermore, the first via conductor 31 may contain at least one of bismuth and indium, which are fourth metals described below. In this case, the second metal and the fourth metal contained in the first via conductor 31 may exist as a eutectic. More specifically, the first via conductor 31 may contain tin as the second metal and bismuth as the fourth metal, or may contain a eutectic of tin and bismuth.

[0047] When the first metal contained in the first via conductor 31 is copper, the surface of the first metal may be coated. This configuration can reduce oxidation and deterioration of the copper. Examples of coating materials include silver (Ag).

[0048] The first alloy layer 33 contains an alloy of the second metal and the third metal. The first alloy layer 33 may contain an alloy of copper (Cu) and tin (Sn).

[0049] In this way, by positioning first alloy layer 33 containing an alloy of the second metal and the third metal between first via conductor 31 containing the second metal and first wiring layer 32 containing the third metal, the bonding strength between first via conductor 31 and first wiring layer 32 can be increased by first alloy layer 33. This can improve the connection reliability of first wiring 30.

[0050] Furthermore, when the first metal and the third metal are the same metal, the first via conductor 31 and the first alloy layer 33 contain two common metals, thereby further increasing the bonding strength between the first via conductor 31 and the first alloy layer 33.

[0051] Furthermore, since the first metal and the third metal are copper (Cu), the thermal conductivity and electrical conductivity of the first via conductor 31 and the first wiring layer 32 are high, and the cost is lower than that of high-conductivity metals other than copper (Cu), such as gold (Au) or silver (Ag).

[0052] Furthermore, since the second metal is tin (Sn), an alloy can be formed at a lower temperature than other metals that form alloys with copper (Cu), such as zinc or lead.

[0053] The first via conductor 31 is made of Cu, which is an alloy of the first metal and the second metal. ６ Sn ５ The first wiring layer 32 may contain copper (Cu) as a third metal. The first alloy layer 33 may contain Cu as an alloy of the second metal and the third metal. ３ Sn may be contained.

[0054] With this configuration, the alloy layer formed at the boundary between the first substrate 10 and the second substrate 20 has a high copper (Cu) ratio, resulting in high conductivity. Furthermore, the high copper (Cu) ratio in the alloy layer formed at the boundary between the first substrate 10 and the second substrate 20 reduces the possibility of voids occurring in the alloy layer during manufacturing of the wiring substrate 110. Furthermore, when the first wiring layer 32 contains copper as the third metal and the first via conductor 31 contains copper as the first metal and tin as the second metal, copper (Cu) and tin (Sn) can be diffused between the first wiring layer 32 and the first via conductor 31. This improves the bonding strength of the wiring.

[0055] Furthermore, in the first wiring 30, the metal composition may continuously change due to diffusion in the respective interface regions between the first via conductor 31, the first alloy layer 33, and the first wiring layer 32. That is, favorable diffusion of metal elements occurs in the respective interface regions between the first via conductor 31, the first alloy layer 33, and the first wiring layer 32, thereby improving the bonding strength of the wiring. In this case, the content of the first metal in the first alloy layer 33 is higher than the content of the first metal in the first via conductor 31 and lower than the content of the first metal in the first wiring layer 32. Note that the respective interface regions between the first via conductor 31, the first alloy layer 33, and the first wiring layer 32 include the interfaces between the first via conductor 31, the first alloy layer 33, and the first wiring layer 32 and the vicinity of these interfaces.

[0056] 4, a plurality of particles 34 of a fourth metal different from the second metal and the third metal may be located at the interface between the first alloy layer 33 and the first wiring layer 32. Specifically, bismuth may be scattered as the fourth metal particles 34 at the interface between the first alloy layer 33 and the first wiring layer 32. In this way, the presence of a plurality of bismuth particles at the interface between the first alloy layer 33 and the first wiring layer 32 so as to fill voids can reduce the occurrence of voids that could be the starting point of cracks. The fourth metal may be a metal other than bismuth, such as indium.

[0057] FIG. 5 is a cross-sectional view showing an example of the configuration of a joint between a first wiring 30 and a connection conductor 421 in the wiring substrate 110 according to the embodiment.

[0058] As shown in FIG. 5 , in one embodiment, the portion of the second wiring layer 42 located between the first substrate 10 and the second substrate 20 may include, for example, an underlayer 24a containing at least one of tungsten, copper, or molybdenum, and at least one of silica or glass; a nickel coating layer 24b located on the underlayer 24a and containing nickel; and a copper coating layer 25 located on the nickel coating layer 24b. When the second wiring layer 42 of the first via conductor 31 and the connecting conductor 421 is joined, the second alloy layer 43 located on the copper coating layer 25 of the nickel coating layer 24b and the copper coating layer 25 sequentially stacked on the ceramic layer 23 contains an alloy of a second metal and a third metal. The second wiring 40 contains a third metal. The second metal is a metal different from the first metal. The second metal may be tin (Sn). The third metal may be the same metal as the first metal. The third metal may be copper (Cu). The nickel coating layer 24b may contain boron (B). The nickel coating layer 24b may be formed by electroless plating. The copper coating layer 25 may also be formed by electroless plating.

[0059] Because there is a difference in the thermal expansion coefficient between ceramic and organic materials, repeated thermal expansion and contraction causes a large load at the boundary between the second substrate 20, which is primarily composed of ceramic, and the first substrate 10, which contains an organic material. Such load may reduce the connection reliability of the wiring between the substrates. In the present disclosure, the second alloy layer 43 is located at the boundary between the second substrate 20 and the first substrate 10, more specifically, between the first via conductor 31 and the second wiring layer 42, thereby improving the connection reliability of the wiring between the substrates.

[0060] Furthermore, compared to when the second alloy layer 43 is not located at the interface between the first substrate 10 and the second substrate 20, i.e., when the first via conductor 31 and the second via conductor 41 are directly joined, the connection strength of the first via conductor 31 and the second via conductor 41, which are connections between different metals, can be increased.

[0061] 5, the first wiring layer 32 may contain copper (Cu), and the second wiring layer 42 may contain a fifth metal having a melting point higher than that of copper (Cu). This facilitates adjustment of the firing temperature of the ceramic during the firing process during manufacturing. The fifth metal may be, for example, tungsten, molybdenum, or manganese.

[0062] Furthermore, in the wiring substrate 110, the first substrate 10 is laminated on the third surface 21 of the second substrate 20. The first surface 11 of the first substrate 10 is bonded to the third surface 21 of the second substrate 20. That is, the first substrate 10 is directly bonded to the second substrate 20 without an adhesive layer. Specifically, the ceramic layer 23 of the second substrate 20 may be primarily composed of ceramic containing hydroxyl groups on its surface. In this case, the first substrate 10 may be chemically bonded to the second substrate 20 via the hydroxyl groups. This allows the first substrate 10 and the second substrate 20 to be hydrogen bonded via the hydroxyl groups.

[0063] 6 is a cross-sectional view showing an example of the configuration of a wiring board 200 according to a comparative example. For example, when a conductor 210 such as solder is located at the boundary between the first substrate 10 and the second substrate 20, as in the wiring board 200 shown in FIG. 6 , it may be possible to absorb the difference in thermal expansion coefficients. However, when a conductor 210 such as solder is located at the boundary between the first substrate 10 and the second substrate 20, the thickness of the board increases, and the wiring board 200 tends to become larger. In the present disclosure, since a conductor 210 such as solder is not located between the first substrate 10 and the second substrate 20, the thickness of the board is reduced, and the wiring board 110 can be made smaller.

[0064] Furthermore, in the wiring substrate 110, the first substrate 10 and the second substrate 20 are in close contact with each other. By bringing the first substrate 10 and the second substrate 20 into close contact with each other in this manner, the possibility that the wiring located at the interface between the first substrate 10 and the second substrate 20 will be exposed to the outside air can be reduced, making the wiring less susceptible to deterioration. This can improve the long-term stability of the wiring substrate 110. Furthermore, in addition to the second substrate 20 mainly composed of ceramic, it is possible to strengthen the bonding of the wiring to the first substrate 10 containing an organic material.

[0065] Although the present disclosure has been described in detail above, the present disclosure is not limited to the above-described embodiments, and various modifications and improvements can be made without departing from the spirit and scope of the present disclosure.

[0066] The disclosed embodiments should be considered in all respects as illustrative and not restrictive. Indeed, the above-described embodiments may be embodied in various forms. Furthermore, the above-described embodiments may be omitted, substituted, or modified in various ways without departing from the scope and spirit of the appended claims.

[0067] For example, in the above embodiment, a low-roughness metal foil may be used for the first wiring layer 32. By using a low-roughness metal foil for the first wiring layer 32, the interfacial conductivity between the first wiring layer 32, which is a conductor, and the dielectric is improved compared to when a high-roughness metal foil is used. This improves the high-frequency characteristics of the wiring substrate 110. The high-frequency characteristics may be, for example, high-frequency characteristics when used in an electronic circuit that handles electronic signals of 5 GHz or higher. The high-frequency characteristics may also be, for example, high-frequency characteristics when used in an electronic circuit that handles electronic signals of 20 GHz or higher. The surface roughness (Srd: Surface Roughness Depth) may be, for example, 0.06 μm or more and 0.7 μm or less.

[0068] The thickness of the first wiring layer 32 in the Z direction may also be increased. In this case, even when the width of the first wiring layer 32 in the XY plane is reduced, it is easy to increase the conductor cross-sectional area of ​​the first wiring layer 32. As a result, even when the area of ​​the wiring substrate 110 in the XY plane is reduced, it is possible to suppress a reduction in the conductor cross-sectional area of ​​the first wiring layer 32 due to miniaturization. Therefore, even when the area of ​​the wiring substrate 110 where wiring is provided is reduced by, for example, providing recesses or through holes in the wiring substrate 110, it is easy to form the first wiring layer 32. Furthermore, when the thickness of the first wiring layer 32 in the Z direction is large, it is easy to reduce the roughness of the first wiring layer 32. Note that in the present disclosure, miniaturization of the first wiring layer 32 may include reducing the width dimension of the first wiring layer 32 in the XY plane and reducing the distance between multiple first wiring layers 32.

[0069] The present technology can also be configured as follows. (1) A wiring board comprising: a first base material containing an organic material; a second base material mainly composed of an inorganic material and bonded to the first base material; and a first wiring located at least inside the first base material, wherein the first wiring comprises: a first via conductor penetrating at least a portion of the first base material; a first wiring layer electrically connected to the first via conductor; and a first alloy layer located at the interface between the first via conductor and the first wiring layer, wherein the first via conductor contains a first metal and a second metal different from the first metal, the first wiring layer contains a third metal, and the first alloy layer contains an alloy of the second metal and the third metal. (2) The wiring board according to (1), wherein the first metal and the third metal are the same metal. (3) The wiring board according to (2), wherein the first metal and the third metal are Cu. (4) The wiring board according to (3), wherein the second metal is Sn. (5) The first via conductor is made of Cu, which is an alloy of the first metal and the second metal. ６ Sn ５ the first wiring layer contains Cu, which is the third metal; and the first alloy layer contains Cu, which is an alloy of the second metal and the third metal. ３(6) The wiring board according to any one of (1) to (5), wherein the metal composition changes continuously in the interface region between the first via conductor, the first alloy layer, and the first wiring layer. (7) The wiring board according to (6), wherein bismuth is scattered at the interface between the first alloy layer and the first wiring layer. (8) The wiring board according to any one of (1) to (7), comprising: a second wiring located on the second base material and electrically connected to the first wiring; and a second alloy layer located at the interface between the first via conductor and the second wiring, wherein the first base material contains ceramic, the second alloy layer contains an alloy of the second metal and the third metal, and the second wiring contains the third metal. (9) The wiring board according to (8), wherein the second wiring comprises: a second via conductor electrically connected to the first via conductor via the second alloy layer and penetrating at least a portion of the second base material; and a second wiring layer electrically connected to the second via conductor, wherein the second wiring layer contains the third metal, and the second via conductor contains a metal different from the metal contained in the first via conductor. (10) The wiring board according to (9), wherein the second via conductor contains a silica component. (11) The wiring board according to (9), wherein the second alloy layer contains a silica component. (12) The wiring board according to (9) or (10), wherein the second wiring comprises: a plurality of second via conductors located at different positions in a thickness direction of the second base material; and a second wiring layer located inside the second base material and electrically connecting at least two of the plurality of second via conductors, wherein the first wiring layer contains Cu, and the second wiring layer contains a metal having a higher melting point than Cu. (13) The wiring board according to any one of (1) to (12), wherein the second base material and the first base material are directly bonded. (14) The wiring board according to any one of (1) to (13), wherein the second base material and the first base material are in close contact. (15) A semiconductor device comprising: the wiring board according to any one of (1) to (14), and a semiconductor element mounted on the wiring board.

[0070] REFERENCE SIGNS LIST 10 First substrate 20 Second substrate 30 First wiring 31 First via conductor 32 First wiring layer 33 First alloy layer 40 Second wiring 41 Second via conductor 42 Second wiring layer 43 Second alloy layer 100 Semiconductor device 110 Wiring substrate 120 Semiconductor element

Claims

1. A wiring board comprising: a first substrate containing an organic material; a second substrate mainly composed of an inorganic material and joined to the first substrate; and a first wiring located at least inside the first substrate, wherein the first wiring includes a first via conductor penetrating at least a part of the first substrate, a first wiring layer electrically connected to the first via conductor, and a first alloy layer located at an interface between the first via conductor and the first wiring layer, the first via conductor contains a first metal and a second metal different from the first metal, the first wiring layer contains a third metal, and the first alloy layer contains an alloy of the second metal and the third metal.

2. The wiring board according to claim 1, wherein the first metal and the third metal are the same metal.

3. The wiring board according to claim 2, wherein the first metal and the third metal are Cu.

4. The wiring board according to claim 3, wherein the second metal is Sn.

5. The first via conductor is Cu, an alloy of the first metal and the second metal. ６ Sn ５ contains, the first wiring layer contains Cu, which is the third metal, and the first alloy layer is Cu, an alloy of the second metal and the third metal. ３ The wiring board according to claim 4, containing Sn.

6. The wiring board according to any one of claims 1 to 5, wherein the metal composition continuously changes in each interface region of the first via conductor, the first alloy layer, and the first wiring layer.

7. The wiring board according to claim 6, wherein bismuth is scattered at an interface between the first alloy layer and the first wiring layer.

8. The wiring board according to any one of claims 1 to 7, further comprising: a second wiring located in the second substrate and electrically connected to the first wiring; and a second alloy layer located at an interface between the first via conductor and the second wiring, wherein the first substrate contains ceramic, the second alloy layer contains an alloy of the second metal and the third metal, and the second wiring contains the third metal.

9. The wiring board according to claim 8, wherein the second wiring includes: a second via conductor electrically connected to the first via conductor through the second alloy layer and penetrating at least a part of the second substrate; and a second wiring layer electrically connected to the second via conductor, the second wiring layer contains the third metal, and the second via conductor contains a metal different from the metal contained in the first via conductor.

10. The wiring board according to claim 9, wherein the second via conductor contains a silica component.

11. The wiring board according to claim 8, wherein the second alloy layer contains a silica component.

12. The second wiring includes a plurality of the second via conductors whose positions in the thickness direction of the second base material are different from each other, and a second wiring layer that is located inside the second base material and electrically connects at least two of the plurality of the second via conductors. The first wiring layer contains Cu, and the second wiring layer contains a metal having a higher melting point than Cu. The wiring board according to claim 9 or 10.

13. The second base material and the first base material are directly joined. The wiring board according to any one of claims 1 to 12.

14. The second base material and the first base material are in close contact with each other. The wiring board according to any one of claims 1 to 13.

15. A semiconductor device including the wiring board according to any one of claims 1 to 14, and a semiconductor element mounted on the wiring board.

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