Electronic device for performing time synchronization, and operation method thereof

Abstract

The present disclosure relates to an electronic device for performing time synchronization, and an operation method thereof. The operation method performed by the electronic device for performing time synchronization, according to an embodiment of the present disclosure, may comprise steps in which at least one processor: checks a synchronization message received from a master device; calls, in response to the synchronization message, a first data pair including a first delay value and a first offset value stored in a memory; performs time synchronization for a slave device on the basis of the first offset value; checks a second delay value between the master device and the slave device; and stores, in the memory, a second data pair including the second delay value and the first offset value.

Description

Electronic device for performing time synchronization and method of operation thereof

[0001] The present disclosure relates to network technology, and more particularly, to an electronic device for performing time synchronization in a network high-latency environment and an operating method thereof.

[0002] The present invention was derived from research conducted as part of the Next Generation Edge Computing System Technology Development Project of the Ministry of Science and ICT (Project Unique Number: 1711193277, Research and Development Project Number: 2020-0-00844-004, Research Project Name: Development of Lightweight System Software Technology for DPT Server System Resource Management and Control, Research Management Specialist Organization: Government Communications Planning and Evaluation Institute, Host Organization: Electronics and Telecommunications Research Institute, Research Period: 2023.01.01~2023.12.31.). Meanwhile, the Korean government has no property interest in any aspect of the present invention.

[0003] Radio Access Networks (RANs) are evolving to improve service quality and expand coverage by linking small cells, such as micro cells, pico cells, and femto cells, with relatively large macro cells. Small cells, which are small mobile communication base stations, are low-power radio access nodes with a relatively narrower service area than general cells. Similar to a DSL (Digital Subscriber Line) modem, they are connected to a home wired IP (Internet Protocol) network, facilitating wired and wireless communication through terminals.

[0004] One of the basic requirements for small cells, especially those based on Time Division Duplexing (TDD) systems, to operate as small mobile communication base stations is frequency and time synchronization with macro base stations, and the IEEE1588 Precision Time Protocol (PTP) is known as one of such synchronization methods. In a PTP environment, the device that serves as the reference time is referred to as the master device, and the device that requires synchronization is referred to as the slave device. The different times of the master device and the slave device can be synchronized through network packets. During the synchronization process, the delay value required for the network packet to reach the slave device from the master device needs to be calculated, and this delay value can be calculated through separate packets called delay request and delay response.

[0005] However, in some cases, the resulting delay can temporarily become very large, making it difficult to calculate the offset between the master and slave devices. To address this issue, LinuxPTP utilizes a delay filter to select the median value among the most recently calculated delay values ​​and use it as the current delay value. However, this method also has the problem that the recording time from the slave device can be significantly delayed due to sudden network delays, which can significantly affect offset calculation.

[0006] In this regard, reference may be made to prior literature such as KR10-2493764B1 and KR10-1650701B1.

[0007] The present disclosure is intended to solve the above-described problems and provides an electronic device and an operating method thereof that performs time synchronization in a network high-delay environment.

[0008] The present disclosure aims to provide an electronic device and an operating method thereof that performs time synchronization based on an offset when the delay is small.

[0009] The problems to be solved by the present disclosure are not limited to the problems described above, and other problems not mentioned will be clearly understood by those skilled in the art from the description below.

[0010] In an operating method by an electronic device performing time synchronization according to an embodiment of the present disclosure, the operating method may include: a step of confirming, by at least one processor, a synchronization message received from a master device; a step of calling, by at least one processor, a first data pair including a first delay value and a first offset value stored in a memory in response to the synchronization message; a step of performing, by at least one processor, time synchronization for a slave device based on the first offset value; a step of confirming, by at least one processor, a second delay value between the master device and the slave device; and a step of storing, by at least one processor, a second data pair including the second delay value and the first offset value in the memory.

[0011] Additionally, the second delay value can be derived based on a delay request by the slave device to the master device and a delay response by the master device to the slave device.

[0012] Additionally, the first delay value may be the smallest value among a plurality of delay values ​​stored in the memory.

[0013] Additionally, the memory includes a plurality of windows for storing data pairs, and the second data pair can be stored in any one of the plurality of windows in which no data pair is stored.

[0014] Additionally, if there is no window among the plurality of windows in which a data pair is not stored, the second data pair may be stored to replace the data pair stored in the window that stored the oldest data pair.

[0015] Additionally, the memory can store multiple data pairs derived from the time synchronization process.

[0016] Additionally, the number of the plurality of data pairs stored in the memory can be determined based on administrator settings.

[0017] Additionally, the step of performing time synchronization for the slave device may include the step of generating a synchronization signal based on the first offset value.

[0018] In an electronic device performing time synchronization according to an embodiment of the present disclosure, the electronic device includes a transceiver, a memory storing instructions, and at least one processor, and the at least one processor connected to the transceiver and the memory can identify a synchronization message received from a master device, call a first data pair including a first delay value and a first offset value stored in the memory in response to the synchronization message, perform time synchronization for a slave device based on the first offset value, identify a second delay value between the master device and the slave device, and store a second data pair including the second delay value and the first offset value in the memory.

[0019] A computer program stored in a computer-readable storage medium according to an embodiment of the present disclosure, wherein the computer program, when executed on at least one processor, performs the following operations to perform time synchronization, wherein the operations may include: checking a synchronization message received from a master device; calling a first data pair including a first delay value and a first offset value stored in a memory in response to the synchronization message; performing time synchronization for a slave device based on the first offset value; checking a second delay value between the master device and the slave device; and storing a second data pair including the second delay value and the first offset value in the memory.

[0020] According to the present disclosure, by performing time synchronization by excluding specific packets from synchronization in response to an unstable network environment, the accuracy of synchronization between a master device and a slave device can be maintained even when a sudden network delay occurs.

[0021] The effects according to the present disclosure are not limited to the effects described above, and other effects not mentioned will be clearly understood by those skilled in the art from the description below.

[0022] FIG. 1 is a block diagram illustrating a network system according to an embodiment of the present disclosure.

[0023] FIG. 2 is a block diagram illustrating the configuration of an electronic device according to an embodiment of the present disclosure.

[0024] FIG. 3 is a drawing for explaining an operation method of an electronic device according to an embodiment of the present disclosure.

[0025] FIG. 4 is a flowchart for explaining an operation method of an electronic device according to an embodiment of the present disclosure.

[0026] Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the contents described in the attached drawings. However, the present invention is not limited or restricted by the exemplary embodiments. Unless otherwise defined, all terms (including technical and scientific terms) used in this specification shall be used with meanings that can be commonly understood by those of ordinary skill in the technical field to which this disclosure pertains. However, this may vary depending on the intentions of those skilled in the art, precedents, the emergence of new technologies, etc.

[0027] Additionally, terms defined in commonly used dictionaries should not be interpreted ideally or excessively unless explicitly and specifically defined otherwise. In certain cases, terms may be arbitrarily selected by the applicant, in which case their meanings will be described in detail in the relevant description. Therefore, the terms used in this disclosure should be defined based on their meaning and the overall content of this disclosure, rather than simply their names.

[0028] Throughout this specification, when a part is said to "include" a certain component, this does not mean that other components may be included, but rather that other components may be excluded, unless specifically stated otherwise. Furthermore, the singular forms used herein also include plural forms unless specifically stated otherwise. Furthermore, the expression "at least one of a, b, and / or c" used throughout this specification can encompass "a alone," "b alone," "c alone," "a and b," "a and c," "b and c," or "all of a, b, and c."

[0029] Meanwhile, terms such as "first and / or second" used in this specification may be used to describe various components, but are only used to distinguish one component from another and are not intended to be limited to the components referred to by those terms. For example, without departing from the scope of the present invention, the first component may be referred to as the second component, and the second component may also be referred to as the first component.

[0030] In addition, terms such as “unit”, “module”, etc. described in this specification mean a unit that processes at least one function or operation, which may be implemented by hardware or software, or a combination of hardware and software. In addition, embodiments of the present disclosure in this specification may be represented by functional block configurations and various processing steps. These functional blocks may be implemented by various numbers of hardware or / and software configurations that execute specific functions. For example, embodiments of the present disclosure may employ direct circuit configurations such as memory, processing, logic, look-up tables, etc. that may execute various functions under the control of one or more microprocessors or other control devices.

[0031] Similar to the components disclosed herein that can be implemented as software programs or software elements, embodiments of the present disclosure may be implemented in a programming or scripting language such as C, C++, Java, assembler, etc., including various algorithms implemented as a combination of data structures, processes, routines, or other programming constructs. Functional aspects may be implemented as algorithms that run on one or more processors. Furthermore, the present embodiments may employ conventional techniques for at least one of electronic configuration, signal processing, and data processing. Terms such as “mechanism,” “element,” “means,” and “configuration” may be used broadly and are not limited to mechanical and physical components. The terms may include the meaning of a series of software routines in connection with a processor, etc.

[0032] Each block of the processing flow diagrams attached to this specification and combinations of the flow diagrams can be performed by computer program instructions. These computer program instructions can be installed in a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing equipment, so that the instructions, when executed by the processor of the computer or other programmable data processing equipment, create a means for performing the functions described in the flow diagram block(s).

[0033] These computer program instructions may be stored in a computer-available or computer-readable memory that can direct a computer or other programmable data processing device to implement a function in a particular manner, and the instructions stored in the computer-available or computer-readable memory may also produce an article of manufacture that includes instruction means for performing the function described in the flowchart block(s).

[0034] Since the computer program instructions may be installed on a computer or other programmable data processing device, a series of operational steps may be performed on the computer or other programmable data processing device to create a computer-executable process, and the instructions that cause the computer or other programmable data processing device to perform the steps for performing the functions described in the flowchart block(s) may also provide steps for performing the functions described in the flowchart block(s).

[0035] Additionally, each block may represent a module, segment, or portion of code that contains one or more executable instructions for performing a specific logical function(s). Furthermore, in some alternative implementation examples, the functions described in the blocks may occur out of order. For example, two blocks depicted in succession may actually be executed substantially concurrently, or the blocks may sometimes be executed in reverse order, depending on their respective functions.

[0036] The "electronic device" or "terminal" referred to herein may be implemented as a computer or portable terminal capable of connecting to a server or other terminal via a network. Here, the computer includes, for example, a notebook, desktop, or laptop equipped with a web browser, and the portable terminal may include, for example, a wireless communication device that ensures portability and mobility, such as a communication-based terminal such as IMT (International Mobile Telecommunication), CDMA (Code Division Multiple Access), W-CDMA (W-Code Division Multiple Access), LTE (Long Term Evolution), and all types of handheld-based wireless communication devices such as smartphones and tablet PCs. In addition, the "electronic device" or "terminal" referred to herein may also include a processor, a memory that stores and executes program data, permanent storage such as a disk drive, a communication port that communicates with an external device, a user interface device such as a touch panel, a key, a button, etc.

[0037] In the present disclosure, methods implemented as software modules or algorithms may be stored on a computer-readable recording medium as computer-readable codes or program instructions executable on a processor. Here, the computer-readable recording medium may include a magnetic storage medium (e.g., read-only memory (ROM), random-access memory (RAM), floppy disks, hard disks, etc.) and an optical reading medium (e.g., CD-ROM, DVD: Digital Versatile Disc)). The computer-readable recording medium may be distributed and executed on network-connected computer systems.

[0038] Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. In describing the embodiments, descriptions of technical details that are well known in the technical field to which the present invention pertains and are not directly related to the present invention will be omitted. This is to convey the gist of the present invention more clearly without obscuring unnecessary explanation. For the same reason, some components in the accompanying drawings are exaggerated, omitted, or schematically depicted. Furthermore, the size of each component does not entirely reflect the actual size. Throughout this specification, the same reference numerals may refer to the same or corresponding components.

[0039] FIG. 1 is a block diagram illustrating a network system (10) according to an embodiment of the present disclosure.

[0040] Referring to FIG. 1, a network system (10) according to an embodiment of the present disclosure may include a master device (110) and a slave device (120).

[0041] In a network system (10) according to an embodiment of the present disclosure, a master device (110) and a slave device (120) can communicate with each other through a network and exchange information. Each of the master device (110) and the slave device (120) illustrated in FIG. 1 may include a transceiver, a memory, and a processor. In addition, each of the master device (110) and the slave device (120) refers to a unit that processes at least one function or operation, which may be implemented by hardware, software, or a combination of hardware and software. According to an embodiment, each of the master device (110) and the slave device (120) may include a plurality of computer systems or computer software implemented as network servers.

[0042] For example, at least some of the master device (110) and the slave devices (120) may refer to a computer system and computer software that are connected to a subordinate device that can communicate with another network server through a computer network such as an intranet or the Internet, obtain a task execution request, perform the task accordingly, and provide the execution result. In addition, at least some of the master device (110) and the slave devices (120) may be understood as a broad concept that includes a series of application programs that can operate on a network server and various databases built inside. For example, at least some of the master device (110) and the slave devices (120) may be implemented using a network server program that is variously provided according to an operating system such as DOS, Windows, Linux, Unix, or MacOS.

[0043] A network system (10) according to an embodiment of the present disclosure may be a system that complies with the IEEE 1588 PTP (Precision Time Protocol) standard, and specifically, may be a Linux-based PTP system. According to an embodiment of the present disclosure, a master device (110) may use time (clock) information acquired based on a Global Positioning System (GPS) or a reference clock source as a reference clock of the network system (10). The master device (110) may transmit time information acquired based on the GPS or a reference clock source to a slave device (120).

[0044] Meanwhile, the slave device (120) according to the embodiment of the present disclosure is a device dependent on the master device (110) and can synchronize its internal time (local clock) based on time information transmitted from the master device (110). In a PTP environment, the slave device (120) can perform synchronization between the master device (110) and the slave device (120) using network packets.

[0045] In a typical synchronization process, the master device (110) sends a synchronization message (M sync ) can be transmitted to the slave device (120). A synchronization message (M sync ) is a synchronization message (M) from the master device (110). sync ) may include first time information (t1) corresponding to the departure time. Alternatively, the master device (110) may include a synchronization message (M sync ) can transmit a follow-up message including the first time information (t1) to the slave device (120). The slave device (120) can transmit a synchronization message (M) from the master device (110).sync ) can be recorded as second time information (t2) corresponding to the time at which the signal was received.

[0046] Synchronization Message (M sync ) is received, the slave device (120) sends a delay request message (D) to the master device (110). req ) can be transmitted. The master device (110) sends a delay request message (D req ) to the slave device (120) in response to the delay response message (D res ) can be transmitted. The slave device (120) can calculate third time information (t3) corresponding to the time taken for the packet to reach the slave device (120) from the master device (110) based on the delay request and response, and the third time information (t3) can mean a delay value. The slave device (120) can calculate an offset based on the first to third time information (t1, t2, t3), determine a time speed based on the offset of the current time and the offset of the past time, and correct the time of the slave device (120) by reflecting the determined time speed.

[0047] However, according to the synchronization process according to the above-described process, if the second time information (t2) increases due to a sudden network delay, a problem occurs in which the offset increases as it is, and the third time information (t3) temporarily increases greatly, which may cause a significant error in offset calculation, and as a result, a situation in which the time difference between the master device (110) and the slave device (120) becomes even larger may occur. Therefore, the present disclosure proposes a synchronization method to solve such a problem, and according to the present disclosure, the network system (10) performs time synchronization by excluding a specific packet from synchronization in an unstable network environment, thereby maintaining the accuracy of synchronization between the master device (110) and the slave device (120) even when a sudden network delay occurs. A synchronization performing method according to an embodiment of the present disclosure will be described in detail with reference to FIGS. 2 to 4 to be described later.

[0048] Meanwhile, in FIG. 1, one master device (110) and one slave device (120) are illustrated as corresponding to each other, but this is only one embodiment and does not limit the configuration of the network system (10) according to the present disclosure. For example, the network system (10) according to the present disclosure may include a plurality of slave devices (120) corresponding to one master device (110).

[0049] FIG. 2 is a block diagram for explaining the configuration of an electronic device (200) according to an embodiment of the present disclosure.

[0050] The electronic device (200) illustrated in FIG. 2 only illustrates components related to embodiments according to the present disclosure, and it will be apparent to those skilled in the art that the electronic device (200) may further include other general components in addition to the components illustrated in FIG. 2. In the embodiment, the electronic device (200) may be included in a slave device (120, see FIG. 1) and perform an operation for time synchronization between the master device (110, see FIG. 1) and the slave device (120).

[0051] Referring to FIG. 2, an electronic device (200) according to an embodiment of the present disclosure may include a transceiver (210), a processor (220), and a memory (230). In FIG. 2, the electronic device (200) according to an embodiment of the present disclosure is illustrated as including one processor (220) and one memory (230), but this is merely for convenience of explanation and does not limit the configuration of the electronic device (200) according to the present disclosure. An electronic device (200) according to another embodiment of the present disclosure may include a plurality of processors (220) or a plurality of memories (230). Meanwhile, in FIG. 2, the processor (220) and the memory (230) are illustrated as separate configurations, but this is merely an embodiment, and each of the processor (220) and the memory (230) may be configured as separate chips or may be configured as a single chip.

[0052] According to an embodiment of the present disclosure, an electronic device (200) is connected to a master device (110) via a transceiver (210) and can exchange data.

[0053] The processor (220) may perform an operation performed by at least one device according to an embodiment of the present disclosure, or may perform at least one method according to an embodiment of the present disclosure. In addition, the processor (220) may execute a program for performing an operation performed by at least one device according to an embodiment of the present disclosure or a program for performing at least one method according to an embodiment of the present disclosure, and may process information and control the electronic device (200) to perform an operation performed by at least one device according to an embodiment of the present disclosure or at least one method according to an embodiment of the present disclosure. In an embodiment, the processor (220) may be implemented as a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), an AP (Application Processor), or the like included in the electronic device (200), but is not limited thereto. Operations performed by the processor (220) according to an embodiment of the present disclosure will be described in detail with reference to FIGS. 3 and 4 described below.

[0054] The memory (230) may store at least a portion of data supporting various functions of the electronic device (200), data being processed, and data input / output to / from the electronic device (200). In addition, the memory (230) may store at least a portion of application programs, drivers, program codes, and commands driven by the electronic device (200). In an embodiment, the application programs may be downloaded from an external server via wireless communication.

[0055] In an embodiment, the memory (230) may include at least one of volatile memory and non-volatile memory, and as a specific example, the memory (230) may include at least one of flash memory, a hard disk, a solid state disk (SDD), random access memory (RAM), static random access memory (SRAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), programmable read-only memory (PROM), magnetic memory, magnetic disk, and optical disk, but is not limited thereto. In addition, in some embodiments, the memory (230) may be implemented as a database that is separate from the electronic device (200) but is connected by wire or wirelessly.

[0056] FIG. 3 is a drawing for explaining an operation method of an electronic device (200, see FIG. 2) according to an embodiment of the present disclosure.

[0057] Referring to FIG. 3, the electronic device (200) may include a control unit (310), a storage unit (320), and a clock (330). The control unit (310) may include a filter unit (311), and the storage unit (320) may include first to n-th windows (321_1, 321_2, , 321_n).

[0058] In an embodiment, the control unit (310) may be implemented as the processor (220, see FIG. 2) of the above-described FIG. 2, and may perform time synchronization of the slave device (120, see FIG. 1) in response to the reference time of the master device (110, see FIG. 1) according to an embodiment of the present disclosure. The filter unit (311) included in the control unit (310) may derive an offset for performing time synchronization in response to the reference time of the master device (110).

[0059] In an embodiment, the storage unit (320) may be implemented as a memory (230, see FIG. 2) of the above-described FIG. 2, and may store data processed by the electronic device (200) for time synchronization according to an embodiment of the present disclosure. In an embodiment, each of the first to n-th windows (321_1, 321_2, , 321_n) included in the storage unit (320) may mean a space in which data processed by the electronic device (200) is stored, and data processed by the electronic device (200) for time synchronization may be stored in any one of the first to n-th windows (321_1, 321_2, , 321_n) according to a set rule. Here, n may be a natural number greater than or equal to 1, and may be determined according to an administrator's setting.

[0060] Meanwhile, in the embodiment, the clock (330) can generate or output a synchronization signal synchronized in response to the reference time of the master device (110) under the control of the control unit (310), and specifically, the control unit (310) can control the clock (330) to generate or output a synchronization signal from the clock (330) based on an offset derived from the filter unit (311).

[0061] In a time synchronization process by an electronic device (200) according to an embodiment of the present disclosure, the delay and offset derived by the filter unit (311) may be stored in each of the first to n-th windows (321_1, 321_2, , 321_n) included in the storage unit (320) according to a predetermined rule. In one embodiment, the most recent n delays and offsets derived in a previous time synchronization process may be stored in each of the first to n-th windows (321_1, 321_2, , 321_n). Hereinafter, for the convenience of explanation, it will be explained on the assumption that the most recent n delay and offset pairs derived from the previous time synchronization process are already stored in each of the first to nth windows (321_1, 321_2, , 321_n), and the delay stored in the nth window will be referred to as the nth delay, the offset stored in the nth window will be referred to as the nth offset, and the delay and offset pair stored in the nth window will be referred to as the nth pair.

[0062] According to an embodiment of the present disclosure, an electronic device (200) receives a synchronization message (M) from a master device (110) to a slave device (120). sync , see Fig. 1) can be confirmed, and the filter unit (311) can be used to check the synchronization message (M sync ) can be used to derive an offset for performing time synchronization in response to the reception of the signal. To derive the offset, the filter unit (311) can call the delay stored in the storage unit (320), and the filter unit (311) can call the smallest delay among the delays stored in the storage unit (320). The filter unit (311) can call the smallest delay from the storage unit (320) and also call an offset paired with the smallest delay. The control unit (310) can control the clock (330) so that the clock (330) generates or outputs a synchronization signal based on the called offset.

[0063] For example, in one embodiment, if the delay stored in the second window among the first to nth windows (321_1, 321_2, , 321_n) is the smallest delay, the filter unit (311) can call the second pair (including the second delay and the second offset) stored in the second window from the storage unit (320), and the control unit (310) can perform time synchronization based on the called second offset.

[0064] Meanwhile, according to an embodiment of the present disclosure, a synchronization message (M sync ) is received, the slave device (120) sends a delay request message (D) to the master device (110). req , see Fig. 1) can be transmitted, and a delay request message (D) from the master device (110) req ) corresponding to the delay response message (D res , see Fig. 1). In the delay request and response process, the control unit (310) can check a new delay value, and store a pair including the checked new delay value and the offset value derived from the above-described process in any one of the first to n-th windows (321_1, 321_2, , 321_n). In one embodiment, if there is at least one data stored in each of the first to n-th windows (321_1, 321_2, , 321_n), a pair including the new delay value and the offset value derived from the above-described process can be stored by replacing the oldest data among the data stored in the existing first to n-th windows (321_1, 321_2, , 321_n).

[0065] For example, if the first pair is stored in the first window (321_1), the second pair is stored in the second window (321_2), and the n-th pair is stored in the n-th window (321_n), and the first to n-th pairs are stored in the first to n-th windows (321_1, 321_2, , 321_n), and the data stored in the first window corresponds to the oldest data, and an n+1-th pair including a new delay value and an offset value derived in the above-described process is derived, the control unit (310) can delete the first pair stored in the first window and store the newly derived n+1-th pair.

[0066] Through the above-described process, the electronic device (200) can perform time synchronization of the slave device (120), and by using an offset in the case where the delay is small during the synchronization process for synchronization, the time error that may occur between the master device (110) and the slave device (120) can be minimized.

[0067] FIG. 4 is a flowchart for explaining an operation method of an electronic device (200, see FIG. 2) according to an embodiment of the present disclosure.

[0068] At step S410, the electronic device (200) according to an embodiment of the present disclosure can receive a synchronization message from a master device (110, see FIG. 1).

[0069] In step S420, the electronic device (200) according to an embodiment of the present disclosure may call a data pair including a stored delay value in response to the synchronization message received in step S410. In an embodiment, the called delay value may be determined based on a pre-stored criterion, and in one embodiment, a data pair including a delay value having a smallest value may be called.

[0070] In step S430, the electronic device (200) according to an embodiment of the present disclosure may perform time synchronization based on the offset value included in the data pair called in step S420. In the embodiment, the electronic device (200) may generate or output a synchronization signal based on the derived offset value.

[0071] Meanwhile, at step S440, the electronic device (200) according to an embodiment of the present disclosure may determine a new delay value. In the embodiment, the electronic device (200) may transmit a delay request message to the master device (110) and receive a delay request message from the master device (110). The new delay value may be derived during the delay request and response process.

[0072] In step S450, the electronic device (200) according to the embodiment of the present disclosure can store a new data pair including the offset value used for synchronization in step S430 and the new delay value identified in step S440. In the embodiment, the new data pair can be stored in any one of the first to nth windows (321_1, 321_2, , 321_n, see FIG. 3), and if there are data pairs stored in all of the first to nth windows (321_1, 321_2, , 321_n), the new data pair can be stored by replacing the oldest data pair.

[0073] The above-described embodiments are specific examples for implementing the present disclosure. The present disclosure will encompass not only the above-described embodiments, but also embodiments that can be simply designed or easily modified. Furthermore, the present disclosure will encompass techniques that can be easily modified and implemented using the above-described embodiments. Therefore, the scope of the present disclosure should not be limited to the above-described embodiments, but should be defined not only by the claims set forth below, but also by equivalents of the claims of the present disclosure.

Claims

1. In a method of operation by an electronic device performing time synchronization, A step of verifying, by at least one processor, a synchronization message received from a master device; A step of calling, by at least one processor, a first data pair including a first delay value and a first offset value stored in a memory in response to the synchronization message; A step of performing time synchronization for a slave device based on the first offset value, by at least one processor; A step of determining a second delay value between the master device and the slave device by at least one processor; and A method of operation comprising the step of storing, by at least one processor, a second data pair including the second delay value and the first offset value in the memory.

2. In paragraph 1, The method of operation wherein the second delay value is derived based on a delay request by the slave device to the master device and a delay response by the master device to the slave device.

3. In paragraph 1, An operating method wherein the first delay value is the smallest value among a plurality of delay values ​​stored in the memory.

4. In paragraph 1, The above memory includes a plurality of windows for storing data pairs, An operating method in which the second data pair is stored in one of the plurality of windows in which no data pair is stored.

5. In paragraph 4, An operating method in which, if there is no window among the above multiple windows in which a data pair is not stored, the second data pair is stored to replace the data pair stored in the window that stored the oldest data pair.

6. In paragraph 1, The above memory is an operating method for storing a plurality of data pairs derived from the above time synchronization process.

7. In paragraph 6, An operating method in which the number of said plurality of data pairs stored in said memory is determined based on an administrator setting.

8. In paragraph 1, A method of operation, wherein the step of performing time synchronization for the slave device includes the step of generating a synchronization signal based on the first offset value.

9. In an electronic device that performs time synchronization, comprising a transceiver, a memory storing instructions, and at least one processor; At least one processor coupled to the transceiver and the memory: Check the synchronization message received from the master device, In response to the above synchronization message, a first data pair including a first delay value and a first offset value stored in the memory is called, Perform time synchronization for the slave device based on the first offset value above, Check the second delay value between the above master device and the above slave device, An electronic device storing a second data pair including the second delay value and the first offset value in the memory.

10. A computer program stored in a computer-readable storage medium, wherein the computer program, when executed on at least one processor, performs the following operations to perform time synchronization, the operations being: An action to verify a synchronization message received from a master device; An operation of calling a first data pair including a first delay value and a first offset value stored in memory in response to the above synchronization message; An operation for performing time synchronization for a slave device based on the first offset value; An operation of checking a second delay value between the master device and the slave device; and A computer program stored in a computer-readable storage medium, comprising an operation of storing a second data pair including the second delay value and the first offset value in the memory.

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