High-bandwidth memory having bridge-integrated logic die and package applying same

Abstract

The present invention relates to a heterogeneously integrated package in which a high-bandwidth memory and a process chip using same are mounted, the heterogeneously integrated package comprising: a package substrate; a logic die which is located on the package substrate and includes a companion physical layer for a high-bandwidth memory; a process chip which is located on the logic die while being electrically connected via the logic die, and includes a physical layer corresponding to the companion physical layer; and a memory package including two or more memory dies, wherein the logic die includes high-speed interconnects which connect the physical layer and the companion physical layer without a through-silicon via and have a length of 4 millimeters or shorter.

Description

High-bandwidth memory with bridge-integrated logic die and package applying the same

[0001] The present invention relates to a high-bandwidth memory (hereinafter referred to as 'HBM') and a processor chip, etc., which are integrated into a single package in a 2.5-dimensional (2.5D) or 3-dimensional (3D) heterogeneously integrated package, which improves high-speed signal transmission characteristics, and structures of a heterogeneously integrated package employing the HBM.

[0002] With the advent of the data-centric era, demand for high-performance and high-capacity memory solutions is increasing, and HBM is positioned as a key technology driving this trend. With its high bandwidth and low power consumption, HBM can significantly improve the speed and efficiency of data processing in fields such as artificial intelligence, big data analytics, autonomous vehicles, and scientific research, which require large-scale data processing and high-performance computing. HBM can provide high bandwidth thanks to its numerous data input / output pins (typically formed with bumps for bonding), which number in the thousands (1,024 for HBM3E and 2,048 for HBM4). However, in order to physically / electrically interconnect so many high-speed input / output pins for communication with the process chip, fine wiring (interconnect; hereinafter referred to as 'interconnect') is required, and for this purpose, 2.5-dimensional or 3-dimensional heterogeneous integration package technology that employs silicon-based interposers or bridges is commonly used.

[0003] Heterogeneous integrated packages (100a, 100b) employing HBM according to the prior art additionally use an intermediate substrate such as a silicon interposer (120) or a silicon bridge (130) to implement high-speed interconnects (126, 136) that electrically interconnect data input / output pins of a process chip (140) and an HBM package (150), as shown in the examples in FIGS. 1a and 1b. The prior HBM package (150) includes memory dies for HBM (Memory Dies; 151a to 151d) stacked in multiple layers; It is located below the above memory dies (151a to 151d), and may include circuits and wiring related to management of the above memory dies (151a to 151d), and is composed of a logic die (160) that can be called an HBM controller, including at least a communication function to the outside of the memory dies (151a to 151d) and the HBM package (150). Currently, DRAM is used as the memory die, and all of these are physically / electrically connected including through-silicon vias (152a to 152d, 162) and bonding (153a to 153d). Although the present invention is illustrated as a case where four HBM memory dies (151a to 151d) are applied, it is obvious that the same can be applied even when more than that (e.g., 16) HBM memory dies are stacked.

[0004] Communication between the process chip (140) and the HBM package (150) is performed by physical layers (commonly referred to as PHY) that handle physical aspects such as transmission, reception, and modulation of signals. Referring to FIGS. 1A and 1B, signal / data input / output is performed by the HBM physical layer (145) of the process chip (140) and the companion physical layer (165) in the HBM logic die (160) that constitutes the HBM package (150), and these are physically / electrically connected to each other by bonding (147, 167) of the two chips (140, 160) and high-speed interconnects (126, 136) in the silicon interposer (120) or bridge (130).

[0005] The number of conductors including through-electrodes (152a to 152d, 162) and bondings (153a to 153d) connecting the companion physical layer (165) of the logic die for HBM and the memory dies for HBM (151a to 151d) stacked on the logic die is a multiple of the number of high-speed interconnects (126, 136) on the interposer (120) or the bridge (130). This is because, by using a serializer / deserializer circuit in the companion physical layer (165) of the logic die for HBM, the signal transmission speed between them can be slowed down by an inverse multiple to maintain the same bandwidth compared to the multiple of increasing the number of connections between the companion physical layer (165) and the respective memory dies for HBM (151a to 151d). By doing this, the burden of having to drive each memory die (151a to 151d) at high speed can be reduced, while also alleviating the signal integrity problem caused by the increase in load (typically capacitive loading) due to connecting multiple memory dies (151a to 151d) for HBM together for high capacity. For example, assuming that the high-speed interconnects (126, 136) within the interposer (120) or bridge (130), that is, the physical layer (145) for HBM of the process chip and the companion physical layer (165) of the logic die for HBM are interconnected by 1,024 high-speed interconnects (126, 136) for data input / output and operate at a speed of 6.4 gigabits per second (Gbps), assuming that an HBM package (150) in which eight memory dies for HBM are stacked is used, the number of data input / output wires between the companion physical layer (165) of the logic die for HBM and the memory dies for HBM (151a to 151h) is 4,096, which is a multiple of 4, and the digital signal on the wires operates at a speed of 1.6 Gbps, which is a multiple of 1 / 4. At this time, the structure is such that two memory dies for HBM are connected to each of the 4,096 wires.

[0006] The length of high-speed interconnects (126, 136) for data communication between the process chip (140) and the HBM package (150) is standardized at 5 millimeters (mm) due to the physical structure of the heterogeneous integrated package. However, in order to implement more than 1,000 interconnects (126, 136) on the interposer (120) or bridge (130), a small size (dimension) is required, and the high electrical resistance (resistance or impedance) of the interconnect due to this makes it difficult to transmit high-speed signals. For example, in the case of a copper wire having a cross-sectional area of ​​1 square micrometer (1 ㎛ × 1 ㎛) and a length of 5 millimeters, the direct current resistance alone reaches 86 ohms (Ohm) or more. Considering the electrical resistance caused by the metallic skin effect at high frequencies and the electrical resistance of the current return path required for digital signal transmission, actual operation requires significantly higher electrical resistance. This high electrical resistance causes loss and reflection of high-speed signals, exacerbating signal integrity issues. The resulting degradation in data transmission reliability and performance can make high-speed operation of HBM impossible.

[0007] FIG. 2 is an example illustrating the transmission characteristics of a digital signal transmitted through an example of a conventional high-speed interconnect (126, 136) having a length of 5 mm implemented on an interposer (120) or a bridge (130) of FIG. 1 in the form of an eye diagram. FIG. 2a shows a case where a digital signal of 6.4 Gbps is transmitted, and FIG. 2b shows a case where a digital signal is transmitted at twice that speed. However, when the eye mask (210) standard illustrated in FIG. 2a is applied, FIG. 2b shows that operation is impossible because the input voltage level is not secured. This means that as the speed of the digital signal increases, the signal transmission characteristics deteriorate rapidly due to the loss characteristics caused by the high electrical resistance of the high-speed interconnect (126, 136).

[0008] Accordingly, the technical problem to be achieved in the present invention is to overcome the signal integrity problem caused by signal attenuation due to the small cross-sectional size (fine interconnect dimension) of many interconnects on an interposer or bridge in a heterogeneous integrated package for high bandwidth memory (HBM), thereby providing a structure of a high bandwidth memory capable of high-speed signal transmission, i.e., high-speed operation, and a heterogeneous integrated package employing the same.

[0009] In order to achieve the above-described technical task, the high bandwidth memory (HBM) and the package employing the same according to the embodiment of the present invention are configured as a heterogeneous integrated package in which the logic die for HBM is also used as a silicon bridge to form many high-speed data input / output interconnects with the process chip, thereby reducing the length of the high-speed interconnect connecting the physical layer for HBM of the process chip and the companion physical layer of the logic die for HBM, thereby improving the signal transmission characteristics. The reduction in the length of the fine interconnect with high electrical resistance has the advantage of not only improving signal integrity, but also reducing the propagation delay of the electrical signal (which increases proportionally to the square of the distance in wiring with high electrical resistance) and reducing the input / output power consumption.

[0010] In the cross-sectional structure of the heterogeneous integrated package according to the present invention, the logic die for HBM is positioned where the conventional silicon bridge was, and a memory package composed only of memory dies for HBM without the logic die is positioned side-by-side adjacent to the side of the process chip. Accordingly, by utilizing the extra height corresponding to the sum of the thickness of the logic die protruding to the outside and its bonding, the number of memory dies for HBM that can be stacked within the same thickness as the process chip in which the silicon wafer itself is the maximum thickness, for the same package thickness required to connect a cooler, etc. to the top, can be increased. Alternatively, the extra height can be utilized to improve the thickness of the memory dies for HBM or their bonding method. It is self-evident that this can lead to a reduction in process cost, an improvement in yield, and an improvement in package reliability.

[0011] In the heterogeneous integrated package according to the present invention, the logic die for HBM can be independently positioned at the bottom like a bridge, and the circuit surface including the companion physical layer therein can be placed face-up. Therefore, since bonding with an intermediate substrate such as an interposer or a bridge for bonding to a process chip is not required, the total number of bonds can be halved, and since through-hole vias (TSVs) for connection with memory dies for HBM do not need to be formed within the logic die for HBM, further improvement of signal transmission characteristics and simplification of the manufacturing process of the logic die for HBM are achieved. In addition, the position of the companion physical layer within the logic die for HBM can be freely positioned according to the input / output operation speed of the companion physical layer and the required length of interconnects for connection with the HBM physical layer of the process chip.

[0012] In the HBM according to the present invention, since the signal transmission speed between the companion physical layer of the logic die for HBM and the memory dies for HBM can be several times slower than the signal transmission speed with the physical layer for HBM of the process chip (1 / 2 times, 1 / 4 times, 1 / 8 times, etc.), the connection length between them can be made longer. Accordingly, in order to improve the heat of the process chip with a higher temperature from deteriorating the memory, it is possible to widen the distance between the process chip and the memory package for HBM or to additionally implement a heat-blocking structure between them.

[0013] The heterogeneous integrated package according to the present invention separately positions a bridge-integrated logic die for high bandwidth memory (HBM) on a package substrate, and performs high-speed signal transmission between an HBM memory package composed only of a process chip and memory dies connected thereon through the HBM bridge-integrated logic die. At this time, since the accompanying physical layer can be freely positioned on the HBM bridge-integrated logic die, the length of the connection wiring (interconnect) between the process chip and the HBM physical layer can be made much shorter than the 5 millimeters standard for conventional HBM-employing heterogeneous integrated packages. Accordingly, high-speed signal transmission becomes possible even with fine interconnects having high electrical resistance per unit length. The ability to finely fabricate a large number of these high-speed interconnects, more than a thousand in number, through a method such as a semiconductor silicon process (Fabrication) can significantly reduce process time and cost. Furthermore, as the logic die is moved to the outside of HBM, which stacks memory dies to create a package within a certain thickness for high capacity, the extra height space can be utilized to stack more memory dies to create higher-capacity memory, or to adjust the thickness of each memory die or the bonding method between them, thereby reducing costs and increasing yield. Furthermore, thermal management can be more effective by increasing the distance between the process chip and the memory package or installing structures that reduce heat transfer while maintaining high-speed characteristics.

[0014] FIG. 1a and FIG. 1b are cross-sectional views conceptually illustrating heterogeneous integrated packages employing high bandwidth memory (HBM) according to the prior art, and illustrate examples in which a silicon interposer and a bridge are used, respectively, to implement high-speed interconnects for data input / output between the physical layer for HBM of a process chip and the companion physical layer of the logic die for HBM.

[0015] Figures 2a and 2b illustrate, in eye diagram form, the results of transmitting digital signals of 6.4 gigabits per second (Gbps) and 12.8 Gbps, respectively, through an example of the high-speed interconnect of Figure 1 having a length of 5 millimeters.

[0016] FIGS. 3A to 3C are cross-sectional views conceptually illustrating heterogeneous integrated packages employing high-bandwidth memory having a bridge-integrated logic die according to embodiments of the present invention.

[0017] FIG. 4 is a cross-sectional view conceptually illustrating the structure of a heterogeneous integrated package employing a cooler as another embodiment employing the high-bandwidth memory structure of the present invention.

[0018] FIG. 5a is an eye diagram illustrating the result of transmitting a 12.8 Gbps digital signal in a 3-millimeter-long interconnect connecting a companion physical layer on a bridge-integrated logic die of the present invention and a physical layer of a process chip for a high-speed interconnect having the same electrical characteristics per unit length as FIG. 2, and FIG. 5b is an eye diagram illustrating the result of transmitting a 3.2 Gbps digital signal in an example of a 6-millimeter-long interconnect connecting the companion physical layer and two memory dies for high-bandwidth memory.

[0019] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the attached drawings. For convenience of understanding and simplification of diagrams, the present invention is illustrated and described based on a case where four memory dies for HBM are stacked. However, this is not meant to be limiting, and memory devices other than DRAM may also be used for the HBM memory. The embodiments introduced in the present invention are intended to complete the disclosed content in an implementable form and sufficiently convey the spirit of the present invention to those skilled in the art. In the drawings, the thickness of each region is exaggerated for clarity, and like reference numerals represent like components throughout the specification.

[0020] FIGS. 3a to 3c conceptually illustrate the structure of heterogeneous integrated packages (300a to 300c) employing high bandwidth memory (HBM) according to an embodiment of the present invention. FIGS. 3a and 3b are examples in which the positions of the companion physical layer (365) on the bridge-integrated logic die (360a, 360b) for HBM of the present invention are different, and FIG. 3c is an example in which the size of the bridge-integrated logic die (300c) for HBM of the present invention and the connection structure with the upper HBM memory package (350) are different. The heterogeneous integrated package (300a to 300c) employing the HBM of the present invention has the logic die (360a to 360c) for HBM positioned on the side of the package substrate (310) separately from the memory dies (351a to 351d) for HBM, and also serves as a bridge (130) for physical / electrical connection with the process chip (140).

[0021] In the bridge-integrated logic die (360a to 360c) for HBM of the present invention, the active surface including the circuits including the companion physical layer (365) can be positioned facing upward. Therefore, referring to FIGS. 3a and 3c, the connection between the HBM physical layer (145) of the process chip and the corresponding HBM companion physical layer (365) can be formed by a high-speed interconnect (366) and bonding (147) formed on the bridge-integrated logic die (360a, 360c). That is, since the logic die (360a to 360c) also provides the function of a bridge, the bonding (167) of the logic die for connection with the interposer (120) or bridge (130) as illustrated in FIG. 1 is eliminated, and thus, in the connection between the companion physical layer (365) of the logic die (360a to 360c) for HBM and the memory dies (351a to 351d) for HBM, there is no need to form through-electrodes (162) as illustrated in FIG. 1 inside the logic die (360a to 360c). This significantly reduces the number of through-electrodes that need to be manufactured compared to the conventional structures illustrated in FIG. 1.

[0022] In embodiments of the present invention, the memory dies (351a to 351d) for HBM are positioned and connected side-by-side to the process chip (140) in the form of a memory package (350) without a logic die, using the bridge-integrated logic dies (360a to 360c) at the bottom as a medium. Accordingly, by stacking more memory dies (351a to 351d) for HBM in the vertical space provided by the logic dies being omitted within the memory package (350) of the same thickness, a larger memory capacity can be secured, or the thickness of the memory dies and the bonding method and height (353a to 353d) can be appropriately selected to reduce process costs or improve yield.

[0023] The position of the companion physical layer (365) on the bridge-integrated logic die (360a to 360c) for HBM is free. Therefore, it is possible to position the companion physical layer (365) and the physical layer (145) for HBM of the process chip closely together so that their connection length is shorter than the conventional 5 millimeters (mm). That is, if the length of the high-speed interconnect (366) between these physical layers (145, 365) in FIG. 3a is reduced, the electrical resistance value also decreases, improving the high-speed signal transmission characteristics. This reduction in electrical resistance due to the reduction in the length of the high-resistive high-speed interconnect (366) has the advantage of reducing the propagation delay proportional to the square of the length and also reducing the operating power consumption of the physical layers (145, 365). FIG. 3b is an example in which a companion physical layer (365) of a bridge-integrated logic die (360b) for HBM is connected to a physical layer (145) for HBM of a process chip, and the connection length between the two physical layers (145, 365) is minimized by the length of wiring (not shown) inside the physical layers (145, 365) and the bonding (147) between them, so that the signal transmission speed and quality between these physical layers (145, 365) can be optimized.

[0024] FIG. 5a is an eye diagram illustrating the results of transmitting a 12.8 Gbps digital signal when the length of a high-speed interconnect (366) having the same electrical characteristics per unit length as FIG. 2, with respect to the embodiment of FIG. 3a or FIG. 3c, is reduced to 3 mm. Compared with FIG. 2b, which transmits a digital signal of the same speed at a length of 5 mm, the degree of improvement in the digital signal due to the reduction in the length of the high-speed interconnect (366) can be clearly seen.

[0025] In the embodiments of FIG. 3, the number of interconnects (364a to 364c) connected from the companion physical layer (365) to the memory package (350) for HBM on the bridge-integrated logic die (360a to 360c) for HBM may be a multiple of 2, 4, 8, or the like compared to the number of high-speed interconnects (366) or bondings (147) that interconnect the two physical layers (145, 365) for HBM. At this time, for the same amount of data to be transmitted, the signal transmission speed on the corresponding interconnects (364a to 364c) may be slower by an inverse multiple of 1 / 2, 1 / 4, 1 / 8, or the like compared to the signal transmission speed on the high-speed interconnects (366). As the signal transmission speed decreases, digital signal transmission becomes possible even with longer high-resistance interconnects (364a to 364c), as illustrated in FIG. 5b. FIG. 5b is an eye diagram illustrating the results of transmitting a digital signal at 3.2 Gbps in a structure in which two memory dies are connected to 6 mm interconnects (364a to 364c) in a multiple of 4, thereby increasing the capacitive loading.

[0026] Although not shown in the embodiments, between the companion physical layer (365) of the bridge-integrated logic die (360a to 360c) for HBM and the memory package (350) for HBM without the logic die, not only circuits and wirings related to the management of the memory dies (351a to 351d) in the memory package (350) for HBM without the logic die, but also a repeater circuit (a device that amplifies or regenerates an electrical signal, and compensates for the attenuation of the signal to extend the transmission distance of the signal or maintain the quality of the signal) may be further included. In order for the repeater circuit to be inserted into the interconnect area and used effectively to improve the quality degradation or propagation delay problem of the signal due to the interconnect being long or having high loss, it must be a small-area and simple circuit. The lower the speed of the digital signal transmitted on the interconnect, the simpler the circuit configuration is. Therefore, referring to FIG. 3, it is preferable that the repeater circuits be inserted and used in the relatively low-speed interconnect (364a to 364c) region between the companion physical layer (365) on the bridge-integrated logic die for HBM and the memory package (350) for HBM, rather than in the region of the high-speed interconnect (366).

[0027] In FIG. 3, the bridge-integrated logic die (360a to 360c) for HBM is positioned on the upper portion of the package substrate (310), which means that it can be embedded or surface mounted on the package substrate (310). When embedded, an additional metal wiring layer (not shown) can be formed on the bridge-integrated logic die (360a to 360c) for HBM through a manufacturing process of the package substrate (310) or a redistribution process. When surface-mounting on the package substrate (310), a dielectric material such as an epoxy mold compound (EMC) may be filled on the upper portion of the package substrate (310) and the side of the bridge-integrated logic die (360a to 360c) for HBM to ensure a flat surface on which the memory package (350) for HBM and the process chip (140) can be mounted. At this time, a metallic pillar or conductor penetrating the dielectric may be formed for direct electrical connection to the upper chips (140, 350) without going through the bridge-integrated logic die (360a to 360c) for HBM. This corresponds to the upper portion of the wirings (312, 314) that vertically connect the package substrate (310) in FIG. 3. In addition, a wide open hole can be dug in the package substrate (310), into which an integrated bridge logic die (360 to 360c) for HBM can be mounted and filled with a dielectric material to achieve planarization. In this case, there is an advantage in that the metallic pillars or conductors can be formed low or those made during the production of the package substrate (310) can be used as is.

[0028] In FIG. 3, between the bridge-integrated logic die (360a to 360c) for HBM and the package substrate (310), an electrical connection may be required for driving the circuits inside the bridge-integrated logic die (360a to 360c) for HBM and the memory package (350) for HBM and the process chip (140) or the physical layer (145) for HBM of the process chip. For this purpose, when the bridge-integrated logic die (360a to 360c) for HBM is embedded in the package substrate (310) and a metal wiring layer (not shown) is further formed on the upper side, electrical connection is possible through the metal wiring layer. However, for more stable operation, bondings (363, 369) and through-electrodes (362, 368) may be additionally formed and connected on the lower side of the bridge-integrated logic die (360a to 360c) for HBM. Some of these may be through-holes (362) and bondings (363) connected to provide power (Power / Ground) and signals for separate purposes to the memory package (350) for HBM and the process chip (140) or the physical layer (145) for HBM of the process chip, and others may be through-holes (368) and bondings (369) connected to provide power and signals for separate purposes to the bridge-integrated logic die (360a to 360c) for HBM.

[0029] Referring to FIG. 3c, some power and signals for separate purposes to the memory package (350) for HBM on the top may be provided directly through the wiring (314) of the package substrate (310) without passing through the bridge-integrated logic die (360c) for HBM.

[0030] FIG. 4 illustrates another embodiment in which the advantages of the present invention can be exerted. Typically, a process chip (140) using HBM consumes a large amount of power due to its high performance, so thermal management is very important. In fact, as illustrated in FIG. 4, cooling is performed in many ways, including water cooling methods (not illustrated) in addition to an air-cooling heat sink (480). It is obvious that such coolers can be applied to conventional structures such as the one illustrated in FIG. 1 and the embodiments of the present invention illustrated in FIG. 3. However, in a heterogeneous integrated package such as the present invention, it may also be important to reduce heat transfer from the process chip (140) at a higher temperature to the memory package (350) in order to reduce memory degradation. To this end, increasing the distance between the process chip (140) and the memory package (350) for HBM or forming a heat-blocking structure (490) between them (140, 350) as illustrated in FIG. 4 may be helpful. At this time, the increase in distance between the process chip and the memory package for HBM also increases the length of the high-speed interconnect (126, 136) between the physical layer (145) for HBM of the process chip and the companion physical layer (165) of the logic die for HBM in the conventional structures as in FIG. 1, which may deteriorate the high-speed signal transmission characteristics. On the other hand, in the present invention, since the companion physical layer (365) can be freely positioned on the bridge-integrated logic die (360a to 360c, 460) for HBM, even if the distance between the process chip (140) and the memory package for HBM without the logic die (350) increases as illustrated in FIG. 4, the length of the high-speed interconnect (466) can be made as short as necessary, 5 mm or less.

[0031] The embodiments of the present invention described above are disclosed for the purpose of illustration, and those skilled in the art will recognize that various modifications, changes, and additions can be made within the spirit and scope of the present invention, and such modifications, changes, and additions should be considered to fall within the scope of the present patent claims.

[0032] The present invention relates to a high-bandwidth memory that improves high-speed signal transmission characteristics in a 2.5D or 3D heterogeneous integrated package that integrates a high-bandwidth memory and a process chip into a single package, and structures of a heterogeneous integrated package employing the same.

[0033] The structures of the above high-bandwidth memory and the heterogeneous integrated package employing it can be applied to artificial intelligence, big data analysis, autonomous vehicles, and other scientific research and industrial fields that require large-scale data processing and high-performance computing.

Claims

1. In a heterogeneous integrated package in which a high bandwidth memory and a process chip using the same are mounted, Package substrate and; A logic die positioned on the upper side of the above package substrate and including a companion physical layer for high bandwidth memory; A memory package comprising a process chip including a physical layer corresponding to the companion physical layer, positioned on the logic die and electrically connected via the logic die, and two or more memory dies; A heterogeneous integrated package, wherein the logic die includes high-speed interconnects having a length of 4 millimeters or less, connecting the physical layer and the companion physical layer without a through electrode.

2. In paragraph 1, A heterogeneous integrated package wherein the logic die for high bandwidth memory further includes low-speed interconnects electrically connecting the companion physical layer and the memory package, wherein the low-speed interconnects are physically N times more numerous than the high-speed interconnects and the speed of a data signal transmitted can be 1 / N times slower. Here, N is a number greater than or equal to 2.

3. In paragraph 1, The above memory dies are heterogeneous integrated packages, which may be DRAM dies connected and stacked using through-hole electrodes.

4. In paragraph 1, A heterogeneous integrated package, wherein the logic die for high bandwidth memory may be embedded within the package substrate or mounted on the surface or within a hole of the package substrate.

5. In any one of paragraphs 1 to 4, A heterogeneous integrated package, wherein the logic die for high bandwidth memory may further include circuits therein and a through-electrode for supplying power, etc. to the memory package and at least a physical layer of the process chip.

6. In paragraph 1, A heterogeneous integrated package, wherein a cooler for heat dissipation may be further included above the above process chip and the above memory package, and a structure for blocking heat transfer from the above process chip to the above memory package may be further included between them.

7. In paragraph 1 or 2, A heterogeneous integrated package, wherein a circuit such as a repeater can be inserted into the low-speed interconnect area connecting the companion physical layer and the memory package on the logic die.

8. In a heterogeneous integrated package with high bandwidth memory and process chips, Package substrate and; A logic die positioned on the above package substrate and including a companion physical layer for high bandwidth memory; A memory package comprising a process chip including a physical layer corresponding to the companion physical layer above the logic die and two or more memory dies; A heterogeneous integrated package including the logic die, high-speed interconnects of 4 millimeters or less in length connecting the physical layer and the companion physical layer without a through-electrode, and low-speed interconnects connecting the companion physical layer and the memory package without a through-electrode.

9. In a heterogeneous integrated package in which high bandwidth memory and the process chip using it are mounted, Package substrate and; A logic die positioned on the upper side of the package substrate and including a companion physical layer for high bandwidth memory; A memory package comprising a process chip including a physical layer corresponding to the companion physical layer, positioned on the logic die and electrically connected via the logic die, and two or more memory dies; The above logic die is positioned on the package substrate independently from the above memory dies to provide vertical space for stacking more memory dies, and includes a companion physical layer to serve as a bridge connecting with the physical layer of the process chip. A heterogeneous integrated package in which the above-mentioned companion physical layer is formed at a free position on the logic die, and the connection between the physical layer and the companion physical layer is formed by a high-speed interconnect formed on the logic die.

10. In paragraph 9, A heterogeneous integrated package in which the above-mentioned companion physical layer and the above-mentioned memory package are electrically connected by low-speed interconnects, the physical number of the low-speed interconnects being N times greater than that of the high-speed interconnects, and the speed of the data signal transmitted is 1 / N times slower. Here, N is a number greater than or equal to 2.

11. In paragraph 10, A heterogeneous integrated package wherein the length of the high-speed interconnect is 4 millimeters or less, and the length of the low-speed interconnect is longer than the length of the high-speed interconnect.

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