Chip packaging structure and preparation method therefor, and electronic device

Abstract

The present application relates to the field of semiconductors, and provides a chip packaging structure and a preparation method therefor, and an electronic device. A first temperature equalizing layer can enable the heat generated by a first bare chip to be conducted in the direction of a plane perpendicular to a Z direction, effectively improving the temperature equalizing capability of the first bare chip, and avoiding frequency reduction caused by high temperature of the first bare chip. The chip packaging structure comprises a first carrier plate, the first bare chip, an interposer, a second carrier plate, and a second bare chip which are sequentially stacked. The first bare chip is flip-chip bonded onto the first carrier plate, and the second bare chip is packaged on the second carrier plate; and the interposer is electrically connected to the first carrier plate and the second carrier plate, respectively. The chip packaging structure further comprises a first temperature equalizing layer, and the first temperature equalizing layer is arranged between the first bare chip and the interposer.

Description

Chip packaging structure and preparation method thereof, and electronic equipment

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on January 4, 2024, with application number 202410027589.8 and application name “Chip packaging structure and its preparation method, electronic device”, all contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of semiconductors, and in particular to a chip packaging structure and a preparation method thereof, and electronic equipment. Background Art

[0003] Electronic devices like mobile phones and wearables typically include multiple chips, such as system-on-chips (SoCs). Chip performance relies heavily on advanced process nodes. Outdated process nodes mean higher power consumption, faster junction temperature limits, and lower frequencies.

[0004] Therefore, it is urgent to reduce the thermal resistance of the chip while maintaining the heat dissipation boundary conditions.

[0005] Summary of the Invention

[0006] In order to solve the above technical problems, the present application provides a chip packaging structure and a preparation method thereof, and an electronic device. The first temperature-balancing layer can enable the heat generated by the first bare chip to be conducted in the direction of the plane perpendicular to the Z direction, thereby effectively improving the temperature-balancing ability of the first bare chip and avoiding the frequency reduction due to the high temperature of the first bare chip.

[0007] In a first aspect, the present application provides a chip packaging structure comprising a first carrier, a first bare chip, an interposer, a second carrier, and a second bare chip stacked in sequence. The first bare chip is flip-packaged on the first carrier, and the second bare chip is packaged on the second carrier; the interposer is electrically connected to the first carrier and the second carrier, respectively. The chip packaging structure also includes a first temperature balancing layer disposed between the first bare chip and the interposer.

[0008] In the present application, by providing a first temperature-averaging layer on the first bare chip, the first temperature-averaging layer can also be used to even out the heat generated by the first bare chip when the first bare chip generates heat. That is, assuming that the direction in which the first bare chip points toward the first temperature-averaging layer is the Z direction, the first temperature-averaging layer can conduct the heat generated by the first bare chip in the direction of a plane perpendicular to the Z direction. In other words, the heat generated by the first bare chip is conducted in the first temperature-averaging layer in a direction perpendicular to the Z direction. In this way, the temperature-averaging capability of the first bare chip can be effectively improved, allowing the first bare chip to effectively dissipate heat, avoiding frequency reduction due to the high temperature of the first bare chip, and improving the performance of the first bare chip.

[0009] Furthermore, since the back surface of the first bare chip is the substrate surface of the first bare chip, rather than the surface of the first bare chip where the first connection pad is disposed, the location of the first temperature-balancing layer does not affect the flip-package of the first bare chip on the first carrier, nor does it affect the electrical connection between the first bare chip and the first carrier.

[0010] In some possible implementations, the surface of the first bare chip facing away from the first carrier includes a groove; the first temperature-uniform layer includes a first temperature-uniform portion and a second temperature-uniform portion, the first temperature-uniform portion is located in the groove, and the second temperature-uniform portion is arranged at other positions between the first bare chip and the interposer.

[0011] In this way, compared with the distance from the second temperature-averaging portion to the heat-generating device (such as a transistor, etc.) in the first bare chip, the first temperature-averaging portion is closer to the heat-generating device in the first bare chip, which is more conducive to improving the temperature-averaging ability of the groove area in the first bare chip.

[0012] On this basis, the thickness of the first temperature-uniform portion is greater than that of the second temperature-uniform portion, along the direction from the first carrier toward the first bare chip. The thicker the first temperature-uniform portion, the greater its heat conduction energy to the first bare chip. Therefore, increasing the thickness of the first temperature-uniform portion increases the temperature-uniformity capability of the area where the groove of the first bare chip is located.

[0013] In some possible implementations, the first temperature-averaging portion comprises a laminate of copper, diamond, or a diamond composite material, and copper; and the second temperature-averaging portion comprises at least one of silicon carbide, copper, graphite, and a graphite composite material. Because diamond and diamond composite materials offer superior thermal conductivity compared to silicon carbide, copper, and graphite, positioning the diamond-containing first temperature-averaging portion in the hotspot projection area further improves temperature averaging in the area where the recess in the first bare chip is located.

[0014] In some possible implementations, the first bare chip is divided into a hotspot projection area and other areas, and the temperature of the portion of the first bare chip located in the hotspot projection area is higher than the temperature of the portion of the first bare chip located in the other areas. The first temperature-averaging portion is located in the hotspot projection area, and the second temperature-averaging portion is located in the other areas. The aforementioned grooves, the thickness of the first temperature-averaging portion being greater than the thickness of the second temperature-averaging portion, and the first temperature-averaging portion being a laminate of copper, diamond, or a diamond composite material, and copper can effectively improve the temperature-averaging energy of the portion of the first bare chip located in the hotspot projection area.

[0015] In some possible implementations, the chip package structure includes a barrier layer positioned between the first bare chip and the first thermally balancing layer to prevent copper from migrating from the first thermally balancing layer into the first bare chip, potentially causing a short circuit within the first bare chip. Optionally, the barrier layer may be made of at least one of titanium, nickel, tungsten, and titanium-tungsten.

[0016] Furthermore, the conductive structure of the first bare chip is exposed. For example, in some application scenarios, a metal network is provided on the back side of the first bare chip to electrically connect the first bare chip to an external circuit. To prevent the conductive structure of the first bare chip from short-circuiting with the first temperature-balancing layer, the barrier layer may optionally include an insulating material to prevent the conductive structure of the first bare chip from being exposed, thereby preventing a short-circuit between the conductive structure of the first bare chip and the first temperature-balancing layer.

[0017] In some possible implementations, the interposer is electrically connected to the first carrier via first solder balls, and the first solder balls are located around the first bare chip and the first temperature-balancing layer. The interposer is also electrically connected to the second carrier via second solder balls, and the chip packaging structure further includes a filler layer disposed between the interposer and the second carrier. The second solder balls are located around the filler layer.

[0018] By arranging a filling layer in the gap between the intermediary layer and the second carrier board, the filling layer can be used to conduct heat between the intermediary layer and the second carrier board.

[0019] Given that phase-change materials absorb heat at their transition points without changing their own temperature, the boost time can be extended. That is, compared to conventional materials, phase-change materials take longer to reach a high temperature. Optionally, the filling layer can include phase-change materials to extend the life of the first bare chip.

[0020] In some possible implementations, the chip packaging structure further includes a retaining wall disposed between the second carrier and the interposer. The retaining wall is disposed sequentially along a direction from the filling layer toward the second solder balls. Prior to forming the filling layer, the retaining wall can be secured to the interposer to act as a dam to prevent overflow of the filling layer.

[0021] In some possible implementations, the thickness of the filling layer, along the direction from the first carrier toward the first bare chip, is greater than or equal to the thickness of the retaining wall. This avoids the situation where the retaining wall is thicker than the filling layer, resulting in a gap between the filling layer and the second carrier, preventing the filling layer from maximizing heat conduction between the interposer and the second carrier within the available space. Furthermore, if the filling layer comprises a phase-change material, its hardness decreases with heat. Therefore, even if the filling layer is thicker than the retaining wall, its thickness can gradually equalize with the retaining wall as the temperature changes.

[0022] In some possible implementations, the chip packaging structure further includes a solder layer disposed between the first temperature-balancing layer and the interposer. Because the thermal resistance of tin is lower than that of the molding compound, coating the first temperature-balancing layer with a solder layer can further improve the temperature-balancing capability of the first bare chip and the interposer.

[0023] Of course, the material of the solder layer can also be other materials, as long as the thermal resistance of the solder layer is less than the thermal resistance of the plastic packaging material, and this application does not limit this.

[0024] In some possible implementations, the chip packaging structure further includes a molding compound and a second temperature-balancing layer. A surface of the second bare chip facing away from the first bare chip includes a first solder pad, and a surface of the second carrier board facing away from the first bare chip includes a second solder pad. The first solder pad and the second solder pad are electrically connected via a bonding wire. The molding compound covers the bonding wire, the sidewall of the second bare chip, and the first solder pad. The molding compound includes an opening that exposes a portion of the surface of the second bare chip facing away from the first bare chip, and the second temperature-balancing layer fills at least the opening.

[0025] By replacing the plastic encapsulation material with a higher thermal resistance with a second temperature-balancing layer, the heat generated by the second bare chip can be conducted in the direction of a plane perpendicular to the Z direction by the second temperature-balancing layer, thereby effectively improving the temperature-balancing capability of the second bare chip, effectively dissipating heat from the second bare chip, avoiding frequency reduction due to the high temperature of the second bare chip, and improving the performance of the second bare chip.

[0026] In some possible implementations, the chip packaging structure further includes an adhesive layer, which is disposed between the molding compound and the second temperature-balancing layer and is used to fix the second temperature-balancing layer on the second bare chip and the molding compound.

[0027] In some possible implementations, the materials of the first temperature-balancing layer and the second temperature-balancing layer include at least one of silicon carbide, copper, graphite, graphite composite material, diamond, and diamond composite material.

[0028] In a second aspect, the present application provides a method for preparing a chip packaging structure, comprising: forming a first temperature-balancing layer on a first bare chip; wherein the first bare chip is flip-packaged on a first carrier, and the first carrier and the first temperature-balancing layer are disposed on opposite sides of the first bare chip. An interposer is formed on a side of the first temperature-balancing layer facing away from the first bare chip, and the interposer is electrically connected to the first carrier. A second bare chip is packaged on a second carrier, and the second carrier is secured to the interposer; wherein the interposer is electrically connected to the second carrier, and the second carrier is disposed between the interposer and the second bare chip.

[0029] In some possible implementations, forming a first temperature-balancing layer on the first bare chip includes: flip-packaging the first bare chip on a first carrier, and forming solder and plastic encapsulation material on the first carrier and the first bare chip; thinning the side of the first bare chip facing away from the first carrier, as well as the solder and plastic encapsulation material; forming a first temperature-balancing layer on the side of the first bare chip facing away from the first carrier; and forming solder and plastic encapsulation material on the first carrier again.

[0030] In some possible implementations, after forming the first temperature-balanced layer on the first bare chip, the preparation method further includes: flip-packaging the first bare chip with the first temperature-balanced layer formed thereon on a first carrier.

[0031] In some possible implementations, forming an interposer on a side of the first temperature-balancing layer facing away from the first bare chip, the interposer being electrically connected to the first carrier, includes: forming the interposer on a side of the first temperature-balancing layer facing away from the first bare chip, the interposer being electrically connected to the first carrier via first solder balls; the first solder balls being located peripherally to the first bare chip and the first temperature-balancing layer. Securing the second carrier to the interposer includes: securing the second carrier to the interposer using second solder balls, such that the second carrier is electrically connected to the interposer. After forming the interposer on a side of the first temperature-balancing layer facing away from the first bare chip, the preparation method further includes: forming a filling layer on a side of the interposer facing away from the first bare chip, the filling layer being located between the interposer and the second carrier; the second solder balls being located peripherally to the filling layer.

[0032] In some possible implementations, a surface of the second bare chip facing away from the first bare chip includes a first solder pad, a surface of the second carrier board facing away from the first bare chip includes a second solder pad, and the first solder pad and the second solder pad are electrically connected via a bonding wire. After encapsulating the second bare chip on the second carrier board and before securing the second carrier board to the interposer, the preparation method further includes: forming a molding compound on a side of the second bare chip facing away from the first bare chip; the molding compound covering the bonding wire, the sidewall of the second bare chip, and the first solder pad; the molding compound including an opening, the opening exposing a portion of the surface of the second bare chip facing away from the first bare chip; and filling the opening with a second temperature balancing layer.

[0033] The second aspect and any implementation of the second aspect correspond to the first aspect and any implementation of the first aspect, respectively. The technical effects corresponding to the second aspect and any implementation of the second aspect can be referred to the technical effects corresponding to the first aspect and any implementation of the first aspect, and will not be repeated here.

[0034] In a third aspect, the present application provides an electronic device, comprising a circuit board, a third solder ball, and the chip packaging structure described in the first aspect, wherein the first carrier of the chip packaging structure is soldered to the circuit board through the third solder ball.

[0035] The third aspect and any implementation of the third aspect correspond to the first aspect and any implementation of the first aspect, respectively. The technical effects corresponding to the third aspect and any implementation of the third aspect can be referred to the technical effects corresponding to the first aspect and any implementation of the first aspect, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] FIG1a is a top view of a bare chip provided in an embodiment of the present application;

[0037] FIG1b is a schematic diagram of a chip packaging structure provided by an embodiment of the present application being packaged on a circuit board;

[0038] FIG2a is a schematic diagram of a chip packaging structure provided in an embodiment of the present application;

[0039] FIG2 b is a perspective view of the first bare chip and the first temperature-balancing layer shown in FIG2 a ;

[0040] FIG3a is a schematic diagram of a chip packaging structure provided in an embodiment of the present application;

[0041] FIG3 b is a perspective view of the first bare chip and the first temperature-balancing layer shown in FIG3 a ;

[0042] FIG4a is a schematic diagram of a chip packaging structure provided in an embodiment of the present application;

[0043] FIG4 b is a top view of a first bare chip provided in an embodiment of the present application;

[0044] FIG4c is a schematic diagram of a chip packaging structure provided in an embodiment of the present application;

[0045] FIG5a is a schematic diagram of a chip packaging structure provided in an embodiment of the present application;

[0046] FIG5 b is a schematic diagram of a chip packaging structure provided in an embodiment of the present application;

[0047] FIG5c is a schematic diagram of a chip packaging structure provided in an embodiment of the present application;

[0048] FIG6 a is a schematic diagram of a chip packaging structure provided in an embodiment of the present application;

[0049] FIG6 b is a schematic diagram of a chip packaging structure provided in an embodiment of the present application;

[0050] FIG7 a is a schematic diagram of a chip packaging structure provided in an embodiment of the present application;

[0051] FIG7 b is a schematic diagram of a chip packaging structure provided in an embodiment of the present application;

[0052] FIG8 is a schematic diagram of a chip packaging structure provided in an embodiment of the present application;

[0053] FIG9 is a schematic diagram of a chip packaging structure provided in an embodiment of the present application;

[0054] FIG10 is a schematic diagram of a chip packaging structure provided in an embodiment of the present application;

[0055] FIG11a is a schematic diagram of a chip packaging structure provided in an embodiment of the present application;

[0056] FIG11b is a top view of the filling layer and retaining wall shown in FIG11a;

[0057] FIG12 is a schematic diagram of a chip packaging structure provided in an embodiment of the present application;

[0058] FIG13 is a schematic diagram of a chip packaging structure provided in an embodiment of the present application;

[0059] FIG14a is a schematic diagram of a chip packaging structure provided in an embodiment of the present application;

[0060] FIG14b is a schematic diagram of a chip packaging structure provided in an embodiment of the present application;

[0061] FIG15 is a schematic diagram of a chip packaging structure provided in an embodiment of the present application;

[0062] FIG16 is a schematic diagram of a chip packaging structure provided in an embodiment of the present application;

[0063] FIG17 is a flowchart of preparing a chip packaging structure according to an embodiment of the present application;

[0064] FIG18a is a diagram showing the preparation process of the chip packaging structure provided in an embodiment of the present application;

[0065] FIG18b is a diagram showing the preparation process of the chip packaging structure provided in an embodiment of the present application;

[0066] FIG18c is a diagram showing the preparation process of the chip packaging structure provided in an embodiment of the present application;

[0067] FIG18d is a diagram showing the preparation process of the chip packaging structure provided in an embodiment of the present application;

[0068] FIG19a is a diagram showing the preparation process of the chip packaging structure provided in an embodiment of the present application;

[0069] FIG19b is a diagram showing the preparation process of the chip packaging structure provided in an embodiment of the present application;

[0070] FIG19c is a diagram showing the preparation process of the chip packaging structure provided in an embodiment of the present application;

[0071] FIG19d is a diagram showing the preparation process of the chip packaging structure provided in an embodiment of the present application;

[0072] FIG20 a is a diagram showing the preparation process of the chip packaging structure provided in an embodiment of the present application;

[0073] FIG20 b is a diagram illustrating the preparation process of the chip packaging structure provided in an embodiment of the present application;

[0074] FIG20c is a diagram showing the preparation process of the chip packaging structure provided in an embodiment of the present application;

[0075] FIG21 is a flow chart of manufacturing a chip packaging structure according to an embodiment of the present application;

[0076] FIG22 is a diagram showing the preparation process of the chip packaging structure provided in an embodiment of the present application. DETAILED DESCRIPTION

[0077] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0078] The term "and / or" in this article is merely a description of the association relationship between associated objects, indicating that three relationships may exist. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone.

[0079] In the description and claims of the embodiments of this application, the terms "first" and "second" are used to distinguish different objects, rather than to describe a specific order of objects. For example, the terms "first target object" and "second target object" are used to distinguish different objects, rather than to describe a specific order of objects.

[0080] In the embodiments of this application, words such as "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary" or "for example" in the embodiments of this application should not be interpreted as being preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0081] In the description of the embodiments of this application, unless otherwise specified, "multiple" means two or more. For example, "multiple processing units" means two or more processing units; "multiple systems" means two or more systems.

[0082] An embodiment of the present application provides an electronic device, which may be a consumer electronic product, a home electronic product, a vehicle-mounted electronic product, a financial terminal product, a communication electronic product, or other device containing a chip.

[0083] Consumer electronic products include mobile phones, tablet computers, laptops, personal computers (PCs), personal digital assistants (PDAs), smart wearable products (e.g., smart watches, smart bracelets, etc.), virtual reality (VR) terminal devices, augmented reality (AR) terminal devices, drones, etc. Home electronic products include smart door locks, TVs, smart speakers, refrigerators, sweeping robots, etc. Car-mounted electronic products include car navigation systems and car displays, etc. Financial terminal products include automated teller machines (ATMs) and self-service terminals, etc. Communication electronic products include servers, storage devices, radars, base stations, and other communication equipment that contain chips.

[0084] For ease of explanation, the following description uses a mobile phone as an example electronic device. The mobile phone may include a circuit board, which may integrate a processor, memory, and the like. For example, the processor may be implemented by connecting circuits on one or more chips. Of course, the mobile phone may also include other components, and the circuit board may also integrate other circuit structures, which are not limited in the present embodiment.

[0085] As chip interconnect density increases and interconnect size continues to shrink, chip packaging technologies are becoming increasingly diverse. Flip-chip technology has become widely used in chip packaging, as it shortens the length of interconnects within a package, thereby better adapting to the development needs of highly integrated systems. Flip-chip technology involves directly fabricating conductive bumps on a bare chip as connection terminals, then flip-chip soldering them to a packaging substrate to achieve an electrical connection between the bare chip and the packaging substrate.

[0086] Specifically, FIG1a shows a top view of a first bare chip 10. The first bare chip 10 includes a first connection pad 11, which may also be referred to as a solder pad or other term. As shown in FIG1b , the first bare chip 10 is flip-mounted on a first substrate 20. Conductive bumps 30 contact the first connection pad 11 of the first bare chip 10 and the second connection pad 21 of the first substrate 20, respectively. The first connection pad 11 is electrically connected to the second connection pad 21 via the conductive bumps 30, thereby leading the first connection pad 11 of the first bare chip 10 to the second connection pad 21 of the first substrate 20 via the conductive bumps 30.

[0087] As shown in FIG1b , the first carrier 20 further includes a third connection pad 22 opposite to the second connection pad 21. The second connection pad 21 and the third connection pad 22 are electrically connected via a wiring layer in the first carrier 20. The first bare chip 10 is soldered to the circuit board 40 via the third connection pad 22 and the solder ball (third solder ball) in the first carrier 20.

[0088] In some possible implementations, the first bare chip 10 can be a bare chip with any function, for example, a SoC. The first carrier 20 can be a package substrate, an integrated passive device (IPD), a redistribution layer (RDL), etc.

[0089] In some possible implementations, the present application does not limit the method of flip-packaging the first bare chip 10 on the first carrier 20. The flip-packaging method can be a flip chip scale package (FCCSP) or a flip chip ball grid array package (FCBGA), etc.

[0090] However, chip performance is highly dependent on advanced process nodes. Outdated process nodes mean higher power consumption and faster junction temperature limits. Furthermore, due to package thickness constraints, the first die 10 is relatively thin, limiting the ability to distribute heat around the heat source. This inability to effectively dissipate heat from the first die 10 can lead to a decrease in frequency, thus impacting performance.

[0091] Furthermore, in the related art, a die attach film (DAF) is directly formed on the first bare chip 10 . However, the thermal resistance of the die attach film is relatively large, which makes it difficult for the first bare chip 10 to dissipate heat.

[0092] The back side of the first bare chip 10 refers to the side of the first bare chip 10 where the first connection pad 11 is located, which is the front side, and the side of the first bare chip 10 opposite the front side, which is the back side. Alternatively, the back side of the first bare chip 10 is the surface of the substrate of the first bare chip 10.

[0093] Based on this, an embodiment of the present application provides a chip packaging structure. In addition to the aforementioned first carrier 20 and the first bare chip 10 flip-packaged on the first carrier 20, the chip packaging structure may further include a first temperature-balancing layer, an interposer substrate, a second carrier, and a second bare chip. When the first bare chip 10 generates heat, the first temperature-balancing layer is used to conduct the heat generated by the first bare chip 10, thereby dissipating heat from the first bare chip 10.

[0094] 2a and 3a, the first carrier 20, the first bare chip 10, the interposer 71, the second carrier 72, and the second bare chip 73 are stacked in sequence. The first bare chip 10 is flip-packaged on the first carrier 20, and the second bare chip 73 is packaged on the second carrier 72.

[0095] The interposer 71 is electrically connected to the first carrier 20 and the second carrier 72 , respectively. Thus, the second bare chip 73 can be electrically connected to the first bare chip 10 through the second carrier 72 , the interposer 71 , and the first carrier 20 .

[0096] The first temperature-distributing layer 51 is disposed between the first bare chip 10 and the interposer 71. Alternatively, the first bare chip 10 is located on the side facing away from the first carrier 20, or on the backside of the first bare chip 10. Since the backside of the first bare chip 10 is the substrate surface of the first bare chip 10, rather than the surface of the first bare chip 10 where the first connection pads 11 are located, the location of the first temperature-distributing layer 51 does not affect the flip-chip packaging of the first bare chip 10 on the first carrier 20, nor does it affect the electrical connection between the first bare chip 10 and the first carrier 20.

[0097] Moreover, by providing the first temperature-averaging layer 51 on the first bare chip 10, when the first bare chip 10 generates heat, the first temperature-averaging layer 51 can be used to average the temperature of the heat generated by the first bare chip 10. That is, assuming that the direction in which the first bare chip 10 points to the first temperature-averaging layer 51 is the Z direction, the first temperature-averaging layer 51 can allow the heat generated by the first bare chip 10 to be conducted in the direction of the plane perpendicular to the Z direction. In other words, the conduction direction of the heat generated by the first bare chip 10 in the first temperature-averaging layer 51 is perpendicular to the Z direction. In this way, the temperature-averaging ability of the first bare chip 10 can be effectively improved, the first bare chip 10 can be effectively dissipated, the frequency reduction caused by the high temperature of the first bare chip 10 can be avoided, and the performance of the first bare chip 10 can be improved. As mentioned above, due to the constraints on the package thickness, the thickness of the first bare chip 10 is relatively thin. In some possible implementation methods, the present application can achieve a thinner first bare chip 10 by thinning the thickness of the first bare chip 10. For example, the back side of the first bare chip 10 is thinned along the direction in which the first bare chip 10 points toward the first carrier 20 to achieve a thinner first bare chip 10. This leaves space between the first bare chip 10 and the interposer 71, and the first temperature-balancing layer 51 is disposed in the reserved space. The thickness of the thinned first bare chip 10 can be close to the thickness of the first temperature-balancing layer 51.

[0098] Optionally, the thickness of the first bare chip 10 that is thinned can range from 10 μm to 100 μm, and the thickness of the first temperature-balancing layer 51 can range from 10 μm to 100 μm. For example, the thickness of the first bare chip 10 that is thinned is 70 μm, and the thickness of the first temperature-balancing layer 51 is also 70 μm. For another example, the thickness of the first bare chip 10 that is thinned is 70 μm, and the thickness of the first temperature-balancing layer 51 is 65 μm. For another example, the thickness of the first bare chip 10 that is thinned is 70 μm, and the thickness of the first temperature-balancing layer 51 is 80 μm.

[0099] In addition, when the chip packaging structure further includes a barrier layer (barrier layer and seed layer), the thickness of the first bare chip 10 can be thinned to be close to the thickness of the first temperature-balancing layer 51 and the barrier layer (barrier layer and seed layer).

[0100] In some possible implementations, the present invention does not limit the material of the first temperature-balancing layer 51, as long as the first temperature-balancing layer 51 can achieve a uniform temperature. Optionally, the material of the first temperature-balancing layer 51 includes at least one of silicon carbide (SiC), copper (Cu), graphite, a graphite composite material, diamond, and a diamond composite material.

[0101] Compared with the case where no other structure is set between the first bare chip 10 and the interposer 71, or a plastic packaging material is set between the first bare chip 10 and the interposer 71, the first local temperature layer 51 not only plays a role in equalizing the temperature of the first bare chip 10, but also can avoid the first bare chip 10 from having difficulty in heat dissipation due to its own large thermal resistance.

[0102] In some possible implementations, the embodiments of the present application do not limit the form of the diamond composite material. For example, the diamond composite material may be formed by using another metal (such as copper) as a matrix, with diamond particles embedded in the matrix. Of course, the diamond composite material may also have other forms.

[0103] In some possible implementations, the entire first temperature-balancing layer 51 can be disposed on the first bare chip 10 by screen printing or adhesive bonding. For example, a layer of metal coating can be printed on the first bare chip 10. Alternatively, a prefabricated sheet of graphite or a graphite composite material can be preformed and then bonded to the first bare chip 10.

[0104] In some possible implementations, the entire first temperature-balancing layer 51 is made of the same material, or the first temperature-balancing layer 51 in different regions is made of different materials.

[0105] For example, as shown in Figure 4a, the surface of the first bare chip 10 facing away from the first carrier 20 includes a groove, and the first temperature-uniform layer 51 includes a first temperature-uniform portion 511 and a second temperature-uniform portion 512. The first temperature-uniform portion 511 is located in the groove, and the second temperature-uniform portion 512 is located at other positions between the first bare chip 10 and the interposer 71.

[0106] Optionally, as shown in FIG4 a , the first bare chip 10 is divided into a hotspot projection area and other areas excluding the hotspot projection area. When the first bare chip 10 is in operation, the temperature of the first bare chip 10 in the hotspot projection area is higher than the temperature of other areas of the first bare chip 10. Specifically, the first temperature-averaging portion 511 is located in the hotspot projection area, and the second temperature-averaging portion 512 is located in other areas.

[0107] In this way, compared with the distance from the second temperature-averaging portion 512 to the heat-generating device (such as a transistor, etc.) in the first bare chip 10, the first temperature-averaging portion 511 is closer to the heat-generating device in the first bare chip 10, which is more conducive to improving the temperature-averaging ability of the groove area in the first bare chip 10.

[0108] It should be understood that, as shown in FIG4 b , the temperatures at various locations within the hotspot projection area of ​​the first bare chip 10 are not all the same, and the temperatures at various locations within other areas of the first bare chip 10 are not all the same. However, the temperature value of the lowest temperature portion within the hotspot projection area is greater than the temperature value of the highest temperature portion within other areas.

[0109] For example, as shown in Figure 4b, the hotspot projection area includes a first area, a second area, and a third area. The temperature of the first area is temperature a, the temperature of the second area is temperature b, and the temperature of the third area is temperature c. Temperature a is greater than temperature b, which is greater than temperature c. The other areas include a fourth area and a fifth area. The temperature of the fourth area is temperature d, and the temperature of the fifth area is temperature e. Temperature d is greater than temperature e. Furthermore, temperature c is greater than temperature d. That is, the temperature value of the third area, which has the lowest temperature in the hotspot projection area, is greater than the temperature value of the fourth area, which has the highest temperature among the other areas.

[0110] In some possible implementations, the embodiments of the present application do not limit the specific location of the hotspot projection area. The location of the hotspot projection area depends on the power consumption of the circuits at various locations in the first bare chip 10. The greater the power consumption of the circuits, the higher the temperature of the area in the first bare chip 10 where the circuits are located. The first bare chip 10 can be divided into the hotspot projection area and other areas based on the temperatures at various locations in the first bare chip 10. Optionally, the circuits in the first bare chip 10 located in the hotspot projection area may include the core of a computer central processing unit (CPU) and / or the core of a graphics processing unit (GPU).

[0111] Based on the above, in the present application, the number of the hotspot projection areas in the first bare chip 10 can be one or more, and the location of the hotspot projection area can be, for example, at the center of the first bare chip 10 .

[0112] Furthermore, for different first bare chips 10, the material of the first temperature-averaging portion 511 and the material of the second temperature-averaging portion 512 may be the same or different. For example, as shown in FIG4c , the first temperature-averaging portion 511 may be a stack of copper, diamond or a diamond composite material, and copper, with the copper, diamond or a diamond composite material, and copper being stacked in this order along the direction from the first carrier 20 toward the first bare chip 10. The material of the second temperature-averaging portion 512 may include at least one of silicon carbide, copper, graphite, and a graphite composite material.

[0113] Since the thermal conductivity of diamond and diamond composite materials is better than that of silicon carbide, copper, graphite, etc., by locating the first temperature-averaging portion 511 containing diamond in the hotspot projection area, the temperature-averaging capability of the portion of the first bare chip 10 located in the hotspot projection area can be further improved.

[0114] In some possible implementations, the temperature uniformity capability of the portion of the first bare chip 10 located in the hotspot projection area may be improved by other means.

[0115] For example, as shown in Figure 5a, along the direction from the first carrier 20 toward the first bare chip 10, the thickness of the first temperature-uniform portion 511 is greater than the thickness of the second temperature-uniform portion 512. The thicker the first temperature-uniform portion 511, the greater its heat conduction energy to the first bare chip 10. Therefore, by increasing the thickness of the first temperature-uniform portion 511, the temperature-uniformity capability of the portion of the first bare chip 10 located in the hotspot projection area is increased. In this case, the surface of the first bare chip 10 facing away from the first carrier 20 has the aforementioned groove in the hotspot projection area, and the thicker first temperature-uniform portion 511 can also be located in the groove. This further improves the temperature-uniformity capability of the portion of the first bare chip 10 located in the hotspot projection area.

[0116] Based on the structure shown in FIG5a, as shown in FIG5b, the first temperature-averaging portion 511 may also be a stack of copper, diamond, and copper, and the material of the second temperature-averaging portion 512 includes at least one of silicon carbide and copper.

[0117] In some possible implementations, as shown in FIG5c , when the first bare chip 10 is divided into a hotspot projection area and other areas, the surface of the first bare chip 10 facing away from the first carrier 20 may not include a groove, and the thickness of the first temperature-uniform portion 511 located in the hotspot projection area may not exceed the thickness of the second temperature-uniform portion 512 located in other areas. Furthermore, the first temperature-uniform portion 511 may be a laminate of copper, diamond, or a diamond composite material and copper. Because diamond and diamond composite materials have better thermal conductivity than silicon carbide, copper, graphite, etc., locating the first temperature-uniform portion 511 containing diamond in the hotspot projection area can further improve the temperature-uniformity of the portion of the first bare chip 10 located in the hotspot projection area.

[0118] In some possible implementations, the embodiments of the present application do not limit the size relationship between the first temperature-distributing layer 51 and the first bare chip 10. Optionally, as shown in Figures 2a and 2b, the size of the first temperature-distributing layer 51 is the same as the size of the first bare chip 10, or the size of the first temperature-distributing layer 51 is larger than the size of the first bare chip 10, and the first temperature-distributing layer 51 completely covers the first bare chip 10. Alternatively, as shown in Figures 3a and 3b, the size of the first temperature-distributing layer 51 can also be smaller than the size of the first bare chip 10, and the first temperature-distributing layer 51 partially covers the first bare chip 10.

[0119] In some possible implementations, as shown in Figures 6a and 6b, in addition to covering the surface of the first bare chip 10 facing away from the first carrier 20, the first temperature-balancing layer 51 may also cover the sidewalls of the first bare chip 10. That is, the first temperature-balancing layer 51 extends from the surface of the first bare chip 10 facing away from the first carrier 20 to the sidewalls of the first bare chip 10. In this way, the first temperature-balancing layer 51 not only conducts heat generated by the first bare chip 10 in the direction of a plane perpendicular to the Z direction, but also conducts heat generated by the first bare chip 10 in the Z direction, further improving the temperature-balancing capability of the first bare chip 10, further effectively dissipating heat from the first bare chip 10, avoiding frequency reduction due to the high temperature of the first bare chip 10, and improving the performance of the first bare chip 10.

[0120] In some possible implementations, as shown in FIG. 6 a , the first temperature-distributing layer 51 completely covers the sidewalls of the first bare chip 10 ; or, as shown in FIG. 6 b , the first temperature-distributing layer 51 partially covers the sidewalls of the first bare chip 10 .

[0121] In some embodiments, as shown in FIG7 a , the chip package structure may further include a barrier layer 61, which is located between the first bare chip 10 and the first temperature-distributing layer 51. The barrier layer 61 prevents copper from migrating from the first temperature-distributing layer 51 into the first bare chip 10, thereby preventing a short circuit within the first bare chip 10. Optionally, the barrier layer 61 may be made of at least one of titanium (Ti), nickel (Ni), tungsten (W), and titanium tungsten (TiW).

[0122] Furthermore, the conductive structure of the first bare chip 10 is exposed. For example, in some applications, a metal network is provided on the back of the first bare chip 10 to electrically connect the first bare chip 10 to an external circuit. To prevent the conductive structure of the first bare chip 10 from short-circuiting with the first temperature-balancing layer 51, the barrier layer 61 may optionally include an insulating material to prevent the conductive structure of the first bare chip 10 from being exposed, which could result in a short-circuit between the conductive structure of the first bare chip 10 and the first temperature-balancing layer 51.

[0123] The metal network may be, for example, a backside power distribution network (BSPDN), which may be formed after the first bare chip 10 is thinned.

[0124] In some possible implementations, as shown in FIG7 b , the barrier layer 61 may include a first barrier layer 611 and a second barrier layer 612. The first barrier layer 611 includes an insulating material to prevent the exposed conductive structure of the first bare chip 10 from short-circuiting through the first temperature-distributing layer 51. The second barrier layer 61 includes at least one of titanium, nickel, tungsten, and titanium-tungsten to prevent copper in the first temperature-distributing layer 51 from migrating to the first bare chip 10.

[0125] The first barrier layer 611 is disposed between the first bare chip 10 and the second barrier layer 612 .

[0126] In some possible implementations, as shown in FIG8 , the chip package structure may further include a seed layer 62 . The seed layer 62 may be made of copper. Typically, the thickness of the seed layer 62 is less than that of the first temperature-balancing layer 51 .

[0127] In related technologies, fanout package on package (FOPoP) or high-bandwidth package on package (HBPOP) are typically used to package two bare chips in the Z direction. However, as shown in FIG9 , there is a large air gap between the interposer 71 and the second carrier 72. Those skilled in the art will recognize that air cannot effectively conduct heat. Therefore, the chip package structure has extremely poor thermal conductivity at this location, significantly increasing the thermal resistance of the chip package structure.

[0128] Based on this, in some embodiments, as shown in FIG10 , the interposer 71 is electrically connected to the first carrier 20 via first solder balls 81, and the interposer 71 is also electrically connected to the second carrier 72 via second solder balls 82. The chip package structure further includes a filler layer 74 disposed between the interposer 71 and the second carrier 72. The first solder balls 81 are positioned around the first bare chip 10 and the first temperature-balancing layer 51, while the second solder balls 82 are positioned around the filler layer 74. The first solder balls 81 may be copper core balls.

[0129] By disposing a filling layer 74 in the gap between the intermediary layer 71 and the second carrier board 72 , the filling layer 74 can be used to conduct heat between the intermediary layer 71 and the second carrier board 72 .

[0130] In some possible implementations, the embodiment of the present application does not limit the material of the filling layer 74, as long as the heat conduction effect of the filling layer 74 on the intermediate layer 71 and the second carrier plate 72 is better than the heat conduction effect of air on the intermediate layer 71 and the second carrier plate 72.

[0131] Considering that phase change material (PCM) absorbs heat at the phase transition point while maintaining its own temperature, the boost time can be extended. That is, compared to conventional materials (such as the adhesive dispensed in FOPOP or HBPOP), PCM takes longer to reach a high temperature. Optionally, the filling layer 74 can include a phase change material to extend the life of the first bare chip 10.

[0132] In some possible implementations, the second bare chip 73 can be a bare chip with any function. For example, the second bare chip 73 can realize the function of double data rate synchronous dynamic random access memory (DDRSDRAM) or dynamic random access memory (DRAM).

[0133] In some possible implementations, the second carrier 72 may be a packaging substrate, an integrated passive device, a redistribution layer, etc.

[0134] In some embodiments, as shown in Figures 11a and 11b , the chip packaging structure further includes a retaining wall 75 disposed between the second carrier 72 and the interposer 71. The retaining wall 75 is disposed sequentially along the direction from the filling layer 74 toward the second solder balls 82. Specifically, as shown in Figure 11b , the retaining wall 75 is located between the filling layer 74 and the second solder balls 82 and surrounds the filling layer 74.

[0135] In some possible implementations, the present invention does not limit the material of retaining wall 75, as long as retaining wall 75 can be fixed on interposer 71 before forming filling layer 74 and acts as a dam to prevent overflow of filling layer 74. Optionally, the material of retaining wall 75 can include a high-viscosity molding compound.

[0136] In some possible implementations, the thickness of the filling layer 74 along the direction from the first carrier 20 toward the first bare chip 10 is greater than or equal to the thickness of the retaining wall 75. This avoids the situation where the retaining wall 75 is thicker than the filling layer 74, resulting in a gap between the filling layer 74 and the second carrier 72, preventing the filling layer 74 from maximally utilizing the available space to conduct heat between the interposer 71 and the second carrier 72. Furthermore, if the filling layer 74 is made of a phase-change material, its hardness decreases when heated. Therefore, even if the filling layer 74 is thicker than the retaining wall 75, its thickness can gradually become equal to that of the retaining wall 75 as the temperature changes.

[0137] Furthermore, as shown in Figure 11a, between the interposer 71 and the second carrier 72, in addition to the filler layer 74, retaining wall 75, and second solder balls 82, a molding compound 83 is also provided. Between the first carrier 20 and the interposer 71, in addition to the first bare chip 10, conductive bumps 30, first temperature-balancing layer 51, and first solder balls 81, a molding compound 83 is also provided. Furthermore, due to process reasons, a small amount of molding compound 83 exists between the first temperature-balancing layer 51 and the interposer 71. However, the molding compound 83 is made of a relatively thick adhesive, resulting in a relatively high thermal resistance.

[0138] Based on this, as shown in FIG12 , the chip packaging structure may further include a solder layer 76, which is disposed between the first temperature-balancing layer 51 and the interposer 71. The solder layer 76 is coated entirely on the first temperature-balancing layer 51 or below the interposer 71, rather than being spaced apart on the first temperature-balancing layer 51 like the conductive bumps 30 or solder balls. Optionally, the material of the solder layer 76 may include tin (Sn). Since the thermal resistance of tin is lower than that of the molding compound 83, the temperature-balancing capability of the first bare chip 10 and the interposer 71 can be further improved by coating a layer of solder layer 76 on the first temperature-balancing layer 51.

[0139] Of course, the material of the solder layer 76 can also be other materials, as long as the thermal resistance of the solder layer 76 is less than the thermal resistance of the molding compound 83 , and this embodiment of the present application does not limit this.

[0140] In some embodiments, as shown in FIG. 13 , the molding compound 83 is also located on the second bare chip 73 and completely covers the second bare chip 73 , resulting in poor heat dissipation of the second bare chip 73 .

[0141] Based on this, as shown in Figures 14a and 14b, the surface of the second bare chip 73 facing away from the first bare chip 10 includes a first solder pad (also called a connection pad) 731, and the surface of the second carrier 72 facing away from the first bare chip 10 includes a second solder pad (also called a connection pad) 721. When the first solder pad 731 and the second solder pad 721 are electrically connected via the bonding wire 77, the molding compound 83 covers the bonding wire 77, the sidewall of the second bare chip 73, and the first solder pad 731. However, the molding compound includes an opening, which exposes a portion of the surface of the second bare chip 73 facing away from the first bare chip 10. The chip packaging structure may further include a second temperature-distributing layer 52, which at least fills the opening.

[0142] By replacing the plastic encapsulation material 83 with a higher thermal resistance with the second temperature-averaging layer 52, the second temperature-averaging layer 52 can be used to conduct the heat generated by the second bare chip 73 in the direction of the plane perpendicular to the Z direction, effectively improving the temperature-averaging ability of the second bare chip 73, enabling the second bare chip 73 to effectively dissipate heat, avoiding frequency reduction due to the high temperature of the second bare chip 73, and improving the performance of the second bare chip 73.

[0143] In some possible implementations, as shown in FIG14a , the second temperature-distributing layer 52 is located in the opening. As shown in FIG14b , the second temperature-distributing layer 52 is not only located in the opening but also located on the side of the molding compound 83 facing away from the first bare chip 10. In some possible implementations, the material of the second temperature-distributing layer 52 is the same as that of the first temperature-distributing layer 51 and will not be further described herein.

[0144] In some possible implementations, the entire second temperature-balancing layer 52 can be filled in the opening by screen printing or bonding. For example, a layer of metallic paint can be printed on the second bare chip 73 (or the second bare chip and the molding compound). Alternatively, a prefabricated sheet of graphite or a graphite composite material can be preformed and then bonded to the second bare chip 73 (or the second bare chip and the molding compound).

[0145] For example, as shown in FIG. 15 , the chip packaging structure may further include an adhesive layer 90 , which is disposed between the molding compound 83 and the second temperature-balancing layer 52 to fix the second temperature-balancing layer 52 on the second bare chip 73 and the molding compound 83 .

[0146] The aforementioned embodiment describes a case where the number of the first bare chip 10 is one. In other embodiments, a plurality of first bare chips 10 are stacked along the direction of the first carrier 20 pointing toward the first bare chip 10 to form a three-dimensional (3D) bare chip.

[0147] As shown in FIG16 , taking the number of first bare chips 10 as an example, the first first bare chip 10 is flip-packaged on the first carrier 20, and the second first bare chip 10 is disposed on the first first bare chip 10. Furthermore, the two first bare chips 10 are connected via hybrid bonding or micro bumps.

[0148] The first temperature-balancing layer 51 is disposed on a side of the second first bare chip 10 away from the first first bare chip 10 .

[0149] In another embodiment, the present application provides a method for preparing a chip packaging structure, as shown in FIG17 , which can be implemented as follows:

[0150] S110 , as shown in FIG18 a , flip-package the first bare chip 10 on the first carrier 20 . That is, the first bare chip 10 is flip-packaged on the first carrier 20 using a plurality of conductive bumps 30 .

[0151] In some possible implementations, the operations of steps S110 and S120 described above can be performed on an uncut wafer, where the wafer includes multiple first bare chips 10, and the multiple first bare chips 10 are flip-packaged on the same large first carrier 20. In this case, after step S110 and before step S120, the wafer needs to be cut to obtain multiple first bare chips 10 and the first carrier 20.

[0152] In some possible implementations, after step S110 and before step S120, as shown in FIG18b , solder and molding compound 83 may be formed on the first carrier 20 by die bonding, molding, or other methods. The molding compound 83 formed this time is the molding compound 83 formed by the first molding process. Through the first molding process, the molding compound 83 formed by the first molding process can be used to secure the first bare chip 10 to the first carrier 20.

[0153] Next, as shown in FIG18c , due to the package thickness constraint, the first bare chip 10 is relatively thin. Therefore, the first bare chip 10 and the initial molding compound 83 can be ground down to a thinner surface. After being ground down, the surface of the first bare chip 10 facing away from the first carrier 20 remains the substrate surface.

[0154] Optionally, the thickness of the first bare chip 10 that is thinned can range from 10 μm to 100 μm, and the thickness of the first temperature-balancing layer 51 can range from 10 μm to 100 μm. For example, the thickness of the first bare chip 10 that is thinned is 70 μm, and the thickness of the first temperature-balancing layer 51 is also 70 μm. For another example, the thickness of the first bare chip 10 that is thinned is 70 μm, and the thickness of the first temperature-balancing layer 51 is 65 μm. For another example, the thickness of the first bare chip 10 that is thinned is 70 μm, and the thickness of the first temperature-balancing layer 51 is 80 μm.

[0155] Of course, in the embodiment of the present application, the first bare chip 10 and the first molding compound 83 may not be ground thin.

[0156] S120, as shown in FIG18d, forms a first temperature-balancing layer 51 on the first bare chip 10. The first carrier 20 and the first temperature-balancing layer 51 are disposed on opposite sides of the first bare chip 10. That is, the first temperature-balancing layer 51 is disposed on the back side of the first bare chip 10. Since the back side of the first bare chip 10 is the substrate surface of the first bare chip 10, rather than the surface of the first bare chip 10 where the first connection pads 11 are disposed, the location of the first temperature-balancing layer 51 does not affect the flip-packaging of the first bare chip 10 on the first carrier 20, nor does it affect the electrical connection between the first bare chip 10 and the first carrier 20.

[0157] Furthermore, by providing the first temperature-balancing layer 51 on the first bare chip 10, the first temperature-balancing layer 51 can also be used to balance the heat generated by the first bare chip 10 when the first bare chip 10 generates heat. That is, assuming that the direction in which the first bare chip 10 points toward the first temperature-balancing layer 51 is the Z direction, the first temperature-balancing layer 51 can conduct the heat generated by the first bare chip 10 in the direction of a plane perpendicular to the Z direction. In other words, the heat generated by the first bare chip 10 is conducted in the first temperature-balancing layer 51 in a direction perpendicular to the Z direction. This effectively improves the temperature-balancing capability of the first bare chip 10, effectively dissipating heat from the first bare chip 10, avoiding frequency reduction due to the high temperature of the first bare chip 10, and improving the performance of the first bare chip 10.

[0158] In some possible implementations, the present invention does not limit the material of the first temperature-balancing layer 51, as long as the first temperature-balancing layer 51 can achieve a uniform temperature. Optionally, the material of the first temperature-balancing layer 51 includes at least one of silicon carbide, copper, graphite, a graphite composite material, diamond, and a diamond composite material.

[0159] Compared with the case where no other structure is provided between the first bare chip 10 and the interposer 71, or a plastic encapsulation material is provided between the first bare chip 10 and the interposer 71, the first local temperature layer 51 not only plays a role in equalizing the temperature of the first bare chip 10, but also can prevent the first bare chip 10 from having difficulty in heat dissipation due to its own large thermal resistance.

[0160] In some possible implementations, the embodiments of the present application do not limit the form of the diamond composite material. For example, the diamond composite material may be formed by using another metal (such as copper) as a matrix, with diamond particles embedded in the matrix. Of course, the diamond composite material may also have other forms.

[0161] In some possible implementations, the entire first temperature-balancing layer 51 can be disposed on the first bare chip 10 by screen printing or bonding. For example, a layer of metal paint can be printed on the first bare chip 10. Alternatively, a prefabricated sheet of graphite or a graphite composite material can be preformed and then bonded to the first bare chip 10.

[0162] In some possible implementations, the entire first temperature-balancing layer 51 is made of the same material, or the first temperature-balancing layer 51 in different regions is made of different materials.

[0163] For example, as shown in Figure 4a, the surface of the first bare chip 10 facing away from the first carrier 20 includes a groove, and the first temperature-uniform layer 51 includes a first temperature-uniform portion 511 and a second temperature-uniform portion 512. The first temperature-uniform portion 511 is located in the groove, and the second temperature-uniform portion 512 is located at other positions between the first bare chip 10 and the interposer 71.

[0164] Optionally, as shown in FIG4 a , the first bare chip 10 is divided into a hotspot projection area and other areas excluding the hotspot projection area. When the first bare chip 10 is in operation, the temperature of the first bare chip 10 in the hotspot projection area is higher than the temperature of other areas of the first bare chip 10. Specifically, the first temperature-averaging portion 511 is located in the hotspot projection area, and the second temperature-averaging portion 512 is located in other areas.

[0165] In this way, compared with the distance from the second temperature-averaging portion 512 to the heat-generating device (such as a transistor, etc.) in the first bare chip 10, the first temperature-averaging portion 511 is closer to the heat-generating device in the first bare chip 10, which is more conducive to improving the temperature-averaging ability of the groove area in the first bare chip 10.

[0166] It should be understood that, as shown in FIG4 b , the temperatures at various locations within the hotspot projection area of ​​the first bare chip 10 are not all the same, and the temperatures at various locations within other areas of the first bare chip 10 are not all the same. However, the temperature value of the lowest temperature portion within the hotspot projection area is greater than the temperature value of the highest temperature portion within other areas.

[0167] For example, as shown in Figure 4b, the hotspot projection area includes a first area, a second area, and a third area. The temperature of the first area is temperature a, the temperature of the second area is temperature b, and the temperature of the third area is temperature c. Temperature a is greater than temperature b, which is greater than temperature c. The other areas include a fourth area and a fifth area. The temperature of the fourth area is temperature d, and the temperature of the fifth area is temperature e. Temperature d is greater than temperature e. Furthermore, temperature c is greater than temperature d. That is, the temperature value of the third area, which has the lowest temperature in the hotspot projection area, is greater than the temperature value of the fourth area, which has the highest temperature among the other areas.

[0168] In some possible implementations, the embodiments of the present application do not limit the specific location of the hotspot projection area. The location of the hotspot projection area depends on the power consumption of the circuits at various locations in the first bare chip 10. The greater the power consumption of the circuits, the higher the temperature of the area in the first bare chip 10 where the circuits are located. The first bare chip 10 can be divided into the hotspot projection area and other areas based on the temperatures at various locations in the first bare chip 10. Optionally, the circuits in the first bare chip 10 located in the hotspot projection area may include CPU cores and / or GPU cores, etc.

[0169] Based on the above, in the present application, the number of the hotspot projection areas in the first bare chip 10 can be one or more, and the location of the hotspot projection area can be, for example, at the center of the first bare chip 10 .

[0170] Furthermore, for different first bare chips 10, the material of the first temperature-averaging portion 511 and the material of the second temperature-averaging portion 512 may be the same or different. For example, as shown in FIG4c , the first temperature-averaging portion 511 may be a stack of copper, diamond or a diamond composite material, and copper, with the copper, diamond or a diamond composite material, and copper being stacked in this order along the direction from the first carrier 20 toward the first bare chip 10. The material of the second temperature-averaging portion 512 may include at least one of silicon carbide, copper, graphite, and a graphite composite material.

[0171] Since the thermal conductivity of diamond and diamond composite materials is better than that of silicon carbide, copper, graphite, etc., by locating the first temperature-averaging portion 511 containing diamond in the hotspot projection area, the temperature-averaging capability of the portion of the first bare chip 10 located in the hotspot projection area can be further improved.

[0172] In some possible implementations, the temperature uniformity capability of the portion of the first bare chip 10 located in the hotspot projection area may be improved by other means.

[0173] For example, as shown in Figure 5a, along the direction from the first carrier 20 toward the first bare chip 10, the thickness of the first temperature-uniform portion 511 is greater than the thickness of the second temperature-uniform portion 512. The thicker the first temperature-uniform portion 511, the greater its heat conduction energy to the first bare chip 10. Therefore, by increasing the thickness of the first temperature-uniform portion 511, the temperature-uniformity capability of the portion of the first bare chip 10 located in the hotspot projection area is increased. In this case, the surface of the first bare chip 10 facing away from the first carrier 20 has the aforementioned groove in the hotspot projection area, and the thicker first temperature-uniform portion 511 can also be located in the groove. This further improves the temperature-uniformity capability of the portion of the first bare chip 10 located in the hotspot projection area.

[0174] Based on the structure shown in FIG5a, as shown in FIG5b, the first temperature-averaging portion 511 may also be a stack of copper, diamond, and copper, and the material of the second temperature-averaging portion 512 includes at least one of silicon carbide and copper.

[0175] In some possible implementations, as shown in FIG5c , when the first bare chip 10 is divided into a hotspot projection area and other areas, the surface of the first bare chip 10 facing away from the first carrier 20 may not include a groove, and the thickness of the first temperature-uniform portion 511 located in the hotspot projection area may not exceed the thickness of the second temperature-uniform portion 512 located in other areas. Furthermore, the first temperature-uniform portion 511 may be a laminate of copper, diamond, or a diamond composite material and copper. Because diamond and diamond composite materials have superior thermal conductivity to silicon carbide, copper, graphite, and the like, locating the first temperature-uniform portion 511 containing diamond in the hotspot projection area further improves the temperature-uniformity capability of the portion of the first bare chip 10 located in the hotspot projection area.

[0176] In some possible implementations, the embodiments of the present application do not limit the size relationship between the first temperature-distributing layer 51 and the first bare chip 10. Optionally, as shown in Figures 2a and 2b, the size of the first temperature-distributing layer 51 is the same as the size of the first bare chip 10, and the first temperature-distributing layer 51 exactly covers the first bare chip 10. Alternatively, as shown in Figures 3a and 3b, the size of the first temperature-distributing layer 51 can also be smaller than the size of the first bare chip 10, and the first temperature-distributing layer 51 partially covers the first bare chip 10.

[0177] In some possible implementations, as shown in Figures 6a and 6b, in addition to covering the surface of the first bare chip 10 facing away from the first carrier 20, the first temperature-balancing layer 51 may also cover the sidewalls of the first bare chip 10. That is, the first temperature-balancing layer 51 extends from the surface of the first bare chip 10 facing away from the first carrier 20 to the sidewalls of the first bare chip 10. In this way, the first temperature-balancing layer 51 not only conducts heat generated by the first bare chip 10 in the direction of a plane perpendicular to the Z direction, but also conducts heat generated by the first bare chip 10 in the Z direction, further improving the temperature-balancing capability of the first bare chip 10, further effectively dissipating heat from the first bare chip 10, avoiding frequency reduction due to the high temperature of the first bare chip 10, and improving the performance of the first bare chip 10.

[0178] In some possible implementations, as shown in FIG. 6 a , the first temperature-distributing layer 51 completely covers the sidewalls of the first bare chip 10 ; or, as shown in FIG. 6 b , the first temperature-distributing layer 51 partially covers the sidewalls of the first bare chip 10 .

[0179] In some embodiments, as shown in FIG7 a , the chip package structure may further include a barrier layer 61. The barrier layer 61 is located between the first bare chip 10 and the first temperature-distributing layer 51 to prevent copper from migrating from the first temperature-distributing layer 51 into the first bare chip 10, thereby preventing a short circuit within the first bare chip 10. Optionally, the barrier layer 61 may be made of at least one of titanium, nickel, tungsten, and titanium-tungsten.

[0180] Furthermore, the conductive structure of the first bare chip 10 is exposed. For example, in some applications, a metal network is provided on the back of the first bare chip 10 to electrically connect the first bare chip 10 to an external circuit. To prevent the conductive structure of the first bare chip 10 from short-circuiting with the first temperature-balancing layer 51, the barrier layer 61 may optionally include an insulating material to prevent the conductive structure of the first bare chip 10 from being exposed, which could result in a short-circuit between the conductive structure of the first bare chip 10 and the first temperature-balancing layer 51.

[0181] The metal network may be, for example, a backside power supply network, which may be formed after the first bare chip 10 is thinned.

[0182] In some possible implementations, as shown in FIG7 b , the barrier layer 61 may include a first barrier layer 611 and a second barrier layer 612. The first barrier layer 611 includes an insulating material to prevent the exposed conductive structure of the first bare chip 10 from short-circuiting through the first temperature-distributing layer 51. The second barrier layer 61 includes at least one of titanium, nickel, tungsten, and titanium-tungsten to prevent copper in the first temperature-distributing layer 51 from migrating to the first bare chip 10.

[0183] The first barrier layer 611 is disposed between the first bare chip 10 and the second barrier layer 612 .

[0184] In some possible implementations, as shown in FIG8 , the chip package structure may further include a seed layer 62 . The seed layer 62 may be made of copper. Typically, the thickness of the seed layer 62 is less than that of the first temperature-balancing layer 51 .

[0185] S130, as shown in Figures 19a-19d, an interposer 71 and a filling layer 74 are sequentially formed on the side of the first bare chip 10 facing away from the first carrier 20. The first carrier 20 and the interposer 71 are electrically connected via first solder balls 81. By providing the filling layer 74 in the gap between the interposer 71 and the second carrier 72, the filling layer 74 can be used to conduct heat to the interposer 71.

[0186] In some possible implementations, the embodiment of the present application does not limit the material of the filling layer 74 , as long as the heat conduction effect of the filling layer 74 on the intermediate layer 71 is better than the heat conduction effect of air on the intermediate layer 71 .

[0187] Considering that phase change material (PCM) has the characteristic of absorbing heat without changing its own temperature, the material of the filling layer 74 may optionally include phase change material.

[0188] In some possible implementations, as shown in FIG19a , interposer 71 can be soldered to first carrier 20 via diebonding. Furthermore, as shown in FIG19b , before forming retaining walls 75 and filler layer 74, a second diebonding and molding process can be performed to form solder and molding compound 83 between first carrier 20 and interposer 71, thereby completely encapsulating the first carrier 20 and interposer 71. The solder formed by these two diebonding processes forms first solder balls 81.

[0189] As mentioned above, the first plastic encapsulation occurs before the first temperature-balancing layer 51 is formed. The first plastic encapsulation can pre-fix the first bare chip 10 on the first carrier 20. Therefore, neither the subsequent step S120 of forming the first temperature-balancing layer 51 on the first bare chip 10 nor the second plastic encapsulation will cause the first bare chip 10 to warp, thereby avoiding the first bare chip 10 from being unable to effectively electrically connect to the first carrier 20 due to the warping of the first bare chip 10.

[0190] In some possible implementations, as shown in FIG19c , before forming the filling layer 74, a retaining wall 75 may be formed on the interposer 71. Then, as shown in FIG19d , the filling layer 74 is formed at the location encircled by the retaining wall 75, under the protection of the retaining wall 75. That is, as shown in FIG11b and FIG19d , the retaining wall 75 is located outside the filling layer 74 and surrounds the filling layer 74.

[0191] In some possible implementations, the present invention does not limit the material of retaining wall 75, as long as retaining wall 75 can be fixed on interposer 71 before forming filling layer 74 and acts as a dam to prevent overflow of filling layer 74. Optionally, retaining wall 75 can be made of a high-viscosity molding compound.

[0192] In some possible implementations, the thickness of the filling layer 74 along the direction from the first carrier 20 toward the first bare chip 10 is greater than or equal to the thickness of the retaining wall 75. This avoids the situation where the retaining wall 75 is thicker than the filling layer 74, resulting in a gap between the filling layer 74 and the second carrier 72, preventing the filling layer 74 from maximally utilizing the available space to conduct heat between the interposer 71 and the second carrier 72. Furthermore, if the filling layer 74 is made of a phase-change material, its hardness decreases when heated. Therefore, even if the filling layer 74 is thicker than the retaining wall 75, its thickness can gradually become equal to that of the retaining wall 75 as the temperature changes.

[0193] S140 , as shown in FIG. 20 a , provides a second carrier board 72 and a second bare chip 73 , and the second bare chip 73 is packaged on the second carrier board 72 .

[0194] In some possible implementations, as shown in Figure 20a, the surface of the second bare chip 73 facing away from the first bare chip 10 includes a first solder pad 731, and the surface of the second carrier 72 facing away from the first bare chip 10 includes a second solder pad 721, and the first solder pad 731 is electrically connected to the second solder pad 721 through a binding wire 77.

[0195] Next, as shown in FIG20b , a molding compound 82 is formed on the side of the second die 73 facing away from the first die 10. The molding compound 83 covers the bonding wires 77, the sidewalls of the second die 73, and the first solder pads 731. The molding compound 83 includes an opening that exposes a portion of the surface of the second die 73 facing away from the first die 10. Next, as shown in FIG20c , a second temperature-balancing layer 52 is filled in the opening.

[0196] By replacing the plastic encapsulation material 83 with a higher thermal resistance with the second temperature-averaging layer 52, the second temperature-averaging layer 52 can be used to conduct the heat generated by the second bare chip 73 in the direction of the plane perpendicular to the Z direction, effectively improving the temperature-averaging ability of the second bare chip 73, enabling the second bare chip 73 to effectively dissipate heat, avoiding frequency reduction due to the high temperature of the second bare chip 73, and improving the performance of the second bare chip 73.

[0197] In some possible implementations, as shown in FIG14 a , the second temperature-distributing layer 52 is located in the opening; as shown in FIG14 b , the second temperature-distributing layer 52 is located not only in the opening but also on the side of the molding compound 83 away from the first bare chip 10 .

[0198] In some possible implementations, the material of the second temperature-balancing layer 52 is the same as that of the first temperature-balancing layer 51 , which will not be described in detail here.

[0199] In some possible implementations, the entire second temperature-balancing layer 52 can be filled in the opening by screen printing or bonding. For example, a layer of metallic paint can be printed on the second bare chip 73 (or the second bare chip and the molding compound). Alternatively, a prefabricated sheet of graphite or a graphite composite material can be preformed and then bonded to the second bare chip 73 (or the second bare chip and the molding compound).

[0200] In some possible implementations, the embodiment of the present application does not limit the order of steps S110 to S130 and step S140. Steps S110 to S130 and step S140 may be performed simultaneously; or, steps S110 to S130 may be performed first, and then step S140; or, step S140 may be performed first, and then step S110 to S130. Steps S110 to S130 are performed in the order of S110, S120, and S130.

[0201] S150, as shown in Figures 13-14b, uses second solder balls 82 to solder the second carrier 72 to the interposer 71. The interposer 71, second carrier 72, and second bare chip 73 are stacked in sequence along the direction from the first carrier 20 toward the first bare chip 10. The filling layer 74 is located between the interposer 71 and the second carrier 72, and the second solder balls 82 are located outside the filling layer 74 and the retaining wall 75.

[0202] In addition, other explanations and beneficial effects of the embodiments of the present application are the same as those of the previous embodiment and will not be repeated here.

[0203] In another embodiment, the present application provides a method for preparing a chip packaging structure, as shown in FIG21 , which can be implemented as follows:

[0204] S210 , as shown in FIG. 22 , a first temperature-balancing layer 51 is formed on the first bare chip 10 .

[0205] In some possible implementations, the embodiment of the present application differs from the previous embodiment in that the previous embodiment may perform step S110 on an uncut wafer before step S120. However, in the embodiment of the present application, the wafer has already been cut before step S210 is performed.

[0206] S220 , as shown in FIG. 18 , the first bare chip 10 with the first temperature-balancing layer 51 formed thereon is flip-packaged on the first carrier 20 .

[0207] In some possible implementations, the first temperature-distributing layer 51 is first formed on the back surface of the first bare chip 10, and then the first bare chip 10 is flip-packaged on the first carrier 20. The first bare chip 10 is typically flip-packaged on the first carrier 20 by bonding or welding. To prevent warping of the first temperature-distributing layer 51 caused by high temperatures during the bonding or welding process, the coefficient of thermal expansion (CTE) of the material of the first temperature-distributing layer 51 may be close to that of the substrate in the first bare chip 10. For example, the substrate in the first bare chip 10 may include silicon (Si), and the CTE of the material of the first temperature-distributing layer 51 may be between 2 ppm / °C and 7 ppm / °C. The material may include at least one of a diamond composite material (such as diamond copper and diamond aluminum), silicon carbide, and boron nitride (BN).

[0208] At step S230, as shown in Figures 19a to 19d, an interposer 71 and a filling layer 74 are sequentially formed on the side of the first bare chip 10 facing away from the first carrier 20. The first carrier 20 and the interposer 71 are electrically connected via first solder balls 81. Providing the filling layer 74 in the gap between the interposer 71 and the second carrier 72 allows for heat conduction from the filling layer 74 to the interposer 71.

[0209] S240 , as shown in FIG. 20 a , provides a second carrier board 72 and a second bare chip 73 , and the second bare chip 73 is packaged on the second carrier board 72 .

[0210] In some possible implementations, the present embodiment does not limit the order of steps S210 to S230 and step S240. Steps S210 to S230 and step S140 may be performed simultaneously; alternatively, steps S210 to S230 may be performed first, followed by step S240; alternatively, step S240 may be performed first, followed by steps S210 to S230. Steps S210 to S230 are performed in the order of S210, S220, and S230.

[0211] S250, as shown in Figures 13-14b, uses second solder balls 82 to solder the second carrier 72 to the interposer 71. The interposer 71, second carrier 72, and second bare chip 73 are stacked in sequence along the direction from the first carrier 20 toward the first bare chip 10. The filling layer 74 is located between the interposer 71 and the second carrier 72, and the second solder balls 82 are located outside the filling layer 74 and the retaining wall 75.

[0212] The process of steps S230 to S250 is the same as that of steps S130 to S150 in the previous embodiment, and will not be repeated here. Other explanations and beneficial effects are the same as those of the above two embodiments, and will not be repeated here.

[0213] The embodiments of the present application are described above in conjunction with the accompanying drawings, but the present application is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of this application, ordinary technicians in this field can also make many forms without departing from the purpose of this application and the scope of protection of the claims, all of which are within the protection of this application.

Claims

1. A chip packaging structure, characterized in that, It includes a first carrier board, a first bare chip, an interposer, a second carrier board, and a second bare chip that are stacked in sequence; The first bare chip is flip-chip packaged on the first carrier board, and the second bare chip is packaged on the second carrier board; the interposer is electrically connected to the first carrier board and the second carrier board respectively; The chip packaging structure further includes a first heat spreader, and the first heat spreader is disposed between the first bare chip and the interposer.

2. The chip packaging structure according to claim 1, wherein The surface of the first bare chip facing away from the first carrier board includes a groove; the first heat spreader includes a first heat spreading portion and a second heat spreading portion, the first heat spreading portion is located in the groove, and the second heat spreading portion is disposed at other positions between the first bare chip and the interposer.

3. The chip packaging structure according to claim 2, characterized in that, Along the direction from the first carrier board to the first bare chip, the thickness of the first heat spreading portion is greater than the thickness of the second heat spreading portion.

4. The chip packaging structure according to claim 2 or 3, characterized in that, The first heat spreading portion includes a stack of copper, diamond, and copper; the material of the second heat spreading portion includes at least one of silicon carbide, copper, graphite, and graphite composite material.

5. The chip package structure according to any one of claims 2-4, characterized in that, The first bare chip is divided into a hot spot projection area and other areas, and the temperature of the part of the first bare chip located in the hot spot projection area is higher than the temperature of the part of the first bare chip located in the other areas; The first heat spreading portion is located in the hot spot projection area, and the second heat spreading portion is located in the other areas.

6. The chip packaging structure according to any one of claims 1-5, characterized in that, The chip packaging structure includes a barrier layer, and the barrier layer is located between the first bare chip and the first heat spreader.

7. The chip packaging structure according to any one of claims 1-5, wherein The interposer is electrically connected to the first carrier board through a first solder ball, and the first solder ball is located outside the first bare chip and the first heat spreader; The interposer is also electrically connected to the second carrier board through a second solder ball; the chip packaging structure further includes a filling layer, and the filling layer is disposed between the interposer and the second carrier board; wherein, the second solder ball is located outside the filling layer.

8. The chip packaging structure according to claim 7, wherein, The material of the filling layer includes a phase change material.

9. The chip packaging structure according to claim 7 or 8, characterized in that The chip packaging structure further includes a retaining wall, and the retaining wall is disposed between the second carrier board and the interposer; Wherein, along the direction from the filling layer to the second solder ball, the filling layer, the retaining wall, and the second solder ball are arranged in sequence.

10. The chip packaging structure according to claim 9, characterized in that, Along the direction from the first carrier board to the first bare chip, the thickness of the filling layer is greater than or equal to the thickness of the retaining wall.

11. The chip packaging structure according to any one of claims 7-10, wherein, The chip packaging structure further includes a solder layer, and the solder layer is disposed between the first heat spreader and the interposer.

12. The chip packaging structure according to any one of claims 7-11, characterized in that, The chip packaging structure further includes a molding compound and a second heat spreader; The surface of the second bare chip facing away from the first bare chip includes a first pad, and the surface of the second carrier board facing away from the first bare chip includes a second pad, and the first pad is electrically connected to the second pad through a bonding wire; the molding compound covers the bonding wire, The side wall of the second bare chip and the first pad; The encapsulant includes an opening that exposes a partial surface of the second bare chip on a side facing away from the first bare chip, and the second heat spreader is at least filled in the opening.

13. The chip packaging structure according to claim 12, characterized in that, The chip package structure further includes an adhesive layer disposed between the encapsulant and the second heat spreader.

14. The chip packaging structure according to claim 12 or 13, wherein The materials of the first heat spreader and the second heat spreader both include at least one of silicon carbide, copper, graphite, graphite composite material, diamond, and diamond composite material.

15. A method for preparing a chip packaging structure, characterized in that, Including: Forming a first heat spreader on the first bare chip; wherein, the first bare chip is flip-chip packaged on the first carrier, and the first carrier and the first heat spreader are respectively disposed on opposite sides of the first bare chip; Forming an interposer on a side of the first heat spreader facing away from the first bare chip, and the interposer is electrically connected to the first carrier; Encapsulating a second bare chip on a second carrier and fixing the second carrier on the interposer; wherein, the interposer is electrically connected to the second carrier, and the second carrier is disposed between the interposer and the second bare chip.

16. The preparation method according to claim 15, characterized in that, The forming the first heat spreader on the first bare chip includes: Flip-chip packaging the first bare chip on the first carrier, and forming solder and encapsulant on the first carrier and the first bare chip; Thinning a side of the first bare chip facing away from the first carrier, as well as the solder and the encapsulant; Forming a first heat spreader on a side of the first bare chip facing away from the first carrier; Forming solder and encapsulant on the first carrier again.

17. The preparation method according to claim 15, characterized in that, After forming the first heat spreader on the first bare chip, the manufacturing method further includes: Flip-chip packaging the first bare chip with the first heat spreader formed thereon on the first carrier.

18. The preparation method according to any one of claims 14-16, characterized in that, The forming the interposer on a side of the first heat spreader facing away from the first bare chip, and the interposer is electrically connected to the first carrier, includes: Forming an interposer on a side of the first heat spreader facing away from the first bare chip, and the interposer is electrically connected to the first carrier through a first solder ball; the first solder ball is located at the periphery of the first bare chip and the first heat spreader; The fixing the second carrier on the interposer includes: Fixing the second carrier on the interposer by using a second solder ball, so that the second carrier is electrically connected to the interposer; After forming the interposer on a side of the first heat spreader facing away from the first bare chip, the manufacturing method further includes: Forming a filling layer on a side of the interposer facing away from the first bare chip, and the filling layer is located between the interposer and the second carrier; the second solder ball is located at the periphery of the filling layer.

19. The preparation method according to claim 18, wherein A surface of the second bare chip on a side facing away from the first bare chip includes a first pad, and a surface of the second carrier on a side facing away from the first bare chip includes a second pad, and the first pad is electrically connected to the second pad through a bonding wire; After encapsulating the second bare chip on the second carrier and before fixing the second carrier on the interposer, the manufacturing method further includes: A molding compound is formed on a side of the second bare die facing away from the first bare die; the molding compound covers the bonding wires, sidewalls of the second bare die, and the first pad; the molding compound includes an opening that exposes a partial surface of the second bare die on the side facing away from the first bare die; A second thermal spreader is filled in the opening.

20. An electronic device, characterized in that, It includes a circuit board, a third solder ball, and the chip packaging structure according to any one of claims 1-14, and the first carrier of the chip packaging structure is soldered to the circuit board through the third solder ball.

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