Modes of operation for a synchronous converter

Abstract

A mechanism for controlling a synchronous converter comprising two switches that connect to a switch node. A first switch connects the switch node to a first node. A second switch connects the switch node to a ground or return path. An inductor connects the switch node to a second node. In a low load mode of operation, one of the two switches is activated to cause the inductor to charge. The switches are then deactivated to cause the voltage at the switch node to approach the voltage of either the first node or the ground or return path, dependent upon which switch was activated during charging of the inductor. The switches are then controlled to allow the voltage at the switch node to oscillate one or more times.

Description

[0001] Modes of operation for a synchronous converter

[0002] FIELD OF THE INVENTION

[0003] The present invention relates to the field of synchronous converters, and in particular to control modes for synchronous converters.

[0004] BACKGROUND OF THE INVENTION

[0005] Synchronous converters, such as synchronous buck or boost converters, are becoming increasingly popular for use in driving loads with variable power demands, such as dimmable LED loads. Moreover, recent development of transistors, such as the production of GaN or SiC transistors, has made small and highly efficient synchronous buck or boost converters possible.

[0006] A synchronous converter will often be associated with a maximum load rating, being the maximum power rating of a load that can draw power from the synchronous converter. It is desirable for the synchronous converter to be able to efficiently provide power to loads having a power rating between zero (or negligible) and the maximum load rating. In other words, it is desirable for the synchronous converter to provide a full load range, with low losses.

[0007] However, to facilitate a full load range whilst maintaining zero-voltage switching (ZVS) within the synchronous converter (for efficiency), it is currently required to provide a large switching frequency range. As the power demanded by a load decreases, so the switching frequency required to maintain zero-voltage switching increases.

[0008] In a synchronous converter, the reactive current is adjusted to operate close to the ZVS limit, in order to keep the rms current at a minimum. To achieve this, in existing or known circuitry embodiments, the frequency at no load would increase by more than a factor of three with respect to the maximum frequency for a load at the maximum load rating. Typically, such a large increase is considered impractical, and the frequency will be simply clamped to a convenient value well below that frequency required for ZVS at low loads. This will naturally result in a large increase of the rms current, which can be more than three times the current required for ZVS (meaning 10 times the rms losses). There is therefore a desire to improve the performance of a synchronous converter, especially at low loads.

[0009] SUMMARY OF THE INVENTION

[0010] The invention is defined by the claims.

[0011] According to examples in accordance with an aspect of the invention, there is provided a synchronous converter arrangement comprising: a first switch connected between a first node and a switch node; a second switch connected between the switch node and a ground or return path; an inductor connected between the switch node and a second node; a control arrangement configured to controllably activate and deactivate the first switch and the second switch, wherein the control arrangement is operable in at least a first low load mode.

[0012] When operating in the first low load mode, the control arrangement is configured to sequentially: for a first period of time, activate the first switch to cause the inductor to store energy; for a second, subsequent period of time, deactivate both the first switch and the second switch at least until the current through the inductor is expected to perform a zero crossing to thereby cause the voltage at the switch node to approach the voltage of the ground or return path; and for a third, subsequent period of time, deactivate both the first switch and the second switch to allow the voltage at the switch node to resonantly oscillate until the voltage at the switch node is expected to perform one or more resonant oscillations and reach the voltage at the first node.

[0013] The present disclosure effectively proposes the use of one or more low load modes for the control arrangement that act as or facilitate an idle or near idle mode for the synchronous converter. Each low load mode may therefore be labelled an idle mode.

[0014] When the control arrangement operates in a low load mode, the synchronous converter undergoes a sequence of periods or intervals including: a first inductor charging interval during which one of the switches is activated; a full swing interval of the voltage at the switch node between the voltage of the first node and the voltage of the ground or return path (or vice versa); a second inductor charging interval; and a resonant oscillation period in which the voltage at the switch node performs N resonant oscillations. This sequence of periods may be iteratively repeated whilst the control arrangement continues to operate in the low load mode.

[0015] The control arrangement may alternate between operating in a power mode of operation (in which the converter is controlled conventionally to provide power to a load) and a low load mode of operation. This can effectively facilitate provision of any desired power (up to a maximum load rating) to a load connected to the converter. This may, for instance, facilitate controllable dimming (if the load comprises one or more LEDs).

[0016] By facilitating one or more resonant oscillations at the switch node, a switching frequency of the switch node is significantly reduced without loss of power and / or increasing noise. The provision of the voltage swing interval(s) between the first node voltage and the ground voltage (or vice versa) facilitates or initiates the oscillation at the switch node, whilst also affording the opportunity to perform power transfer with zerovoltage switching. The latter advantage can be achieved by appropriate activation of a switch when the switch node voltage reaches the first node voltage or the ground voltage.

[0017] In some examples, the control arrangement may be configured to operate in the first low load mode only when the voltage at the second node is no less than half the voltage at the first node.

[0018] Here, a full resonant transition of the switch node between the voltage of the first node and ground node is only achieved if the inductor has been previously charged (for a predetermined time to a predetermined value) via the first switch in a first period of time.

[0019] On the other hand, if the voltage of the second node voltage is less than half the voltage of the first node, then the transition of the switch node voltage between ground and the voltage of the first node will require an initial inductor current, which then, is performed by activating the second switch.

[0020] The control arrangement may be configured to operate in the first low load mode only when there is no or negligible load drawing power from the synchronous converter arrangement.

[0021] The control arrangement may be further operable in a second low load mode in which the control arrangement is configured to sequentially: for a fourth period of time, activate the second switch to cause the inductor to store energy; for a fifth, subsequent period of time, deactivate both the first switch and the second switch at least until the current through the inductor is expected to perform a zero crossing to thereby cause the voltage at the switch node to approach the voltage at the first node; and for a sixth, subsequent period of time, deactivate both the first switch and the second switch to allow the voltage at the switch node to resonantly oscillate, until the voltage at the switch node is expected to perform one or more resonant oscillations and reach the voltage at the ground or return path.

[0022] In some examples, the control arrangement is configured to operate in the second low load mode only when the voltage at the second node is no more than half the voltage at the first node. In some examples, the control arrangement is configured to operate in the second low load mode only when there is no or negligible load drawing power from the synchronous converter arrangement.

[0023] In some examples, the control arrangement is further operable in a third low load mode in which the control arrangement is configured to sequentially: for a seventh period of time, activate the second switch to cause the inductor to store energy; for an eighth, subsequent period of time, deactivate both the first switch and the second switch at least until the current through the inductor is expected to perform a zero crossing to thereby cause the voltage at the switch node to approach the voltage at the first node; for a ninth, subsequent period of time, activate the first switch to allow power to flow between the first node and the second node; and for a tenth, subsequent period of time, deactivate both the first switch and the second switch to allow the voltage at the switch node to resonantly oscillate, until the voltage at the switch node is expected to perform one or more resonant oscillations and reach the voltage at the ground or return path.

[0024] In some examples, the control arrangement is configured to operate in the third low load mode only when the voltage at the second node is no more than half the voltage at the first node.

[0025] In some examples, during the third period of time in the first low mode, the voltage at the switch node is expected to perform two or more resonant oscillations.

[0026] In some examples, the control arrangement is further operable in a fourth low load mode in which the control arrangement is configured to sequentially: for an eleventh period of time, activate the first switch to cause the inductor to store energy; for a twelfth, subsequent period of time, deactivate both the first switch and the second switch at least until the current through the inductor is expected to perform a zero crossing to thereby cause the voltage at the switch node to approach the voltage at the ground or return path; for a thirteenth, subsequent period of time, activate the second switch to allow power to flow between the first node and the second node; and for a fourteenth, subsequent period of time, deactivate both the first switch and the second switch to allow the voltage at the switch node to resonantly oscillate, until the voltage at the switch node is expected to perform one or more resonant oscillations and reach the voltage at the first node.

[0027] In some examples, the control arrangement is configured to operate in the fourth low load mode only when the voltage at the second node is no less than half the voltage at the first node. The synchronous converter arrangement may further comprise a first capacitor connected between the second node and the ground or return path.

[0028] The synchronous converter arrangement may further comprise a second capacitor connected between the second node and the first node.

[0029] The synchronous converter arrangement may further comprise a third capacitor connected between the first node and the ground or return path.

[0030] In some examples, the length of the third period of time is dependent upon a resonant frequency of the switch node.

[0031] In some examples, the first switch is a first FET and the second switch is a second FET.

[0032] The synchronous converter arrangement may be configured to control a voltage at a gate of the first FET to controllably activate and deactivate the first switch; and control a voltage at a gate of the second FET to controllably activate and deactivate the second switch.

[0033] These and other aspects of the invention will be apparent from and elucidated with reference to the embodiment s) described hereinafter.

[0034] BRIEF DESCRIPTION OF THE DRAWINGS

[0035] For a better understanding of the invention, and to show more clearly how it may be carried into effect, reference will now be made, by way of example only, to the accompanying drawings, in which:

[0036] Fig. 1 illustrates a synchronous converter;

[0037] Fig. 2 illustrates waveforms during a first low load mode;

[0038] Fig. 3 illustrates waveforms during a variant to the first low load mode;

[0039] Fig. 4 is a state plane trajectory diagram during the first low load mode;

[0040] Fig. 5 illustrates waveforms during a second low load mode;

[0041] Fig. 6 illustrates waveform during a variant to the second low load mode;

[0042] Fig. 7 is a state plane trajectory diagram during the second low load mode;

[0043] Fig. 8 illustrates waveforms during a third low load mode; and

[0044] Fig. 9 illustrates waveforms during a fourth low load mode.

[0045] DETAILED DESCRIPTION OF THE EMBODIMENTS

[0046] The invention will be described with reference to the Figures. It should be understood that the detailed description and specific examples, while indicating exemplary embodiments of the apparatus, systems and methods, are intended for purposes of illustration only and are not intended to limit the scope of the invention. These and other features, aspects, and advantages of the apparatus, systems and methods of the present invention will become better understood from the following description, appended claims, and accompanying drawings. It should be understood that the Figures are merely schematic and are not drawn to scale. It should also be understood that the same reference numerals are used throughout the Figures to indicate the same or similar parts.

[0047] The invention provides a mechanism for controlling a synchronous converter comprising two switches that connect to a switch node. A first switch connects the switch node to a first node. A second switch connects the switch node to a ground or return path. An inductor connects the switch node to a second node. In a low load mode of operation, one of the two switches is activated to cause the inductor to charge. The switches are then deactivated to cause the voltage at the switch node to approach the voltage of either the first node or the ground or return path, dependent upon which switch was activated during charging of the inductor. The switches are then controlled to allow the voltage at the switch node to oscillate one or more times.

[0048] Figure 1 illustrates a generic synchronous converter 100 in which proposed approaches may be employed. The generic synchronous converter 100 can be configured for operating as a boost converter or a buck converter.

[0049] The synchronous converter 100 comprises a first switch SI connected between a first node N 1 and a switch node x; a second switch S2 connected between the switch node x and a ground or return path GND; an inductor LI connected between the switch node x and a second node N2; and a control arrangement 150 configured to controllably activate and deactivate the first switch and the second switch.

[0050] The first switch SI and the second switch S2 may both be embodied as a fieldeffect transistor, such as a MOSFET or an HEMT (e.g., the GaN HEMT). However, any suitable form of electrically controllably switch could be employed, e.g., any form of transistor having a body diode or diode conduction mode.

[0051] A switch is activated when it is controlled to allow bidirectional current flow therethrough, and is deactivated when it is controlled to prevent or restrict bidirectional current flow. Of course, each switch may comprise or define a body diode that permits or allows unidirectional current when deactivated. The control arrangement may be configured, for instance, to control a gate-source voltage at a switch in order to controllably activate and deactivate the switch.

[0052] Thus, the control arrangement may be configured to: control a voltage at a gate of the first switch (e.g., first FET) to controllably activate and deactivate the first switch; and control a voltage at a gate of the second switch (e.g., second FET) to controllably activate and deactivate the second switch.

[0053] For the sake of convenience in this disclosure, it is assumed that a high gatesource voltage at a switch will cause the switch to become conductive, with a low gate-source voltage causing the switch to block or restrict a flow of current. Thus, it can be assumed that each switch is an n-type or n-channel switch. Alternative approaches may effectively configure the switch(es) to operate in reverse.

[0054] An alternative label for the first switch SI is a high-side switch. An alternative label for the second switch S2 is a low-side switch. Where the switches are embodied as FETs, the first switch SI may be labelled a first FET or a high-side FET and the second switch S2 may be labelled a second FET or low-side FET.

[0055] To function as a buck converter, a power supply is provided to the first node N 1. The voltage at the second node N2 acts as the output to the buck converter. Thus, when the converter 100 operates as a buck converter, a load will be connected to draw power from the second node N2. Approaches for controlling the activation of the first and second switches to perform a buck conversion process are well-established in the art.

[0056] To function as a boost converter, a power supply is provided to the second node N2. The voltage at the first node will act as the output to the boost converter. Thus, when the converter 100 operates as a boost converter, a load will be connected to draw power from the first node Nl. Approaches for controlling the activation of the first and second switches to perform a boost conversion process are well-established in the art.

[0057] In general, the control arrangement may be operable in one or more power modes, in which both switches are controllably activated and deactivated to facilitate power transfer between the first node and the second node. The precise switching timing depends upon the type of power transfer desired (e.g., buck conversion or boost conversion) as well as the desired magnitude of amplification.

[0058] The synchronous converter 100 may further comprise one or more capacitors Cl, C2, C3.

[0059] A first capacitor Cl may be connected between the second node N2 and the ground or return path GND, and acts as a power buffer or storage unit. In particular, the first capacitor Cl will buffer an output voltage when the synchronous converter functions as a buck converter. The first capacitor Cl will buffer an input voltage when the synchronous converter functions as a boost converter, as well as act as a low-pass noise filter for the input voltage.

[0060] A second capacitor C2 may be connected between the first node N 1 and the second node N2, and acts as a noise filter.

[0061] A third capacitor C3 may be connected between the first node N1 and the ground or return path GND, and acts as a power buffer or storage unit. In particular, the third capacitor C2 will buffer an output voltage when the synchronous converter functions as a boost converter. The second capacitor C2 will buffer an input voltage when the synchronous converter functions as a buck converter, as well as act as a low-pass noise filter for the input voltage.

[0062] The present disclosure provides a new set of operational modes, so-called low load modes, for the control arrangement. These operational modes are designed for use with low loads (i.e., small demands from a load). The proposed approaches facilitate low-loss operation at low load levels, with quick turn-on capability if a load is suddenly demanded.

[0063] More particularly, the proposed approaches facilitate lower frequency operation of the synchronous converter during low load operation than previously available. High switching frequencies are considered impractical, due to the difficulty in achieving high switching frequencies, as well as non-ideal effects such as turn-on or turn-off times of switches.

[0064] The proposed operational modes can be performed regardless of whether the converter 100 is operating as a buck converter or as a boost converter, and the principles of the operation(s) are near identical. Commentary will be made, where appropriate, on recommended (but not essential) practice for use of the proposed low load modes.

[0065] It is noted that, functionally, the voltage at the first node will be larger than the voltage at the second node, regardless of whether the converter acts as a buck converter or a boost converter. The proposed low load modes make use of this recognition.

[0066] In the following description, each low load mode of operation is described with reference to a single (repeatable) cycle. In use, one or more cycles of a particular low load mode of operation may be performed one or more times, e.g., in between rated load cycles to yield any level of power supply or demand to a load between zero and full load operation. This can, for instance, achieve any desired level of light dimming if the load comprises one or more LEDs. Figure 2 illustrates waveforms in the converter 100 during a (proposed) first low load mode of operation for the control arrangement 150.

[0067] The first low load mode of operation is particularly suited for use when the voltage at the second node is no less than half the voltage at the first node. Thus, in some examples, the control arrangement may be configured to operate in the first low load mode only when the voltage at the second node is no less than half the voltage at the first node.

[0068] Moreover, the first low load mode of operation is also particularly suited for use when there is no or negligible load drawing power from the synchronous converter arrangement. Thus, in some examples, the control arrangement is configured to operate in the first low load mode only when there is no or negligible load drawing power from the synchronous converter arrangement.

[0069] One waveform V(x) represents the voltage at the switch node (a “switch node voltage”); another waveform I(x) represents the current through the switch node, i.e., through the inductor LI; another waveform vgl represents the gate-source voltage at the first switch SI; and another waveform vg2 represents the gate-source voltage at the second switch S2.

[0070] Initially, the switch node voltage V(x) is at the voltage V(N1) of the first node (the first node voltage).

[0071] When operating in the first low load mode, the control arrangement sequentially operates in a first period of time, then a second period of time, then a third period of time.

[0072] During the first period of time (to - ti), the first switch is activated by the control arrangement to cause the inductor to store energy. In particular, the first switch is activated such that current flows from the first node and towards the second node (i.e., through the inductor). This causes the inductor to begin storing energy, such that the current at the inductor will rise.

[0073] During the second, subsequent period of time (ti - 1?), both the first switch and the second switch are deactivated by the control arrangement. The second period of time lasts at least until the current through the inductor is expected to perform a zero crossing, i.e., until the inductor “discharges”. The “discharging” of the inductor causes the voltage at the switch node to drop, so as to approach the voltage of the ground or return path (alternatively labelled the “ground voltage).

[0074] During the third, subsequent period of time (t2 - ti), both the first switch and the second switch remain deactivated by the control arrangement. This allows or causes the voltage at the switch node to resonantly oscillate at the resonant frequency of the converter. The third period of time is held until the voltage at the switch node is expected to perform one or more resonant oscillations and reach the voltage at the first node. In the illustrated example, the switch node voltage V(x) undergoes a single resonant oscillation 210.

[0075] At the end of the third period of time, one cycle of the first low load mode is completed.

[0076] After the third period of time, if continuing to operate in the first low load mode, the control arrangement will then revert back to operating as described with reference to the first period of time (i.e., another instance of the first period of time is performed).

[0077] The length of the first period of time will define how much energy is stored by the inductor. This, in turn, defines how closely the switch node voltage approaches the ground voltage. Preferably, the first period of time is chosen such that the switch node voltage reaches the ground voltage. Even more preferably, the first period of time is chosen such that the switch node voltage reaches the ground voltage, but remains at the ground voltage for no more than a predetermined period of time (e.g., to reduce a length of time that, or preferably prevent, the (body diode (or functional equivalent) of the) second switch from conducting current).

[0078] Appropriate selection of the length of the first period of time will depend upon the precise component values of the electronic components used to construct the synchronous converter as well as the first node voltage and the second node voltage, as would be readily apparent to the appropriately skilled person. More particularly, the length of the first period of time may be predetermined based on known values either of both the switch node capacitance and the inductance or of their resonant frequency only.

[0079] In practice, the length of the first period of time to - ti may be such that the switch node voltage reaches the ground voltage and remains at the ground voltage for a nonzero period of time (during the second time period ti - 1?). Thus, the second period of time may be conceptually sub-divided into a first sub-period of time ti - tr, during which the switch node voltage approaches the ground voltage and a second sub-period of time tr - 12, during which time the switch node voltage is held at the ground voltage. During this second sub-period of time tr - 12, the body diode (or functional equivalent) of the second switch will be conducting current (e.g., causing power loss). This power loss is due to the non-zero voltage drop of the body diode. Some forms of switches, such as the GaN HEMT, may comprise no body diode, however - the effective function of the switch behaves like there is one and conducts in a reverse direction when the gate is kept off at a voltage drop of a few volts. The length of the first period of time will control or define the length of the second sub-period of time. It may therefore be desirable if the first period of time is chosen to minimize or reduce the second sub-period of time, to reduce power loss in the converter. This configuration is particularly suitable when there is no or negligible load drawing power from the synchronous converter arrangement.

[0080] However, a non-zero length for the second sub-period of time tr - 12 may be advantageous for recharging any bootstrap circuitry (not illustrated in the Figures), such as driving circuitry, which may be used to drive the first switch. Thus, the length of the first period of time may be purposively selected to provide a non-zero length for the second subperiod of time, e.g., to facilitate charging of circuitry.

[0081] Moreover, a non-zero length for the second sub-period of time may cause a power transfer from the first node N1 to the second node N2. A non-zero second sub-period of time may therefore advantageously (e.g., if the converter is operating as a buck converter) facilitate transfer of power to a load drawing a small amount of power from the buck converter. This can thereby provide a small level of power transfer for low (but non-zero) loads.

[0082] In some examples, the length of the first period of time is controlled responsive to a power demand from the load (e.g., if the converter is operating as a buck converter). In particular, the length of the first period of time may be increased responsive to an increase in the power demand from the load. This facilitates control over the amount of power provided to the load.

[0083] Figure 3 illustrates waveforms in the converter 100 during a variant to the (proposed) first low load mode of operation for the control arrangement 150.

[0084] In this variant, two additional time periods are introduced, which take place between the second time period and the third time period. These time periods are labelled a first intermediate time period t2 - t2-i and a second intermediate time period t2-i - 12-2. The third time period t2-2 - ti takes place after the second intermediate time period.

[0085] In the first intermediate time period, the first and second switches SI, S2 are deactivated, such that the switch node voltage V(x) returns to the first node voltage V(N1). Current continues to flow through the switch node (and therefore the inductor).

[0086] In the second intermediate time period t2-i - 12-2, the first switch SI is activated with the second switch S2 remaining deactivated. This causes the inductor LI to discharge to zero. By activating the first switch SI in the second intermediate time period t2-i - 12-2, losses in the converter 100 are reduced, as the body diode (or functional equivalent) of the first switch does not conduct during this time period.

[0087] Controlling the switches to operate in this way during the first intermediate time period (to allow the switch node voltage to return to the first node voltage) facilitates zero-voltage switching of the switches.

[0088] However, it will be appreciated that it is not essential for the first switch SI to be activated during the second intermediate time period. Rather, both the first switch and the second switch may be maintained in a deactivated state through the first intermediate time period and the second intermediate time period. This effectively results in the control scheme described with reference to Figure 2.

[0089] It is recognized that the power savings due to the extra switching action would be relatively low because of the low current whilst complicating the control of the switches and disadvantageously increasing the effective switching frequency of the switches. High switching frequencies are considered impractical.

[0090] Figure 4 is a state plane trajectory diagram of the switch node voltage V(x) against the switch node current I(x) for the first low load mode of operation. This aids in the conceptual understanding of the voltage and current fluctuations throughout the first low load mode of operation.

[0091] Figure 5 illustrates waveforms in the converter 100 during a (proposed) second low load mode of operation for the control arrangement 150.

[0092] The second low load mode of operation is particularly suited for use when the voltage at the second node is less than half the voltage at the first node. Thus, in some examples, the control arrangement is configured to operate in the second low load mode only when the voltage at the second node is no more than half the voltage at the first node.

[0093] Moreover, the second low load mode of operation is also particularly suited for use when there is no or negligible load drawing power from the synchronous converter arrangement. Thus, in some examples, the control arrangement is configured to operate in the second low load mode only when there is no or negligible load drawing power from the synchronous converter arrangement.

[0094] One waveform V(x) represents the voltage at the switch node (a “switch node voltage”); another waveform I(x) represents the current through the switch node, i.e., through the inductor LI; another waveform vgl represents the gate-source voltage at the first switch SI; and another waveform vg2 represents the gate-source voltage at the second switch S2. Initially, the switch node voltage V(x) is at the voltage V(N1) of the ground or return path (ground).

[0095] When operating in the second low load mode, the control arrangement sequentially operates in a fourth period of time ton - , then a fifth period of time t4 - ts, then a sixth period of time ts - te.

[0096] For the fourth period of time, the control arrangement activates the second switch to cause the inductor to store energy. Current flows from the second node N2 in the direction of the ground or return path to charge the inductor.

[0097] For the fifth, subsequent period of time, the control arrangement deactivates both the first switch and the second switch. The fifth period of time lasts at least until the current through the inductor is expected to perform a zero crossing to thereby cause the voltage at the switch node to approach (and preferably reach) the voltage at the first node.

[0098] For the sixth, subsequent period of time, the control arrangement deactivates both the first switch and the second switch to allow the voltage at the switch node to resonantly oscillate. In the illustrated example, the switch node voltage V(x) undergoes two resonant oscillations 510, 520. However, the sixth, subsequent period of time may be selected or chosen to achieve or target any number of resonant oscillations.

[0099] The sixth period of time lasts until the voltage at the switch node is expected to perform one or more resonant oscillations and reach the voltage at the first node. At the end of the sixth period of time, one cycle of the second low load mode is completed.

[0100] After the sixth period of time, if continuing to operate in the second low load mode, the control arrangement will then revert back to operating at described with reference to the fourth period of time (i.e., another instance of the fourth period of time is performed).

[0101] The length of the fourth period of time will define how much energy is stored by the inductor. This, in turn, defines how closely the switch node voltage approaches the first node voltage during the fifth period of time. Preferably, the fourth period of time is chosen such that the switch node voltage reaches the first node voltage. Even more preferably, the fifth period of time is chosen such that the switch node voltage reaches the first node voltage, but remains at the first node voltage for no more than a predetermined period of time (e.g., to reduce a length of time that the (body diode (or functional equivalent) of the) first switch conducts current, or preferably prevent the (body diode (or functional equivalent) of the) first switch from conducting current).

[0102] Appropriate selection of the length of the fourth period of time - i.e., the length of time that the second switch is activate - will depend upon the precise component values of the electronic components used to construct the synchronous converter as well as the first node voltage and the second node voltage, as would be readily apparent to the appropriately skilled person. More particularly, the length of the fourth period of time may be predetermined based on known values either of both the switch node capacitance and the inductance or of their resonant frequency only.

[0103] In practice, the length of the fourth period of time ton - may be such that the switch node voltage reaches the first node voltage and remains at the first node voltage for a non-zero period of time (during the fifth time period - ts). Thus, the fifth period of time may be conceptually sub-divided into a third sub-period of time, during which the switch node voltage approaches the first node voltage and a fourth sub-period of time, during which the switch node voltage is held at the first node voltage (e.g., by the body diode (or functional equivalent) of the first switch). During this fourth sub-period of time, the body diode (or functional equivalent) of the first switch will be conducting current (e.g., causing power loss).

[0104] The length of the fourth period of time will control or define the length of the fourth sub-period of time. It may therefore be desirable, in some use-case scenarios, if the fourth period of time is chosen to minimize or reduce the length of the fourth sub-period of time, to reduce power loss in the converter.

[0105] However, a non-zero length for the fourth sub-period of time may cause a power transfer from the second node N2 to the first node Nl. A non-zero fourth sub-period of time may therefore advantageously (e.g., if the converter is operating as a boost converter) facilitate transfer of power to a load drawing a small amount of power from the boost converter, e.g., connected to the first node. This can thereby provide a small level of power transfer for low (but non-zero) loads.

[0106] In the illustrated example, the length of the first period of time has been appropriately selected such that the switch node voltage reaches the first node voltage (during the fifth period of time) without the body diode (or functional equivalent) of the first switch becoming conductive.

[0107] Figure 6 illustrates waveforms in the converter 100 during a variant to the (proposed) second low load mode of operation for the control arrangement 150.

[0108] In this variant, two additional time periods are introduced, which take place between the fifth time period and the sixth time period. These time periods are labelled a third intermediate time period ts - ts-i and a fourth intermediate time period ts-i - ts-2- The sixth time period ts-2 - te takes place after the fourth intermediate time period. In the third intermediate time period ts - ts-i, the first and second switches SI, S2 are deactivated, such that the switch node voltage V(x) returns to the ground voltage GND. Current continues to flow through the switch node (and therefore the inductor).

[0109] In the fourth intermediate time period ts-i - ts-2, the second switch S2 is activated with the first switch SI remaining deactivated. This causes the inductor LI to discharge to zero. By activating the second switch S2 in the fourth intermediate time period ts-i - ts-2, losses in the converter 100 are reduced, as the body diode (or functional equivalent) of the second switch does not need to conduct during this time period.

[0110] Controlling the switches to operate in this way during the third intermediate time period (to allow the switch node voltage to return to the ground voltage GND) facilitates zero-voltage switching of the switches.

[0111] However, it will be appreciated that it is not essential for the second switch S2 to be activated during the fourth intermediate time period. Rather, both the first switch and the second switch may be maintained in a deactivated state throughout the third intermediate time period and the fourth intermediate time period. This effectively results in the control scheme described with reference to Figure 2.

[0112] It is recognized that the power savings due to the extra switching action would be relatively low because of the low current whilst complicating the control of the switches and disadvantageously increasing the effective switching frequency of the switches.

[0113] Figure 7 is a state plane trajectory diagram of the switch node voltage V(x) against the switch node current I(x) for the second low load mode of operation. This aids in the conceptual understanding of the voltage and current fluctuations throughout the second low load mode of operation.

[0114] Figure 8 illustrates waveforms in the converter 100 during a (proposed) third low load mode of operation for the control arrangement 150. The third low load mode of operation is designed for transferring (some) power from the first node to the second node.

[0115] The third low load mode of operation is particularly suited for use when the voltage at the second node is no less than half the voltage at the first node. Thus, in some examples, the control arrangement is configured to operate in the third low load mode only when the voltage at the second node is no more than half the voltage at the first node.

[0116] Moreover, the third low load mode of operation is also particularly suited for use when there is a non-negligible load drawing power from the synchronous converter arrangement, particularly from the second node. This is because the third low mode of operation is designed for facilitating power transfer between the first and second nodes. Thus, in some examples, the control arrangement is configured to operate in the third low load mode only when there is a non-negligible load drawing power from the synchronous converter arrangement.

[0117] One waveform V(x) represents the voltage at the switch node (a “switch node voltage”); another waveform I(x) represents the current through the switch node, i.e., through the inductor LI; another waveform vgl represents the gate-source voltage at the first switch SI; and another waveform vg2 represents the gate-source voltage at the second switch S2.

[0118] Initially, the switch node voltage V(x) is at the voltage V(N1) of the ground or return path (ground).

[0119] When operating in the third low load mode, the control arrangement sequentially operates in a seventh period of time toe -t?, then an eighth period of time t? - ts, then a ninth period of time ts - to and then a tenth period of time to - tio.

[0120] For the seventh period of time toe - t?, the control arrangement is configured to activate the second switch to cause the inductor to store energy. This is similar to the operation for the fourth period of time described with reference to the second low load mode.

[0121] For the eighth, subsequent period of time t? - ts, the control arrangement is configured to deactivate both the first switch and the second switch until the current through the inductor is expected to perform a zero crossing to thereby cause the voltage at the switch node to approach the voltage at the first node. This is similar to the operation for the fifth period of time described with reference to the second low load mode.

[0122] For the ninth, subsequent period of time ts - 19, the control arrangement is configured to activate the first switch to allow power to flow between the first node and the second node. In particular, current is able to flow from the first node to the second node. This effectively causes (when the converter is operating as a buck converter) a transfer of power to any load connected to the second node.

[0123] For the tenth, subsequent period of time t9 - tio, the control arrangement is configured to deactivate both the first switch and the second switch to allow the voltage at the switch node to resonantly oscillate, until the voltage at the switch node is expected to perform one or more resonant oscillations and reach the voltage at the ground or return path. This is similar to the operation for the sixth period of time described with reference to the second low mode.

[0124] In one variant, two additional time periods are introduced, which take place between the ninth time period and the tenth time period. These time periods are labelled a fifth intermediate time period (not illustrated) and a sixth intermediate time period (not illustrated). The fifth intermediate time period takes place after the ninth time period. The sixth intermediate time period takes place after the fifth intermediate time period. The tenth time period takes place after the sixth intermediate time period.

[0125] In the fifth intermediate time period, the first and second switches SI, S2 are deactivated, such that the switch node voltage V(x) returns to the ground voltage GND. Current continues to flow through the switch node (and therefore the inductor).

[0126] In the sixth intermediate time period, the second switch S2 is activated with the first switch SI remaining deactivated. This causes the inductor LI to discharge to zero. By activating the second switch S2 in the sixth intermediate time period, losses in the converter 100 are reduced, as the body diode (or functional equivalent) of the second switch does not need to conduct during this time period.

[0127] Controlling the switches to operate in this way during the fifth intermediate time period, and particularly allowing the switch node voltage to return to the ground voltage GND, facilitates zero-voltage switching of the switches.

[0128] Figure 9 illustrates waveforms in the converter 100 during a (proposed) fourth low load mode of operation for the control arrangement 150. The fourth low load mode of operation is designed for transferring (some) power from the second node to the first node.

[0129] The fourth low load mode of operation is particularly suited for use when the voltage at the second node is no less than half the voltage at the first node. Thus, in some examples, the control arrangement is configured to operate in the fourth low load mode only when the voltage at the second node is no less than half the voltage at the first node.

[0130] Moreover, the fourth low load mode of operation is also particularly suited for use when there is a non-negligible load drawing power from the synchronous converter arrangement, particularly from the first node. This is because the fourth low mode of operation is designed for facilitating power transfer from the second node to the first node. Thus, in some examples, the control arrangement is configured to operate in the fourth low load mode only when there is a non-negligible load drawing power from the synchronous converter arrangement.

[0131] One waveform V(x) represents the voltage at the switch node (a “switch node voltage”); another waveform I(x) represents the current through the switch node, i.e., through the inductor LI; another waveform vgl represents the gate-source voltage at the first switch SI; and another waveform vg2 represents the gate-source voltage at the second switch S2.

[0132] Initially, the switch node voltage V(x) is at the voltage V(N1). When operating in the fourth low load mode, the control arrangement sequentially operates in an eleventh period of time too -tn, then a twelfth period of time tn - tn, then a thirteenth period of time tn - ti3 and then a fourteenth period of time ti3 - ti4.

[0133] For the eleventh period of time too - tn, the control arrangement 150 is configured to activate the first switch SI to cause the inductor to store energy. This is similar to the operation for the first period of time to - ti described with reference to the first low load mode.

[0134] For the twelfth, subsequent period of time tn - tn, the control arrangement 150 is configured to deactivate both the first switch SI and the second switch SI until the current through the inductor LI is expected to perform a zero crossing to thereby cause the voltage V(x) at the switch node x to approach the voltage V(N2) at the second node N2. This is similar to the operation for the second period of time ti - 12 described with reference to the first low load mode.

[0135] For the thirteenth, subsequent period of time tn - ti3, the control arrangement 150 is configured to activate the second switch S2 to allow power to flow between the first node N1 and the second node N2. In particular, current is able to flow from the second node N2 through the inductor LI. This effectively causes (e.g., when the synchronous converter 100 is operating as a boost converter) a transfer of power to any load connected to the first node N 1.

[0136] For the fourteenth, subsequent period of time ti3 - ti4, the control arrangement 150 is configured to deactivate both the first switch SI and the second switch S2 to allow the voltage V(x) at the switch node x to resonantly oscillate, until the voltage at the switch node is expected to perform one or more resonant oscillations and reach the voltage at the first node. This is similar to the operation for the third period of time t2 - ti described with reference to the first low mode.

[0137] In one variant, two additional time periods are introduced, which take place between the thirteenth time period and the fourteenth time period. These time periods are labelled a seventh intermediate time period (not illustrated) and an eighth intermediate time period (not illustrated). The seventh intermediate time period takes place after the thirteenth time period. The eighth intermediate time period takes place after the seventh intermediate time period. The fourteenth time period takes place after the eighth intermediate time period.

[0138] In the seventh intermediate time period, the first and second switches SI, S2 are deactivated, such that the switch node voltage V(x) returns to the voltage of the first node. Current continues to flow through the switch node (and therefore the inductor). In the eight intermediate time period, the first switch SI is activated with the second switch S2 remaining deactivated. This causes the inductor LI to discharge to zero. By activating the first switch SI in the eight intermediate time period, losses in the converter 100 are reduced, as the body diode (or functional equivalent) of the first switch does not need to conduct during this time period.

[0139] Controlling the switches to operate in this way during the seventh intermediate time period, and particularly allowing the switch node voltage to return to the first node voltage, facilitates zero-voltage switching of the switches.

[0140] Four low-low modes of operation for the control arrangement have been previously described. Table 1 illustrates preferred use-case scenarios for each low load mode. These options are dependent upon the specific use-case scenario and may depend upon whether a load is drawing power from one of the first and second nodes and / or whether there is a power leak within the synchronous converter (e.g., for driving or powering bootstrap or auxiliary circuitry).

[0141] In Table 1, the low load mode “1” represents a variant of the first low load mode in which the length of the second sub-period of time ti’ -t? is 0 or negligible (i.e., is omitted), the low load mode “1*” represents a variant of the first low load mode in which the length of the second sub-period of time ti -t2 is non-negligible.

[0142] In Table 1, the low load mode “2” represents a variant of the second low load mode in which the length of the fourth sub-period of time or negligible (i.e., is omitted), the low load mode “2*” represents a variant of the second low load mode in which the length of the fourth sub-period of time is non-negligible.

[0143] In Table 1, the low load mode “3” represents the third low load mode and the low load mode “4” represents the fourth low load mode.

[0144] Direction of Power Flow

[0145] Low load mode V(N2) N1 N2 N2 N1

[0146] 1 >1 / 2V(N1) N N

[0147] 1* >1 / 2V(N1) Y N

[0148] 4 >1 / 2V(N1) N Y

[0149] 2 <1 / 2V(N1) N N

[0150] 2* <1 / 2V(N1) N Y

[0151] 3 <1 / 2V(N1) Y N

[0152] TABLE 1

[0153] In any foregoing described mode of operation, the length of time that it will take a switch node voltage or current to reach a desired value (e.g., a ground voltage, a first node voltage, a zero current etc.) will depend upon the precise characteristics of the components that make up the synchronous converter - such as the inductance of the inductor, the capacitance of any capacitors, parasitic inductances and so on. Similarly, the length of time for a resonant oscillation of switch node voltage will depend upon such component values or a resonant frequency at the switch node (e.g., which may be separately determined using a frequency detection technique or known in advance).

[0154] It is therefore possible to predict an expected time or length of time that any given charging or discharging process will take, based on the component values of the synchronous converter and / or the resonant frequency at the switch node. Aforementioned mechanisms make use of time periods in which a current or voltage at the switch node is “expected” to reach a particular value. In this context, the term “expected” is therefore to be understood or defined as “expected for the known or determined component values of the synchronous converter or known or determined resonant frequency at the switch node”.

[0155] The low load modes proposed in this disclosure are thereby able to operate without the need to detect or respond to a voltage at the switch node whatsoever, i.e., without any feedback. Thus, each low load mode may function as an open-loop control modes for the control arrangement. Put another way, the first, second and / or third low load mode may be open-loop modes that perform open-loop control of the switches, i.e., operate without direct feedback.

[0156] It is recognized that one advantage of the proposed approach is the avoidance of any need to perform zero crossing detection and / or the need to provide processing or driving means able to immediately (e.g., with minimal delay) respond to a zero crossing. Thus, proposed approaches operate using an open-loop control system.

[0157] All above-described modes include a period of time during which the voltage at the switch node resonantly oscillates (or is expected to resonantly oscillate) one or more times.

[0158] In some examples, the number of oscillations is greater than one. This further reduces the switching frequency of the converter during the low load mode(s) of operation.

[0159] In some examples, the number of oscillations is less than 10, e.g., less than 5. The greater the number of oscillations, the less likely that zero-voltage switching - or nearzero-voltage switching will occur. In particular, the length of the time during which the switch node voltage oscillates may be dependent upon component values for the synchronous converter, e.g., to determine or predict the resonant frequency. Due at least to acceptable manufacturing tolerances, the actual resonant frequency of the switch node may differ from a predicted resonant frequency. Thus, extremely large numbers of resonant oscillations will cause the true voltage to drift from an expected voltage to an unacceptable degree, thereby preventing zero-voltage switching from occurring.

[0160] For the sake of completeness, it is noted that any above-described period of time is non-zero.

[0161] Variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed invention, from a study of the drawings, the disclosure and the appended claims. In the claims, the word “comprising” does not exclude other elements or steps, and the indefinite article “a” or “an” does not exclude a plurality.

[0162] The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.

[0163] If the term “adapted to” is used in the claims or description, it is noted the term “adapted to” is intended to be equivalent to the term “configured to”. If the term “arrangement” is used in the claims or description, it is noted the term “arrangement” is intended to be equivalent to the term “system”, and vice versa.

[0164] Any reference signs in the claims should not be construed as limiting the scope.

Claims

CLAIMS:

1. A synchronous converter arrangement (100) comprising: a first switch (SI) connected between a first node (Nl) and a switch node (x); a second switch (S2) connected between the switch node (x) and a ground or return path (GND); an inductor (LI) connected between the switch node (x) and a second node (N2); a control arrangement (150) configured to controllably activate and deactivate the first switch and the second switch, wherein the control arrangement is operable in at least a first low load mode in which the control arrangement is configured to sequentially: for a first period of time (to - ti), activate the first switch to cause the inductor to store energy; for a second, subsequent period of time (ti-t?), deactivate both the first switch and the second switch at least until the current (IA(X)) through the inductor is expected to perform a zero crossing to thereby cause the voltage (V(x)) at the switch node to approach the voltage of the ground or return path; and for a third, subsequent period of time (t2-ts), deactivate both the first switch and the second switch to allow the voltage at the switch node to resonantly oscillate until the voltage at the switch node is expected to perform one or more resonant oscillations (210) and reach the voltage at the first node.

2. The synchronous converter arrangement of claim 1, wherein the control arrangement is configured to operate in the first low load mode only when the voltage at the second node (V(N2)) is no less than half the voltage at the first node (V(N1)).

3. The synchronous converter arrangement of any of claims 1 or 2, wherein the control arrangement is configured to operate in the first low load mode only when there is no or negligible load drawing power from the synchronous converter arrangement.

4. The synchronous converter arrangement of any of claims 1 to 3, wherein the control arrangement is further operable in a second low load mode in which the control arrangement is configured to sequentially: for a fourth period of time (ton - ), activate the second switch to cause the inductor to store energy; for a fifth, subsequent period of time ( - ts), deactivate both the first switch and the second switch at least until the current through the inductor is expected to perform a zero crossing to thereby cause the voltage at the switch node to approach the voltage at the first node; and for a sixth, subsequent period of time (ts - te), deactivate both the first switch and the second switch to allow the voltage at the switch node to resonantly oscillate, until the voltage at the switch node is expected to perform one or more resonant oscillations and reach the voltage at the ground or return path.

5. The synchronous converter arrangement of claim 4, wherein the control arrangement is configured to operate in the second low load mode only when the voltage at the second node is no more than half the voltage at the first node.

6. The synchronous converter arrangement of claim 4 or 5, wherein the control arrangement is configured to operate in the second low load mode only when there is no or negligible load drawing power from the synchronous converter arrangement.

7. The synchronous converter arrangement of any of claims 1 to 4, wherein the control arrangement is further operable in a third low load mode in which the control arrangement is configured to sequentially: for a seventh period of time (toe - 1?), activate the second switch to cause the inductor to store energy; for an eighth, subsequent period of time (t? - ts), deactivate both the first switch and the second switch at least until the current through the inductor is expected to perform a zero crossing to thereby cause the voltage at the switch node to approach the voltage at the first node; for a ninth, subsequent period of time (ts - tg), activate the first switch to allow power to flow between the first node and the second node; andfor a tenth, subsequent period of time (t9 - tio), deactivate both the first switch and the second switch to allow the voltage at the switch node to resonantly oscillate, until the voltage at the switch node is expected to perform one or more resonant oscillations and reach the voltage at the ground or return path.

8. The synchronous converter arrangement of claim 7, wherein the control arrangement is configured to operate in the third low load mode only when the voltage at the second node is no more than half the voltage at the first node.

9. The synchronous converter arrangement of any of claims 1 to 8, wherein the control arrangement is further operable in a fourth low load mode in which the control arrangement is configured to sequentially: for an eleventh period of time, activate the first switch to cause the inductor to store energy; for a twelfth, subsequent period of time, deactivate both the first switch and the second switch at least until the current through the inductor is expected to perform a zero crossing to thereby cause the voltage at the switch node to approach the voltage at the ground or return path; for a thirteenth, subsequent period of time, activate the second switch to allow power to flow between the first node and the second node; and for a fourteenth, subsequent period of time, deactivate both the first switch and the second switch to allow the voltage at the switch node to resonantly oscillate, until the voltage at the switch node is expected to perform one or more resonant oscillations and reach the voltage at the first node.

10. The synchronous converter arrangement of claim 9, wherein the control arrangement is configured to operate in the fourth low load mode only when the voltage at the second node is no less than half the voltage at the first node.

11. The synchronous converter arrangement of any of claims 1 to 10, wherein, during the third period of time in the first low mode, the voltage at the switch node is expected to perform two or more resonant oscillations.

12. The synchronous converter arrangement of any of claims 1 to 11, further comprising: a first capacitor (Cl) connected between the second node (N2) and the ground or return path (GND); and / or a second capacitor (C2) connected between the second node (N2) and the first node (Nl); and / or a third capacitor (C3) connected between the first node (Nl) and the ground or return path (GND).

13. The synchronous converter arrangement of any of claims 1 to 12, wherein the length of the third period of time is dependent upon a resonant frequency of the switch node (x).

14. The synchronous converter arrangement of any of claims 1 to 13, wherein the first switch (SI) is a first FET and the second switch (S2) is a second FET.

15. The synchronous converter arrangement of claim 14, wherein the control arrangement is configured to: control a voltage at a gate of the first FET to controllably activate and deactivate the first switch; and control a voltage at a gate of the second FET to controllably activate and deactivate the second switch.

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