Printed circuit board and printed circuit board assembly

Abstract

A printed circuit board (1) that has a plurality of layers (11-18), the layers (11-18) including a top circuitry layer (11), the top circuitry layer (11) configured to contact a sensor chip (2), an analog ground layer (13) arranged below the top layer (11), the analog ground layer (13) configured to be connected to an analog ground or combined with the top layer (11) in a single layer (110), and a plurality of current carrying layers (15-18) arranged below the top circuitry layer (11) and the analog ground layer (13) and configured to carry alternating currents. At protective earth layer (14) is further provided which is configured to be connected to a chassis ground, an earth ground or a protective ground, wherein the protective earth layer (14) is arranged between the analog ground layer (13) and the uppermost (15) of the current carrying layers (15-18). A printed circuit board assembly with such a printed circuit board is also provided.

Description

[0001] Printed Circuit Board and Printed Circuit Board Assembly

[0002] Description

[0003] Field of the disclosure

[0004] The present disclosure relates a printed circuit board and to a printed circuit board assembly.

[0005] Background

[0006] It is known to integrate active and passive components of a power electronics device such as of a power converter on a printed circuit board. For example, power electronics modules may be attached to a printed circuit board (PCB), wherein the modules are electrically connected through high-voltage current carrying layers of the printed circuit board, also referred to as power lines. It is further known to measure the current carried by layers of a printed circuit board by means of current-sensor chips which are typically surface-mounted. Such current sensor chips are usually necessary for the functionality of power converters, by providing the electrical current measurement feedback. Indirect current measurement techniques have the advantage over direct current measurement techniques that the current does not need to be routed through a sensor but that it is sufficient that the current flows near the sensor.

[0007] More particularly, surface-mounted current-sensor chips for PCB based power electronics devices may be placed directly over power lines to sample the main current. However, a strong capacitive coupling exists between an analog ground layer of the PCB and the high voltage current carrying layers which carry an alternating current. Such strong capacitive coupling leads to EMI currents that are injected into the powering and signal wires of the current-sensor chip, thereby negatively affecting the performance of the current-sensor chip. Also, strong magnetic fields are generated at the boundary of the main power lines which induce eddy current in the analog ground layer that lead to an undesired heating of the PCB.

[0008] There is a need to reduce or avoid some or all of the above-mentioned negative effects.

[0009] There is a need provide a printed circuit board and a printed circuit board assembly that reduces capacitive coupling into an analog ground layer of the printed circuit board and alleviates the heating of the printed circuit board or at least provides a useful alternative to known printed circuit boards and / or printed circuit board assemblies.

[0010] Summary of the disclosure

[0011] In a first aspect, there is provided a printed circuit board that comprises a plurality of layers, the layers including a top circuitry layer, the top circuitry layer configured to contact a sensor chip; an analog ground layer arranged below the top layer or combined with the top layer in a single layer, the analog ground layer configured to be connected to an analog ground; and a plurality of current carrying layers arranged below the top circuitry layer and the analog ground layer and configured to carry alternating currents.

[0012] It is provided that the printed circuit board further comprises a protective earth layer which is configured to be connected to a chassis ground, an earth ground or a protective ground, wherein the protective earth layer is arranged between the analog ground layer and the uppermost of the current carrying layers.

[0013] Aspects of the present invention are thus based on the idea to minimize capacitive coupling and EMI currents related thereto by implementing a new earthed layer into the printed circuit board which is arranged between the analog ground layer and the current carrying layers. The added protective earth layer removes or at least reduces capacitive coupling in that EMI current flows through the protective earth layer instead of being injected in the analog ground layer and the top circuitry layer, thereby sheltering signals in the top circuitry layer from the current carrying layers, and thereby also sheltering sensor chips which are located on the top circuitry layer from EMI currents. Performance and reliability of the sensor chips are thus improved.

[0014] The protective earth layer is connected to one of a) chassis ground which is the ground of the metal housing in which the printed circuit board may be encased, or b) earth ground, or c) protective earth which is a safety ground that provides a low-impedance path to the earth ground. The analog ground layer is connected to analog ground which is a reference point for analog circuits of the printed circuit board.

[0015] It is pointed out that within the meaning of the present disclosure that side of the printed circuit board on which the sensor chip is located is always considered to be the top side, irrespective of the actual 3D position of the printed circuit board.

[0016] In some embodiments, the present invention regards electric field shielding of a magnetic sensor chip, wherein near field electric field and magnetic field shielding effects are separated. As the magnetic field is measured by the sensor chip, some of the magnetic field shall be retained, while the electric field shall be shielded. Accordingly, in such embodiment, the shielding is associated with shielding electrical fields and magnetic fields differently. There is thus a ratio of magnetic to electric field shielding. It is desired to remain enough magnetic field to measure by the sensor chip but not enough so that adjacent sensitive circuitry is affected. The ratio may be influenced by the thickness of the protective earth layer and / or by the number of grounding points, wherein a single grounding point provides for primarily shielding against electrical but not against magnetic fields.

[0017] In some embodiments, the protective earth layer is a copper layer or other metal layer (such as aluminum or silver) connected to chassis ground, earth ground, or protective earth. The analog ground layer may be a copper layer or other metal layer (such as aluminum or silver) connected to analog ground. The analog ground layer provides the return path for low-voltage signals in the top circuitry layer.

[0018] In some embodiments, the current carrying layers are configured to operate under high- voltage condition, which is alternating voltage of 1000 V or more. In some embodiments, the current carrying layers operate under less than 1000 V alternating voltage

[0019] In some embodiments, the top circuitry layer is a low-voltage signal circuit layer configured to carry low-voltage signals. Such low-voltage signals may include low-voltage signals of a sensor chip connected to the top circuitry layer.

[0020] In some embodiments, the analog ground layer and the top circuitry layer are combined into a single layer, wherein the top circuitry layer forms at least one confined area in the single layer, and wherein the analog ground layer occupies the area of the single layer around and between the at least one confined area. In such embodiments, the top layer includes both the circuitry layer and the analog ground layer. The subsequent layer is the protective earth layer.

[0021] In some embodiments, the printed circuit board comprises at least one further protective earth layer, wherein the protective earth layers are interconnected by one or several vertical electrical connections such as vertical plated holes. The further protective earth layer may be arranged on the opposite side of the plurality of current carrying layers.

[0022] In some embodiments, an area of the analog ground layer and / or of the protective earth layer that is arranged - in a top view on the printed circuit board - adjacent a boundary of the current carrying layers comprises slitting features configured to reduce eddy currents caused by the alternating current of the current carrying layers.

[0023] This aspect is based on the idea to reduce eddy currents in the analog ground layer which are caused by strong magnetic fields generated at the boundary of the current carrying layers (which are the main power lines of the printed circuit board), wherein the eddy currents are reduced in that a slitted architecture is implemented in those areas of the analog ground layer through which the magnetic field passes. By reducing eddy currents, heating of the printed circuit board and of components located thereon is alleviated.

[0024] The slitting features are vertically slitted to prevent the formation of eddy currents. The slitting features may generally have any form suitable for preventing eddy currents. In some embodiments, the slitting features comprise straight, zig zag or curved vertical slits.

[0025] In a second aspect, there is provided a printed circuit board that comprises a plurality of layers, the layers including a top circuitry layer, the top circuitry layer configured to contact a sensor chip; an analog ground layer arranged below the top layer or combined with the top layer in a single layer, the analog ground layer configured to be connected to an analog ground; and a plurality of current carrying layers arranged below the top circuitry layer and the analog ground layer and configured to carry alternating currents. It is further provided that an area of the analog ground layer that is arranged - in a top view on the printed circuit board - adjacent a boundary of the current carrying layers comprises slitting features configured to reduce eddy currents caused by the alternating current of the current carrying layers.

[0026] This aspect is based on the idea to reduce eddy currents in the analog ground layer, wherein the eddy currents are reduced in that a slitted architecture is implemented in those areas of the analog ground layer through which the magnetic field passes. By reducing eddy currents, heating of the printed circuit board and of components located thereon is alleviated.

[0027] The slitting features may generally have any form suitable for preventing eddy currents. In some embodiments, the slitting features comprise straight, zig zag or curved vertical slits.

[0028] In a third aspect, there is provided a printed circuit board assembly. The printed circuit board assembly comprises a printed circuit board of the first aspect or the second aspect, and a sensor chip located on the top circuitry layer of the printed circuit board. Further, power modules may be arranged on or beneath the printed circuit board and electrically connected to the current carrying layers of the printed circuit board.

[0029] The printed circuit board assembly may provide high voltage alternating current to the power modules while sheltering the sensor chip located on the top circuitry layer of the printed circuit board from EMI currents. In some embodiments, the sensor chip is a current sensing sensor chip and configured to sense the current in at least one of the current carrying layers. Such current sensing sensor chip may be implemented in a plurality of known manners, such as by an inductive sensor, a MEMS magnetic field sensor, a Hall effect sensor, or a magnetooptical sensor.

[0030] In some embodiments, the sensor chip is arranged in an area of the top circuitry layer that is - in a top view on the printed circuit board - adjacent the current carrying layers. For example, the current carrying layers may be formed as longitudinal layer strips within the printed circuit board. The sensor chip may be located in an area on the top circuitry layer in which the magnetic fields generated by the alternating current of the current carrying layers are strong such that a strong signal is produced by the sensor.

[0031] The power modules arranged on or beneath the printed circuit board may be power modules which each comprise a power semiconductor, the power semiconductors forming a power converter circuitry, such as a three phase inverter circuitry suitable to drive electric motors.

[0032] In a fourth aspect, there is provided a printed circuit board assembly. The printed circuit board assembly comprises a printed circuit board of the first aspect, and a sensor chip located on the top circuitry layer of the printed circuit board, wherein the top circuitry layer contacts the sensor chip. There is further provided a chassis, wherein the protective earth layer is connected to a chassis ground, earth ground or protective ground of the chassis.

[0033] The skilled person will appreciate that except where mutually exclusive, a feature or parameter described in relation to any one of the above aspects may be applied to any other aspect. Furthermore, except where mutually exclusive, any feature or parameter described herein may be applied to any aspect and / or combined with any other feature or parameter described herein.

[0034] Brief description of the disclosure

[0035] The invention will be explained in more detail on the basis of exemplary embodiments with reference to the accompanying drawings in which:

[0036] FIG. 1 is a schematic, sectional view of a printed circuit board that comprises a top circuitry layer, an analog ground layer, a protective earth layer and a plurality of current carrying layers;

[0037] FIG. 2 is a schematic top view onto the printed circuit board of FIG. 1 depicting partially the top circuitry layer, the analog ground layer and the current carrying layers, wherein a sensor chip is located on the top circuitry layer and wherein an area of the analog ground layer comprises slitting features;

[0038] FIG. 3 is a first alternative of the printed circuit board of FIG. 1 , wherein the analog ground layer and the top circuitry layer are combined into a single layer;

[0039] FIG. 4 is a second alternative of the printed circuit board of FIG. 1 , wherein several protective earth layers are implemented in the printed circuit board;

[0040] FIG. 5 shows schematically alternative slitting features of the analog ground layer of the printed circuit board of FIG. 2;

[0041] FIG. 6 shows schematically further alternative slitting features of the analog ground layer of the printed circuit board of FIG. 2;

[0042] FIG. 7 is a printed circuit board not in accordance with the present invention, the printed circuit board comprising a top circuitry layer, an analog ground layer and a plurality of current carrying layers, wherein FIG. 5 also depicts a magnetic field produced by alternating current in the current carrying layers; and

[0043] FIG. 8 is a schematic top view onto the printed circuit board of FIG. 7 depicting partially the top circuitry layer, the analog ground layer and the current carrying layers, wherein an area of the analog ground layer in which a strong magnetic field and associated eddy currents are present is depicted.

[0044] Detailed description

[0045] Before discussing embodiments of the present invention with respect to FIGs. 1 to 6, the background of the invention is discussed with respect to FIGs. 7 and 8 which do not represent an embodiment of the present invention.

[0046] FIG. 7 shows schematically a printed circuit board 1 . The printed circuit board 1 comprises a plurality of stacked layers, the layers including layers of conductive material such as copper layers and layers of isolating material such as glass-reinforced epoxy laminate material (FR4) layers, as is well known to the skilled person. In the context of the present disclosure, particular layers of a printed circuit board are considered, wherein the printed circuit board may contain further layers. Also, non-conducting layers of isolating material are not specifically addressed in the subsequent description.

[0047] The printed circuit board 1 comprises a top circuitry layer 1 1 which may be a low-voltage signal circuit layer which is configured to carry low-voltage signals. Below the top circuitry layer 1 1 , an analog ground copper layer 13 is arranged. The analog ground layer 13 may also be referred to as shielding layer. The analog ground layer 13 is connected to an analog ground, wherein the analog ground layer 13 forms the return path for low-voltage signals in the top circuitry layer 1 1 . The analog ground of the analog ground layer 13 is thus the reference point for the voltages in the circuitry layer 1 1 .

[0048] On the top circuitry layer 1 , a sensor chip 2 is arranged and contacted through the top circuitry layer 1 . The sensor chip 2 may be a current sensing sensor chip and be part of a protective circuit that determines fault conditions such as short-circuit conditions. The sensor chip 2 may be a current sensing sensor chip that measures a magnetic field.

[0049] The printed circuit board 1 further comprises a plurality of current carrying layers 15 to 17 (e.g., copper layers) which carry a high voltage alternating current. As shown in FIG. 8, which is a top view of the printed circuit board of FIG. 7, the current carrying layers 15 to 17 comprise a longitudinal main direction A. The width of the current carrying layers 15 to 17 is smaller than that of the printed circuit board 1 . For example, the current carrying layers 15 to 17 are formed as strips having longitudinal boundaries 151 , 152.

[0050] The high voltage alternating current creates a magnetic field M that is schematically depicted in FIG. 7. The magnetic field M is caused by the alternating of the main current in the current carrying layers 15 to 17 at its fundamental frequency. As can also be seen from FIG. 8, the created magnetic field M is particularly strong in areas 130 and 110 adjacent the boundaries 151 , 152 of the current carrying layers 15 to 17. In area 130 adjacent boundary 151 , due to the strong magnetic field eddy currents 135 are created in the analog ground layer 13. The eddy currents 135 lead to an undesired heating of the printed circuit board 1 and of critical components on the top circuitry layer 11 such as the sensor chip 2.

[0051] In the area 1 10 adjacent boundary 152, the sensor chip 2 is located, as for the sensor chip 2 it is preferable to be in an area of high magnetic field to provide for a strong signal.

[0052] Referring again to FIG. 7, it is schematically depicted that a capacitive coupling CO exists between the current carrying layers 15 to 17 and the analog ground layer 13. As the alternating current in the current carrying layers 15 to 17 typically exhibits a high gradient of the voltage dV / dt, the capacitive coupling is strong and gives rise to large EMI currents in the analog ground layer 13 which are injected into the powering and signal lines of the sensor chip 2, thereby affecting accuracy of the measured current and even threatening the safety operation of the sensor chip 2.

[0053] FIG. 1 depicts an embodiment of a printed circuit board assembly. The printed circuit board assembly comprises a printed circuit board 1 and a sensor chip 2 located on the printed circuit board 1 . The printed circuit board 1 comprises a top circuitry layer 11 on which the sensor chip 2 is located, an analog ground layer 13, and a plurality of current carrying layers 15 to 18. Regarding these layers and sensor chip 2, reference is made to the description of the printed circuit board of FIGS. 7 and 8 which similarly applies to the description of FIG. 1 except where stated differently.

[0054] Accordingly, the top circuitry layer 11 may be a low-voltage signal circuit layer which is configured to carry low-voltage signals. The sensor chip 2 may be a current sensing sensor chip configured to measure the current in the current carrying layers 15 to 18. The sensor chip 2 may be part of a protective circuit.

[0055] FIG. 1 further depicts schematically a plurality of electrical power modules 4 which are located on the lower side 12 of the printed circuit board 1 . Alternatively, the power modules 4 may be located on the upper side of the printed circuit board 1 . The electrical power modules 4 may be formed in a variety of ways. In embodiments, they include a power semiconductor such as, for example, a power MOSFET or an IGBT device. The electrical power modules 4 may form together with other components such as capacitors a PCB-based power converter which provides a three-phase alternating current to an electric motor, wherein the three-phase alternating current is guided in the current carrying layers 15 to 18 or some of these. Other layers may be provided for providing a DC current.

[0056] The magnetic field M depicted in FIG. 7 is not shown in FIG. 1 but is present in the same manner. To avoid a capacitive coupling into the analog ground layer 13 and the negative effects associated therewith as discussed with respect to FIGS. 7 and 8, the printed circuit board 1 further comprises a protective earth layer 14 which is arranged between the analog ground layer 13 and the uppermost of the current carrying layers, i.e., current carrying layer 15. The protective earth layer 14 is connected to a chassis ground or alternatively to an earth ground or protective ground. On the other hand, the analog ground layer 13 is connected to analog ground which is the reference point for the voltage in the circuitry layer 11 .

[0057] As schematically shown in FIG. 1 , the analog ground layer 13 is connected to analog ground G1 and the protective ground layer 14 is connected to chassis ground G2 of a chassis 5 (or alternatively to earth ground or protective ground). As mentioned before, analog ground G1 is a reference point for analog signals of the printed circuit board. Chassis ground G2 connects the chassis 5 to a common ground point. The chassis ground G2 may be connected to an earth ground.

[0058] The protective earth layer 14 shelters the analog ground layer 13 and low-voltage signals in the top circuitry layer 11 , wherein capacitive coupling CC takes place with protective earth layer 14 and EMI currents, accordingly, flow in the protective earth layer 14. The protective earth layer 14 may be a copper layer or other metal layer. In embodiments, the protective earth layer 14 may be a 1 oz or 2 oz copper layer.

[0059] Furthermore, it is pointed out that a single-point grounding G2 is implemented in FIG. 1. This is advantageous in contrast to an alternative “loop” with another, e.g. opposite, grounding point, because in this way primarily a shielding against electrical, but not against magnetic fields is achieved.

[0060] FIG. 2 is a schematic top view on the printed circuit board assembly of FIG. 1 . Similar as with FIG. 8, the current carrying layers 15 to 18 comprise a longitudinal main direction A. The width of the current carrying layers 15 to 18 is smaller than that of the printed circuit board 1 . For example, the current carrying layers 15 to 18 are formed as strips having longitudinal boundaries 151 , 152.

[0061] As discussed, the high voltage alternating current in the current carrying layers 15 to 18 creates a magnetic field that is particularly strong in area 130 of the analog ground layer 13 and in area 110 of the top circuitry layer 11 adjacent the longitudinal boundaries 151 , 152 of the current carrying layers 15 to 17 (when viewing from the top). In area 130 cross to the longitudinal direction A and adjacent boundary 151 the analog ground layer 13 comprises slitting features 31 which are configured to reduce eddy currents otherwise caused by the alternating current of the current carrying layers and the magnetic field produced thereby, as discussed with respect to FIG. 8.

[0062] In FIG. 2, the slitting features are formed by vertical straight slits 31 in the analog ground layer 13. However, in principle, the slits can have a plurality of forms to avoid the induction of eddy currents. As schematically shown in FIGS. 5 and 6, alternatively, the vertical slits may be formed as vertical zig zag slits 32 or curved slits 33.

[0063] The slits 31-33 may be formed by etching the analog ground layer 13.

[0064] It is pointed out that, similarly, slitting features such as slits 31-33 may also be formed in the protective earth layer 14 in respective areas.

[0065] The slitting features cut the circular path of the eddy currents that corresponds to the strong magnetic field which is induced by the alternating of the main current at its fundamental frequency and, thereby, avoid heating of the printed circuit board 1 and components located thereon. The number and width of the slits 31-33 may be chosen to achieve a best reduction of eddy currents, wherein the analog ground layer may be a 1 oz or 2 oz copper layer.

[0066] In area 110 of circuitry layer 1 cross to the longitudinal direction A and adjacent boundary 152, the sensor chip 2 is located, as for the sensor chip 2 it is preferable to be in an area of high magnetic field to provide for a strong signal. However, the sensor chip 2 may be located at other locations on the top circuitry layer 11 in other embodiments, such as above the current carrying layers 15 to 18.

[0067] FIG. 3 depicts an embodiment of a printed circuit board in which the analog ground layer 13 and the top circuitry layer 11 are combined into a single top layer 110. This is schematically illustrated in the upper part of FIG. 3 which is a top view on the top layer 110 of the printed circuit board 1 . As depicted, the top layer 110 comprises confined areas 11-1 , 11 -2 formed by the top circuitry layer 11 . The area of the top layer 110 between and around the confined areas 11-1 , 11 -2 forms the analog ground area 13. The protective earth layer 14 is arranged below the top layer 110. As to the other elements of the printed circuit board, reference is made to the description of FIG. 1 .

[0068] FIG. 4 depicts an embodiment of a printed circuit board in which several protective earth layers 14, 14’ are provided, namely, an upper protective earth layer 14 and a lower protective earth layer 14’ which are arranged on opposite sides of the current carrying layers 15-18. The upper protective earth layer 14 is arranged in the same manner as described with respect to FIG. 1 . The lower protective earth layer 14’ is arranged below the current carrying layers 15-18. In the same manner as with the upper protective earth layer 14, capacitive coupling CO takes place between the current carrying layers 15-18 and the lower protective earth layer 14’ wherein EMI currents flow in the lower protective earth layer 14’. The upper and lower protective earth layers 14, 14’ are electrically connected by one or several vertical connections 19. The vertical connection 19 between the upper and lower protective earth layers 14, 14’ may be realized in the form of vias / plated holes or by soldered copper “pin” structures.

[0069] It should be understood that the above description is intended for illustrative purposes only, and is not intended to limit the scope of the present disclosure in any way. Also, those skilled in the art will appreciate that other aspects of the disclosure can be obtained from a study of the drawings, the disclosure and the appended claims. All methods described herein can be performed in any suitable order unless otherwise indicated herein or otherwise clearly contradicted by context. Various features of the various embodiments disclosed herein can be combined in different combinations to create new embodiments within the scope of the present disclosure. In particular, the disclosure extends to and includes all combinations and sub-combinations of one or more features described herein. Any ranges given herein include any and all specific values within the range and any and all sub-ranges within the given range.

Claims

CLAIMS1 . A printed circuit board (1 ) comprising a plurality of layers (11-18), the layers (11-18) including: a top circuitry layer (11), the top circuitry layer (11) configured to contact a sensor chip (2); an analog ground layer (13) arranged below the top layer (11 ) or combined with the top layer (11 ) in a single layer (110), the analog ground layer (13) configured to be connected to an analog ground; and a plurality of current carrying layers (15-18) arranged below the top circuitry layer (11 ) and the analog ground layer (13) and configured to carry alternating currents; characterized by a protective earth layer (14) configured to be connected to a chassis ground, an earth ground or a protective ground, wherein the protective earth layer (14) is arranged between the analog ground layer (13) and the uppermost (15) of the current carrying layers (15-18).

2. The printed circuit board of claim 1 , wherein the protective earth layer (14) is a copper layer or other metal layer.

3. The printed circuit board of claim 1 or 2, wherein the analog ground layer (13) is a copper layer or other metal layer.

4. The printed circuit board of any preceding claim, wherein the current carrying layers (15-18) are configured to operate under high-voltage condition.

5. The printed circuit board of any preceding claim, wherein the top circuitry layer (11 ) is a low-voltage signal circuit layer configured to carry low-voltage signals.

6. The printed circuit board of any preceding claim, wherein the analog ground layer (13) and the top circuitry layer (11) are combined into a single layer (110), wherein the top circuitry layer (11) forms at least one confined area (11-1 , 11 -2) in the single layer (110), and wherein the analog ground layer (13) occupies the area of the single layer (110) around and between the at least one confined area (11-1 , 11-2).

7. The printed circuit board of any preceding claim, wherein the printed circuit board comprises at least one further protective earth layer (14’), wherein the protectiveearth layers (14, 14’) are interconnected by one or several vertical electrical connections (9).

8. The printed circuit board of claim 7, wherein the further protective earth layer (14’) is arranged on the opposite side of the plurality of current carrying layers (15-18).

9. The printed circuit board of any preceding claim, wherein an area (130) of the analog ground layer (13) and / or of the protective earth layer (14) that is arranged - in a top view on the printed circuit board - adjacent a boundary (151) of the current carrying layers (15 to 18) comprises slitting features (31-33) configured to reduce eddy currents caused by the alternating current of the current carrying layers (15-18).

10. The printed circuit board of claim 9, wherein the slitting features comprise straight, zig zag or curved vertical slits (31-33).11 . A printed circuit board (1) comprising: a plurality of layers (11 -18), the layers (11-18) including: a top circuitry layer (11), the top circuitry layer (11) configured to contact a sensor chip (2); an analog ground layer (13) arranged below the top layer (11 ) or combined with the top layer (11 ) in a single layer (110), the analog ground layer (13) configured to be connected to an analog ground; and a plurality of current carrying layers (15-18) arranged below the top circuitry layer (11 ) and the analog ground layer (13) and configured to carry alternating currents; characterized in that an area (130) of the analog ground layer (13) that is arranged, in a top view on the printed circuit board, adjacent a boundary (151) of the current carrying layers (15-18) comprises slitting features (31-33) configured to reduce eddy currents caused by the alternating current of the current carrying layers (15-18).

12. The printed circuit board of claim 11 , wherein the slitting features comprise straight vertical slits (31).

13. The printed circuit board of claim 11 , wherein the slitting features comprise zig zag or curved vertical slits (32-33).

14. A printed circuit board assembly comprising: a printed circuit board (1 ) of any preceding claim; a sensor chip (2) located on the top circuitry layer (1 1 ) of the printed circuit board (1 ); and power modules (4) arranged on or beneath the printed circuit board (1 ) and electrically connected to the current carrying layers (15-18) of the printed circuit board(1)-15. The printed circuit board assembly of claim 14, wherein the sensor chip (2) is a current sensing sensor chip and configured to sense the current in at least one of the current carrying layers (15-18).

16. The printed circuit board assembly of claim 14 or 15, wherein the sensor chip (2) is arranged in an area (110) of the top circuitry layer (1 ) which, in a top view on the printed circuit board, is adjacent the current carrying layers (15 to 18).

17. A printed circuit board assembly comprising: a printed circuit board (1 ) of any of claims 1 to 10; a sensor chip (2) located on the top circuitry layer (1 1 ) of the printed circuit board (1 ), wherein the top circuitry layer (11 ) contacts the sensor chip (2); a chassis (5), wherein the protective earth layer (14) is connected to a chassis ground (G2), an earth ground or a protective ground of the chassis (5).

18. The printed circuit board assembly of claim 17, wherein the sensor chip (2) is arranged in an area (110) of the top circuitry layer (1 ) which, in a top view on the printed circuit board, is adjacent the current carrying layers (15 to 18).

19. The printed circuit board assembly of claim 17 or 18, further comprising power modules (4) arranged on or beneath the printed circuit board (1 ) and electrically connected to the current carrying layers (15-18) of the printed circuit board (1 ).

20. The printed circuit board assembly of any of claims 17 to 19, wherein the protective earth layer (14) is connected by a single-point grounding to chassis ground, earth ground or protective ground.

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