Time-to-digital converter circuit and digital phase locked loop including time-to-digital converter circuit

Abstract

A time-to-digital converter (TDC) circuit, according to one embodiment of the present invention, may comprise: a processing circuit which generates a first value of a first gain signal indicating a first time sensing range in a first mode and a first value of a second gain signal indicating a second time sensing range in the first mode; a first delay circuit which generates a plurality of first delay signals by delaying an input signal on the basis of the first value of the first gain signal; a first arbiter circuit which generate first results based on each of the plurality of first delay signals and a first clock signal; a second delay circuit which generates a plurality of second delay signals by delaying the input signal on the basis of the first value of the second gain signal; a second arbiter circuit which generates second results based on each of the plurality of second delay signals and the first clock signal; and an adder circuit which generates a first sum result on the basis of the first results and the second results.

Description

A time-to-digital converter circuit and a digital phase-locked loop including the time-to-digital converter circuit.

[0001] One embodiment relates to a time-to-digital converter circuit, and more particularly to a time-to-digital converter circuit used in a digital phase-locked loop.

[0002] Implementing an all-digital PLL (ADPLL) that generates low-noise, high-speed, GHz-range output frequencies requires a high-resolution Time-to-Digital Converter (TDC). Additionally, to ensure ADPLL stability, considering process / voltage / temperature (PVT) variations, the TDC's detectable time range must be at least one oscillator cycle.

[0003] Resolution and detection time range, the most important aspects of TDC performance, are subject to trade-offs. Typically, higher resolution requires a reduced detection time range, while wider detection time ranges require lower resolution. Therefore, to achieve both of these performance benefits, a TDC that combines coarse and fine structures is used in ADPLL.

[0004] In one embodiment, a time-to-digital converter (TDC) circuit may include a processing circuit that generates a first value of a first gain signal representing a first time detection range in a first mode and a first value of a second gain signal representing a second time detection range in the first mode, a first delay circuit that generates a plurality of first delay signals by delaying an input signal based on the first value of the first gain signal, a first arbiter circuit that generates first results based on each of the plurality of first delay signals and a first clock signal, a second delay circuit that generates a plurality of second delay signals by delaying the input signal based on the first value of the second gain signal, a second arbiter circuit that generates second results based on each of the plurality of second delay signals and the first clock signal, and an adding circuit that generates a first sum result based on the first results and the second results.

[0005] According to one embodiment, a digital phase locked loop includes a time-to-digital converter (TDC) circuit for detecting a phase and frequency difference between an input signal and a clock signal and generating a sum result representing the detected difference, a digital loop filter (DLF) for generating a filtered phase error signal by filtering the sum result, a delta-sigma modulator (DSM) for generating noise based on the sum result, a digitally controlled oscillator (DCO) for generating an output oscillation signal based on the phase error signal and noise, and a divider for dividing the output oscillation signal of the digitally controlled oscillator by a set division ratio, wherein the time-to-digital converter circuit includes a processing circuit for generating a first value of a first gain signal representing a first time detection range in a first mode and a first value of a second gain signal representing a second time detection range in the first mode, a first delay circuit for generating a plurality of first delay signals by delaying an input signal based on the first value of the first gain signal, a first arbiter circuit for generating first results based on each of the plurality of first delay signals and the first clock signal, and a first arbiter circuit for generating first results based on the first clock signal and the first value of the second gain signal by delaying the input signal based on the first value of the second gain signal. It may include a second delay circuit that generates a plurality of second delay signals, a second arbiter circuit that generates second results based on each of the plurality of second delay signals and the first clock signal, and an adder circuit that generates a first sum result based on the first results and the second results.

[0006] According to one embodiment, a method performed by a time-to-digital converter circuit may include: a processing circuit generating a first value of a first gain signal representing a first time detection range in a first mode and a first value of a second gain signal representing a second time detection range in the first mode; a first delay circuit generating a plurality of first delay signals by delaying an input signal based on the first value of the first gain signal; a first arbiter circuit generating first results based on each of the plurality of first delay signals and a first clock signal; a second delay circuit generating a plurality of second delay signals by delaying the input signal based on the first value of the second gain signal; a second arbiter circuit generating second results based on each of the plurality of second delay signals and the first clock signal; and an adding circuit generating a first sum result based on the first results and the second results.

[0007] FIG. 1 is a block diagram of an electronic device within a network environment according to one embodiment.

[0008] Figure 2 is a schematic diagram of a DPLL according to one embodiment.

[0009] Figure 3 is a configuration diagram of a TDC according to one embodiment.

[0010] Figure 4 is a circuit diagram of a DTC according to one embodiment.

[0011] Figure 5 is a circuit diagram of an arbiter according to one embodiment.

[0012] FIG. 6 is a flowchart of a method for generating a first summation result of a TDC used to generate a clock signal, according to one embodiment.

[0013] FIG. 7 is a flowchart of a method for generating a second summation result of a TDC used to generate a clock signal, according to one embodiment.

[0014] FIG. 8 is a flowchart of a method for determining whether to change the operation mode from the first mode to the second mode based on the first sum result, according to one embodiment.

[0015] FIG. 9 illustrates codes output by a TDC according to an operating mode, according to one embodiment.

[0016] Hereinafter, various embodiments of the present disclosure will be described with reference to the attached drawings. However, this is not intended to limit the present disclosure to specific embodiments, and it should be understood that the present disclosure encompasses various modifications, equivalents, and / or alternatives of the embodiments.

[0017] FIG. 1 is a block diagram of an electronic device within a network environment according to one embodiment.

[0018] FIG. 1 is a block diagram of an electronic device (101) within a network environment (100) according to an embodiment. Referring to FIG. 1, in the network environment (100), the electronic device (101) may communicate with the electronic device (102) via a first network (198) (e.g., a short-range wireless communication network), or may communicate with at least one of the electronic device (104) or the server (108) via a second network (199) (e.g., a long-range wireless communication network). According to an embodiment, the electronic device (101) may communicate with the electronic device (104) via the server (108). According to one embodiment, the electronic device (101) may include a processor (120), a memory (130), an input module (150), an audio output module (155), a display module (160), an audio module (170), a sensor module (176), an interface (177), a connection terminal (178), a haptic module (179), a camera module (180), a power management module (188), a battery (189), a communication module (190), a subscriber identification module (196), or an antenna module (197). In some embodiments, the electronic device (101) may omit at least one of these components (e.g., the connection terminal (178)), or may have one or more other components added. In some embodiments, some of these components (e.g., the sensor module (176), the camera module (180), or the antenna module (197)) may be integrated into one component (e.g., the display module (160)).

[0019] The processor (120) may control at least one other component (e.g., a hardware or software component) of the electronic device (101) connected to the processor (120) by executing, for example, software (e.g., a program (140)), and may perform various data processing or calculations. According to one embodiment, as at least a part of the data processing or calculation, the processor (120) may store a command or data received from another component (e.g., a sensor module (176) or a communication module (190)) in a volatile memory (132), process the command or data stored in the volatile memory (132), and store the resulting data in a non-volatile memory (134). According to one embodiment, the processor (120) may include a main processor (121) (e.g., a central processing unit or an application processor) or a secondary processor (123) (e.g., a graphics processing unit, a neural processing unit (NPU), an image signal processor, a sensor hub processor, or a communication processor) that can operate independently or together therewith. For example, if the electronic device (101) includes a main processor (121) and a secondary processor (123), the secondary processor (123) may be configured to use less power than the main processor (121) or to be specialized for a specified function. The secondary processor (123) may be implemented separately from the main processor (121) or as a part thereof.

[0020] The auxiliary processor (123) may control at least a part of functions or states associated with at least one component (e.g., a display module (160), a sensor module (176), or a communication module (190)) of the electronic device (101), for example, on behalf of the main processor (121) while the main processor (121) is in an inactive (e.g., sleep) state, or together with the main processor (121) while the main processor (121) is in an active (e.g., application execution) state. In one embodiment, the auxiliary processor (123) (e.g., an image signal processor or a communication processor) may be implemented as a part of another functionally related component (e.g., a camera module (180) or a communication module (190)). In one embodiment, the auxiliary processor (123) (e.g., a neural network processing unit) may include a hardware structure specialized for processing artificial intelligence models. The artificial intelligence models may be generated through machine learning. This learning can be performed, for example, on the electronic device (101) itself where the artificial intelligence model is executed, or can be performed through a separate server (e.g., server (108)). The learning algorithm can include, for example, supervised learning, unsupervised learning, semi-supervised learning, or reinforcement learning, but is not limited to the examples described above. The artificial intelligence model can include multiple artificial neural network layers.The artificial neural network may be one of a deep neural network (DNN), a convolutional neural network (CNN), a recurrent neural network (RNN), a restricted Boltzmann machine (RBM), a deep belief network (DBN), a bidirectional recurrent deep neural network (BRDNN), a deep Q-network, or a combination of two or more of the above, but is not limited to the examples described above. In addition to, or alternatively to, a hardware structure, an artificial intelligence model may include a software structure.

[0021] The memory (130) can store various data used by at least one component (e.g., processor (120) or sensor module (176)) of the electronic device (101). The data can include, for example, software (e.g., program (140)) and input data or output data for commands related thereto. The memory (130) can include volatile memory (132) or non-volatile memory (134).

[0022] The program (140) may be stored as software in the memory (130) and may include, for example, an operating system (142), middleware (144), or an application (146).

[0023] The input module (150) can receive commands or data to be used in a component of the electronic device (101) (e.g., a processor (120)) from an external source (e.g., a user) of the electronic device (101). The input module (150) can include, for example, a microphone, a mouse, a keyboard, a key (e.g., a button), or a digital pen (e.g., a stylus pen).

[0024] The audio output module (155) can output audio signals to the outside of the electronic device (101). The audio output module (155) can include, for example, a speaker or a receiver. The speaker can be used for general purposes, such as multimedia playback or recording playback. The receiver can be used to receive incoming calls. According to one embodiment, the receiver can be implemented separately from the speaker or as part of the speaker.

[0025] The display module (160) can visually provide information to an external party (e.g., a user) of the electronic device (101). The display module (160) may include, for example, a display, a holographic device, or a projector and a control circuit for controlling the device. According to one embodiment, the display module (160) may include a touch sensor configured to detect a touch, or a pressure sensor configured to measure the intensity of a force generated by the touch.

[0026] The audio module (170) can convert sound into an electrical signal, or vice versa, convert an electrical signal into sound. According to one embodiment, the audio module (170) can acquire sound through the input module (150), output sound through the sound output module (155), or an external electronic device (e.g., electronic device (102)) (e.g., speaker or headphone) directly or wirelessly connected to the electronic device (101).

[0027] The sensor module (176) can detect the operating status (e.g., power or temperature) of the electronic device (101) or the external environmental status (e.g., user status) and generate an electrical signal or data value corresponding to the detected status. According to one embodiment, the sensor module (176) can include, for example, a gesture sensor, a gyro sensor, a barometric pressure sensor, a magnetic sensor, an acceleration sensor, a grip sensor, a proximity sensor, a color sensor, an IR (infrared) sensor, a biometric sensor, a temperature sensor, a humidity sensor, or an illuminance sensor.

[0028] The interface (177) may support one or more designated protocols that may be used to directly or wirelessly connect the electronic device (101) with an external electronic device (e.g., the electronic device (102)). In one embodiment, the interface (177) may include, for example, a high definition multimedia interface (HDMI), a universal serial bus (USB) interface, an SD card interface, or an audio interface.

[0029] The connection terminal (178) may include a connector through which the electronic device (101) may be physically connected to an external electronic device (e.g., electronic device (102)). According to one embodiment, the connection terminal (178) may include, for example, an HDMI connector, a USB connector, an SD card connector, or an audio connector (e.g., a headphone connector).

[0030] A haptic module (179) can convert electrical signals into mechanical stimuli (e.g., vibration or movement) or electrical stimuli that a user can perceive through tactile or kinesthetic sensations. According to one embodiment, the haptic module (179) can include, for example, a motor, a piezoelectric element, or an electrical stimulation device.

[0031] The camera module (180) can capture still images and videos. According to one embodiment, the camera module (180) may include one or more lenses, image sensors, image signal processors, or flashes.

[0032] The power management module (188) can manage power supplied to the electronic device (101). According to one embodiment, the power management module (188) can be implemented as, for example, at least a part of a power management integrated circuit (PMIC).

[0033] A battery (189) may power at least one component of the electronic device (101). In one embodiment, the battery (189) may include, for example, a non-rechargeable primary battery, a rechargeable secondary battery, or a fuel cell.

[0034] The communication module (190) may support the establishment of a direct (e.g., wired) communication channel or a wireless communication channel between the electronic device (101) and an external electronic device (e.g., electronic device (102), electronic device (104), or server (108)), and the performance of communication through the established communication channel. The communication module (190) may operate independently from the processor (120) (e.g., application processor) and may include one or more communication processors that support direct (e.g., wired) communication or wireless communication. According to one embodiment, the communication module (190) may include a wireless communication module (192) (e.g., a cellular communication module, a short-range wireless communication module, or a global navigation satellite system (GNSS) communication module) or a wired communication module (194) (e.g., a local area network (LAN) communication module, or a power line communication module). Among these communication modules, the corresponding communication module can communicate with an external electronic device (104) via a first network (198) (e.g., a short-range communication network such as Bluetooth, wireless fidelity (WiFi) direct, or infrared data association (IrDA)) or a second network (199) (e.g., a long-range communication network such as a legacy cellular network, a 5G network, a next-generation communication network, the Internet, or a computer network (e.g., a LAN or WAN)). These various types of communication modules can be integrated into a single component (e.g., a single chip) or implemented as multiple separate components (e.g., multiple chips). The wireless communication module (192) can verify or authenticate the electronic device (101) within a communication network such as the first network (198) or the second network (199) by using subscriber information (e.g., an international mobile subscriber identity (IMSI)) stored in the subscriber identification module (196).

[0035] The wireless communication module (192) can support 5G networks and next-generation communication technologies following the 4G network, such as NR access technology (new radio access technology). The NR access technology can support high-speed transmission of high-capacity data (eMBB (enhanced mobile broadband)), minimization of terminal power and connection of multiple terminals (mMTC (massive machine type communications)), or high reliability and low latency (URLLC (ultra-reliable and low-latency communications)). The wireless communication module (192) can support, for example, a high-frequency band (e.g., mmWave band) to achieve a high data transmission rate. The wireless communication module (192) can support various technologies for securing performance in a high-frequency band, such as beamforming, massive multiple-input and multiple-output (MIMO), full dimensional MIMO (FD-MIMO), array antenna, analog beam-forming, or large scale antenna. The wireless communication module (192) can support various requirements specified in the electronic device (101), an external electronic device (e.g., the electronic device (104)), or a network system (e.g., the second network (199)). According to one embodiment, the wireless communication module (192) may support a peak data rate (e.g., 20 Gbps or more) for eMBB realization, a loss coverage (e.g., 164 dB or less) for mMTC realization, or a U-plane latency (e.g., 0.5 ms or less for downlink (DL) and uplink (UL), or 1 ms or less for round trip) for URLLC realization.

[0036] The antenna module (197) can transmit or receive signals or power to or from an external device (e.g., an external electronic device). According to one embodiment, the antenna module (197) may include an antenna including a radiator formed of a conductor or a conductive pattern formed on a substrate (e.g., a PCB). According to one embodiment, the antenna module (197) may include a plurality of antennas (e.g., an array antenna). In this case, at least one antenna suitable for a communication method used in a communication network, such as the first network (198) or the second network (199), may be selected from the plurality of antennas, for example, by the communication module (190). A signal or power may be transmitted or received between the communication module (190) and an external electronic device via the at least one selected antenna. According to some embodiments, in addition to the radiator, another component (e.g., a radio frequency integrated circuit (RFIC)) may be additionally formed as a part of the antenna module (197).

[0037] In one embodiment, the antenna module (197) may form a mmWave antenna module. In one embodiment, the mmWave antenna module may include a printed circuit board, an RFIC disposed on or adjacent a first side (e.g., a bottom side) of the printed circuit board and capable of supporting a designated high-frequency band (e.g., a mmWave band), and a plurality of antennas (e.g., an array antenna) disposed on or adjacent a second side (e.g., a top side or a side side) of the printed circuit board and capable of transmitting or receiving signals in the designated high-frequency band.

[0038] A digital phase locked loop (DPLL) (105) can detect or determine the phase or frequency of an input signal. The DPLL (105) can generate a clock signal synchronized with the phase or frequency of the input signal. The electronic device (101) can operate based on the clock signal generated by the DPLL (105). The DPLL (105) can be used for communication systems, digital signal processing, signal demodulation, frequency synthesis, and timing locking. For example, in wireless communication, the DPLL (105) can be used to accurately recover data by determining the phase of a received signal and demodulating the signal based on the determined phase. For example, the DPLL (105) can stably maintain a digital clock used in a data conversion and processing system. The DPLL (105) is described in detail below with reference to FIGS. 2 to 9.

[0039] An electronic device including a DPLL (105) is not limited to the electronic device (101) described above with reference to FIG. 1. For example, a DPLL (105) may be included in an electronic device that must detect the phase or frequency of an input signal for communication systems, digital signal processing, signal demodulation, frequency synthesis, and timing locking.

[0040] At least some of the above components can be interconnected and exchange signals (e.g., commands or data) with each other via a communication method between peripheral devices (e.g., a bus, GPIO (general purpose input and output), SPI (serial peripheral interface), or MIPI (mobile industry processor interface)).

[0041] According to one embodiment, commands or data may be transmitted or received between the electronic device (101) and an external electronic device (104) via a server (108) connected to a second network (199). Each of the external electronic devices (102 or 104) may be the same or a different type of device as the electronic device (101). According to one embodiment, all or part of the operations executed in the electronic device (101) may be executed in one or more of the external electronic devices (102, 104, or 108). For example, when the electronic device (101) is to perform a certain function or service automatically or in response to a request from a user or another device, the electronic device (101) may, instead of or in addition to executing the function or service by itself, request one or more external electronic devices to perform the function or at least a part of the service. One or more external electronic devices that receive the request may execute at least a portion of the requested function or service, or an additional function or service related to the request, and transmit the result of the execution to the electronic device (101). The electronic device (101) may process the result as is or additionally and provide it as at least a portion of a response to the request. For this purpose, cloud computing, distributed computing, mobile edge computing (MEC), or client-server computing technology may be used, for example. The electronic device (101) may provide an ultra-low latency service by using distributed computing or mobile edge computing, for example. In another embodiment, the external electronic device (104) may include an Internet of Things (IoT) device. The server (108) may be an intelligent server utilizing machine learning and / or a neural network. According to one embodiment, the external electronic device (104) or the server (108) may be included in the second network (199).The electronic device (101) can be applied to intelligent services (e.g., smart home, smart city, smart car, or healthcare) based on 5G communication technology and IoT-related technology.

[0042] Electronic devices according to the various embodiments disclosed in this document may take various forms. Electronic devices may include, for example, portable communication devices (e.g., smartphones), computer devices, portable multimedia devices, portable medical devices, cameras, wearable devices, or home appliances. Electronic devices according to the embodiments disclosed in this document are not limited to the aforementioned devices.

[0043] The various embodiments of this document and the terminology used therein are not intended to limit the technical features described in this document to specific embodiments, but should be understood to include various modifications, equivalents, or substitutes of the embodiments. In connection with the description of the drawings, similar reference numerals may be used for similar or related components. The singular form of a noun corresponding to an item may include one or more of the items, unless the context clearly indicates otherwise. In this document, each of the phrases "A or B", "at least one of A and B", "at least one of A or B", "A, B, or C", "at least one of A, B, and C", and "at least one of A, B, or C" can include any one of the items listed together in the corresponding phrase among those phrases, or all possible combinations thereof. Terms such as "first," "second," or "first" or "second" may be used merely to distinguish one component from another, and do not limit the components in any other respect (e.g., importance or order). When a component (e.g., a first component) is referred to as "coupled" or "connected" to another component (e.g., a second component), with or without the terms "functionally" or "communicatively," it means that the component can be connected to the other component directly (e.g., wired), wirelessly, or through a third component.

[0044] The term "module" used in various embodiments of this document may include a unit implemented in hardware, software, or firmware, and may be used interchangeably with terms such as logic, logic block, component, or circuit. A module may be an integral component, or a minimum unit or part of such a component that performs one or more functions. For example, according to one embodiment, a module may be implemented in the form of an application-specific integrated circuit (ASIC).

[0045] Various embodiments of the present document may be implemented as software (e.g., a program (140)) including one or more commands stored in a storage medium (e.g., an internal memory (136) or an external memory (138)) readable by a machine (e.g., an electronic device (101)). For example, a processor (e.g., a processor (120)) of the machine (e.g., an electronic device (101)) may call at least one command among the one or more commands stored from the storage medium and execute it. This enables the machine to operate to perform at least one function according to the at least one command called. The one or more commands may include code generated by a compiler or code executable by an interpreter. The machine-readable storage medium may be provided in the form of a non-transitory storage medium. Here, 'non-transitory' simply means that the storage medium is a tangible device and does not contain signals (e.g., electromagnetic waves), and the term does not distinguish between cases where data is stored semi-permanently or temporarily on the storage medium.

[0046] According to one embodiment, the method according to the various embodiments disclosed in the present document may be provided as included in a computer program product. The computer program product may be traded as a product between a seller and a buyer. The computer program product may be distributed in the form of a machine-readable storage medium (e.g., compact disc read only memory (CD-ROM)), or may be distributed online (e.g., downloaded or uploaded) via an application store (e.g., Play Store™) or directly between two user devices (e.g., smart phones). In the case of online distribution, at least a portion of the computer program product may be temporarily stored or temporarily generated in a machine-readable storage medium, such as the memory of a manufacturer's server, an application store's server, or an intermediary server.

[0047] According to various embodiments, each component (e.g., a module or a program) of the above-described components may include one or more entities, and some of the entities may be separated and placed in other components. According to various embodiments, one or more components or operations of the aforementioned components may be omitted, or one or more other components or operations may be added. Alternatively or additionally, a plurality of components (e.g., a module or a program) may be integrated into a single component. In such a case, the integrated component may perform one or more functions of each of the plurality of components identically or similarly to those performed by the corresponding component among the plurality of components prior to the integration. According to various embodiments, the operations performed by a module, program, or other component may be executed sequentially, in parallel, iteratively, or heuristically, or one or more of the operations may be executed in a different order, omitted, or one or more other operations may be added.

[0048] Figure 2 is a schematic diagram of a DPLL according to one embodiment.

[0049] According to one embodiment, referring to FIG. 1, the DPLL (105) may include a TDC (210), an adder (or an adder circuit) (220), a TDC controller (230), a digital loop filter (DLF) (240), a delta-sigma modulator (DSM) (250), a digital controlled oscillator (DCO) (260), and a divider (DIV) (270). For example, the TDC circuit may include a TDC (210), an adder (220), and a TDC controller (230).

[0050] The TDC (210) can receive an input signal and a clock signal, and output a result indicating a time difference between the input signal and the clock signal. For example, the result indicating the time difference can be expressed as a bit value. The TDC (210) can generate a plurality of delay signals by applying different delays to the input signal. The TDC (210) can output a result indicating a time difference between each of the plurality of delay signals and the clock signal. For example, the input signal can be a reference clock signal (CLK). REF ) may be. The input signal may be generated by a crystal oscillator. For example, the input signal may be a signal received via wireless communication. For example, the clock signal may be a signal output via a divider (270). The number of results generated by the TDC (210) is the number of signal paths included in the TDC (210) (e.g., 2 N ) can correspond to. For example, if the total number of signal paths included in TDC (210) is 256, N can be 8.

[0051] The adder (220) can generate a sum result by adding the values ​​output from the TDC (210). For example, when the TDC (210) generates first results and second results, the adder (220) can generate a first sum result based on the first results and second results.

[0052] The TDC controller (230) can generate a plurality of delay signals (e.g., M) for controlling delay circuits within the TDC (210). Here, M may correspond to the number of circuit groups included in the TDC (210), which will be described later. For example, the TDC controller (230) can generate a plurality of delay signals based on the sum result generated by the adder (220). The TDC controller (230) may be referred to as a processing circuit. For example, the TDC controller (230) may be a dedicated processor configured to generate a plurality of delay signals for controlling delay circuits within the TDC (210). For example, the TDC controller (230) may be a general-purpose processor.

[0053] DLF (240) can generate a filtered phase error signal by filtering the sum result generated by the adder (220).

[0054] The DSM (250) can generate noise based on the summation result generated by the adder (220). The phase error signal generated by the DLF (240) and the noise generated by the DSM (250) can be synthesized.

[0055] DCO (260) can generate an output oscillation signal based on a signal in which a phase error signal and noise are synthesized. For example, the output oscillation signal may be an output clock signal (CLK). OUT ) may be.

[0056] The divider (270) can generate a clock signal by dividing the output oscillation signal by a set division ratio. The generated clock signal can be input again to the TDC (210).

[0057] Figure 3 is a configuration diagram of a TDC according to one embodiment.

[0058] According to one embodiment, the TDC (210) described above with reference to FIG. 2 may include a first circuit group having a plurality of signal paths and a second circuit group having a plurality of signal paths. For example, the TDC (210) may include 16 circuit groups, and the number of circuit groups is not limited to the described embodiment. Each circuit group of the TDC (210) may include 16 signal paths, and the number of signal paths included in one circuit group is not limited to the described embodiment.

[0059] According to one embodiment, one signal path may include a digital-to-time converter (DTC) (311a) and an arbiter (321a). For example, DTCs within the same circuit group may have the same value of a gain signal (e.g., SEL DTC <n>< / n> ) can be received. For example, the DTCs corresponding to the first delay circuit in the first circuit group (300a) can receive the value of the first gain signal (e.g., SEL DTC1 ) and the DTCs corresponding to the 16th delay circuit in the 16th circuit group (300b) receive the value of the 16th gain signal (e.g., SEL DTC16 ) can be received.

[0060] The DTC (311a) can generate a first delay signal by delaying an input signal based on the value of the first gain signal. The structure of the DTC (311a) is described in detail below with reference to FIG. 4.

[0061] The arbiter (321a) can generate a first result based on the first delay signal and clock signal generated by the DTC (311a). The first result may vary based on the time difference between the first delay signal and the clock signal. The structure of the arbiter (321a) is described in detail below with reference to FIG. 5.

[0062] The first circuit group (300a) may include a first delay circuit (310a) composed of DTCs that generate a plurality of first delay signals by delaying an input signal based on a value of a first gain signal. The plurality of first delay signals may include a first sub-delay signal and a second sub-delay signal. For example, the first delay circuit (310a) may include a DTC (311a) of a first signal path and a DTC (312a) of a second signal path. The DTC (311a) of the first signal path may be referred to as a first sub-delay circuit, and the DTC of the second signal path may be referred to as a second sub-delay circuit. The first sub-delay circuit may generate the first sub-delay signal based on a first value of the first gain signal. The second sub-delay circuit may generate the second sub-delay signal based on the first value of the first gain signal.

[0063] The first circuit group (300a) may include a first arbiter circuit (320a) comprising arbiters that generate first results based on each of a plurality of first delay signals and a clock signal. For example, the first arbiter circuit (320a) may include an arbiter (321a) of a first signal path and an arbiter (322a) of a second signal path.

[0064] In one embodiment, if the first circuit group (300a) includes 16 signal paths, the first results generated by the first arbiter circuit (320a) can be expressed by 16 bits.

[0065] Since the same value of the first gain signal is applied to the DTCs in the first delay circuit (310a) of the first circuit group (300a), the DTCs can generate time differences with high resolution within the same time detection range. Since the same value of the second gain signal is applied to the DTCs in the second delay circuit of the second circuit group, the DTCs can generate time differences with high resolution within the same time detection range. Although each of the DTCs has the same circuit structure, the circuit elements of each of the DTCs may have slightly different physical properties due to tolerances occurring in the manufacturing process. Due to the above tolerances, the DTCs can generate time differences with high resolution within the same time detection range.

[0066] For example, when the values ​​of the first gain signal and the second gain signal are the same, the first circuit group (300a) and the second circuit group can generate results representing time differences between the input signal and the clock signal for the same time detection range. For example, when the values ​​of the first gain signal and the second gain signal are different from each other, the first circuit group (300a) and the second circuit group can generate results representing time differences between the input signal and the clock signal for each of different time detection ranges.

[0067] According to one embodiment, the values ​​of a plurality of gain signals may be generated by the TDC controller (230) described above with reference to FIG. 2. For example, the TDC controller (230) may change the values ​​of the plurality of gain signals generated depending on the operating mode. A method for generating the values ​​of a plurality of gain signals based on the operating mode is described in detail below with reference to FIG. 6.

[0068] According to one embodiment, the clock signal input to the DTC (310a) can be changed by the divider (270) of the DPLL (105) described above with reference to FIG. 2. The TDC circuit can repeatedly generate a sum result by repeatedly comparing the changed clock signal with the input signal. The TDC controller (230) can determine the values ​​of a plurality of gain signals based on the sum result.

[0069] Figure 4 is a circuit diagram of a DTC according to one embodiment.

[0070] According to one embodiment, the DTC (311a) (e.g., the first sub-delay circuit) described above with reference to FIG. 3 may include a plurality of delay elements. For example, when the value of the gain signal is composed of 4 bits, the plurality of delay elements may include a first delay element (410), a second delay element (420), a third delay element (430), and a fourth delay element (440). Each of the first delay element (410), the second delay element (420), the third delay element (430), and the fourth delay element (440) may be composed of identical delay cells. For example, one delay cell may include a transistor and a capacitor. The transistor of the delay cell may be controlled based on the bit of the value of the gain signal.

[0071] For example, the first delay element (410) may include eight delay cells. Each of the eight delay cells may contain a bit of the value of the same gain signal (e.g., SEL <3> ) can be controlled based on the delay cells. The eight delay cells can be connected in parallel with each other.

[0072] For example, the second delay element (420) may include four delay cells. Each of the four delay cells may contain a bit of the value of the same gain signal (e.g., SEL <2> ) can be controlled based on the four delay cells. The four delay cells can be connected in parallel with each other.

[0073] For example, the third delay element (430) may include two delay cells. Each of the two delay cells may include a bit of the value of the same gain signal (e.g., SEL <1> ) can be controlled based on the two delay cells. The two delay cells can be connected in parallel with each other.

[0074] For example, the fourth delay element (440) may include one delay cell. One delay cell may be configured to store a bit of the value of the gain signal (e.g., SEL <0> ) can be controlled based on.

[0075] In one embodiment, the plurality of delay elements may include a dummy delay element (450). For example, the dummy delay element (450) may include one delay cell. The one delay cell may be controlled by VDD.

[0076] Based on the bits of the value of the gain signal input to the DTC (311a), the input signal can be delayed by an amount corresponding to the bits of the value of the gain signal. For example, when the bits of the value of the gain signal are '1111', the input signal can be delayed the most, and when the bits of the value of the gain signal are '0000', the input signal can be delayed the least.

[0077] Figure 5 is a circuit diagram of an arbiter according to one embodiment.

[0078] According to one embodiment, the arbiter (321a) described above with reference to FIG. 3 may include a plurality of delay elements. For example, the arbiter (321a) may include two NAND elements, two inverter elements, a plurality of delay elements, and a D flip-flop. The arbiter (321a) may receive a delay signal and a clock signal through the two NAND elements, and generate a comparison result for the delay signal and the clock signal through the D flip-flop.

[0079] FIG. 6 is a flowchart of a method for generating a first summation result of a TDC used to generate a clock signal, according to one embodiment.

[0080] The operations 610 to 660 below may be performed by a TDC circuit. For example, the TDC circuit may include a TDC (e.g., TDC (210) of FIG. 2), an adder circuit (e.g., adder (220) of FIG. 2), and a processing circuit (e.g., TDC controller (230) of FIG. 2).

[0081] In operation 610, the processing circuit can generate a first value of a first gain signal representing a first time detection range in a first mode and a first value of a second gain signal representing a second time detection range in the first mode. For example, the processing circuit can generate values ​​of a plurality of gain signals.

[0082] In one embodiment, the first mode may be an initial operating mode. For example, the TDC may be 2 N When including 16 circuit groups, the number of multiple gain signals generated for the first mode is 2. N It can be. Each of the values ​​of the multiple gain signals can have a different time detection range. Each of the values ​​of the multiple gain signals can be represented by N bits. For example, in the first mode, the first value of the first gain signal can be '0000', and the first value of the second gain signal can be '0001'.

[0083] In operation 620, a first delay circuit (e.g., the first delay circuit (310a) of FIG. 3) may generate a plurality of first delay signals by delaying an input signal based on a first value of a first gain signal. For example, the first delay circuit may be included in a first circuit group.

[0084] According to one embodiment, the first delay circuit can generate a plurality of first delay signals by delaying an input signal by a delay time corresponding to a first value of a first gain signal using a plurality of DTCs in the first delay circuit. The plurality of first delay signals can have slightly different time differences due to differences in physical properties between the DTCs. For example, the number of the plurality of first delay signals is 2 N It could be a dog.

[0085] Operation 620 may include an operation in which a first sub-delay circuit of a first delay circuit generates a first sub-delay signal among a plurality of first delay signals based on a first value of a first gain signal.

[0086] Operation 620 may include an operation in which a second sub-delay circuit of the first delay circuit generates a second sub-delay signal among a plurality of first delay signals based on a first value of the first gain signal.

[0087] In operation 630, the first arbiter circuit (e.g., the first arbiter circuit (320a) of FIG. 3) may generate first results based on each of the plurality of first delay signals and the first clock signal. For example, the number of arbiters included in the first arbiter circuit (320a) is 2. N It can be 2. For example, the number of first results generated by the first arbiter circuit is 2. N It could be a dog.

[0088] In operation 640, the second delay circuit can generate a plurality of second delay signals by delaying the input signal based on the first value of the second gain signal. For example, the second delay circuit can be included in a second circuit group.

[0089] According to one embodiment, the second delay circuit can generate a plurality of second delay signals by delaying an input signal by a delay time corresponding to a first value of a second gain signal using a plurality of DTCs within the second delay circuit. The plurality of second delay signals can have slightly different time differences due to differences in physical properties between the DTCs. For example, the number of the plurality of second delay signals is 2 N It could be a dog.

[0090] Action 640 is independent of action 620 and can be performed in parallel.

[0091] In operation 650, the second arbiter circuit can generate second results based on each of the plurality of second delay signals and the first clock signal. For example, the number of arbiters included in the second arbiter circuit is 2. N It can be 2. For example, the number of second results generated by the second arbiter circuit is 2. N It could be a dog.

[0092] Action 650 is independent of action 630 and can be performed in parallel.

[0093] In one embodiment, the TDC (210) is 2 N If we include 16 circuit groups, the total number of generated results is 2 N ×2 N It can be 4. For example, if N is 4, the total number of generated results can be 256.

[0094] In operation 660, the addition circuit may generate a first sum result based on the first results and the second results. For example, the first sum result may be represented by 2×N bits. For example, when N is 4, the first sum result may be represented by 8 bits.

[0095] After operation 660 is performed, the DPLL (e.g., DPLL (105) of FIG. 2) can change the clock signal generated by the divider (e.g., divider (270) of FIG. 2) based on the first summation result. A second clock signal can be generated based on the first summation result. For example, the first clock signal input to the TDC can be changed to the second clock signal.

[0096] According to one embodiment, the TDC circuit can repeatedly generate a summation result based on an input signal and a clock signal, and the DPLL can change the clock signal based on the summation result. The TDC circuit can adjust the time detection range by changing the operating mode based on the summation result. For example, the processing circuit can adjust the time detection range by adjusting the time delay range indicated by the values ​​of the gain signals input to the TDC. As the time detection range becomes narrower, the resolution for detecting a time difference increases.

[0097] FIG. 7 is a flowchart of a method for generating a second summation result of a TDC used to generate a clock signal, according to one embodiment.

[0098] The operations 710 to 770 below may be performed by a TDC circuit. For example, the TDC circuit may include a TDC (e.g., TDC (210) of FIG. 2), an adder circuit (e.g., adder (220) of FIG. 2), and a processing circuit (e.g., TDC controller (230) of FIG. 2). In one embodiment, the operation 710 below may be performed after the operation 660 described above with reference to FIG. 6 is performed.

[0099] In operation 710, the processing circuit can determine whether to change the operating mode from the first mode to the second mode based on the first sum result.

[0100] According to one embodiment, the processing circuit may determine to change the operating mode from the first mode to the second mode when the first sum result is less than a first threshold value preset for the first mode. For example, for the first mode, when the first sum result is generated, the processing circuit may determine whether the first sum result is less than the first threshold value and greater than or equal to a second threshold value. The processing circuit may change the operating mode from the first mode to the second mode when the first sum result is less than the first threshold value and greater than or equal to the second threshold value. For example, when the first sum result is expressed in 8 bits, the first sum result may represent any value from 0 to 255. A first sum result of 0 means that all delay signals are faster than the first clock signal, and a first sum result of 255 means that all delay signals are slower than the first clock signal. If the first clock signal is properly locked to the input signal, the first sum result may have a value intermediate between 0 and 255 (e.g., 127 or 128). The first threshold value and the second threshold value may be set to include a value intermediate to the range of values ​​that the first sum result may represent.

[0101] An embodiment of determining whether to change the operation mode from the first mode to the second mode is described in detail below with reference to FIG. 8.

[0102] In operation 720, the processing circuit can generate a second value of the first gain signal indicating a third time detection range of the second mode and a second value of the second gain signal indicating a fourth time detection range of the second mode when the operation mode is changed to the second mode.

[0103] According to one embodiment, when the delay time of the input signal according to the first value of the first gain signal is less than the median value in the entire time detection range, the second value of the first gain signal may represent a value equal to or greater than the first value of the first gain signal. By making the second value of the first gain signal greater than the first value of the first gain signal, the entire time detection range may be reduced.

[0104] According to one embodiment, when the delay time of the input signal according to the first value of the second gain signal is equal to or greater than the median value in the entire time detection range, the second value of the second gain signal may represent a value equal to or smaller than the first value of the second gain signal. By making the second value of the second gain signal smaller than the first value of the second gain signal, the entire time detection range may be reduced.

[0105] Depending on the multiple operation modes, the values ​​of the multiple gain signals generated in each mode are exemplified below with reference to [Table 1]. For example, the value of the gain signal may be expressed as 4 bits.

[0106] Gain signal operation mode 1 mode 2 mode 3 mode 4 mode 5 mode 6 mode SEL DTC1 000000010010001101000101SEL DTC2 000100100011010001010110SEL DTC3 001000110100010101100110SEL DTC4 001101000101011001100110SEL DTC5 010001010110011101110111SEL DTC6 0101011001110111011101110111SEL DTC7 0110011101110111011101110111SEL DTC8 0111100010001000100010001000SEL DTC9 1000100010001000100010001000SEL DTC10100110001000100010001000SEL DTC11 101010011001100110011001SEL DTC12 101110101001100110011001SEL DTC13 110010111010100110011001SEL DTC14 110111001011101010101010SEL DTC15 111011011100101110101010SEL DTC16 111111101101110010111010

[0107] The time detection range in the first mode may be a time corresponding to 0000 to 1111. The time detection range in the second mode may be a time corresponding to 0001 to 1110. The time detection range in the third mode may be a time corresponding to 00101 to 1101. The time detection range in the fourth mode may be a time corresponding to 0010 to 1100. The time detection range in the fifth mode may be a time corresponding to 0100 to 1011. The time detection range in the sixth mode may be a time corresponding to 0101 to 1010. The sixth mode may be a final operation mode. The median value in the entire time detection range may be 1000.

[0108] As the operation mode switches to the subsequent mode, the value of the gain signal (e.g., the first gain signal) that was indicating a value lower than 1000 may increase or not change. For example, in the first mode, SEL DTC1 The first value is 0000, and in the second mode SEL DTC1 The second value can be 0001.

[0109] Even if the operation mode is switched to the subsequent mode, the value of the gain signal (e.g., the first gain signal) that was indicating 1000 may not change. For example, in the first mode, SEL DTC9 The first value is 1000, and in the second mode SELDTC9 The second value can be 1000.

[0110] As the operation mode switches to the subsequent mode, the value of the gain signal (e.g., the second gain signal) that was indicating a value higher than 1000 may decrease or not change. For example, in the first mode, SEL DTC16 The first value is 1111, and in the second mode SEL DTC16 The second value of may be 1110.

[0111] In operation 730, a first delay circuit (e.g., the first delay circuit (310a) of FIG. 3) can generate a plurality of third delay signals by delaying an input signal based on a second value of the first gain signal.

[0112] According to one embodiment, the first delay circuit can generate a plurality of third delay signals by delaying an input signal by a delay time corresponding to a second value of the first gain signal using a plurality of DTCs within the first delay circuit. The plurality of third delay signals can have slightly different time differences due to differences in physical properties between the DTCs. For example, the number of the plurality of third delay signals is 2 N It could be a dog.

[0113] In operation 740, the first arbiter circuit (e.g., the first arbiter circuit (320a) of FIG. 3) may generate third results based on each of the plurality of third delay signals and the second clock signal. For example, the number of third results generated by the first arbiter circuit is 2 N It can be. The second clock signal can be a signal generated by a divider (e.g., divider (270) of FIG. 2). For example, the second clock signal can be different from the first clock signal.

[0114] In operation 750, the second delay circuit can generate a plurality of fourth delay signals by delaying the input signal based on the second value of the second gain signal.

[0115] According to one embodiment, the second delay circuit can generate a plurality of fourth delay signals by delaying the input signal by a delay time corresponding to the second value of the second gain signal using a plurality of DTCs in the second delay circuit. The plurality of fourth delay signals can have slightly different time differences due to differences in physical properties between the DTCs. For example, the number of the plurality of fourth delay signals is 2 N It could be a dog.

[0116] Action 750 is independent of action 730 and can be performed in parallel.

[0117] In operation 760, the second arbiter circuit can generate fourth results based on each of the plurality of fourth delay signals and the second clock signal. For example, the number of fourth results generated by the second arbiter circuit is 2 N It could be a dog.

[0118] In operation 770, the addition circuit may generate a second sum result based on the third and fourth results. For example, the second sum result may be represented by 2×N bits. For example, when N is 4, the second sum result may be represented by 8 bits.

[0119] After operation 770 is performed, the DPLL (e.g., DPLL (105) of FIG. 2) can change the clock signal generated by the divider based on the second sum result. For example, the second clock signal input to the TDC can be changed to a third clock signal.

[0120] According to one embodiment, operations 710 and 770 may be performed repeatedly. For example, in operation 710, the processing circuit may determine whether to change the operating mode from the current mode to the next mode based on the current sum result. Through operations 720 to 770, a sum result for the changed mode is generated, and the generated sum result may be used again for operation 710.

[0121] According to one embodiment, the processing circuit can determine whether the current operating mode is the final mode (e.g., the sixth mode in [Table 1]). If the current operating mode is the final mode, the processing circuit can input the values ​​of the plurality of gain signals corresponding to the final mode to the TDC and then not change the values ​​of the plurality of gain signals. If the number of iterations for the final mode is preset, after the corresponding iterations are performed, the processing circuit can no longer input the values ​​of the plurality of gain signals to the TDC.

[0122] FIG. 8 is a flowchart of a method for determining whether to change the operation mode from the first mode to the second mode based on the first sum result, according to one embodiment.

[0123] According to one embodiment, the operation 710 described above with reference to FIG. 7 may include operations 810 to 830 below. Operations 810 to 830 may be performed by a TDC circuit. For example, the TDC circuit may include a TDC (e.g., TDC (210) of FIG. 2), an adder circuit (e.g., adder (220) of FIG. 2), and a processing circuit (e.g., TDC controller (230) of FIG. 2).

[0124] In operation 810, the processing circuit can determine first differences between each of the plurality of sum results in the first mode including the first sum result and a first value preset for the first mode. For example, when the number of interactions set for the first mode is 20, the processing circuit can determine first differences between each of the 20 plurality of sum results and the first value preset for the first mode. For example, when the first sum result is expressed by N bits, the first value preset for the first mode is 2 N-1 may be. When the first sum result is expressed in 8 bits, the first sum result may represent 0 to 255, and the first value preset for the first mode may be 128. In the above case, the first difference may represent any one of -128 to 127.

[0125] At operation 820, the processing circuit can determine a first maximum value among the first differences. The first maximum value can decrease as the phase or frequency of the input signal is accurately determined.

[0126] At operation 830, the processing circuit may determine to change the operating mode from the first mode to the second mode if the first maximum value is less than a first threshold value preset for the first mode.

[0127] In one embodiment, the processing circuit may not change the operating mode if the first maximum value is greater than or equal to a first threshold value preset for the first mode. If the operating mode is not changed, operations 610 to 660 for the first mode may be re-performed.

[0128] FIG. 9 illustrates codes output by a TDC according to an operating mode, according to one embodiment.

[0129] According to one embodiment, the graph (910) depicts a curve (914) in which results output over time differences in the first mode are accumulated. Each curve within the first region (912) represents a curve in which results output by each circuit group of a TDC (e.g., TDC (210) of FIG. 2) are accumulated. For example, if the number of circuit groups is 16 and each circuit group includes 16 signal paths, the curve (914) ultimately accumulates 256 results. The first time difference at which the first result appears to the second time difference at which the 256th result appears may be the first overall time detection range in the first mode.

[0130] The time detection range of the TDC shown in the graph (910) is approximately 200 ps (pico seconds), and the resolution can be 0.3 ps / bit.

[0131] According to one embodiment, the graph (920) depicts a curve (924) in which results output over time differences in the second mode are accumulated. Each curve in the second region (922) represents a curve in which results output by each circuit group of the TDC are accumulated. For example, if the number of circuit groups is 16 and each circuit group includes 16 signal paths, the curve (924) ultimately accumulates 256 results. The third time difference at which the first result appears to the fourth time difference at which the 256th result appears may be the second overall time detection range in the second mode. For example, the first overall time detection range in the first mode may be wider than the second overall time detection range in the second mode.

[0132] The time detection range of the TDC shown in the graph (920) is approximately 110 ps, ​​and the resolution can be 0.2 ps / bit.

[0133] According to one embodiment, a time-to-digital converter (TDC) circuit may include a processing circuit (230) that generates a first value of a first gain signal representing a first time detection range in a first mode and a first value of a second gain signal representing a second time detection range in the first mode, a first delay circuit (310a) that generates a plurality of first delay signals by delaying an input signal based on the first value of the first gain signal, a first arbiter circuit (320a) that generates first results based on each of the plurality of first delay signals and a first clock signal, a second delay circuit that generates a plurality of second delay signals by delaying the input signal based on the first value of the second gain signal, a second arbiter circuit that generates second results based on each of the plurality of second delay signals and the first clock signal, and an addition circuit (220) that generates a first sum result based on the first results and the second results.

[0134] According to one embodiment, the plurality of first delay signals may include a first sub-delay signal and a second sub-delay signal.

[0135] According to one embodiment, a first delay circuit that generates a plurality of first delay signals may include a first sub-delay circuit (311a) that generates a first sub-delay signal based on a first value of a first gain signal, and a second sub-delay circuit that generates a second sub-delay signal based on the first value of the first gain signal.

[0136] According to one embodiment, the processing circuit may determine whether to change the operating mode from the first mode to the second mode based on the first sum result, and if the operating mode is changed to the second mode, may generate a second value of the first gain signal representing a third time detection range of the second mode and a second value of the second gain signal representing a fourth time detection range of the second mode.

[0137] In one embodiment, the processing circuit may determine to change the operating mode from the first mode to the second mode if the first sum result is less than a first threshold value preset for the first mode.

[0138] According to one embodiment, the processing circuit may determine first differences between each of a plurality of sum results in a first mode including a first sum result and a first value preset for the first mode, determine a first maximum value among the first differences, and determine to change the operating mode from the first mode to the second mode when the first maximum value is less than a first threshold value preset for the first mode.

[0139] According to one embodiment, the first overall time detection range in the first mode may be wider than the second overall time detection range in the second mode.

[0140] According to one embodiment, the first delay circuit can generate a plurality of third delay signals by delaying the input signal based on the second value of the first gain signal.

[0141] According to one embodiment, the first arbiter circuit can generate third results based on each of the plurality of third delay signals and the second clock signal.

[0142] According to one embodiment, the second delay circuit can generate a plurality of fourth delay signals by delaying the input signal based on the second value of the second gain signal.

[0143] According to one embodiment, the second arbiter circuit can generate fourth results based on each of the plurality of fourth delay signals and the second clock signal.

[0144] In one embodiment, the addition circuit can generate a second sum result based on the third results and the fourth results.

[0145] According to one embodiment, the second clock signal may be generated based on the first summation result.

[0146] In one embodiment, the input signal may be generated by a crystal oscillator.

[0147] According to one embodiment, a digital phase locked loop (105) includes a time-to-digital converter (TDC) circuit that detects a phase and frequency difference between an input signal and a clock signal and generates a sum result representing the detected difference, a digital loop filter (DLF) (240) that filters the sum result to generate a filtered phase error signal, a delta-sigma modulator (DSM) (250) that generates noise based on the sum result, a digitally controlled oscillator (DCO) (260) that generates an output oscillation signal based on the phase error signal and noise, and a divider (270) that divides the output oscillation signal of the digitally controlled oscillator by a set division ratio, and the time-to-digital converter circuit includes a processing circuit (230) that generates a first value of a first gain signal representing a first time detection range in a first mode and a first value of a second gain signal representing a second time detection range in the first mode, a first delay circuit (310a) that generates a plurality of first delay signals by delaying an input signal based on the first value of the first gain signal, and a plurality of first delay signals, respectively. It may include a first arbiter circuit (320a) that generates first results based on a first clock signal, a second delay circuit that generates a plurality of second delay signals by delaying an input signal based on a first value of a second gain signal, a second arbiter circuit that generates second results based on each of the plurality of second delay signals and the first clock signal, and an addition circuit (220) that generates a first sum result based on the first results and the second results.

[0148] According to one embodiment, a method performed by a time-to-digital converter (TDC) circuit comprises: an operation (610) in which a processing circuit (230) generates a first value of a first gain signal representing a first time detection range in a first mode and a first value of a second gain signal representing a second time detection range in the first mode; an operation (620) in which a first delay circuit (310a) generates a plurality of first delay signals by delaying an input signal based on the first value of the first gain signal; an operation (630) in which a first arbiter circuit (320a) generates first results based on each of the plurality of first delay signals and a first clock signal; an operation (640) in which a second delay circuit generates a plurality of second delay signals by delaying an input signal based on the first value of the second gain signal; an operation (650) in which a second arbiter circuit generates second results based on each of the plurality of second delay signals and the first clock signal; and an operation (650) in which an adding circuit (220) generates a plurality of first results based on the first results and the second results. It may include an operation (660) for generating a first sum result.

[0149] According to one embodiment, the operation (620) of generating a plurality of first delay signals may include an operation in which a first sub-delay circuit of the first delay circuit generates a first sub-delay signal among the plurality of first delay signals based on a first value of the first gain signal, and an operation in which a second sub-delay circuit of the first delay circuit generates a second sub-delay signal among the plurality of first delay signals based on the first value of the first gain signal.

[0150] According to one embodiment, the method may include an operation (710) of determining whether the processing circuit changes the operating mode from the first mode to the second mode based on the first sum result.

[0151] According to one embodiment, the method may include an operation (720) in which the processing circuit generates a second value of the first gain signal representing a third time detection range of the second mode and a second value of the second gain signal representing a fourth time detection range of the second mode when the operating mode is changed to the second mode.

[0152] According to one embodiment, the operation (710) of determining whether to change the operating mode from the first mode to the second mode may include an operation in which the processing circuit determines to change the operating mode from the first mode to the second mode when the first sum result is less than a first threshold value preset for the first mode.

[0153] According to one embodiment, the operation (710) of determining whether to change the operating mode from the first mode to the second mode may include the operation (810) of the processing circuit determining first differences between each of a plurality of sum results in the first mode including the first sum result and a first value preset for the first mode, the operation (820) of the processing circuit determining a first maximum value among the first differences, and the operation (830) of the processing circuit determining that the operating mode is to be changed from the first mode to the second mode when the first maximum value is less than a first threshold value preset for the first mode.

[0154] According to one embodiment, the first overall time detection range in the first mode may be wider than the second overall time detection range in the second mode.

[0155] According to one embodiment, the method may include an operation (730) in which the first delay circuit generates a plurality of third delay signals by delaying the input signal based on the second value of the first gain signal.

[0156] According to one embodiment, the method may include an operation (740) in which the first arbiter circuit generates third results based on each of the plurality of third delay signals and the second clock signal.

[0157] According to one embodiment, the method may include an operation (750) in which the second delay circuit generates a plurality of fourth delay signals by delaying the input signal based on a second value of the second gain signal.

[0158] According to one embodiment, the method may include an operation (760) in which the second arbiter circuit generates fourth results based on each of the plurality of fourth delay signals and the second clock signal.

[0159] According to one embodiment, the method may include an operation (770) in which the addition circuit generates a second sum result based on the third results and the fourth results.

[0160] According to one embodiment, the second clock signal may be generated based on the first summation result.

[0161] In one embodiment, the input signal may be generated by a crystal oscillator.

[0162] The embodiments described above may be implemented using hardware components, software components, and / or a combination of hardware components and software components. For example, the devices, methods, and components described in the embodiments may be implemented using a general-purpose computer or a special-purpose computer, such as, for example, a processor, a controller, an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a programmable logic unit (PLU), a microprocessor, or any other device capable of executing instructions and responding to them. The processing device may execute an operating system (OS) and software applications running on the operating system. The processing device may also access, store, manipulate, process, and generate data in response to the execution of the software. For ease of understanding, the processing device is sometimes described as being used alone; however, one of ordinary skill in the art will recognize that the processing device may include multiple processing elements and / or multiple types of processing elements. For example, a processing unit may include multiple processors, or a processor and a controller. Other processing configurations, such as parallel processors, are also possible.

[0163] Software may include a computer program, code, instructions, or a combination of one or more of these, and may configure a processing device to perform a desired operation or, independently or collectively, command the processing device. The software and / or data may be permanently or temporarily embodied in any type of machine, component, physical device, virtual equipment, computer storage medium or device, or transmitted signal wave, for interpretation by the processing device or for providing instructions or data to the processing device. The software may also be distributed over networked computer systems and stored or executed in a distributed manner. The software and data may be stored on a computer-readable recording medium.

[0164] The method according to the embodiment may be implemented in the form of program commands that can be executed through various computer means and recorded on a computer-readable medium. The computer-readable medium may include program commands, data files, data structures, etc., alone or in combination, and the program commands recorded on the medium may be those specially designed and configured for the embodiment or may be known and available to those skilled in the art of computer software. Examples of the computer-readable recording medium include magnetic media such as hard disks, floppy disks, and magnetic tapes, optical media such as CD-ROMs and DVDs, magneto-optical media such as floptical disks, and hardware devices specially configured to store and execute program commands such as ROMs, RAMs, and flash memories. Examples of program commands include not only machine language codes such as those generated by a compiler, but also high-level language codes that can be executed by a computer using an interpreter, etc.

[0165] The hardware device described above may be configured to operate as one or more software modules to perform the operations of the embodiment, and vice versa.

[0166] Although the embodiments described above have been described with limited drawings, those skilled in the art will appreciate that various technical modifications and variations can be applied based on the described embodiments. For example, appropriate results can still be achieved even if the described techniques are performed in a different order than described, and / or components of the described systems, structures, devices, circuits, etc. are combined or combined in a different manner than described, or are replaced or substituted with other components or equivalents.

[0167] Therefore, other implementations, other embodiments, and equivalents to the claims also fall within the scope of the claims described below.

Claims

1. In a time-to-digital converter (TDC) circuit, A processing circuit (230) that generates a first value of a first gain signal representing a first time detection range in a first mode and a first value of a second gain signal representing a second time detection range in the first mode; A first delay circuit (310a) that generates a plurality of first delay signals by delaying an input signal based on a first value of the first gain signal; A first arbiter circuit (320a) for generating first results based on each of the plurality of first delay signals and the first clock signal; A second delay circuit that generates a plurality of second delay signals by delaying the input signal based on the first value of the second gain signal; A second arbiter circuit for generating second results based on each of the plurality of second delay signals and the first clock signal; and An addition circuit (220) that generates a first sum result based on the first results and the second results Including, Time-to-digital converter circuit.

2. In paragraph 1, The above plurality of first delay signals include a first sub-delay signal and a second sub-delay signal, The first delay circuit generating the plurality of first delay signals, A first sub-delay circuit (311a) that generates the first sub-delay signal based on the first value of the first gain signal; and A second sub-delay circuit that generates the second sub-delay signal based on the first value of the first gain signal Including, Time-to-digital converter circuit.

3. In paragraph 1 or 2, The above processing circuit, Based on the first sum result, determine whether to change the operation mode from the first mode to the second mode, When the above operation mode is changed to the second mode, a second value of the first gain signal representing the third time detection range of the second mode and a second value of the second gain signal representing the fourth time detection range of the second mode are generated. Time-to-digital converter circuit.

4. In any one of paragraphs 1 to 3, The above processing circuit, If the first sum result is less than the first threshold value preset for the first mode, it is determined to change the operation mode from the first mode to the second mode. Time-to-digital converter circuit.

5. In any one of paragraphs 1 to 4, The above processing circuit, Determine first differences between each of the plurality of sum results in the first mode including the first sum result and a first value preset for the first mode, Determine the first maximum value among the above first differences, If the first maximum value is less than the first threshold value preset for the first mode, it is determined to change the operation mode from the first mode to the second mode. Time-to-digital converter circuit.

6. In any one of paragraphs 1 to 5, The first overall time detection range in the first mode is wider than the second overall time detection range in the second mode. Time-to-digital converter circuit.

7. In any one of paragraphs 1 to 6, The first delay circuit generates a plurality of third delay signals by delaying the input signal based on the second value of the first gain signal, The above first arbiter circuit generates third results based on each of the plurality of third delay signals and the second clock signal, The second delay circuit generates a plurality of fourth delay signals by delaying the input signal based on the second value of the second gain signal, The second arbiter circuit generates fourth results based on each of the plurality of fourth delay signals and the second clock signal, The above addition circuit generates a second sum result based on the third results and the fourth results. Time-to-digital converter circuit.

8. In any one of paragraphs 1 to 7, The second clock signal is generated based on the first summation result. Time-to-digital converter circuit.

9. In any one of paragraphs 1 to 8, The above input signal is generated by a crystal oscillator. Time-to-digital converter circuit.

10. Digital phase-locked loop (105) A time-to-digital converter (TDC) circuit that detects the phase and frequency differences between an input signal and a clock signal and produces a sum result representing the detected difference; A digital loop filter (DLF) (240) that generates a filtered phase error signal by filtering the above sum result; A delta-sigma modulator (DSM) (250) that generates noise based on the above summation result; A digital controlled oscillator (DCO) (260) that generates an output oscillation signal based on the phase error signal and the noise; and A divider (270) that divides the output oscillation signal of the above digitally controlled oscillator by a set division ratio. Including, The above time-to-digital converter circuit, A processing circuit (230) that generates a first value of a first gain signal representing a first time detection range in a first mode and a first value of a second gain signal representing a second time detection range in the first mode; A first delay circuit (310a) that generates a plurality of first delay signals by delaying an input signal based on a first value of the first gain signal; A first arbiter circuit (320a) for generating first results based on each of the plurality of first delay signals and the first clock signal; A second delay circuit that generates a plurality of second delay signals by delaying the input signal based on the first value of the second gain signal; A second arbiter circuit for generating second results based on each of the plurality of second delay signals and the first clock signal; and An addition circuit (220) that generates a first sum result based on the first results and the second results Including, Digital phase-locked loop.

11. A method performed by a time-to-digital converter (TDC) circuit, An operation (610) in which a processing circuit (230) generates a first value of a first gain signal representing a first time detection range in a first mode and a first value of a second gain signal representing a second time detection range in the first mode; An operation (620) in which a first delay circuit (310a) generates a plurality of first delay signals by delaying an input signal based on a first value of the first gain signal; An operation (630) in which a first arbiter circuit (320a) generates first results based on each of the plurality of first delay signals and the first clock signal; An operation (640) in which a second delay circuit generates a plurality of second delay signals by delaying the input signal based on the first value of the second gain signal; The second arbiter circuit generates second results based on each of the plurality of second delay signals and the first clock signal (650); and An operation (660) in which an addition circuit (220) generates a first sum result based on the first results and the second results. Including, method.

12. In paragraph 11, The operation (620) of generating the plurality of first delay signals is: An operation in which a first sub-delay circuit of the first delay circuit generates a first sub-delay signal among the plurality of first delay signals based on a first value of the first gain signal; and An operation in which a second sub-delay circuit of the first delay circuit generates a second sub-delay signal among the plurality of first delay signals based on the first value of the first gain signal. Including, method.

13. In paragraph 11 or 12, An operation (710) for determining whether the processing circuit changes the operation mode from the first mode to the second mode based on the first sum result; and When the above operation mode is changed to the second mode, the processing circuit generates a second value of the first gain signal representing a third time detection range of the second mode and a second value of the second gain signal representing a fourth time detection range of the second mode (720). Including more, method.

14. In any one of paragraphs 11 to 13, The operation (710) for determining whether to change the above operation mode from the first mode to the second mode is: An operation in which the processing circuit determines to change the operation mode from the first mode to the second mode when the first sum result is less than a first threshold value preset for the first mode. Including, method.

15. In any one of paragraphs 11 to 14, The operation (710) for determining whether to change the above operation mode from the first mode to the second mode is: An operation (810) in which the processing circuit determines first differences between each of a plurality of sum results in the first mode including the first sum result and a first value preset for the first mode; The above processing circuit determines a first maximum value among the first differences (820); and An operation (830) in which the processing circuit determines to change the operating mode from the first mode to the second mode when the first maximum value is less than the first threshold value preset for the first mode. Including, method.

Images