Circuit board, and semiconductor package comprising same

Abstract

A circuit board according to an embodiment includes: a build-up insulating portion including a plurality of insulating layers stacked in the vertical direction; a first insulating layer disposed on the build-up insulating portion; a first via electrode disposed in the first insulating layer; and a second wiring layer arranged in each of the plurality of insulating layers and a second via electrode connected to the second wiring layer, wherein the side surface of the first via electrode has an inclination in a direction different from that of the side surface of the second via electrode, and the thickness of the first insulating layer in the vertical direction may be smaller than the thickness of each of the plurality of insulating layers in the vertical direction.

Description

Circuit boards and semiconductor packages including the same

[0001] The present invention relates to a circuit board and a semiconductor package including the same.

[0002] As the performance of electrical and electronic products continues to improve, technologies are being proposed and researched to accommodate a greater number of semiconductor devices on circuit boards of limited size. However, conventional semiconductor packages typically consist of a single semiconductor device, limiting their ability to achieve desired performance.

[0003] Accordingly, semiconductor packages that incorporate multiple semiconductor devices across multiple substrates have recently been developed. These semiconductor packages have a structure in which multiple semiconductor devices are connected horizontally and / or vertically on the circuit board. Consequently, semiconductor packages offer the advantages of efficiently utilizing the mounting area of ​​semiconductor devices and enabling high-speed signal transmission through short signal transmission paths between semiconductor devices.

[0004] Meanwhile, the circuit board includes a build-up insulator including an insulating layer and a build-up wiring portion arranged on the build-up insulator. For example, the circuit board may mean that a mounting position of each semiconductor device is predetermined for mounting at least one semiconductor device, and a build-up wiring portion connected to the semiconductor device is arranged on the build-up insulator. The build-up wiring portion includes a wiring layer arranged on the surface of each insulating layer and a via electrode for vertically connecting each wiring layer. The semiconductor device is mounted on the circuit board and can transmit and receive signals through the build-up wiring portion.

[0005] Meanwhile, in order to implement fine patterns on circuit boards, methods such as the Embedded Trace Substrate (ETS) method, which embeds a wiring layer within an insulating layer, are being used; however, additional processes are required to expose pads for connection to external chips / elements or substrates on the outermost layer of the circuit board, or there is a problem of reduced electrical connection reliability.

[0006] One of the technical challenges of the embodiment is to improve the electrical connection reliability of pads arranged on the outermost layer of a circuit board.

[0007] Additionally, one of the technical challenges of the embodiment is to simultaneously achieve miniaturization of the circuit pattern and reduction of resistance of the pad for bumps.

[0008] Additionally, one of the technical challenges of the embodiment is to prevent loss of signals transmitted from an external chip or substrate.

[0009] The technical problems of the embodiment are not limited to those described in this article, but include those that can be understood through the description of the invention.

[0010] A circuit board according to an embodiment includes a build-up insulating portion including a plurality of insulating layers stacked along a vertical direction; a first insulating layer disposed on the build-up insulating portion; a first via electrode disposed within the first insulating layer; and a second wiring layer disposed on each of the plurality of insulating layers and a second via electrode connected to the second wiring layer; wherein a side surface of the first via electrode has a different inclination from a side surface of the second via electrode, and a vertical thickness of the first insulating layer may be thinner than a vertical thickness of each of the plurality of insulating layers.

[0011] Additionally, in the embodiment, the vertical thickness of the first insulating layer may be the same as the vertical thickness of the first via electrode.

[0012] Additionally, the embodiment may include a second insulating layer disposed on the first insulating layer and a first wiring layer connected to the first via electrode.

[0013] Additionally, in the embodiment, the height of the upper surface of the second insulating layer may be lower than the height of the upper surface of the first wiring layer.

[0014] Additionally, in the embodiment, the vertical thickness of the first via electrode may be thinner than the vertical thickness of the first wiring layer.

[0015] Additionally, in an embodiment, the build-up insulation may include a fourth insulation layer, a fifth insulation layer disposed under the fourth insulation layer, and a sixth insulation layer disposed under the fifth insulation layer.

[0016] Additionally, the embodiment may include a second-first wiring layer disposed within the fourth insulating layer and connected to the first via electrode, and a second-first via electrode connected to the second-first wiring layer.

[0017] Additionally, in the embodiment, the vertical thickness of the fourth insulating layer may be equal to the sum of the vertical thickness of the 2-1 via electrode and the vertical thickness of the 2-1 wiring layer.

[0018] Additionally, in the embodiment, the first via electrode may have a width of the upper surface greater than the width of the lower surface, and the second via electrode may have a width of the upper surface less than the width of the lower surface.

[0019] The circuit board according to the embodiment has a technical effect of improving the electrical connection reliability of a pad placed on the outermost layer.

[0020] In addition, the embodiment has a technical effect of simultaneously realizing refinement of the circuit pattern and reducing resistance of the pad for bumps.

[0021] Additionally, the embodiment can prevent loss of electrical signals connected to external chips or substrates.

[0022] In addition, the embodiment has a technical effect of simplifying the pad formation process in a circuit board manufactured by the ETS method.

[0023] Additionally, the embodiment has a technical effect of being able to implement a micro pattern in an insulating layer disposed adjacent to the outermost layer.

[0024] The technical effects of the embodiments are not limited to those described in this article, but include those that can be understood through the description of the invention.

[0025] Figures 1a and 1b are cross-sectional views of a circuit board (100) according to an embodiment.

[0026] Figures 2a to 2d are process diagrams showing a manufacturing process of a circuit board according to an embodiment.

[0027] FIG. 3 is a drawing showing a semiconductor package including a circuit board according to a second embodiment.

[0028] Hereinafter, a preferred embodiment of the present invention will be described in detail with reference to the attached drawings.

[0029] However, the technical idea of ​​the present invention is not limited to some of the embodiments described, but can be implemented in various different forms, and within the scope of the technical idea of ​​the present invention, one or more of the components between the embodiments can be selectively combined or substituted for use.

[0030] In addition, terms (including technical and scientific terms) used in the embodiments of the present invention may be interpreted as having a meaning that can be generally understood by those of ordinary skill in the technical field to which the present invention pertains, unless explicitly and specifically defined and described. Commonly used terms, such as terms defined in a dictionary, may have their meanings interpreted in consideration of the contextual meaning of the relevant technology. In addition, the terms used in the embodiments of the present invention are for the purpose of describing the embodiments and are not intended to limit the present invention.

[0031] In this specification, singular forms may also include plural forms unless specifically stated otherwise in the phrase, and when it is described as “A and / or at least one (or more) of B, C,” it may include one or more of all combinations that can be combined with A, B, and C. In addition, terms such as first, second, A, B, (a), (b), etc. may be used to describe components of embodiments of the present invention.

[0032] In this specification, for the convenience of explanation, components may be described in the horizontal direction and the vertical direction. The vertical direction means the top (above) or bottom (below) of each component, and the horizontal direction means the direction perpendicular to the vertical direction. In addition, the horizontal direction may include a first horizontal direction and a second horizontal direction. Here, when the horizontal direction follows a Cartesian coordinate system, the first horizontal direction may mean the X-axis, the second horizontal direction may mean the Y-axis, and the vertical direction may mean the Z-axis. When following a cylindrical coordinate system, the first horizontal direction may mean a direction along an azimuth, and the second horizontal direction may mean a direction toward a radius, and these may be selectively used in combination. In addition, the direction along an azimuth may be referred to as a circumferential direction, and the direction toward a radius may be referred to as a centrifugal direction.

[0033] These terms are only intended to distinguish the component from other components, and are not intended to limit the nature, order, or sequence of the component by the term. In addition, when a component is described as being "connected," "coupled," or "connected" to another component, it may include not only cases where the component is directly connected, coupled, or connected to the other component, but also cases where the component is "connected," "coupled," or "connected" by another component between the component and the other component.

[0034] Additionally, the statement that component A is exposed from component B should be understood to mean that component A is exposed from component B, not that component A is exposed from the entire product. That is, when it is stated that component A is exposed from component B, it should be understood to mean that component A is at least partially covered by component C.

[0035] Additionally, when it is described that a component A is in "contact" with a component B, it may include not only cases where that component is in "contact" with the other component directly, but also cases where that component is "contacted" by another component between that component and the other component. Thus, if a component A is to be understood to be in "direct contact" with a component B, it is described as being in "direct contact."

[0036] In addition, when it is written that configuration A is 'covered' by configuration B, it should be understood that configuration A is covered by configuration B, and that the part for the function and purpose to be solved is covered, and unless there are special circumstances, it should not be understood that the entire configuration A is covered by configuration B.

[0037] In addition, when it is described that configuration A is 'fixed' to configuration B, it should be understood that configuration A is not only fixed by being directly combined with configuration B, but also indirectly fixed to configuration B through configuration C and / or configuration D, etc., unless otherwise specified, taking into account the function and purpose to be solved, and when configuration A is only understood to be 'directly fixed' to configuration B, it is described as being 'directly fixed'.

[0038] Additionally, when it is described as being formed or arranged "above or below" each component, "above" or "below" includes not only cases where the two components are in direct contact with each other, but also cases where one or more other components are formed or arranged between the two components. Furthermore, when it is expressed as "above" or "below", it can include the meaning of the downward direction as well as the upward direction based on one component.

[0039]

[0040] (Example)

[0041] Figures 1a and 1b are cross-sectional views of a circuit board (100) according to an embodiment.

[0042] Referring to FIGS. 1A and 1B, a circuit board (100) according to an embodiment may include a first build-up structure (110S), a second build-up structure (120S), and protective layers (140, 145). For example, the first build-up structure (110S) may include, but is not limited to, a first build-up insulating portion (110), a first build-up wiring portion (115), and a second protective layer (145). The first build-up wiring portion (115) may include a wiring layer (130) disposed on a surface of each insulating layer, and a via electrode (135) for vertically connecting each wiring layer (130). In addition, the second build-up structure (120S) may include, but is not limited to, a first insulating layer (120), a second insulating layer (122), and a first protective layer (140). The above first protective layer (140) may be referred to as a third insulating layer. The first and second build-up structures (110S, 120S) may function as a laminated circuit for connection to electronic components / main boards, etc.

[0043]

[0044] The first build-up insulation portion (110) may include a single or multiple laminated insulation layers and may provide insulation properties between the build-up wiring portions. The first build-up insulation portion (110) may be referred to as a build-up insulator. The first build-up insulation portion (110) may include, but is not limited to, a fourth insulation layer (111), a fifth insulation layer (112), and a sixth insulation layer (113).

[0045] Additionally, a first insulating layer (120) may be placed on the first build-up insulating portion (110). Additionally, a second insulating layer (122) may be placed on the first insulating layer (120).

[0046] The vertical thickness of the first insulating layer (120) may be thinner than the vertical thickness of each of the plurality of insulating layers of the first build-up insulating member (110). In addition, the vertical thickness of the second insulating layer (122) may correspond to the vertical thickness of the first insulating layer (120).

[0047] Additionally, the thickness of the third insulating layer, which is the first protective layer (140), may be thicker than the vertical thickness of the first insulating layer (120), thereby preventing warping of the substrate.

[0048] In addition, the circuit board (100) according to the embodiment may be classified as a coreless board. Specifically, the build-up structure of the circuit board (100) may not include a core layer and may only include a build-up structure. For example, the build-up structure may be manufactured by performing a process of forming a build-up insulating portion, a wiring layer, and a via electrode through a sequential build-up process in one direction of the insulating member based on the insulating member.

[0049] The insulating layer has the function of arranging the wiring layer or via electrode of the build-up wiring section, securing insulation between circuits, and controlling impedance or insertion loss due to the circuit, and includes an insulating layer including at least one of a thermosetting resin, a photocurable resin, or an optically isotropic film, taking into consideration dielectric constant, mechanical rigidity, and processability.

[0050]

[0051] For example, the plurality of insulating layers (110) of the first build-up structure (110S) may include at least one of an inorganic filler and glass fiber. On the other hand, at least one of the at least one insulating layer of the second build-up structure (120S) may not include an inorganic filler and glass fiber.

[0052] For example, each insulating layer (111, 112, 113) of the first build-up insulating portion (110) may include at least one of Ajinomoto build-up film (ABF), epoxy resin, polyimide, phenolic resin, bismaleimide triazine (BT) resin, and silicone resin.

[0053] In addition, each insulating layer (111, 112, 113) of the first build-up insulating portion (110) may include a prepreg, thereby having a strength of a certain level or higher that can improve the bending characteristics of the circuit board. The prepreg constituting each insulating layer (111, 112, 113) of the first build-up insulating portion (110) may have a structure in which a glass fiber layer in the form of a fabric sheet, such as a glass fabric, is impregnated with an epoxy resin or the like.

[0054]

[0055] Meanwhile, the second build-up structure (120S) includes a first insulating layer (120) and a second insulating layer (122) that are laminated in a vertical direction, and the first insulating layer (120) of the second build-up structure (120S) may not include an inorganic filler and glass fibers. On the other hand, the second insulating layer (122) of the second build-up structure (120S) may include an inorganic filler or glass fibers.

[0056] For example, the first insulating layer (120) of the second build-up structure (120S) may be a photocurable material, and may include, for example, one or more of a photocurable resin (PID: Photo Imageable Dielectric resin), a photosensitive polyimide, a liquid photoimageable solder resist (LPI), a photosensitive epoxy, or a photosensitive acrylic.

[0057] Additionally, the first insulating layer (120) of the second build-up structure (120S) may include an optically isotropic film, and may include, for example, one or more of a cyclic olefin copolymer (COC), a cyclic olefin polymer (COP), an optically isotropic polycarbonate (PC), or an optically isotropic polymethyl methacrylate (PMMA).

[0058]

[0059] Next, the first build-up wiring portion (115) of the circuit board (100) may include a second wiring layer (130) arranged on the surface of each insulating layer and a second via electrode (135) for vertically connecting each second wiring layer (130).

[0060] The second via electrode (135) is formed in a through hole that penetrates each insulating layer of the first build-up insulating portion (110), and the through hole can be formed by any one of mechanical processing, laser processing, and chemical processing. When the through hole is formed by mechanical processing, methods such as milling, drilling, and routing can be used. When formed by laser processing, a UV or CO2 laser method can be used, and for chemical processing, a chemical agent including aminosilane, ketones, etc. can be used.

[0061] The second via electrode (135) can be formed by forming a through hole penetrating each insulating layer of the first build-up insulating portion (110) and filling the inside of the formed through hole with a conductive material. Once the through hole is formed, the inside of the through hole can be filled with a conductive material to form the second via electrode (135). The metal material forming the second via electrode (135) can be at least one material selected from copper (Cu), silver (Ag), tin (Sn), gold (Au), nickel (Ni), and palladium (Pd). In addition, the filling of the conductive material can use any one of electroless plating, electrolytic plating, screen printing, sputtering, evaporation, inkjetting, and dispensing, or a combination thereof.

[0062] The second build-up structure (120S) includes a plurality of first via electrodes (125) formed in through holes penetrating the first insulating layer (120). The first via electrode (125) may be the via electrode closest to the outermost layer of the circuit board (100).

[0063]

[0064] Meanwhile, in the embodiment, the expansion direction of the first via electrode (125) of the second build-up structure (120S) and the second via electrode (130) of the first build-up structure (110S) may be different.

[0065] In detail, the horizontal width of the first via electrode (125) may become smaller from the upper surface to the lower surface. The width of the upper surface of the first via electrode (125) may be larger than the width of the lower surface.

[0066] On the other hand, the horizontal width of the second via electrode (130) may increase from the upper surface to the lower surface. The width of the upper surface of the second via electrode (130) may be smaller than the width of the lower surface.

[0067] Accordingly, the embodiment has a technical effect of preventing loss of a signal transmitted from an external element or substrate by increasing the area in contact with the pad by forming the first via electrode (125) connected to the pad arranged on the outermost layer of the circuit board so that the width of the upper surface is greater than the width of the lower surface.

[0068]

[0069] Next, the first build-up structure (110S) may include a second wiring layer (118) electrically connected to the second via electrode (135). The second wiring layer (118) may include pads and / or traces (or connection patterns) for connecting to the second via electrode (135) and / or semiconductor elements and / or capacitors. The traces may be signal wiring lines connecting between a plurality of pads. The second wiring layer (118) may be referred to as a wiring pattern layer, a metal wiring, or a wiring portion.

[0070] Additionally, the second build-up structure (120S) may include a first wiring layer (126) electrically connected to the first via electrode (125).

[0071] The first wiring layer (126) can have the function of transmitting signals and / or power to semiconductor elements placed on the circuit board (100) and the function of impedance matching.

[0072] At this time, the pad of the first wiring layer (126) may include a connection pad or a connecting pad. The connection pad may be a mounting pad on which an electronic component or semiconductor chip is mounted, or a terminal pad connected to an external substrate. The connection pad is a contact portion that comes into contact with a via electrode, and may include a lateral extension portion with a horizontal width greater than that of the trace for alignment margin.

[0073] Any one of the first build-up wiring portions (115) described above may have an ETS (Embedded Trace Substrate) structure. For example, the first build-up wiring portion (115) disposed on the upper surface of the circuit board (100) may have an ETS structure. For example, the build-up wiring portion disposed on the upper surface of the circuit board (100) may be disposed in a recess provided on the upper surface of the fourth uppermost insulating layer (111). The ETS structure may also be referred to as a buried structure. The ETS structure is advantageous for miniaturization compared to a build-up wiring portion having a general protruding structure. Accordingly, the embodiment enables the formation of electrodes corresponding to the size and pitch of terminals provided in the semiconductor device. Through this, the embodiment can improve the circuit integration. Furthermore, the embodiment can minimize the transmission distance of a signal transmitted through the semiconductor device, thereby minimizing signal transmission loss.

[0074] Additionally, any one of the first build-up wiring sections (115) can be formed by an additive process, a subtractive process, a modified semi-additive process (MSAP), or a semi-additive process (SAP).

[0075] In addition, the first build-up wiring portion (115) may be formed of at least one metal material selected from gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), aluminum (Al), silicon (Si), and zinc (Zn). In addition, the first build-up wiring portion (115) may be formed of a paste or solder paste including at least one metal material selected from gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn) having excellent bonding strength.

[0076]

[0077] The second wiring layer (135) may include, but is not limited to, a 2-1 wiring layer (136) connected to the upper surface of the second via electrode (130), a 2-2 wiring layer (137) connected to the lower surface of the second via electrode (130), and a 2-3 wiring layer (138) disposed under the first build-up insulation (110).

[0078] Meanwhile, the second wiring layer (135) can be arranged to be embedded in each insulating layer of the first build-up insulating portion (110).

[0079] On the other hand, the first wiring layer (126) may have a protruding shape on the second insulating layer (122). The upper surface of the first wiring layer (126) may be positioned higher than the upper surface of the second insulating layer (122). Accordingly, the embodiment has a technical effect of implementing the second wiring layer (135) in a fine pattern through the ETS method while at the same time forming the first wiring layer (126) to protrude outside the insulating layer, thereby improving the reliability of electrical connection with a bump or a connection portion.

[0080]

[0081] Next, the circuit board (100) according to the embodiment may include first and second protective layers (140, 145) respectively disposed on the wiring layer of the uppermost or lowermost insulating layer. For example, the embodiment may include the first protective layer (140) disposed on the second insulating layer (122) and the second protective layer (145) disposed under the sixth insulating layer (113).

[0082] The first and second protective layers (140, 145) can prevent problems such as oxidation or peeling of the build-up structure due to penetration of moisture and / or external contaminants. In addition, the protective layer is formed of a material having low solder wettability to prevent short circuits between adjacent solders when connecting the build-up structure and electronic components or a main board, thereby preventing bridging short circuits between adjacent solders.

[0083] In addition, the first and second protective layers (140, 145) include an insulating material, and include various materials that can be cured by heating or light irradiation after being applied to protect the surfaces of the insulating layers and the surfaces of the wiring layers. The first and second protective layers (140, 145) may be resist layers, and for example, the first and second protective layers (140, 145) may be solder resist layers that include organic polymer materials. For example, the first and second protective layers (140, 145) include an epoxy acrylate series resin. In detail, the first and second protective layers (140, 145) include a resin, a curing agent, a photoinitiator, a pigment, a solvent, a filler, an additive, an acrylic series monomer, etc. However, the embodiment is not limited thereto, and the first and second protective layers (140, 145) may be any one of a photosolder resist layer, a cover-lay, and a polymer material.

[0084] Meanwhile, although FIGS. 1A and 1B illustrate that the first protective layer (140) is disposed on the second insulating layer (122), the embodiment may include a case where the first protective layer (140) is not disposed. In this case, the second insulating layer (122) may perform the function of the protective layer.

[0085]

[0086] Next, FIGS. 2A to 2D are process diagrams showing a manufacturing process of a circuit board according to an embodiment. First, referring to FIG. 2A, the first build-up insulating portion (110) can be manufactured using an ETS (Embedded Trace Substrate) method. For example, the first build-up insulating portion (110) can include a fourth insulating layer (111), a fifth insulating layer (112) disposed under the fourth insulating layer (111), and a sixth insulating layer (113) disposed under the fifth insulating layer (112).

[0087] The plurality of insulating layers (110) of the first build-up structure (110S) may include at least one of an inorganic filler and glass fiber.

[0088] For example, each insulating layer (111, 112, 113) of the first build-up insulating portion (110) may include at least one of Ajinomoto build-up film (ABF), epoxy resin, polyimide, phenolic resin, bismaleimide triazine (BT) resin, and silicone resin.

[0089] Alternatively, each insulating layer (111, 112, 113) of the first build-up insulating portion (110) may include a prepreg, thereby having a strength of a certain level or higher that can improve the bending characteristics of the circuit board. The prepreg constituting each insulating layer (111, 112, 113) of the first build-up insulating portion (110) may have a structure in which a glass fiber layer in the form of a fabric sheet, such as a glass fabric, is impregnated with an epoxy resin or the like.

[0090] Next, a second-first wiring layer (136) and a second-first via electrode (131) can be formed within the fourth insulating layer (111). A second-second wiring layer (137) and a second-second via electrode (132) can be formed within the fifth insulating layer (112). A second-third wiring layer (138) can be formed within the sixth insulating layer (113). Each of the second wiring layers (135) can include a plurality of them. In addition, the second via electrode (130) can have a larger area on the lower surface than on the upper surface.

[0091]

[0092] Next, referring to FIG. 2b, a first insulating layer (120) can be formed on the first build-up insulating portion (110). The first insulating layer (120) can be formed using an additive process, a subtractive process, a modified semi-additive process (MSAP), a semi-additive process (SAP), or the like. For example, after forming the first insulating layer (120) on the first build-up insulating portion (110), a through hole can be formed, and a first via electrode (125) and a first wiring layer (126) can be formed using plating.

[0093] Meanwhile, the second build-up structure (120S) includes a first insulating layer (120) and a second insulating layer (122) that are laminated in a vertical direction, and the first insulating layer (120) of the second build-up structure (120S) may not include an inorganic filler and glass fibers. On the other hand, the second insulating layer (122) of the second build-up structure (120S) may include an inorganic filler or glass fibers.

[0094] For example, the first insulating layer (120) of the second build-up structure (120S) may be a photocurable material, and may include, for example, one or more of a photocurable resin (PID: Photo Imageable Dielectric resin), a photosensitive polyimide, a liquid photoimageable solder resist (LPI), a photosensitive epoxy, or a photosensitive acrylic.

[0095] Additionally, the first insulating layer (120) of the second build-up structure (120S) may include an optically isotropic film, and may include, for example, one or more of a cyclic olefin copolymer (COC), a cyclic olefin polymer (COP), an optically isotropic polycarbonate (PC), or an optically isotropic polymethyl methacrylate (PMMA).

[0096] Meanwhile, the second insulating layer (122) may include an inorganic filler or glass fiber.

[0097] For example, the second insulating layer (122) may include at least one of Ajinomoto Build-up Film (ABF), epoxy resin, polyimide, phenolic resin, bismaleimide triazine (BT) resin, and silicone resin.

[0098] In addition, the second insulating layer (122) may include a prepreg, thereby having a strength of a certain level or higher that can improve the bending characteristics of the circuit board. The prepreg constituting the second insulating layer (122) may have a structure in which a glass fiber layer in the form of a fabric sheet, such as a glass fabric, is impregnated with an epoxy resin or the like.

[0099] The first via electrode (125) may be formed so that the upper surface has a larger area than the lower surface. Accordingly, the expansion directions of the first via electrode (125) and the second via electrode (130) may be opposite to each other. In addition, the first via electrode (125) may have a shape in which the horizontal width becomes smaller as it goes downward. The second via electrode (130) may have a shape in which the horizontal width becomes larger as it goes downward. In addition, the side surface of the first via electrode (125) may have a slope in a different direction from the side surface of the second via electrode (130). Accordingly, the embodiment has a technical effect in that the first via electrode (125) connected to the first wiring layer (126) arranged on the outermost layer of the circuit board is formed so that the width of the upper surface is greater than the width of the lower surface, thereby increasing the area in contact with the first wiring layer (126), thereby reducing electrical resistance and preventing loss of signals transmitted from external elements or the board.

[0100] In addition, in the embodiment, the vertical thickness of the first insulating layer (120) may be thinner than the vertical thickness of each insulating layer of the first build-up insulating portion (110). In detail, the first thickness (T1) of the first insulating layer (120) may be thinner than the second thickness (T2) of the fourth insulating layer (111). In addition, the first thickness (T1) of the first insulating layer (120) may be thinner than the third thickness (T3) of the fifth insulating layer (112). In addition, the first thickness (T1) of the first insulating layer (120) may be thinner than the fourth thickness (T4) of the sixth insulating layer (113). The vertical thicknesses of the fourth insulating layer (111), the fifth insulating layer (112), and the sixth insulating layer (113) may correspond to each other.

[0101] Accordingly, the embodiment has a technical effect of reducing the thickness of the first via electrode (125) connected to the first wiring layer (126) by forming the first insulating layer (120) thinner than the insulating layer of the first build-up insulating portion (110), thereby reducing the electrical resistance and reducing the thickness of the circuit board. In addition, since the first insulating layer (120) does not contain an inorganic filler or glass fiber, it can be formed as a thin insulating layer, and has a technical effect of forming a fine pattern.

[0102] In addition, the vertical thickness of the first via electrode (125) may be the same as the first thickness (T1) of the first insulating layer (120). In addition, the second thickness (T2) of the fourth insulating layer (111) may be the same as the sum of the vertical thickness of the 2-1 via electrode (131) and the vertical thickness of the 2-1 wiring layer (136). In addition, the third thickness (T3) of the fifth insulating layer (112) may be the same as the sum of the vertical thickness of the 2-2 via electrode (132) and the vertical thickness of the 2-2 wiring layer (137). In addition, the vertical thickness of the first via electrode (125) may be smaller than the vertical thickness of the second via electrode (130).

[0103] In addition, a first wiring layer (126) may be formed on the first insulating layer (120). The first wiring layer (126) may include a plurality of layers. The first wiring layer (126) may be electrically connected to the first via electrode (125). The first wiring layer (126) may vertically overlap the first via electrode (125). The first wiring layer (126) may be arranged on the outermost surface of the circuit board and may function as a pad connected to an external chip / component or board. The thickness of the first wiring layer (126) may be greater than the thickness of the first via electrode (125).

[0104]

[0105] Additionally, a third wiring layer (139) can be formed under the first build-up insulation portion (110). The third wiring layer (139) can be formed under the lower surface of the sixth insulation layer (113).

[0106] Accordingly, the embodiment has a technical effect of implementing circuit pattern refinement through a first build-up insulating portion (110) formed by an ETS method, and at the same time, by laminating a first insulating layer (120) on the first build-up insulating portion (110) and forming a first wiring layer (126), thereby preventing exposure of the circuit pattern of the first build-up insulating portion (110) and simplifying the pad formation process.

[0107]

[0108] Next, referring to FIG. 2c, a second insulating layer (122) may be formed on the first insulating layer (120). The second insulating layer (122) may be formed to cover the first wiring layer (126). In addition, a second protective layer (145) may be formed under the first build-up insulating portion (110). The second protective layer (145) may be formed to cover the third wiring layer (139). The second insulating layer (122) and the second protective layer (145) may include different materials.

[0109]

[0110] Next, referring to FIG. 2d, a portion of the second insulating layer (122) may be etched. The etching may be plasma etching, but is not limited thereto. In addition, the height of the upper surface of the second insulating layer (122) may be lower than the height of the upper surface of the first wiring layer (126). The side surface of the second insulating layer (122) may expose a portion of the upper surface and side surface of the first wiring layer (126) by the second insulating layer (122).

[0111] In addition, the fifth thickness (T5) of the second insulating layer (122) may be thinner than the second thickness (T2) of the fourth insulating layer (111). In addition, the fifth thickness (T5) of the second insulating layer (122) may correspond to the first thickness (T1) of the first insulating layer (120), but is not limited thereto. The second insulating layer (122) may be in contact with the side surface of the first wiring layer (126) to prevent the first wiring layer (126) from being detached from external impact.

[0112] Accordingly, the embodiment has a technical effect in that the first wiring layer (126) connected to the external terminal or connection / bump is formed to protrude outside the insulating layer, thereby improving electrical connection reliability. In addition, the first wiring layer (126) has a technical effect in that the area that can be connected to the connection / bump increases as the top and side surfaces are exposed, thereby reducing electrical resistance.

[0113]

[0114] FIG. 3 is a drawing showing a semiconductor package (102) according to a second embodiment. The semiconductor package (102) of the second embodiment may include a circuit board (100) having the build-up structure of FIG. 1. Referring to FIG. 3, the semiconductor package (102) according to the second embodiment may include a circuit board and a chip arranged on the circuit board. In detail, the circuit board may have a connection portion (175) arranged on a first wiring layer (126) arranged on the outermost layer. The connection portion (175) may have a spherical shape. The connection portion (175) may be a solder ball, but is not limited thereto.

[0115] In addition, the circuit board may further include a bonding portion on the first protective layer (140). The bonding portion is positioned on the upper surface of the first protective layer (140) to perform thermal compression bonding with the semiconductor element, and may be used when the pitch of the first wiring layer (126) of the semiconductor element becomes fine and it is difficult to implement with conventional solder bonding.

[0116] In addition, in the second embodiment, a post bump (180) may be disposed on the first wiring layer (126). A surface treatment layer (185) may be disposed on the upper surface of the post bump (180). In addition, a chip or a component may be disposed on the circuit board. The chip (200, 201) may be a processor chip. For example, the chip (200, 201) may be an application processor (AP) chip of any one of a central processor (e.g., CPU), a graphics processor (e.g., GPU), a digital signal processor, an encryption processor, a microprocessor, and a microcontroller. The lower surface of the chip (200, 201) may include terminals (205, 206), and the terminals (205, 206) may include a plurality of terminals.

[0117] Meanwhile, the semiconductor package (102) of the second embodiment may include a plurality of chips that are arranged spaced apart from each other on a single circuit board. For example, the second embodiment may include a first chip (201) that is electrically connected to a first wiring layer (126) through a connection portion (175) and a second chip (200) that is electrically connected to the first wiring layer (126) through a post bump (180). The first chip (201) and the second chip (200) may be different types of application processor (AP) chips.

[0118] The circuit board or semiconductor package according to the embodiment may be applied to any one of a CSP (Chip Scale Package), an FC-CSP (Flip Chip-Chip Scale Package), an FC-BGA (Flip Chip Ball Grid Array), a POP (Package On Package), and a SIP (System In Package).

[0119] Additionally, the circuit board or semiconductor package may be applied to, but is not limited to, smart phones, personal digital assistants, digital video cameras, digital still cameras, vehicles, high-performance servers, network systems, computers, monitors, tablets, laptops, netbooks, televisions, video games, smart watches, automotives, etc.

[0120] The features, structures, effects, etc. described in the above-described embodiments are included in at least one embodiment of the present invention, and are not necessarily limited to just one embodiment. Furthermore, the features, structures, effects, etc. exemplified in each embodiment can be combined or modified in other embodiments by those skilled in the art to which the embodiments pertain. Therefore, the contents related to such combinations and modifications should be construed as falling within the scope of the present invention.

[0121] Although the above description focuses on examples, these are merely examples and do not limit the present invention. Those skilled in the art to which the present invention pertains will appreciate that various modifications and applications not exemplified above are possible without departing from the essential characteristics of the present embodiments. For example, each component specifically shown in the embodiments can be modified and implemented. In addition, differences related to such modifications and applications should be interpreted as being included within the scope of the present invention defined in the appended claims.

Claims

1. A built-up insulation comprising a plurality of insulating layers laminated along a vertical direction; A first insulating layer disposed on the above build-up insulation portion; a first via electrode disposed within the first insulating layer; and A second wiring layer disposed on each of the plurality of insulating layers and a second via electrode connected to the second wiring layer; The side surface of the first via electrode has a different slope from the side surface of the second via electrode, A circuit board, wherein the vertical thickness of the first insulating layer is thinner than the vertical thickness of each of the plurality of insulating layers.

2. In paragraph 1, A circuit board, wherein the vertical thickness of the first insulating layer is the same as the vertical thickness of the first via electrode.

3. In paragraph 1, A circuit board comprising a second insulating layer disposed on the first insulating layer and a first wiring layer connected to the first via electrode.

4. In paragraph 3, A circuit board, wherein the height of the upper surface of the second insulating layer is lower than the height of the upper surface of the first wiring layer.

5. In paragraph 4, A circuit board, wherein the vertical thickness of the first via electrode is thinner than the vertical thickness of the first wiring layer.

6. In paragraph 1, A circuit board, wherein the build-up insulation layer comprises a fourth insulating layer, a fifth insulating layer disposed under the fourth insulating layer, and a sixth insulating layer disposed under the fifth insulating layer.

7. In paragraph 6, A circuit board comprising a 2-1 wiring layer disposed within the 4th insulating layer and connected to the 1st via electrode, and a 2-1 via electrode connected to the 2-1 wiring layer.

8. In paragraph 7, A circuit board, wherein the vertical thickness of the fourth insulating layer is equal to the sum of the vertical thickness of the 2-1 via electrode and the vertical thickness of the 2-1 wiring layer.

9. In paragraph 1, The first via electrode has a width of the upper surface greater than the width of the lower surface, The above second via electrode is a circuit board having a width of the upper surface smaller than the width of the lower surface.

10. A semiconductor package comprising a circuit board according to any one of claims 1 to 9.

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