Circuit board and semiconductor package comprising same

Abstract

Disclosed in an embodiment of the present invention is a circuit board comprising: a first insulating layer; a second insulating layer arranged on the first insulating layer; a first via land arranged between the first insulating layer and the second insulating layer; a second via land arranged between the first via land and the top surface of the second insulating layer; a first via electrode arranged between the first via land and the top surface of the second insulating layer; a second via electrode arranged between the second via land and the top surface of the second insulating layer; and a third via electrode arranged between the bottom surface of the first insulating layer and the top surface of the second insulating layer, wherein the thickness of the first via electrode, the thickness of the second via electrode, and the thickness of the third via electrode are different from each other.

Description

Circuit boards and semiconductor packages including the same

[0001] Embodiments according to the present invention relate to circuit boards and semiconductor packages.

[0002] As the performance of electrical and electronic products continues to improve, technologies are being proposed and researched to attach a greater number of packages to a limited-size substrate. However, because typical packages are based on mounting a single semiconductor chip, achieving the desired performance is limited.

[0003] A typical circuit board or package substrate consists of a processor package, which houses the processor chip, and a memory package, which houses the memory chips, all connected together. These package substrates integrate the processor and memory chips into a single package, reducing the chip footprint and enabling high-speed signal transmission through short paths. Due to these advantages, these package substrates are widely used in mobile devices and other devices.

[0004] Meanwhile, the recent advancements in electronic devices, such as mobile devices, and the adoption of High Bandwidth Memory (HBM) have led to larger package sizes. Furthermore, as the number of functions required for application processors increases, there is a growing demand for separate processor chips for each function, along with circuit boards capable of mounting these processor chips. Even when the application processor is split into two processor chips, the number of terminals (input / output) provided on each processor chip is increasing.

[0005] In addition, due to recent trends such as 5G, the Internet of Things (IoT), increased image quality, and increased communication speed, the number of terminals on processor chips is gradually increasing due to the increase in power and signal quantity. Accordingly, the area, thickness, and circuit pattern density of circuit boards are also increasing. When the area and thickness of circuit boards increase, it becomes difficult to miniaturize products, and there are problems such as reliability issues such as warpage of circuit boards, and product price increases. Therefore, increasing the density of circuit patterns is more advantageous in terms of product price, reliability issues such as warpage, and product miniaturization than increasing the area and thickness of circuit boards. Therefore, miniaturization of circuit patterns and through-holes is required.

[0006] In particular, improvements in the reliability of circuit boards and performance of electrical connections with dies are required.

[0007] An embodiment of the present invention implements a circuit board that is easy to electrically connect to an upper die and a semiconductor package including the same.

[0008] In addition, the embodiment can implement a circuit board and a semiconductor package including the same that reduce capacitance deviation by controlling the area of ​​a via land.

[0009] In addition, the embodiment can implement a circuit board and a semiconductor package including the same with improved integration, increased input / output count, and reduced signal loss through an embedded capacitor structure.

[0010] In addition, the embodiment can implement a circuit board and a semiconductor package including the same in which the occurrence of voids or gaps at the interface of the insulating layers is suppressed by adding a via land instead of a via electrode penetrating the insulating layers of the multi-layers.

[0011] Additionally, the embodiment can implement a circuit board and a semiconductor package including the same with improved reliability of electrical connection through an additional vialand.

[0012] The problem to be solved in the embodiment is not limited to this, and it can be said that the purpose or effect that can be understood from the solution or implementation form of the problem described below is also included.

[0013] A circuit board according to an embodiment of the present invention includes a first insulating layer; a second insulating layer disposed on the first insulating layer; a first via land disposed between the first insulating layer and the second insulating layer; a second via land disposed between the first via land and an upper surface of the second insulating layer; a first via electrode disposed between the first via land and an upper surface of the second insulating layer; a second via electrode disposed between the second via land and an upper surface of the second insulating layer; a third via electrode disposed between a lower surface of the first insulating layer and an upper surface of the second insulating layer; and a dielectric layer disposed between the first via land and the second via land, wherein the dielectric layer overlaps the first insulating layer and the second insulating layer in a horizontal direction, and a thickness of the first via electrode, a thickness of the second via electrode, and a thickness of the third via electrode are different from each other.

[0014] The thickness of the first via electrode may be greater than the thickness of the second via electrode.

[0015] The thickness of the third via electrode may be greater than the thickness of the second via electrode.

[0016] The third via electrode can penetrate the second insulating layer and a portion of the first insulating layer.

[0017] The above first via electrode can overlap the above second via electrode in the horizontal direction.

[0018] The third via electrode may overlap the first via electrode and the second via electrode in a horizontal direction.

[0019] The area of ​​the upper surface of the first via land may be greater than the area of ​​the upper surface of the second via land.

[0020] The thickness of the first via land may be different from the thickness of the second via land.

[0021] The width of the first via electrode and the second via electrode may gradually decrease from the upper surface of the second insulating layer toward the lower surface of the second insulating layer.

[0022] The width of the third via electrode may gradually decrease from the upper surface of the second insulating layer toward the lower surface of the first insulating layer.

[0023] The first via electrode may include a first width having the smallest width on the upper surface of the first insulating layer, the second via electrode may include a second width having the smallest width on the lower surface of the second insulating layer, and the third via electrode may include a third width having the smallest width in an area adjacent to the lower surface of the first insulating layer.

[0024] The above first width may be smaller than the above second width.

[0025] The third width may be smaller than the first width.

[0026] It may include a capacitor structure including the first via land, the dielectric layer, and the second via land sequentially stacked on the first insulating layer.

[0027] The second via electrode may be disposed on the capacitor structure.

[0028] The above first via electrode can penetrate the capacitor structure.

[0029] An embodiment of the present invention provides a substrate that is easily electrically connected to an upper die and a semiconductor package including the same.

[0030] In addition, the embodiment can provide a circuit board and a semiconductor package including the same that reduce capacitance deviation by controlling the area of ​​a via land.

[0031] Additionally, the embodiment can provide a circuit board and a semiconductor package including the same with improved integration, increased input / output count, and reduced signal loss through an embedded capacitor structure.

[0032] In addition, the embodiment can provide a circuit board and a semiconductor package including the same in which the occurrence of voids or gaps at the interface of the insulating layers is suppressed by adding a via land instead of a via electrode penetrating the insulating layers of the multi-layers.

[0033] Additionally, the embodiment can provide a circuit board and a semiconductor package including the same with improved reliability of electrical connection through an additional vialand.

[0034] The various advantageous and beneficial effects of the present invention are not limited to the above-described contents, and will be more easily understood in the course of explaining specific embodiments of the present invention.

[0035] Figure 1 is a cross-sectional view of a circuit board according to a first embodiment of the present invention.

[0036] Figure 2 is an enlarged view of part K1 in Figure 1,

[0037] Figure 3 is an enlarged view of part K2 in Figure 1,

[0038] FIG. 4 is a plan view of a first via electrode, a second via electrode, a first via land, and a second via land in a circuit board according to an embodiment.

[0039] Figure 5 is a cross-sectional view of a circuit board according to a second embodiment of the present invention.

[0040] Figure 6 is an enlarged view of K3 in Figure 5,

[0041] FIG. 7 is a plan view of a first via electrode, a second via electrode, a first via land, and a second via land in a circuit board according to a second embodiment.

[0042] FIG. 8 is a cross-sectional view of a first via electrode, a second via electrode, a first via land, and a second via land in a circuit board according to a modified example.

[0043] FIG. 9 is a plan view of a first via electrode, a second via electrode, a first via land, and a second via land in a circuit board according to a modified example.

[0044] Fig. 10 is a cross-sectional view of a circuit board according to a third embodiment of the present invention.

[0045] Figure 11 is an enlarged view of K4 of Figure 10,

[0046] Figures 12a to 12o are drawings explaining a method for manufacturing a circuit board according to a third embodiment.

[0047] Fig. 13 is a schematic diagram of a semiconductor package according to an embodiment.

[0048] The present invention can be modified in various ways and has various embodiments, and specific embodiments are illustrated and described in the drawings. However, this is not to be construed as a specific embodiment of the present invention.

[0049] It is not intended to be limited to the embodiments, and should be understood to include all modifications, equivalents, or substitutes included in the spirit and technical scope of the present invention.

[0050] Terms that include ordinal numbers, such as "second," "first," etc., may be used to describe various components, but the components are not limited by the terms. The terms are used solely to distinguish one component from another. For example, without departing from the scope of the present invention, a second component may be referred to as "first component," and similarly, a first component may also be referred to as "second component." The term "and / or" includes a combination of multiple related items described herein or any of multiple related items described herein.

[0051] When a component is referred to as being "connected" or "connected" to another component, it should be understood that it may be directly connected or connected to that other component, but that there may be other components intervening. Conversely, when a component is referred to as being "directly connected" or "connected" to another component, it should be understood that there are no other components intervening.

[0052] The terminology used in this application is only used to describe specific embodiments and is not intended to limit the present invention. The singular expression includes the plural expression unless the context clearly indicates otherwise. In this application, it should be understood that the terms "comprise" or "have" indicate the presence of a feature, number, step, operation, component, part, or combination thereof described in the specification, but do not exclude in advance the possibility of the presence or addition of one or more other features, numbers, steps, operations, components, parts, or combinations thereof.

[0053] Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. Terms defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology, and will not be interpreted in an idealized or overly formal sense unless explicitly defined herein.

[0054] Hereinafter, embodiments will be described in detail with reference to the attached drawings. Regardless of the drawing numbers, identical or corresponding components are given the same reference numbers, and redundant descriptions thereof will be omitted.

[0055] Before describing the embodiments, an electronic device to which the circuit board and semiconductor package of the embodiments are applied will be briefly described. The electronic device includes a main board (not shown). The main board may be physically and / or electrically connected to various components. For example, the main board may be connected to the semiconductor package of the embodiments. The semiconductor package may further include a circuit board, a plurality of semiconductor elements arranged on the circuit board, and a connecting member electrically connecting the plurality of semiconductor elements.

[0056] The circuit board may include a plurality of laminated insulating layers, circuit patterns arranged within each of the plurality of laminated insulating layers, and via electrodes for connecting the circuit patterns arranged within each of the insulating layers.

[0057] The semiconductor device may be mounted on a circuit board, and may be a semiconductor chip in the form of an integrated circuit (IC) in which hundreds to millions or more active and / or passive devices are integrated into a single chip. For example, the semiconductor device may be a logic chip, a memory chip, etc. The logic chip may be a central processor (CPU), a graphics processor (GPU), etc. For example, the logic chip may be an application processor (AP) chip including at least one of a central processor (CPU), a graphics processor (GPU), a digital signal processor, an encryption processor, a microprocessor, a microcontroller, or an analog-to-digital converter, an application-specific IC (ASIC), a field programmable gate array (FPGA), etc., or a chip set including a specific combination of the above. In addition, the semiconductor device may be a memory device such as a high bandwidth memory (HBM).

[0058] A connecting member is a component that functions to electrically connect a plurality of semiconductor elements, and can be placed between the semiconductor elements and the circuit board. For example, the connecting member can be embedded in the circuit board, or can be placed on the circuit board. When embedded in the circuit board, it can have the advantage of reducing the thickness of the semiconductor package. The connecting member can be formed of silicon, but is not limited thereto, and can be formed of an organic material, and since it functions to electrically interconnect a plurality of semiconductor elements, it can be referred to as a bridge.

[0059] Additionally, the connecting member may be placed on a circuit board. When placed on a circuit board, the connecting member may be covered with a molding member, and the circuit board, semiconductor element, and connecting member may be electrically interconnected through a Through Mold Via (TMV) penetrating the molding member. Additionally, a redistribution layer may be placed between the molding member and the semiconductor element.

[0060] Meanwhile, the product group to which the semiconductor package of the embodiment is applied may be any one of CSP (Chip Scale Package), FC-CSP (Flip Chip-Chip Scale Package), FC-BGA (Flip Chip Ball Grid Array), POP (Package On Package), and SIP (System In Package), but is not limited thereto.

[0061] Additionally, the electronic device may be a smart phone, a personal digital assistant, a digital video camera, a digital still camera, a vehicle, a high-performance server, a network system, a computer, a monitor, a tablet, a laptop, a netbook, a television, a video game, a smart watch, an automotive device, etc. However, the present invention is not limited thereto, and it is to be understood that the electronic device may be any other electronic device that processes data.

[0062] Hereinafter, a circuit board according to an embodiment of the present invention may include a core layer, a first build-up layer disposed on one surface of the core layer, and a second build-up layer disposed on the other surface of the core layer. In addition, the first build-up layer and the second build-up layer may each include a plurality of laminated insulating layers. The circuit board is not limited thereto, and may be composed of the first build-up layer and / or the second build-up layer without including the core layer. That is, the circuit board may be composed of insulating layers of the first build-up layer, the core layer, and the second build-up layer (or the first build-up layer and / or the second build-up layer). In addition, the first build-up layer and the second build-up layer may be distinguished by a structure in which the expansion directions of via holes within the layers are opposite to each other. For example, the width or area of ​​the via hole may increase (increase) toward the top of the first build-up layer. In addition, the width or area of ​​the via hole may decrease (increase) toward the top of the second build-up layer. In addition, each build-up layer may correspond to an insulating layer other than the core layer. A detailed explanation of this will be provided later.

[0063] FIG. 1 is a cross-sectional view of a circuit board according to a first embodiment of the present invention, FIG. 2 is an enlarged view of a portion K1 in FIG. 1, FIG. 3 is an enlarged view of a portion K2 in FIG. 1, and FIG. 4 is a plan view of a first via electrode, a second via electrode, a first via land, and a second via land in a circuit board according to an embodiment.

[0064] Referring to FIG. 1, a circuit board (100) according to the first embodiment may include an insulating layer (110), an electrode portion (120), and a capacitor structure (CAS). Furthermore, the circuit board (100) may include a protective layer disposed on the electrode portion (120), or a core layer, which is an insulating layer disposed within the insulating layer (110).

[0065] The insulating layer (110) may be composed of multiple layers. The insulating layer (110) may include a first insulating layer (111), a second insulating layer (112), a third insulating layer (113), and a fourth insulating layer (114).

[0066] The fourth insulating layer (114), the third insulating layer (113), the first insulating layer (111), and the second insulating layer (112) may be sequentially positioned along the stacking direction or the vertical direction (X-axis direction). In other words, the fourth insulating layer (114), the third insulating layer (113), the first insulating layer (111), and the second insulating layer (112) may be sequentially stacked.

[0067] The insulating layer (110) may include a thermosetting resin such as an epoxy resin or a thermoplastic resin such as a polyimide. In addition, the insulating layer (110) may further include a reinforcing material in the resin. The reinforcing material may be, for example, a fabric reinforcing material, an inorganic filler, etc. The fabric reinforcing material may be glass fiber, and the glass fiber may be impregnated into the resin to form a prepreg (PPG).

[0068] For example, the insulating layer (110) may be formed of any insulating resin, such as a thermosetting and / or photocurable resin. As the thermosetting resin, ABF (Ajinomoto Build-up Film), a product released by Ajinomoto, can be used, and a material such as prepreg (PPG) containing glass fiber can be used. As the photocurable resin, any insulating resin, such as PID (Photo Imageable Dielectric) resin, can be used. The above-described arbitrary insulating resin may be, for example, an epoxy resin, a bismaleimide triazine resin (BT resin), a phenol resin, etc., and may include an inorganic filler such as silica. When the insulating resin is used as a core, it may include a reinforcing material formed of glass fiber or aramid fiber. For example, the insulating layer (110) may use ABF (Ajinomoto Build-up Film), a product released by Ajinomoto Co., Ltd., as an example, and FR-4, BT (Bismaleimide Triazine), PID (Photo Imageable Dielectric resin), BT, etc. may be used. For example, the insulating layer (110) may include a plurality of layers composed of ABF.

[0069] Each insulating layer may be made of the same or different material. For example, the second insulating layer may be made of the same or different material from the other insulating layers.

[0070] Additionally, a protective layer may be further disposed on the uppermost or lowermost portion of the insulating layer (110). The protective layer (not shown) may function to protect the pad from external moisture or contaminants, and may be formed of, for example, a solder resist to prevent a short circuit problem when bonding between a semiconductor element and / or a main board and a circuit board. Specifically, the semiconductor element and / or the main board, etc., have a plurality of terminals to be connected to the circuit board. In addition, the plurality of terminals may be arranged at a high density. When bonding the plurality of terminals and the pads of the circuit board, solder may be used, for example. When using solder, a solder short circuit problem may occur between terminals having a high density, and thus, a solder resist that does not have good wettability with the solder may be arranged to solve this short circuit problem. In addition, the protective layer (not shown) may be formed of a material that has insulating properties for electrical connection. Accordingly, the protective layer (not shown) may be referred to as an 'insulating layer' and may be a component of the above-described insulating layer. The protective layer (not shown) may include a resin, a curing agent, a photoinitiator, a pigment, a solvent, a filler, an additive, an acrylic monomer, etc. In addition, the third insulating layer (not shown) may include any one of a photo solder resist layer, a cover-lay, and a polymer material.

[0071] And the insulating layer or protective layer (not shown) located in the outer laminated area of ​​the circuit board may have an opening. Through the opening, it may be electrically connected to other semiconductor elements, the circuit board, etc.

[0072] The electrode portion (120) may include a circuit pattern (or circuit pattern layer), a pad, and a via electrode. The wiring may correspond to an 'electrode pattern', a 'pattern', a 'line', etc.

[0073] In an embodiment, the electrode portion (120) may include a wiring electrode and a via electrode. The embryonic electrode may include a wiring (or circuit pattern, pattern) and a pad arranged in an insulating layer. The via electrode may be located within a through hole or a via (Vertical Interconnect Access) hole formed in the insulating layer. Through the via electrode, an electrical connection may be implemented within the insulating layer or above or below the insulating layer.

[0074] The electrode portion (120) may include a first electrode portion (121), a second electrode portion (122), a third electrode portion (123), a fourth electrode portion (124), a fifth electrode portion (125), and a sixth electrode portion (126). Each electrode portion may include a wiring portion and a via electrode.

[0075] The first electrode portion (121) may be positioned on the second insulating layer (112). The second electrode portion (122) may be positioned on the second insulating layer (112). The third electrode portion (123) may be positioned on the first insulating layer (111) and the second insulating layer (112). In addition, the fourth electrode portion (124) may be positioned on the third insulating layer (113). The fifth electrode portion (125) may be positioned on the fourth insulating layer (114). The sixth electrode portion (126) may be positioned on the first insulating layer (111). Furthermore, additional electrode portions may be further arranged on each insulating layer. A detailed description thereof will be provided later.

[0076] And the first electrode part (121) may include a first via electrode (121a) and a first wiring part (121b). In addition, the second electrode part (122) may include a second via electrode (122a) and a second wiring part (122b). The third electrode part (123) may include a third via electrode (123a) and a third wiring part (123b). In addition, the fourth electrode part (124) may include a fourth via electrode (124a) and a fourth wiring part (124b). And the fifth electrode part (125) may include a fifth via electrode (125a) and a fifth wiring part (125b). The sixth electrode part (126) may include a sixth via electrode (126a) and a sixth wiring part (126b).

[0077] In addition, the outer pad of the electrode portion (120) can be bonded to a semiconductor element, substrate, board, etc. using solder, wire, conductive adhesive, etc., and can be arranged with a width larger than the width of the circuit pattern to solve problems such as securing yield. However, the present invention is not limited thereto, and can have the same width as the width of the circuit pattern depending on the technical limitations of the bonding process.

[0078] And the pads arranged on the inside have the function of connecting the via electrode and the circuit pattern. When the via electrode is arranged with a wider width than the circuit pattern, a pad with a wider width than the circuit pattern is provided for positional alignment during the manufacturing process of the via electrode to be arranged on each circuit pattern. Therefore, each via electrode may have an upper surface that is located on the same plane as the lower surface of the upper pad that is in direct contact with the via electrode, and a lower surface that is located on the same plane as the upper surface of the lower pad that is in direct contact with the lower surface of the via electrode. Here, the lower surface of the upper pad and the upper surface of the lower pad do not necessarily mean a flat surface, and it should be understood that even concave or convex surfaces that may appear depending on various processes may be present.

[0079] Additionally, semiconductor devices may be mounted within or on the circuit board. The semiconductor devices may be logic chips, memory chips, or the like.

[0080] The capacitor structure (CAS) may be located on the first insulating layer (111). Alternatively, the capacitor structure (CAS) may be located between the first insulating layer (111) and the second insulating layer (112). Additionally, the capacitor structure (CAS) may be covered by the second insulating layer (112).

[0081] A capacitor structure (CAS) according to an embodiment may include a first via land (VL1), a dielectric layer (DL), and a second via land (VL2). In the capacitor structure (CAS), the first via land (VL1), the dielectric layer (DL), and the second via land (VL2) may be sequentially stacked or positioned along a vertical direction (X-axis direction). The second via land (VL2) may be positioned above the first via land (VL1). For example, the second via land (VL2) may be positioned between the first via land (VL1`) and the upper surface (US2) of the second insulating layer (112). The first and second via lands (VL1, VL2) may be directly connected to a via electrode. Through the first and second via lands (VL1, VL2), functions such as securing the positional alignment of the via electrodes and the function of a circuit electrically connected to the via electrodes can be implemented. In addition, the via land here may mean an electrode, for example, one electrode (layer) and another electrode (layer) of a capacitor structure that performs the role of a capacitor. Furthermore, although the via electrodes connected to the first and second via lands of the capacitor are illustrated as a single via land, a single or multiple via electrodes may be connected depending on the circuit connection.

[0082] Furthermore, as the processor of an electronic device or package substrate continues to draw more power, first droop and power transmission noise can be obstacles. Specifically, first droop can occur when the circuitry within the die or semiconductor device pulls power. To improve this first droop, a capacitor can be added to the circuit substrate on which the die or semiconductor device is provided, as in the embodiment. In particular, it may be desirable to add the capacitor near the die or semiconductor device, which is the source of the droop. In this case, when the capacitor is placed on the die side or the side land of the substrate, the electrical path between the capacitor on the die and the land side (or the die side) becomes longer, which may reduce the additional effect of the capacitor due to added parasitic inductance, etc. In addition, the capacitor on the land side may cause interference with the interface of the circuit substrate or package substrate.

[0083] Therefore, by embedding the capacitor structure in the circuit board under the die as in the embodiment, droop and power transmission noise can be suppressed. In addition, a high-k dielectric layer (DL) can be applied to form a large capacitance capacity. Furthermore, in the embodiment, the capacitor structure can have any suitable shape and dimension. For example, the capacitor structure can have a rectangular or circular shape in plan view. Furthermore, the capacitor structure can be arranged at any position within the circuit board. For example, in order to reduce the electrical path, the capacitor structure can be positioned in a layer adjacent to the upper die within the circuit board. That is, the capacitor structure is positioned in an area adjacent to the die in the insulating layer, so that electrical performance degradation can be suppressed.

[0084] Referring further to FIG. 2, in the circuit board (100) according to the embodiment, the second insulating layer (112) may be disposed on the first insulating layer (111). Furthermore, the first via land (VL1) may be positioned between the first insulating layer (111) and the second insulating layer (112).

[0085] In an embodiment, the first via electrode (121a), the second via electrode (122a), and the third via electrode (123a) may also have different positions in the vertical direction. In addition, the first via electrode (121a), the second via electrode (122a), and the third via electrode (123a) penetrating the second insulating layer (112) may have different lengths in the vertical direction (X-axis direction). In an embodiment, the first via electrode (121a), the second via electrode (122a), and the third via electrode (123a) may have different thicknesses. In addition, the first via electrode (121a), the second via electrode (122a), and the third via electrode (123a) may be spaced apart from each other in the horizontal direction (Y-axis direction).

[0086] For example, the first insulating layer (111) may include an upper surface (US1) and a lower surface (BS1). The second insulating layer (112) may include an upper surface (US2) and a lower surface (BS2). The upper surface (US1) of the first insulating layer (111) may be in contact with the lower surface (BS2) of the second insulating layer (112). For example, the upper surface (US1) of the first insulating layer (111) and the lower surface (BS2) of the second insulating layer (112) may form the same plane. However, the second insulating layer (112) may have a step difference from the upper surface (US1) of the first insulating layer (111) in a region where the lower surface is in contact with the upper surface of the third via land (VL3).

[0087] And the first via electrode (121a) may be arranged between the upper surface (US2) of the second insulating layer (112) and the first via land (VL1). In addition, the first via electrode (121a) may be positioned between the upper surface (US2) of the second insulating layer (112) and the first insulating layer (111). The first via electrode (121a) may penetrate at least a portion of the second insulating layer (112).

[0088] The second via electrode (122a) may be arranged between the first via land (VL1) and the upper surface (US2) of the second insulating layer (112). In addition, the second via electrode (122a) may be positioned between the upper surface (US1) of the first insulating layer (111) (or the lower surface, BS2, of the second insulating layer (112)) and the upper surface (US2) of the second insulating layer (112). The second via electrode (122a) may penetrate at least a portion of the second insulating layer (112).

[0089] The third via electrode (123a) may be disposed between the lower surface (BS1) of the first insulating layer (111) and the upper surface (US2) of the second insulating layer (112). In addition, the third via electrode (123a) may be disposed between the lower surface (BS1) of the first insulating layer (111) and the upper surface (US2) of the second insulating layer (112). In addition, the third via electrode (123a) may be positioned between the sixth wiring portion (126b) and the upper surface (US2) of the second insulating layer (112). In addition, the third via electrode (123a) may penetrate at least a portion of the first insulating layer (111) and the second insulating layer (112). In an embodiment, the third via electrode (123a) may penetrate the second insulating layer (112) and a portion of the first insulating layer (111).

[0090] Furthermore, the third via electrode (123a) can penetrate the entirety of the first insulating layer (111) and the second insulating layer (112) and come into contact with the sixth wiring portion (126b). And the second via electrode (122a) can come into contact with the second via land (VL2) in the capacitor structure (CAS). In addition, the first via electrode (121a) can come into contact with the first via land (VL1) in the capacitor structure (CAS). That is, the first via electrode (121a) is electrically connected to the first via land (VL1) and the capacitor structure by the first via land (VL1), and the second via electrode (122a) is electrically connected to the second via land (VL2), whereby the capacitor embedded in the circuit board (100) can be easily electrically connected to the upper semiconductor element.

[0091] In addition, the upper surface (US1) of the first insulating layer (111) may not be flush with the upper surface of the first via land (VL1). For example, the upper surface (US1) of the first insulating layer (111) may have a step difference from the upper surface of the first via land (VL1). The upper surface of the first via land (VL1) may be positioned closer to the first via electrode (121a) than the upper surface (US1) of the first insulating layer (111). This is because the first via land (VL1) is partially removed from the first insulating layer (111) by desmear after being separated from the carrier substrate by the Embedded Trace Substrate (ETS) method. As a result, a recess may be formed on the upper surface of the first via land (VL1) in the first insulating layer (111) or at a position corresponding to the first via land (VL1).

[0092] Furthermore, since the dielectric layer (DL) is disposed on the first via land (VL1), it can overlap horizontally with the upper surface (US1) of the first insulating layer (111). In other words, the dielectric layer (DL) can overlap horizontally (Y-axis direction) with the first insulating layer (111). In addition, the dielectric layer (DL) can overlap horizontally (Y-axis direction) with the second insulating layer (112).

[0093] In this way, a fine via land can be formed in the first insulating layer (111), and both the first insulating layer (111) and the second insulating layer (112) can be overlapped in the horizontal direction on the dielectric layer (DL), which is the insulating layer, so that electrical insulation can be easily secured.

[0094] Additionally, as a variation, for various parallel / series connections to the capacitor structure (CAS), the sixth via electrode (126a) of the sixth electrode portion (126) may be in contact with the first via land (VL1) of the capacitor structure (CAS).

[0095] In this specification, the via electrode may be located within a via hole formed in each insulating layer, etc. This corresponds to the via electrode penetrating each insulating layer, etc. This is described based on this.

[0096] In an embodiment, the thickness (T1) of the first via electrode (121a), the thickness (T2) of the second via electrode (122a), and the thickness (T3) of the third via electrode (123a) may be different from each other.

[0097] For example, the thickness (T1) of the first via electrode (121a) may be greater than the thickness (T2) of the second via electrode (122a). And the thickness (T2) of the third via electrode (123a) may be greater than the thickness of at least one of the first via electrode (121a) and the second via electrode (122a). For example, the thickness (T3) of the third via electrode (123a) may be greater than the thickness (T1) of the first via electrode (121a) and the thickness (T2) of the second via electrode (122a). By this configuration, at least one die (or semiconductor element) disposed on the upper portion of the circuit board (100) can be easily connected to the capacitor. In addition, by forming a connection space with the upper die, an overlapping area in the vertical direction between the first via land and the second via land can be easily secured. That is, the capacitance deviation according to the overlapping area between the first vialand and the second vialand can be minimized.

[0098] In addition, as an embodiment, the third via electrode (123a) may overlap the first via electrode (121a) and the second via electrode (122a) in the horizontal direction (Y-axis direction). And the third via electrode (123a) may also overlap at least partially with the capacitor structure (CAS) in the horizontal direction (Y-axis direction). In addition, at least a portion of the third via electrode (123a) may not overlap with the first via electrode (121a) and the second via electrode (122a) in the horizontal direction (Y-axis direction). In addition, a portion of the third via electrode (123a) may also overlap with the dielectric layer (DL) in the horizontal direction.

[0099] And the third via electrode (123a) can overlap the entire capacitor structure (CAS) in the horizontal direction (Y-axis direction). Meanwhile, the first via electrode (121a) can overlap at least a part of the capacitor structure (CAS) in the horizontal direction (Y-axis direction). The first via electrode (121a) can overlap the dielectric layer (DL) and the second via land (VL2) of the capacitor structure (CAS) in the horizontal direction (Y-axis direction).

[0100] Additionally, the width (W1) of the first via electrode (121a) may gradually decrease from the upper surface (US2) of the second insulating layer (112) toward the lower surface (BS2) of the second insulating layer (112). For example, the width (or diameter, etc.) of the first via electrode (121a) may increase in the vertical direction.

[0101] In addition, the minimum width (W1a) of the first via electrode (121a) may be smaller than the maximum width (W1b) of the first via electrode (121a). In an embodiment, the first width (W1a), which is the minimum width of the first via electrode (121a), may correspond to the smallest width at the lower surface (BS2) of the second insulating layer (112). Alternatively, the first width (W1a), which is the minimum width of the first via electrode (121a), may correspond to the width at the region closest to the lower surface (BS2) of the second insulating layer (112). And the maximum width (W1b) of the first via electrode (121a) may correspond to the width at the upper surface (US2) of the second insulating layer (112). Alternatively, the maximum width of the first via electrode (121a) may correspond to the width in the area closest to the upper surface (US2) of the second insulating layer (112).

[0102] Additionally, the width (W2) of the second via electrode (122a) may gradually decrease from the upper surface (US2) of the second insulating layer (112) toward the lower surface (BS2) of the second insulating layer (112). Alternatively, the width (W2) of the second via electrode (122a) may gradually increase in the vertical direction.

[0103] The minimum width (W2a) of the second via electrode (122a) may be smaller than the maximum width (W2b) of the second via electrode (122a). In an embodiment, the second width (W2a), which is the minimum width of the second via electrode (122a), may correspond to the smallest width on the lower surface (BS2) of the second insulating layer (112) (or the upper surface of the first insulating layer). Alternatively, the second width (W2a), which is the minimum width of the second via electrode (122a), may correspond to the width in the region closest to the upper surface (US1) of the first insulating layer (111) (or the lower surface (BS2) of the second insulating layer). In addition, the maximum width (W2b) of the second via electrode (122a) may correspond to the width on the upper surface (US2) of the second insulating layer (112). Alternatively, the maximum width of the second via electrode (122a) may correspond to the width in the area closest to the upper surface (US2) of the second insulating layer (112).

[0104] In addition, the width (W3) of the third via electrode (123a) may gradually decrease from the upper surface (US2) of the second insulating layer (112) toward the lower surface (BS1) of the first insulating layer (111) (or from the upper surface (or lower surface) of the second insulating layer to the upper surface (or lower surface) of the first insulating layer). Alternatively, the width (W3) of the third via electrode (123a) may gradually increase in the vertical direction.

[0105] The minimum width (W3a) of the third via electrode (123a) may be smaller than the maximum width (W3b) of the third via electrode (123a). In an embodiment, the third width (W3a), which is the minimum width of the third via electrode (123a), may correspond to the width at the lower surface (BS1) of the first insulating layer (111). Alternatively, the third width (W3a), which is the minimum width of the third via electrode (123a), may correspond to the width at the area closest to the lower surface (BS1) of the first insulating layer (111). And the maximum width (W3b) of the third via electrode (123a) may correspond to the width at the upper surface (US2) of the second insulating layer (112). Alternatively, the maximum width of the third via electrode (123a) may correspond to the width in the area closest to the upper surface (US2) of the second insulating layer (112).

[0106] The first width (W1a), which is the minimum width of the first via electrode (121a), may be greater than the third width (W3a), which is the minimum width of the third via electrode (123a). In addition, the second width (W2a), which is the minimum width of the second via electrode (122a), may be greater than the first width (W1a), which is the minimum width of the first via electrode (121a). In this case, the maximum widths of the first via electrode (121a), the second via electrode (122a), and the third via electrode (123a) may be the same.

[0107] Referring further to FIGS. 3 and 4, the capacitor structure (CAS) may be positioned in the first insulating layer (111). In addition, the capacitor structure (CAS) may be positioned between the first insulating layer (111) and the second insulating layer (112). At least a portion of the capacitor structure (CAS) may be embedded in the first insulating layer (111). In addition, at least a portion of the capacitor structure (CAS) may be embedded in the second insulating layer (112).

[0108] A capacitor structure (CAS) may include a first via land (VL1), a dielectric layer (DL), and a second via land (VL2). The first via land (VL1), the dielectric layer (DL), and the second via land (VL2) may be sequentially stacked in a vertical direction.

[0109] A dielectric layer (DL) can be interposed between the first via land (VL1) and the second via land (VL2) to form a storage capacity or capacitance. In other words, the capacitor structure (CAS) can function as a 'capacitor'.

[0110] These capacitor structures or capacitors need to be further reduced in size to accommodate substrates and semiconductor devices that require increased integration.

[0111] As a method for improving the storage capacity of such a capacitor, increasing the effective area of ​​the first and second via lands (electrodes), reducing the thickness of the dielectric film, using a high-k material as the dielectric film, etc. can be considered. In particular, when the high-k material is used as the dielectric film, the leakage current that frequently occurs between the first via land, which is the lower electrode, and the second via land, which is the upper electrode, can be sufficiently reduced while maintaining a thin equivalent oxide thickness. In an embodiment, a high-k material can be used as the dielectric film. For example, the high-k material can include, for example, tantalum oxide, aluminum oxide, zirconium oxide, hafnium oxide, titanium oxide, etc.

[0112] In addition, the circuit board according to the embodiment can solve problems such as reduced circuit board integration and input / output count due to the volume of the capacitor when mounting a high-capacity capacitor as described above. In other words, the capacitor structure according to the embodiment can increase the circuit board integration and input / output count while providing improved storage capacity.

[0113] In an embodiment, at least one of the first via electrode (121a) and the second via electrode (122a) may overlap with the capacitor structure (CAS) in a vertical direction (X-axis direction). In particular, the first via electrode (121a) and the second via electrode (122a) may overlap with the first via land (VL1) in a vertical direction (X-axis direction). And the first via electrode (121a) and the second via electrode (122a) may be positioned on the first via land (VL1). In addition, the first via electrode (121a) and the second via electrode (122a) may be connected to the capacitor structure (CAS).

[0114] For example, the second via electrode (122a) may be electrically connected to the capacitor structure (CAS). In an embodiment, the second via electrode (122a) may be disposed on the second via land (VL2). In addition, the second via electrode (122a) may be disposed on the capacitor structure (CAS). Accordingly, the second via electrode (122a) may overlap the capacitor structure (CAS) in a vertical direction (X-axis direction).

[0115] In addition, the first via electrode (121a) may be electrically connected to the capacitor structure (CAS). In an embodiment, the first via electrode (121a) may be disposed on the first via land (VL1). That is, the first via electrode (121a) may be disposed on a portion of the capacitor structure (CAS). Accordingly, the first via electrode (121a) may overlap with the capacitor structure (CAS) in the vertical direction (X-axis direction). In addition, the first via electrode (121a) may be misaligned with the second via electrode (122a) or the dielectric layer (DL) in the vertical direction (X-axis direction). Furthermore, the first via electrode (121a) may be spaced apart from the second via electrode (122a) in the horizontal direction (Y-axis direction) and may overlap at least partially in the horizontal direction (Y-axis direction). Accordingly, a capacitor structure (CAS) is positioned between the die or chip mounted on the upper portion of the circuit board (100), so that the capacitor can be placed between the die (or chip) and the main circuit board.

[0116] Additionally, there may be at least one capacitor structure (CAS) on the circuit board (100). In an embodiment, the capacitor structure (CAS) may be multiple, including a first capacitor structure (CAS1) and a second capacitor structure (CAS2). The first capacitor structure (CAS1) and the second capacitor structure (CAS2) may be spaced apart from each other.

[0117] The third via electrode (123a) may be spaced apart from the first capacitor structure (CAS1) and the second capacitor structure (CAS2). In addition, the third via electrode (123a) may be placed between the first capacitor structure (CAS1) and the second capacitor structure (CAS2). The third via electrode (123a) may penetrate at least one of the first capacitor structure (CAS1) and the second capacitor structure (CAS2). Accordingly, at least a portion of the third via electrode (123a) may overlap the first capacitor structure (CAS1) and the second capacitor structure (CAS2) in the horizontal direction (Y-axis direction).

[0118] In addition, as described above, at least a portion of the capacitor structure (CAS) may be embedded in the first insulating layer (111). A portion of the first via electrode (121a) may be in contact with the second insulating layer (112). Alternatively, a portion of the first via electrode (121a) may overlap the second insulating layer (112) in a horizontal direction. More specifically, the upper surface (US1) of the first insulating layer (111) (or the lower surface, BS2, of the second insulating layer) may be positioned to be misaligned with the upper surface or lower surface of the first via land (VL1). In addition, the upper surface (US1) of the first insulating layer (111) may not be flush with the upper surface of the first via land (VL1). For example, as shown in FIG. 3, the upper surface (US1) of the first insulating layer (111) may not be flush with the upper surface of the first via land (VL1). Accordingly, the upper surface (US1) of the first insulating layer (111) can form a step with the lower surface of the dielectric layer (DL). Accordingly, the second insulating layer (112) can have a maximum thickness on the upper surface of the third via land (VL3) or in a region that overlaps the third via land (VL3) in the vertical direction (X-axis direction).

[0119] Furthermore, since the first capacitor structure (CAS1) and the second capacitor structure (CAS2), which are spaced apart from each other, overlap in the horizontal direction, the first via land (VL1) of the first capacitor (CAS1) and the first via land (VL1) of the second capacitor structure (CAS2) may overlap each other at least partially in the horizontal direction. For example, the upper surface of the first via land (VL1) of the first capacitor (CAS1) and the upper surface of the first via land (VL1) of the second capacitor structure (CAS2) may form the same plane. In addition, as another example, the upper surface of the first via land (VL1) of the first capacitor (CAS1) and the upper surface of the first via land (VL1) of the second capacitor structure (CAS2) may be misaligned with each other. For example, the upper surface of the first via land (VL1) in the first capacitor (CAS1) and the upper surface of the first via land (VL1) in the second capacitor structure (CAS2) may have a vertical separation distance.

[0120] In a circuit board according to a modified example, a first capacitor structure (CAS1) and a second capacitor structure (CAS2) of a capacitor structure (CAS) may be embedded in an upper surface (US1) of a first insulating layer (111). Furthermore, an upper surface of a first via land (VL1) of at least one of the first capacitor structure (CAS1) and the second capacitor structure (CAS2) and an upper surface (US1) of the first insulating layer (111) may be misaligned. For example, an upper surface of the first via land (VL1) may be positioned with a vertical distance (gap) in the X-axis direction relative to an upper surface (US1) of the first insulating layer (111).

[0121] Additionally, the upper surface of the first via land (VL1) in the first capacitor (CAS1) and the upper surface (US1) of the first insulating layer (111) may be misaligned.

[0122] Additionally, in the second capacitor structure (CAS2), the upper surface of the first via land (VL1) and the upper surface (US1) of the first insulating layer (111) may be misaligned with each other.

[0123] In an embodiment, the area (S1) of the first via land (VL1) may be larger than the area (S2) of the second via land (VL2). For example, the area (S1) of the upper surface of the first via land (VL1) may be larger than the area (S2) of the upper surface of the second via land (VL2). In addition, the area (S1) of the lower surface of the first via land (VL1) may be larger than the area (S2) of the lower surface of the second via land (VL2). In addition, the thickness of the first via land (VL1) may be different from the thickness of the second via land (VL2). Furthermore, the area (S1) of the first via land (VL1) may overlap with the area (S2) of the second via land (VL2) in both the vertical direction (X-axis direction). By this configuration, capacitance deviation and error occurrence due to the difference in the overlapping areas can be suppressed.

[0124] Additionally, the planar area of ​​the dielectric layer (DL) may be smaller than the area (S1) of the first via land (VL1). And the area of ​​the dielectric layer (DL) may be larger than the area (S2) of the second via land (VL2). Accordingly, a decrease in the size of the capacitance due to the dielectric layer can be prevented.

[0125] FIG. 5 is a cross-sectional view of a circuit board according to a second embodiment of the present invention, FIG. 6 is an enlarged view of K3 of FIG. 5, and FIG. 7 is a plan view of a first via electrode, a second via electrode, a first via land, and a second via land in a circuit board according to the second embodiment.

[0126] Referring to FIGS. 5 to 7, a circuit board (100A) according to the second embodiment may include an insulating layer (110), an electrode portion (120), and a capacitor structure (CAS). Furthermore, the circuit board (100A) may include a protective layer disposed on the electrode portion (120), or a core layer, which is an insulating layer disposed within the insulating layer (110). Furthermore, the configuration described in the embodiments of the present invention may be applied in the same manner, except for the contents described below.

[0127] In the circuit board (100A) according to the present embodiment, the first via electrode (121a) can penetrate at least a portion of the capacitor structure (CAS). That is, the first via electrode (121a) can be surrounded by the capacitor structure (CAS).

[0128] And the spacing between the capacitor structures (CAS) through which the first via electrode (121a) penetrates may be the same. For example, the spacing between the outer surface of the first via electrode (121a) and the adjacent capacitor structure (CAS) may be maintained the same along the shape or edge of the first via electrode (121a).

[0129] In addition, the first via electrode (121a) may penetrate the second via land (VL2) and may not be in contact with the second via land (VL2). And the second via land (VL2) may be spaced apart from the first via electrode (121a) by a predetermined distance (gap). The inner surface of the through hole (Hcas1) of the second via land (VL2) and the outer surface of the first via electrode (121a) may be spaced apart.

[0130] The first via electrode (121a) can penetrate the dielectric layer (DL). And the first via electrode (121a) can be in contact with the upper surface of the first via land (VL1). The first via electrode (121a) can be in contact with the inner surface of the through hole (Hcas2) of the dielectric layer (DL). Accordingly, the occurrence of capacitance deviation due to the reduction in the area of ​​the dielectric layer (DL) can be suppressed. In addition, the first via electrode (121a) may be spaced apart from the inner surface of the through hole (Hcas2) of the dielectric layer (DL). For example, the first via electrode (121a) may be arranged at a predetermined distance from the inner surface of the through hole (Hcas2) of the dielectric layer (DL).

[0131] Furthermore, the second insulating layer (112) may be positioned on the inside of the capacitor structure (CAS). For example, the second insulating layer (112) may penetrate the capacitor structure (CAS). A portion of the second insulating layer (112) may penetrate the second via land (VL2) of the capacitor structure (CAS). A portion of the second insulating layer (112) may be positioned within the through hole (Hcas1) of the second via land (VL2) of the capacitor structure (CAS). Accordingly, electrical insulation between the first via electrode (121a) and the capacitor structure (CAS) may be maintained. By this configuration, a circuit board with improved integration may be provided by forming a third via electrode penetrating the first and second insulating layers, which are multiple layers, and at the same time forming the capacitor structure (CAS).

[0132] In addition, when the first via electrode (121a) is spaced apart from the inner surface of the through hole (Hcas2) of the dielectric layer (DL), the second insulating layer (112) can also be placed within the through hole (Hcas2) of the dielectric layer (DL).

[0133] Furthermore, the second via electrode (122a) and the first via electrode (121a) may be in contact with the second via land and the first via land of the capacitor structure (CAS), respectively. For example, the second via electrode (122a) may be in contact with the second via land of the capacitor structure (CAS), and the first via electrode (121a) may be in contact with the first via land of the capacitor structure (CAS). At this time, an area where the second via electrode (122a) is in contact with the second via land may not overlap at least partially in the vertical direction with an area where the first via electrode (121a) is in contact with the first via land. Accordingly, an electrical connection in a circuit board according to an embodiment can be easily designed and changed.

[0134] FIG. 8 is a cross-sectional view of a first via electrode, a second via electrode, a first via land, and a second via land in a circuit board according to a modified example, and FIG. 9 is a plan view of a first via electrode, a second via electrode, a first via land, and a second via land in a circuit board according to a modified example.

[0135] Referring to FIGS. 8 and 9, a circuit board according to a modified example may include an insulating layer (110), an electrode portion (120), and a capacitor structure (CAS). Furthermore, the circuit board may include a protective layer disposed on the electrode portion (120), or a core layer, which is an insulating layer disposed within the insulating layer (110). Furthermore, the configuration described in the embodiments of the present invention may be applied in the same manner, except for the contents described below.

[0136] Furthermore, the third via electrode (123a) may penetrate the capacitor structure (CAS). The third via electrode (123a) may penetrate the first via land (VL1), the dielectric layer (DL), and the second via land (VL2). That is, the third via electrode (123a) may be surrounded by the capacitor structure (CAS). Similarly, the third via electrode (123a) may be spaced apart from the first via electrode (121a) and the second via electrode (122a).

[0137] And the capacitor structure (CAS) may include a through hole (Hcas3). A third via electrode (123a) may be positioned in the through hole (Hcas3) of the capacitor structure (CAS). The third via electrode may be positioned a predetermined distance apart from the inner surface of the through hole (Hcas3) of the capacitor structure (CAS). Accordingly, the third via electrode (123a) may be electrically connected to the sixth wiring portion (126b) or the like at the bottom, rather than to the capacitor structure (CAS). Furthermore, the second insulating layer (112) may be positioned within the through hole (Hcas3) of the capacitor structure (CAS). For example, the second insulating layer (112) may penetrate the capacitor structure (CAS). Accordingly, electrical insulation between the third via electrode (123a) and the capacitor structure (CAS) may be maintained. By this configuration, a circuit board with improved integration can be provided by forming a capacitor structure (CAS) while forming a third via electrode penetrating the first and second insulating layers, which are double layers.

[0138] Furthermore, as another example, the third via electrode (123a) may be electrically connected to the first via land (VL1) or the second via land (VL2) of the capacitor structure (CAS), and may be electrically connected to the first via land (VL1) or the second via land (VL2) for a series / parallel connection with the capacitor.

[0139] Fig. 10 is a cross-sectional view of a circuit board according to a third embodiment of the present invention, and Fig. 11 is an enlarged view of K4 of Fig. 10.

[0140] Referring to FIGS. 10 and 11, a circuit board (100B) according to a third embodiment may include an insulating layer (110), an electrode portion (120), and a capacitor structure (CAS). Furthermore, the circuit board (100B) may include a protective layer disposed on the electrode portion (120) or a core layer, which is an insulating layer disposed within the insulating layer (110). In addition, the circuit board (100B) may include a third via land (VL3). Furthermore, the configuration described in the embodiments of the present invention may be applied in the same manner, except for the contents described below.

[0141] The circuit board (100B) may include a via land (third via land, VL3) positioned corresponding to the first via land (VL1) of the capacitor structure (CAS). The third via land (VL3) may overlap the first via land (VL1) in the horizontal direction (Y-axis direction). In addition, as described below, the first via land (VL1) and the third via land (VL3) may be formed in the same process.

[0142] In addition, in the embodiment, the first electrode portion (121) may include a first via electrode (121a) and a first wiring portion (121b). The first electrode portion (121) may correspond to the sixth electrode portion described above. The first via electrode (121a) may be disposed between the lower surface (BS1) of the first insulating layer (111) and the first via land (VL1). In addition, the first via electrode (121a) may be positioned between the lower surface (BS1) of the first insulating layer (111) and the first via land (VL1). The first via electrode (121a) may penetrate at least a portion of the first insulating layer (111).

[0143] The third via land (VL3) may be located between the first insulating layer (111) and the second insulating layer (112). For example, the third via land (VL3) may be located between the lower surface (BS1) of the first insulating layer (111) and the upper surface (US2) of the second insulating layer (112).

[0144] In addition, the third via electrode (123a) may be located between the third via land (VL3) and the upper surface (US2) of the second insulating layer (112). In addition, the third via electrode (123a) may be in contact with the third via land (VL3). The third via electrode (123a) may penetrate the second insulating layer (112) and be in contact with the upper surface of the third via land (VL3). The upper surface of the third via land (VL3) may be flush with the upper surface of the first via land (VL1).

[0145] The third via electrode (123a) may be positioned opposite the first via electrode (121a) with respect to the third via land (VL3). Alternatively, the second via electrode (122a) may be positioned opposite the first via electrode (121a) with respect to the capacitor structure (CAS).

[0146] In an embodiment, the length or thickness in the vertical direction (X-axis direction) of the third via electrode (123a) penetrating the second insulating layer (112) may be different from the length or thickness in the vertical direction (X-axis direction) of the second via electrode (122a) penetrating the second insulating layer (112). For example, the thickness of the inner surface where the second insulating layer (112) and the third via electrode (123a) come into contact may be greater than the thickness of the inner surface where the second insulating layer (112) and the second via electrode (122a) come into contact. Accordingly, the third via electrode (123a) may be greater in thickness or length in the second direction than the second via electrode (122a). By this configuration, when forming the first insulating layer (111) and the second insulating layer (112) and forming the via electrode penetrating the first insulating layer (111) and the second insulating layer (112), cracks or damage occurring at the interface between the first insulating layer (111) and the second insulating layer (112) for forming the third via electrode can be prevented. For example, a crevasse occurring at the interface of the insulating layers can be suppressed according to the via electrode penetrating both the first and second insulating layers. In other words, a via hole or via electrode penetrating the double insulating layers can be avoided. Furthermore, a decrease in structural reliability when forming a via hole can be suppressed through the third via land (VL3). Furthermore, a decrease in electrical function due to a decrease in the area or width of the via electrode penetrating the double insulating layers can also be suppressed. Furthermore, an electrical connection through a capacitor structure (CAS) can be made with one end located on the lower surface of the circuit board and the other end located on the upper surface of the circuit board.

[0147] And the third via electrode (123a) may not overlap with the first via electrode (121a) in the horizontal direction (Y-axis direction). The third via electrode (123a) may be positioned to be misaligned with the first via electrode (121a) in the horizontal direction (Y-axis direction).

[0148] Additionally, the width of the first via electrode (121a) may gradually increase from the upper surface (US1) of the first insulating layer (111) toward the lower surface (BS1) of the first insulating layer (111).

[0149] In an additional use case, a fourth via land (not shown) may be additionally arranged on the third via land (VL3). That is, the circuit board may further include a fourth via land (not shown). The fourth via land (not shown) may overlap at least one of the second via land (VL2) and the dielectric layer (DL) in the horizontal direction (Y-axis direction). And the third via electrode (123a) may be positioned between the fourth via land (not shown) and the upper surface (US2) of the second insulating layer (112).

[0150] Figures 12a to 12o are drawings explaining a method for manufacturing a circuit board according to a third embodiment.

[0151] Referring to FIG. 12A, in an embodiment, a carrier board can be prepared. The carrier board can include a carrier insulating layer (310) and a carrier metal layer (320) disposed on at least one surface of the carrier insulating layer (310). Specifically, in the carrier board, the carrier metal layer (320) can be disposed on the carrier insulating layer (310) and at least one surface of the carrier insulating layer (310). In this case, the carrier metal layer (320) can be disposed on only one surface of the carrier insulating layer (310), or alternatively, can be disposed on both surfaces. For example, the carrier metal layer (320) can be disposed on only one surface of the carrier insulating layer (310), and thus, an ETS process for manufacturing a circuit board can be performed on only one surface. Alternatively, the carrier metal layer (320) can be disposed on both surfaces of the carrier insulating layer (310), and thus, an ETS process for manufacturing a circuit board can be performed simultaneously on both surfaces of the carrier board. In this case, two circuit boards can be manufactured at once.

[0152] The carrier metal layer (320) may be formed by electroless plating on the carrier insulating layer (310). Alternatively, the carrier insulating layer (310) and the carrier metal layer (320) may be CCL (Copper Clad Laminate). That is, the carrier metal layer (320) may be a copper foil layer. For example, the carrier metal layer (320) may be a copper foil. For example, the carrier metal layer (320) may be an electroless plating layer formed on the carrier insulating layer (310). That is, the carrier metal layer (320) is the first metal layer formed in the manufacturing process of the circuit board.

[0153] Referring to FIG. 12B, in an embodiment, a dry film (330) may be formed on a carrier metal layer (320). At this time, after the dry film (330) covers the entire carrier metal layer (320), an opening exposing the surface of the carrier metal layer (320) may be formed through exposure and development. The opening may be formed on the surface of the carrier metal layer (320) to correspond to an area where a first via land (VL1) is to be formed. In addition, the first via land (VL1) may be formed in the above-described opening.

[0154] In an embodiment, a process of forming a first via land (VL1) that fills the opening of the dry film (330) can be performed by electroplating the carrier metal layer (320) as a seed layer.

[0155] At this time, in the embodiment, a curing process for heat treating the dry film (330) may be additionally performed before the electrolytic plating process of the first via land (VL1). For example, in the embodiment, a process for curing the dry film (330) may be performed after the exposure and development process of the dry film (330). Curing of the dry film (330) may include curing using ultraviolet rays and curing using infrared rays. For example, in the embodiment, the dry film (330) may be cured using ultraviolet rays in the range of 5 mV to 100 mV. Alternatively, in the embodiment, the dry film (330) may be thermally cured using infrared rays. As described above, in the embodiment, by additionally performing a process for curing the dry film (330), the bonding strength between the carrier metal layer (320) and the dry film (330) may be improved. Accordingly, in the embodiment, the first via land (VL1) formed in the opening can be made finer by improving the bonding strength between the dry film (330) and the carrier metal layer (320). For example, in the embodiment, the trace line width and spacing of the first via land (VL1) can be reduced by additionally performing a process of curing the dry film (330).

[0156] Referring to FIG. 12c, a first insulating layer (111) can be laminated. The first insulating layer (111) can cover the first via land (VL1).

[0157] Referring to FIG. 12d, a first electrode portion (121) can be formed on a first insulating layer (111). The first electrode portion (121) can be formed by sequentially forming a mask such as a dry film, forming a mask pattern, etching a portion of the first insulating layer (forming a via hole, etc.), and forming an electrode.

[0158] And a third insulating layer (113) may be formed on the first insulating layer (111) and the first electrode portion (121). The third insulating layer (113) may be positioned on the first insulating layer (111) and the first electrode portion (121).

[0159] And, on the third insulating layer (113), mask formation such as a dry film, mask pattern formation, partial etching of the first insulating layer (formation of a via hole, etc.), and electrode formation can be sequentially performed. Accordingly, a fourth electrode portion (124) can be formed on the third insulating layer (113).

[0160] Referring to FIG. 12E, in the embodiment, a process for removing the carrier board may be performed. For example, a process for removing the carrier insulation layer (310) from the carrier board may be performed. For example, in the embodiment, a process for separating the carrier insulation layer (310) from the carrier metal layer (320) may be performed. Accordingly, in the circuit board of the embodiment, the carrier metal layer (320) included in the carrier board remains at the outermost portion.

[0161] Referring to FIG. 12F, the embodiment may perform a process of etching the carrier metal layer (320). At this time, the embodiment may remove a portion of the first via land (VL1) (or the third via land) together with the carrier metal layer (320) in the process of etching the carrier metal layer (320). Through this, a recess may be formed in all pattern portions of the first via land (VL1) (or the third via land). That is, the upper surface of the first insulating layer (111) and the upper surfaces of the first via land (Vl1) and the third via land (VL3) may not form the same surface.

[0162] In addition, a mask (330') may be formed in an area other than the first via land (VL1) and the third via land (VL3). For example, the mask (330') may be a dry film. Then, exposure and development, etc. may be performed on the mask (330') to form an open area. In other words, patterning may be performed on the dry film. The mask (330') may be positioned at a position corresponding to the first via land. Furthermore, a curing process of the mask may be performed after the formation of the open area by exposure, etc. This mask formation may be applied to other mask formations in the same manner.

[0163] Referring to FIG. 12g, a dielectric layer (DL) can be formed on top of the first via land (VL1).

[0164] Similarly, referring to FIG. 12h, a second via land (VL2) may be formed on top of the dielectric layer (DL). The dielectric layer (DL) and the second via land (VL2) may be formed on the first via land (VL1) by forming and etching, etc. As a result, the capacitor structure may be positioned on the first insulating layer (111).

[0165] Referring to FIG. 12i, a second insulating layer (112) can be formed on the first insulating layer (111). The second insulating layer (112) can cover the capacitor structure (CAS) and the first insulating layer (111). Furthermore, a fourth insulating layer (114) can be formed under the third insulating layer (113).

[0166] Referring to FIG. 12j, a first via (V1) and a second via (V2) can be formed by etching and drilling in the second insulating layer (112). The first via (V1) and the second via (V2) can have different lengths in the vertical direction. The first via (V1) and the second via (V2) can penetrate the second insulating layer (112). Etching and drilling can also be performed on the fourth insulating layer (114). Alternatively, etching and the like on the fourth insulating layer (114) may be performed previously.

[0167] And the first via (V1) may be located on the capacitor structure. The second via (V2) may be spaced apart from the capacitor structure. The capacitor structure may be exposed by the first via (V1). The first via land may be exposed by the second via (V2).

[0168] Referring to FIG. 12k, a plating layer (340) for plating can be formed on the second insulating layer (112). For example, a plating layer (340) for chemical plating can be formed. However, various processes other than this plating process can be applied. In addition, the plating layer (340) can be formed in the same manner under the fourth insulating layer (114).

[0169] Referring to FIG. 12l, a mask (330'') can be formed on the second insulating layer (112) and the plating layer (340). For example, the mask (330'') can be a dry film. Then, exposure and development, etc. can be performed on the mask (330'') to form an open area. In other words, patterning can be performed on the dry film. The mask (330'') can be positioned in an area other than the first via (V1) and the second via (V2).

[0170] Furthermore, a mask curing process can be performed after the formation of an open area by exposure, etc. This mask formation can be applied to other mask formations in the same manner.

[0171] And the formation and patterning of this mask (330'') can be equally applied to the lower portion of the fourth insulating layer (114). In other words, the formation and patterning of the mask (330'') can be equally applied to the via or around the via formed in the fourth insulating layer (114).

[0172] Referring to FIG. 12m, a second electrode portion (122) and a third electrode portion (123) can be formed. For example, plating can be performed on the first via (V1) and the second via (V2) through an electroplating process. Accordingly, the second electrode portion (122) can be formed on the first via (V1), and the third electrode portion (123) can be formed on the second via (V2).

[0173] In addition, the same can be applied to the lower part of the fourth insulating layer (114) through electroplating. Thus, the fifth electrode portion (125) can be formed.

[0174] Referring to FIG. 12n, the mask (330'') can be removed. The mask (330'') can be removed by various etching methods. For example, the mask (330'') on the second insulating layer (112) and the mask (330'') under the fourth insulating layer (114) can be removed.

[0175] Referring to FIG. 12o, etching (e.g., flash etching) may be performed on the plating layer (340). That is, the plating layer (340) may be removed by etching. For example, the plating layer (340) at a location corresponding to the mask (330'') may be removed.

[0176] The plating layer (340) on the upper side of the second insulating layer (112) and the plating layer (340) on the lower side of the fourth insulating layer (114) can be removed.

[0177] By this configuration, the second electrode portion (122) and the third electrode portion (123) can be electrically separated. Furthermore, electrical separation can be achieved between a plurality of second electrode portions (122). In addition, electrical separation can be achieved between a plurality of third electrode portions (123). Similarly, electrical separation can be achieved between a plurality of fifth electrode portions (125).

[0178] Additionally, as a variation, a portion of the circuit board described above can be manufactured using the process described below, prior to FIG. 5i. Based on the above-described content and drawings, for example, a carrier board can be prepared in a variation. Similarly, the ETS method can be used to prepare basic materials for manufacturing a circuit board or a semiconductor package including the circuit board.

[0179] The carrier board may include a carrier insulating layer (310) and a carrier metal layer (320) disposed on at least one surface of the carrier insulating layer (310).

[0180] Furthermore, a second electrode layer, a dielectric layer, and a first electrode layer for a capacitor structure may be sequentially laminated on a carrier board. The first electrode layer may correspond to the first via land described above. And the second electrode layer may correspond to the second via land described above. In addition, the dielectric layer may correspond to the above-described dielectric layer.

[0181] And the carrier metal layer (320) can be placed on only one of the upper and lower surfaces of the carrier insulating layer (310), or alternatively, can be placed on both surfaces.

[0182] For example, the carrier metal layer (320) may be disposed on both sides of the carrier insulating layer (310). In addition, when the carrier metal layer (320) is disposed on both sides of the carrier insulating layer (310), a process of manufacturing two semiconductor packages simultaneously on both sides of the carrier board may be performed. In this case, two semiconductor packages may be manufactured at one time.

[0183] This carrier metal layer (320) can be formed by electroless plating on the carrier insulating layer (310). Alternatively, the carrier insulating layer (310) and the carrier metal layer (320) can be CCL (Copper Clad Laminate).

[0184] Next, patterning of the outer first electrode layer can be performed. For example, the first electrode layer can be etched using various methods. Accordingly, the first electrode layer can have a shape corresponding to the first via land (VL1) described above. In other words, the first electrode layer can be etched to control the position of the capacitor structure.

[0185] Next, a first insulating layer (111) can be laminated. The first insulating layer (111) can cover the first via land (VL1). Furthermore, the first insulating layer (111) can be positioned on top of the dielectric layer.

[0186] Next, a first electrode portion (121) can be formed on the first insulating layer (111). The first electrode portion (121) can be formed by sequentially forming a mask such as a dry film, forming a mask pattern, etching part of the first insulating layer (forming a via hole, etc.), and forming an electrode.

[0187] And a third insulating layer (113) may be formed on the first insulating layer (111) and the first electrode portion (121). The third insulating layer (113) may be positioned on the first insulating layer (111) and the first electrode portion (121).

[0188] And, on the third insulating layer (113), mask formation such as a dry film, mask pattern formation, partial etching of the first insulating layer (formation of a via hole, etc.), and electrode formation can be sequentially performed. Accordingly, a fourth electrode portion (124) can be formed on the third insulating layer (113).

[0189] Next, in the embodiment, a process for removing the carrier board may be performed. For example, a process for removing the carrier insulation layer (310) from the carrier board may be performed. For example, in the embodiment, a process for separating the carrier insulation layer (310) from the carrier metal layer (320) may be performed.

[0190] Next, a mask (330') may be formed on the second electrode layer. For example, the mask (330') may be a dry film. Then, exposure and development, etc. may be performed on the mask (330') to form an open area. In other words, patterning of the dry film may be performed. The mask (330') may be positioned at a position corresponding to the first via land. Furthermore, a curing process of the mask may be performed after the formation of the open area by exposure, etc. This mask formation may be applied to other mask formations in the same manner.

[0191] Next, etching may be performed on the open area. In other words, etching may be performed on a portion of the second electrode layer. As a portion of the second electrode layer is removed, a second via land (VL2), which is a residual layer of the second electrode layer, may be formed corresponding to the first via land (VL1).

[0192] Next, etching of the dielectric layer may be performed. In other words, etching may be performed on a portion of the dielectric layer. As a portion of the dielectric layer is removed, the remaining dielectric layer (DL) may be positioned between the first via land (VL1) and the second via land (VL2). This allows the capacitor structure to be positioned on the first insulating layer (111).

[0193] Furthermore, the mask (330') can be removed. The mask (330') can be removed by various etching methods.

[0194] Fig. 13 is a schematic diagram of a semiconductor package according to an embodiment.

[0195] Referring to FIG. 13, a semiconductor package according to an embodiment may include a lower substrate (200), a circuit board (100), and a semiconductor element (DI).

[0196] The lower substrate (200) may refer to a package substrate. For example, the lower substrate (200) may provide a space to which at least one external substrate is coupled. The external substrate may refer to a circuit board (100) coupled on the lower substrate (200). In addition, the external substrate may refer to a main board included in an electronic device coupled to the lower portion of the lower substrate (200). In addition, although not shown in the drawing, the lower substrate (200) may provide a space to which at least one semiconductor element is mounted. The lower substrate (200) may include at least one insulating layer and an electrode portion disposed on the at least one insulating layer.

[0197] A circuit board (100) may be placed on the lower substrate (200). The circuit board (100) may include a circuit board according to various embodiments described above.

[0198] In addition, the circuit board (100) may be an interposer. For example, the circuit board (100) may provide a space in which at least one semiconductor element is mounted. The circuit board (100) may be connected to at least one semiconductor element (DI). For example, the circuit board (100) may provide a space in which the first semiconductor element (DI) to the third semiconductor element (DI3) are mounted. The circuit board (100) may electrically connect the first semiconductor element (DI) to the third semiconductor element (DI3) and electrically connect the first semiconductor element (DI) to the third semiconductor element (DI3) and the lower substrate (200). That is, the circuit board (100) may perform a horizontal connection function between a plurality of semiconductor elements and a vertical connection function between the semiconductor elements and the package substrate.

[0199] Although three semiconductor elements (DI) are illustrated as being arranged on the circuit board (100), this is not a limitation. For example, one semiconductor element may be arranged on the circuit board (100), or alternatively, a plurality of semiconductor elements may be arranged. The circuit board (100) may be arranged between at least one semiconductor element (DI) and the lower substrate (200).

[0200] In one embodiment, the circuit board (100) may be an active interposer that functions as a semiconductor device. When the circuit board (100) functions as a semiconductor device, the semiconductor package of the embodiment may have a vertically stacked structure on the lower substrate (200) and may function as a plurality of logic chips. Having the function of a logic chip may mean having the functions of an active device and a passive device. Unlike passive devices, the characteristics of current and voltage may not be linear in the case of an active device, and the active interposer may have the function of an active device. In addition, the active interposer may perform the function of a corresponding logic chip while performing a signal transmission function between a second logic chip disposed thereon and the lower substrate (200).

[0201] In another embodiment, the circuit board (100) may be a passive interposer. For example, the circuit board (100) may function as a signal relay between the semiconductor element (DI) and the lower substrate (200), and may have passive element functions such as a resistor, a capacitor, and an inductor. For example, the number of terminals in the semiconductor element (DI) is gradually increasing due to reasons such as 5G, the Internet of Things (IoT), increased image quality, and increased communication speed. That is, the number of terminals provided in the semiconductor element (DI) is increasing, and accordingly, the width of the terminals or the spacing between the plurality of terminals is decreasing. At this time, the lower substrate (200) may be connected to the main board of the electronic device. Accordingly, in order for the electrodes provided in the lower substrate (200) to have a width and spacing for being connected to the semiconductor element (DI) and the main board, respectively, there is a problem in that the thickness of the lower substrate (200) increases or the layer structure of the lower substrate (200) becomes complicated. Accordingly, the first embodiment can place a circuit board (100) on a lower substrate (200) and a semiconductor element (DI). And the circuit board (100) can include electrodes having a microscopic width and spacing corresponding to the terminals of the semiconductor element (DI).

[0202] Semiconductor devices (DIs) can be logic chips, memory chips, etc. Logic chips can be central processors (CPUs), graphics processors (GPUs), etc.

[0203] Additionally, the semiconductor package of the embodiment may include a connection portion.

[0204] For example, a semiconductor package may include a first connector positioned between a lower substrate (200) and a circuit board (100). The first connector may electrically connect the circuit board (100) to the lower substrate (200) while bonding them therebetween.

[0205] For example, the semiconductor package may include a second connector positioned between the circuit board (100) and the semiconductor element (DI). The second connector may electrically connect the semiconductor element (DI) to the circuit board (100) while bonding them thereto.

[0206] The semiconductor package may include a third connector positioned on the lower surface of the lower substrate (200). The third connector may electrically connect the lower substrate (200) to the main board while connecting them.

[0207] At this time, the first connection portion, the second connection portion, and the third connection portion can electrically connect the plurality of components using at least one bonding method among wire bonding, solder bonding, and direct metal-to-metal bonding. That is, since the first connection portion, the second connection portion, and the third connection portion have the function of electrically connecting the plurality of components, when direct metal-to-metal bonding is used, the semiconductor package can be understood as a part that is electrically connected rather than solder or wire.

[0208] In at least one of the lower substrate (200) and the circuit board (100), the electrodes on which the first connection portion, the second connection portion, and the third connection portion are arranged may be provided with a protrusion that protrudes outwardly away from the insulating layer of the corresponding substrate. The protrusion may protrude outwardly from the lower substrate (200) or the circuit board (100).

[0209] The protrusion may be referred to as a bump. The protrusion may also be referred to as a post. The protrusion may also be referred to as a pillar. Preferably, the protrusion may refer to an electrode on which a second connection portion for coupling with a semiconductor element (DI) is arranged among the electrodes of the circuit board (100). That is, as the pitch of the terminals of the semiconductor element (DI) becomes finer, a short circuit may occur between a plurality of second connection portions, which are respectively connected to a plurality of terminals of the semiconductor element (DI) by a conductive adhesive such as solder. Therefore, the embodiment may perform thermal compression bonding to reduce the volume of the second connection portion. Accordingly, the embodiment may include a protrusion in the electrode of the circuit board (100) on which the second connection portion is arranged, in order to secure matching, diffusion, and diffusion prevention to prevent an intermetallic compound (IMC) formed between the conductive adhesive such as solder and the protrusion from diffusing into the interposer and / or the substrate.

[0210] In addition, the semiconductor package may include a connecting member. The connecting member may be referred to as a bridge substrate. For example, the connecting member may include a redistribution layer. The connecting member may function to horizontally electrically connect a plurality of semiconductor devices to each other. For example, since the area that a semiconductor device must have is generally very large, the connecting member may include a redistribution layer. Since the semiconductor package and the semiconductor device have a large difference in the width or width of the circuit pattern, etc., a buffering function of the circuit pattern for electrical connection is required. The buffering function may mean having a size between the width or width of the circuit pattern of the semiconductor package and the width or width of the circuit pattern of the semiconductor device, and the redistribution layer may have a function of performing a buffering function.

[0211] In an embodiment, the connecting member may be an organic bridge. For example, the connecting member may include an organic material. For example, the connecting member may include an organic substrate instead of a silicon substrate. The connecting member may be embedded within the circuit board (100).

[0212] To this end, the circuit board (100) may include a cavity, and a connecting member may be placed within the cavity of the circuit board (100). The connecting member may horizontally connect a plurality of semiconductor elements placed on the circuit board (100).

[0213] Furthermore, the circuit board according to the embodiment can be divided into a package board and an interposer corresponding to the lower board according to the function of the circuit board, and applied thereto. The package board has a function for mounting semiconductor devices and / or interposers. As the area of ​​the circuit board increases due to the increase in data, or as the number of laminated insulating layers increases, the yield of the circuit board may be greatly reduced. Therefore, in order to improve the yield of a circuit board with a high number of laminated layers, the yield of the circuit board can be improved by separating it into an interposer and a package board. In addition, as the density of terminals of semiconductor devices increases, it may be difficult to implement pads of the package board having an area corresponding to the terminals of the semiconductor devices. Therefore, the pad size of the package board and the fine pattern size of the terminals of the semiconductor devices can act as a buffer.

[0214] The package substrate and interposer described above can be classified into core substrates and coreless substrates, depending on the composition of the insulating layer. In the case of a core substrate, the insulating layer may include a core layer, and the core layer may refer to a layer among the laminated insulating layers that includes a reinforcing member. The reinforcing member may refer to glass fiber. The core layer may have the function of preventing warpage of the circuit board during the process by being arranged thicker than other insulating layers. However, the core layer may cause problems such as voltage drop and signal loss, or may be difficult to thin. Therefore, depending on the application, the insulating layer of the circuit board may use a coreless substrate that does not include a core layer.

[0215] In various semiconductor packages, circuit boards according to the various embodiments described above may be located in some areas or correspond to one substrate.

[0216] Meanwhile, when a circuit board having the characteristics of the invention described above is used in IT devices such as smartphones, server computers, TVs, or home appliances, it can stably perform functions such as signal transmission or power supply. For example, when a circuit board having the characteristics of the invention performs a semiconductor package function, it can safely protect semiconductor chips from external moisture or contaminants, and can solve problems such as leakage current or electrical shorts between terminals, or electrical open circuits in terminals supplying semiconductor chips. Furthermore, when it performs a signal transmission function, it can solve noise problems. Through this, the circuit board having the characteristics of the invention described above can maintain the stable function of IT devices or home appliances, thereby enabling the entire product and the circuit board to which the invention is applied to achieve functional integration or technical interoperability with each other.

[0217] When a circuit board having the characteristics of the invention described above is used in a transportation device such as a vehicle, it can solve the problem of signal distortion transmitted to the transportation device, safely protect the semiconductor chip controlling the transportation device from external sources, and solve the problem of leakage current or electrical short circuit between terminals, or electrical open of the terminal supplying the semiconductor chip, thereby further improving the stability of the transportation device. Accordingly, the transportation device and the circuit board to which the present invention is applied can achieve functional integration or technical interoperability with each other.

[0218] The features, structures, effects, etc. described in the embodiments above are included in at least one embodiment, and are not necessarily limited to just one embodiment. Furthermore, the features, structures, effects, etc. exemplified in each embodiment can be combined or modified in other embodiments by those skilled in the art to which the embodiments pertain. Therefore, the contents related to such combinations and modifications should be construed as being included within the scope of the embodiments.

[0219] Although the above description focuses on examples, these are merely examples and are not intended to limit the examples. Those skilled in the art will appreciate that various modifications and applications not exemplified above are possible without departing from the essential characteristics of the present examples. For example, each component specifically shown in the examples can be modified and implemented. In addition, differences related to such modifications and applications should be interpreted as being included within the scope of the embodiments set forth in the appended claims.

Claims

1. First insulation layer; A second insulating layer disposed on the first insulating layer; A first via land disposed between the first insulating layer and the second insulating layer; A second via land disposed between the first via land and the upper surface of the second insulating layer; A first via electrode disposed between the first via land and the upper surface of the second insulating layer; A second via electrode disposed between the second via land and the upper surface of the second insulating layer; A third via electrode disposed between the lower surface of the first insulating layer and the upper surface of the second insulating layer; and A dielectric layer disposed between the first vialand and the second vialand; The dielectric layer overlaps the first insulating layer and the second insulating layer in the horizontal direction, A circuit board in which the thickness of the first via electrode, the thickness of the second via electrode, and the thickness of the third via electrode are different from each other.

2. In paragraph 1, A circuit board wherein the thickness of the first via electrode is greater than the thickness of the second via electrode.

3. In paragraph 1, A circuit board wherein the thickness of the third via electrode is greater than the thickness of the second via electrode.

4. In paragraph 1, A circuit board in which the third via electrode penetrates the second insulating layer and a portion of the first insulating layer.

5. In paragraph 1, A circuit board in which the first via electrode horizontally overlaps the second via electrode.

6. In paragraph 1, A circuit board in which the third via electrode is horizontally overlapped with the first via electrode and the second via electrode.

7. In paragraph 1, A circuit board wherein the area of ​​the upper surface of the first via land is larger than the area of ​​the upper surface of the second via land.

8. In paragraph 1, A circuit board wherein the thickness of the first via land is different from the thickness of the second via land.

9. In paragraph 1, A circuit board in which the widths of the first via electrode and the second via electrode gradually decrease from the upper surface of the second insulating layer toward the lower surface of the second insulating layer.

10. In paragraph 1, A circuit board in which the width of the third via electrode gradually decreases from the upper surface of the second insulating layer toward the lower surface of the first insulating layer.

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