Systems and methods for manufacturing high-efficiency capacitor layers and capacitors with 2d / 3d structures

Abstract

Systems and methods for the fabrication of highly efficient capacitor layers and capacitors by transferring 2D or 3D layers on a ferroelectric layer, lifted off from the host substrate, including electrodes. The type of 2D or 3D layer may be selected according to the specific situation, and may include up to thousands of layers. Capacitors and capacitor layers derived from these systems and methods are capable of providing higher energy storage than the conventional approaches that include a dielectric / ferroelectric / dielectric layer structure due to reduction in the dielectric constant and polarization density that is much less than that of the ferroelectric layer.

Description

CT SYSTEMS AND METHODS FOR MANUFACTURING HIGH-EFFICIENCY CAPACITOR LAYERS AND CAPACITORS WITH 2D / 3D STRUCTURES CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims the benefit of priority to U.S. Provisional Application numbers (i) 63 / 617,314 filed on January 3, 2024, and (ii) 63 / 635,275 filed on April 17, 2024, the entire content and disclosures of each of which are incorporated herein by reference in their respective entireties for all purposes. FIELD

[0002] The present disclosure generally relates to high-efficiency ferroelectric capacitors and methods of producing the high-efficiency ferroelectric capacitors. The present disclosure also relates to multilayer ceramic capacitors and methods of producing the multilayer ceramic capacitors. BACKGROUND

[0003] Electrostatic capacitors are foundational components in advanced electronics and high-power electrical systems due to their ultrafast charging / discharging capability. To further enhance the energy density of electrostatic capacitors, it has been considered to utilize ferroelectric materials, which offer substantially high maximum polarization. Yet the persistent challenge of high remnant polarization within ferroelectric materials has hindered their effective deployment in energy storage applications. Numerous innovative approaches have been proposed to tackle this challenge. However, these methodologies have encountered hurdles in enhancing performance, attributed to the deteriorated crystallinity of the ferroelectric materials.

[0004] As research on high-frequency, high-power, and miniaturized electronic devices emerges, demand for very small capacitors with high energy storage capacity dramatically increases. Although the dielectric constant of conventional ferroelectric materials is much higher than that of dielectric materials, the energy density is low due to energy loss caused by remnant polarization. Dielectric (DE) materials with a high dielectric constant are used in capacitors. However, their dielectric constant is much lower than that of ferroelectric material such as BaTiO3 (BTO), which has a dielectric constant ofCT 1,500. Ferroelectric materials have high dielectric constant, but they have a remnant polarization, which causes significant energy loss and reduces efficiency. Many researchers are studying to reduce the energy loss of ferroelectric materials. Doping engineering and composition engineering reduce the crystallinity of the ferroelectric layer and decrease the dielectric constant. The thin film stacking approach does not affect the crystallinity of the ferroelectric layer but reduces the total energy storage by stacking relatively low dielectric constant and thin layers. Ultimately, developing materials with high dielectric constant, high energy storage, and low energy loss is necessary.

[0005] What is needed are systems, methods, and devices for (i) fabricating capacitor layers and / or capacitor devices with high dielectric constant, high energy storage, and low energy loss; (ii) precise control of the relaxation time of polarization, and / or (iii) highly efficient and vertically heterointegrated multilayer ceramic capacitors with crystalline (e.g., single crystalline, polycrystalline) ferroelectric materials without energy loss.

[0006] This background section is intended to introduce the reader to various aspects of art that may be related to various aspects of the present disclosure, which are described and / or claimed below. This discussion is believed to be helpful in providing the reader with background information to facilitate a better understanding of the various aspects of the present disclosure. Accordingly, it should be understood that these statements are to be read in this light, and not as admissions of prior art. BRIEF DESCRIPTION OF THE DISCLOSURE

[0007] One aspect of the present disclosure is a capacitor device including: a 3D layer including a crystalline ferroelectric material, the 3D layer including a first surface and a second surface, the first surface being opposite the second surface; a first 2D layer on the first surface of the 3D layer; and a second 2D layer on the second surface of the 3D layer, wherein application of (i) the first 2D layer on the first surface and (ii) the second 2D layer on the second surface does not disrupt a crystalline structure of the crystalline ferroelectric material.

[0008] Another aspect of the present disclosure is a method of fabricating a capacitor device including: forming, on a first substrate, a 3D layer on a sacrificial layer, the 3D layer including a 3D ferromagnetic material; forming a 3D layer structure from at leastCT the 3D layer and the first substrate; forming a freestanding 3D layer from at least the 3D layer structure; forming at least one 2D layer; forming a 2D layer structure from at least the at least one 2D layer; contacting an exposed surface of the at least one 2D layer with a target substrate; forming a structure including the 3D layer, the 2D layer, and the target substrate; and forming the capacitor device with the structure including the 3D layer, the 2D layer, and the target substrate.

[0009] Yet another aspect of the present disclosure is a method of fabricating a capacitor device including: growing (i) a first sacrificial layer on a first substrate and (ii) a second sacrificial layer on a second substrate; growing (i) a first 2D layer on the first sacrificial layer and (ii) a second 2D layer on the second sacrificial layer, thereby forming a first 2D layer / first sacrificial layer structure on the first substrate and a second 2D layer / second sacrificial layer structure on the second substrate; depositing (i) a first handling layer on the first 2D layer of the first 2D layer / first sacrificial layer structure and (i) a second handling layer on the second 2D layer of the second 2D layer / second sacrificial layer structure, thereby forming (i) a first handling layer / first 2D layer / first sacrificial layer structure on the first substrate and (ii) a second handling layer / second 2D layer / second sacrificial layer structure on the second substrate; etching (i) the first sacrificial layer to release a first handling layer / first 2D layer structure from the first substrate and (ii) the second sacrificial layer to release a second handling layer / second 2D layer structure from the second substrate; depositing a third sacrificial layer on a growth substrate; growing a single crystal of a 3D ferromagnetic material on the first sacrificial layer, thereby forming a 3D layer / third sacrificial layer structure on the growth substrate; depositing a third handling layer on the single crystal of the 3D ferromagnetic material, thereby forming a third handling layer / 3D layer / third sacrificial layer structure on the growth substrate; etching the third sacrificial layer to separate a third handling layer / 3D layer structure from the growth substrate; scooping the third handling layer / 3D layer structure onto a fourth handling layer to form a freestanding fourth handling layer / third handling layer / 3D layer structure; contacting an exposed ferromagnetic crystal surface of the fourth handling layer / third handling layer / 3D layer structure with an exposed 2D surface of the second 2D layer, thereby forming a second 2D layer / 3D layer / third handling layer / fourth handling layer structure; etching the first and fourth handling layers of a second 2D layer / 3D layer / third handling layer structure and contacting the exposed surface of the second 2D layer with a target substrateCT to form a third handling layer / 3D layer / second 2D layer / target substrate structure; etching the third handling layer and contacting the exposed ferromagnetic crystal surface of a resulting 3D layer / second 2D layer / target substrate structure with the exposed first 2D layer of the first 2D layer / first sacrificial layer structure to form a first sacrificial layer / first 2D layer / 3D layer / second 2D layer / target substrate structure; and etching the first handling layer to form the capacitor device including a first 2D layer / 3D layer / second 2D layer / target substrate structure.

[0010] Various refinements exist of the features noted in relation to the above-mentioned aspects. Further features may also be incorporated in the above-mentioned aspects as well. These refinements and additional features may exist individually or in any combination. For instance, various features discussed below in relation to any of the illustrated embodiments may be incorporated into any of the above-described aspects, alone or in any combination. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The patent or application file contains at least one drawing executed in color. Copies of this patent or patent application publication with color drawing(s) will be provided by the Office upon request and payment of the necessary fee.

[0012] The embodiments described herein may be better understood by referring to the following description in conjunction with the accompanying drawings. Those of skill in the art will understand that the drawings, described below, are for illustrative purposes only. The drawings are not intended to limit the scope of the present teachings in any way.

[0013] FIG.1A is a diagram illustrating band gap versus dielectric constant of materials of the present disclosure.

[0014] FIG. 1B is a diagram illustrating polarization versus electric field curves of dielectric and ferroelectric materials of the present disclosure.

[0015] FIG. 1C is a table illustrating approaches to reduce energy loss of the present disclosure.CT

[0016] FIG. 1D is a plot illustrating dielectric permittivity and Curie temperature of various ferroelectric materials of the present disclosure.

[0017] FIG. 1E is a diagram illustrating problems faced in dielectric / ferroelectric / dielectric multilayer ceramic capacitors of the present disclosure.

[0018] FIG. 2A illustrates a dielectric / ferroelectric / dielectric high- efficiency capacitor and capacitor layer configuration according to one embodiment of the present disclosure.

[0019] FIG.2B is a plot illustrating polarization versus electric field curves for a dielectric / ferroelectric / dielectric high-efficiency capacitor configuration according to one embodiment of the present disclosure.

[0020] FIG. 2C is a diagram illustrating applications for a dielectric / ferroelectric / dielectric high-efficiency capacitor configuration according to the present disclosure.

[0021] FIG. 3 is a diagram illustrating techniques for manufacturing a multilayer ceramic capacitor according to one embodiment of the present disclosure.

[0022] FIG.4 is a diagram illustrating applications for a multilayer ceramic capacitor according to the present disclosure.

[0023] FIGs.5A-5D illustrate management of spontaneous polarization via Miller model inspired from classic Debye relaxation for a first experiment of the present disclosure. FIG. 5A illustrates a diagram of Miller model polarizability vs. ωτ curve, according to the first experiment of the present disclosure. FIG.5B illustrates a diagram of a summary of the conductivity vs. dielectric constant curve of several two-dimensional (2D) materials according to the first experiment of the present disclosure. FIG. 5C illustrates dielectric Cole-Cole plots according to the first experiment of the present disclosure. FIG. 5D illustrates a diagram of Tan δ vs. frequency curves of C-BTO, 2D / C-3D / 2D, and 3D / C- 3D / 3D structures according to the first experiment of the present disclosure.

[0024] FIGs.6A-6D illustrate management of spontaneous polarization via Miller model inspired from classic Debye relaxation for a second experiment of the presentCT disclosure. FIG. 6A illustrates a diagram of Miller model polarizability vs. ωτ curve, according to the second experiment of the present disclosure. FIG.6B illustrates a diagram of a summary of the conductivity vs. dielectric constant curve of several 2D materials according to the second experiment of the present disclosure. FIG.6C illustrates dielectric Cole-Cole plots according to the second experiment of the present disclosure. FIG. 6D illustrates a diagram of Tan δ vs. frequency curves of C-BaTiO3 (BTO), 2D / C-3D / 2D, and 3D / C-3D / 3D structures according to the second experiment of the present disclosure.

[0025] FIGs. 7A-7E illustrate polarization of the C-BTO, 3D / 3D / 3D, and 2D / 3D / 2D heterostructures for each of the first and second experiments of the present disclosure. FIG.7A is a plot illustrating a P-E loop of C-BTO. FIG.7B is a plot illustrating a comparison of P-E loops of Al2O3 / C-BTO / Al2O3with strongly and weakly bonded interfaces. FIG. 7C is a plot illustrating a P-E loop of the 2D / 3D / 2D heterostructure. FIG. 7D is a plot illustrating Pm- Pr. FIG.7E is a plot illustrating Pm / Pr calculated from the P-E loops.

[0026] FIGs. 8A-8E illustrate atomic-scale polarization distribution and additional electrical performance under bias for the first experiment. FIG. 8A illustrates a STEM-HAADF image and an iDPC image of 2ML-MoS2 / C-BTO / 2ML-MoS2. FIG.8B is a plot illustrating a P-E loop of the C-BTO, 2ML-MoS2 / C-BTO / 2ML-MoS2, and 2ML- MoS2 / C-BTO / 2ML-MoS2 after mechanically exfoliating the MoS2 layers. FIG. 8C is a dielectric Cole-Cole plot for C-BTO. FIG.8D is a plot illustrating 2ML-MoS2 / C-BTO / 2ML- MoS2, under DC bias from 0 to 5 MV / cm. FIG.8E is a plot illustrating the ωτ under electric field of C-BTO, 1ML-MoS2 / C-BTO / 1ML-MoS2, and 2ML-MoS2 / C-BTO / 2ML-MoS2.

[0027] FIGs. 9A-9E illustrate atomic-scale polarization distribution and additional electrical performance under bias for the second experiment. FIG.9A illustrates a STEM-HAADF image and an iDPC image of 2ML-MoS2 / C-BTO / 2ML-MoS2. FIG.9B is a plot illustrating a P-E loop of the C-BTO, 2ML-MoS2 / C-BTO / 2ML-MoS2, and 2ML- MoS2 / C-BTO / 2ML-MoS2 after mechanically exfoliating the MoS2 layers. FIG. 9C is a dielectric Cole-Cole plot for C-BTO. FIG.9D is a plot illustrating 2ML-MoS2 / C-BTO / 2ML- MoS2, under DC bias from 0 to 5 MV / cm. FIG.9E is a plot illustrating the ωτ under electric field of C-BTO, 1ML-MoS2 / C-BTO / 1ML-MoS2, and 2ML-MoS2 / C-BTO / 2ML-MoS2.CT

[0028] FIGs.10A-10F illustrate energy storage performance of C-BTO and MoS2 / C-BTO / MoS2 with respect to the number of MoS2 layers of the first experiment. FIG. 10A is a plot illustrating two-parameter Weibull distribution analysis of the characteristic breakdown fields. FIG. 10B is a plot illustrating voltage-dependent energy density and efficiency of the C-BTO and MoS2 / C-BTO / MoS2heterostructures. FIG. 10C is a plot illustrating temperature-dependence of energy densities and efficiencies at the temperature range from 250 to 400K. FIG.10D is a plot illustrating P-E loops of C-BTO. FIG.10E is a plot illustrating 1ML-MoS2 / C-BTO / 1ML-MoS2. FIG. 10F is a plot illustrating 2ML- MoS2 / C-BTO / 2ML-MoS2 at temperatures ranging from 250 to 400K.

[0029] FIGs.11A-11D illustrate energy storage performance of C-BTO and MoS2 / C-BTO / MoS2with respect to the number of MoS2layers of the second experiment. FIG. 11A is a plot illustrating two-parameter Weibull distribution analysis of the characteristic breakdown fields. FIG. 11B is a plot illustrating voltage-dependent energy density and efficiency of the C-BTO and MoS2 / C-BTO / MoS2heterostructures. FIG.11C is a plot illustrating temperature-dependence of energy densities and efficiencies at the temperature range from 250 to 400K. FIG.11D is a plot illustrating P-E loops of C-BTO.

[0030] FIGs. 12A and 12B illustrate atomic-force microscopy (AFM) images of an as-grown BTO used in the first and second experiments according to one embodiment of the present disclosure. FIG. 12A illustrates a plan-view and FIG. 12B illustrates a three-dimensional AFM image of the as-grown BTO.

[0031] FIG. 13 is a plot of an XRD rocking curve of the as-grown BTO used in the first and second experiments according to one embodiment of the present disclosure.

[0032] FIG. 14 illustrates an electron back-scattering diffraction (EBSD) mapping of the as-grown BTO according to one embodiment of the present disclosure.

[0033] FIGs.15 and 16 are plots illustrating a capacitance vs. voltage (CV) curve of the C-BTO according to one embodiment of the present disclosure. FIG.15 is a plot illustrating results of the first experiment and FIG. 16 is a plot illustrating results of the second experiment.CT

[0034] FIG.17 is a diagram illustrating a 2D / C-BTO / 2D fabrication process according to one embodiment of the present disclosure, illustrating a plurality of steps of the fabrication process for a 2D / C-BTO / 2D structure in each of the first and second experiments.

[0035] FIG. 18 is a diagram illustrating a strongly chemically-bonded 3D / C-BTO / 3D fabrication process according to one embodiment of the present disclosure, illustrating a plurality of steps of the fabrication process for a 3D / C-BTO / 3D structure with a strongly chemically bonded interface used for each of the first and second experiments.

[0036] FIG. 19 is a diagram illustrating a weakly bonded 3D / C-BTO / 3D fabrication process according to one embodiment of the present disclosure, illustrating a plurality of steps of the fabrication process for a 3D / C-BTO / 3D structure without strong chemical bonds at the interface used for each of the first and second experiments.

[0037] FIG. 20 is Cole-Cole plot for each of the first and second experiments, illustrating calculated relaxation time according to one embodiment of the present disclosure.

[0038] FIG.21 is a plot 2100 illustrating P-E loops of C-BTO with different thicknesses for the first experiment according to one embodiment of the present disclosure.

[0039] FIGs.22A and 22B are diagrams illustrating an electronic structure of a 1ML-MoS2 / C-BTO / 1ML-MoS2heterostructure from density-functional theory (DFT) for each of the first and second experiments according to one embodiment of the present disclosure. FIG. 22A is a diagram illustrating an atomic configuration and layer-projected density of states across the ‘Au / lML-MoS2 / BaTiO3 / 1ML-MoS2 / Au’ heterostructure. FIG. 22B is a diagram illustrating laterally averaged charge density difference along the c-axis of the ‘Au / lML-MoS2 / BaTiO3 / 1ML-MoS2 / Au’ heterostructure.

[0040] FIGs.23A and 23B are diagrams illustrating an electronic structure of a 2ML-MoS2 / C-BTO / 2ML-MoS2heterostructure for each of the first and second experiments according to one embodiment of the present disclosure. FIG.23A is a diagram illustrating an atomic configuration and layer-projected density of states across the ‘Au / 2ML-MoS2 / BaTiO3 / 2ML-MoS2 / Au’ heterostructure. FIG.23B is a diagram illustratingCT laterally averaged charge density difference along the c-axis of the ‘Au / 2ML- MoS2 / BaTiO3 / 2ML-MoS2 / Au’ heterostructure.

[0041] FIGs. 24 and 25 are plots illustrate a dielectric Cole-Cole plot according to one embodiment of the present disclosure. FIG.24 is a plot illustrating results of the first experiment and FIG. 25 is a plot illustrating results of the second experiment, each for 2ML-MoS2 / C-BTO / 2ML-MoS2.

[0042] FIG.26 is high-angle annular dark field (HAADF) images of 2ML- MoS2 / C-BTO / 2ML-MoS2for each of the first and second experiments according to one embodiment of the present disclosure.

[0043] FIGs.27A-27C are plots illustrating frequency dependent dielectric constant curves for the first experiment according to one embodiment of the present disclosure. FIG. 27A is a plot illustrating frequency dependent real dielectric constant and imaginary dielectric constant curves of the C-BTO. FIG. 27B is a plot illustrating 1ML- MoS2 / C-BTO / 1ML-MoS2. FIG.27C is a plot illustrating 2ML-MoS2 / C-BTO / 2ML-MoS2.

[0044] FIGs.28A-28C are plots illustrating frequency dependent dielectric constant curves for the second experiment according to one embodiment of the present disclosure. FIG. 28A is a plot illustrating frequency dependent real dielectric constant and imaginary dielectric constant curves of the C-BTO. FIG. 28B is a plot illustrating 1ML- MoS2 / C-BTO / 1ML-MoS2. FIG.28C is a plot illustrating 2ML-MoS2 / C-BTO / 2ML-MoS2.

[0045] FIGs. 29 and 30 are DC electric field dependent Cole-Cole plots according to one embodiment of the present disclosure, where FIG.29 illustrates results of the first experiment and FIG.30 illustrates results of the second experiment.

[0046] FIG. 31 is a plot illustrating a two-parameter Weibull distribution analysis of breakdown strengths for each of the first and second experiments according to one embodiment of the present disclosure.

[0047] FIGs.32A-32C are plots illustrating leakage current densities of the C-BTO and MoS2 / C-BTO / MoS2 for each of the first and second experiments according to one embodiment of the present disclosure. FIG. 32A is a plot illustrating leakage currentCT density vs. electric field for C-BTO. FIG.32B is a plot illustrating 1ML-MoS2 / C-BT0 / 1ML- MoS2. FIG.32C is a plot illustrating 2ML-MoS2 / C-BTO / 2ML-MoS2.

[0048] FIG. 33 is a diagram illustrating comparative energy densities of different structural configurations for each of the first and second experiments according to one embodiment of the present disclosure.

[0049] FIG. 34 is a plot illustrating frequency dependent energy storage performance of the 2ML-MoS2 / BTO / 2ML-MoS2 for the first experiment according to one embodiment of the present disclosure, specifically a P-E loop of the 2ML-MoS2 / BTO / 2ML- MoS2.

[0050] FIGs.35A-35C are plots illustrating cyclic tests of the C-BTO and MoS2 / C-BTO / MoS2samples for the second experiment according to one embodiment of the present disclosure. FIG. 35A is a plot illustrating P-E loops of C-BTO. FIG. 35B is a plot illustrating 1ML-MoS2 / C-BTO / 1ML-MoS2. FIG. 35C is a plot illustrating 2ML-MoS2 / C- BTO / 2ML-MoS2.

[0051] FIGs. 36A-36C are plots illustrating temperature-dependent P-E loops of the C-BTO and MoS2 / C-BTO / MoS2 samples for each of the first and second experiments according to one embodiment of the present disclosure. FIG. 36A is a plot illustrating P-E loops of C-BTO. FIG. 36B is a plot illustrating 1ML-MoS2 / C-BTO / 1ML- MoS2. FIG.36C is a plot illustrating 2ML-MoS2 / C-BTO / 2ML-MoS2.

[0052] FIGs. 37A-37C illustrate aspects of a 2ML-MoS2 / C-BTO / 2ML- MoS2array according to one embodiment of the present disclosure. FIG.37A is a photograph and light microscope image. FIG. 37B is a plot illustrating P-E loops of 2ML-MoS2 / C- BTO / 2ML-MoS2 in an array. FIG.7C is a Pm histogram of the 2ML-MoS2 / BTO / 2ML-MoS2 heterostructures in the array.

[0053] FIG.38 is a schematic diagram of a fabrication configuration according to one embodiment of the present disclosure.

[0054] FIG.39 is a schematic diagram of a testing configuration according to one embodiment of the present disclosure.CT

[0055] FIG.40 is a flow chart of a method according to one embodiment of the present disclosure.

[0056] FIG. 41 is a flow chart of another method according to one embodiment of the present disclosure.

[0057] FIG. 42 is a schematic diagram of a configuration of a computer system 4200 according to one embodiment of the present disclosure.

[0058] FIG.43 is a schematic diagram of a configuration of a remote or user computing device according to one embodiment of the present disclosure.

[0059] Corresponding reference characters indicate corresponding parts throughout the drawings. There are shown in the drawings arrangements that are presently discussed, it being understood, however, that the present embodiments are not limited to the precise arrangements and are instrumentalities shown. While multiple embodiments are disclosed, still other embodiments of the present disclosure will become apparent to those skilled in the art from the following detailed description, which shows and describes illustrative aspects of the disclosure. As will be realized, the invention is capable of modifications in various aspects, all without departing from the spirit and scope of the present disclosure. Accordingly, the drawings and detailed description are to be regarded as illustrative in nature and not restrictive. DETAILED DESCRIPTION

[0060] The following detailed description illustrates embodiments of the present disclosure by way of example and not by way of limitation. The description enables one skilled in the art to make and use the disclosure, describes several embodiments, adaptations, variations, alternatives, and uses of the disclosure, including what is presently believed to be the best mode of carrying out the disclosure.

[0061] Described herein is a new approach to, and systems, devices, and methods for, fabricating and / or manufacturing capacitors with nearly zero energy loss and ultrahigh energy density by sandwiching an atomically thin two-dimensional (2D) layer between a freestanding ferroelectric nanomembrane. More specifically, described herein are systems, devices, and methods for (i) fabricating capacitor layers and / or capacitor devicesCT with high dielectric constant, high energy storage, and low energy loss; (ii) precisely controlling the relaxation time of polarization, and (iii) fabricating highly efficient and vertically heterointegrated MLCCs with crystalline (e.g., single crystalline, polycrystalline) ferroelectric materials without energy loss.

[0062] Capacitors with high energy density and low energy loss are important electronic components with a wide range of applications in electrical and electronic circuits because of energy storage, timing components in oscillators, signal coupling / decoupling, frequency tuning, and power factor correction. Dielectric materials with a high dielectric constant are used in capacitors. However, their dielectric constant is much lower than that of ferroelectric material such as BaTiO3, which has a dielectric constant of 1,500, aspects of which are shown in diagram 100 of FIG.1A. Ferroelectric materials have high dielectric constant, but they have a remnant polarization, aspects of which are shown in diagram 120 of FIG. 1B, which causes significant energy loss and reduces efficiency, illustrated in FIG.1B by quantities including energy storage (Ue) 122 and energy loss (Uloss) 124. Many studies to reduce the energy loss of ferroelectric materials have been conducted, and aspects and characteristics of materials and / or devices used in and / or resulting from these studies are shown table 140 shown in FIG.1C, including: (i) methods used (e.g., component engineering, doping engineering, thick film stacking method, and the method disclosed herein); (ii) crystal quality; (iii) energy density; (iv) energy loss; (v) efficiency; and (vi) size. Doping engineering and composition engineering reduce the crystallinity of the ferroelectric layer and decrease the dielectric constant. The thin film stacking approach does not affect the crystallinity of the ferroelectric layer but reduces the total energy storage by stacking relatively low dielectric constant and thin layers. Ultimately, the development of materials with high dielectric constant, high energy storage, and low energy loss is necessary.

[0063] Shifting the focus to multilayer ceramic capacitors (MLCCs), MLCCs offer high stability and low losses for resonant circuit applications and high volumetric efficiency for buffer, by-pass, and coupling applications. The key factors for the development of highly volumetric efficient and high capacitance MLCCs are (i) using dielectric materials with high dielectric permittivity, (ii) stacking more dielectric layers, (iii) increasing the overlapped area of internal electrodes, and (iv) reducing the thickness of the dielectric layer. Ferroelectric (FE) materials, including BaTiO3, are outstanding candidates for MLCCs because of their high dielectric constant, aspects of which are shown in plot 160CT of FIG. 1D. However, since the energy loss of FE materials is large, many researchers fabricate MLCCs based on polycrystalline FE nanoparticle agglomerated films. Unfortunately, this approach significantly decreases the dielectric constant owing to low crystallinity and multi-grains.

[0064] Dielectric / ferroelectric / dielectric (DE / FE / DE) vertical heterostructures based on the Landau theory have attracted attention as an innovative approach to reducing energy loss in (e.g., single-crystal) ferroelectric materials. However, it is difficult to fabricate MLCCs using this method because the large lattice mismatch and high thermal expansion coefficient difference between DE, FE, and metal impede the crystal quality of FE material, aspects of which are shown in diagram 180 of FIG.1E. Considering these results, it is necessary to develop innovative device manufacturing technologies for highly efficient and vertically heterointegrated MLCC with (e.g., single) crystalline FE materials without energy loss.

[0065] In one example embodiment shown in FIG. 2A, configuration 200 illustrates a highly efficient capacitor layer configuration, and a highly efficient capacitor 202 fabricated by transferring 2D layers 204 and 206 on top and bottom, respectively, of a ferroelectric nanomembrane 208, lifted off from the host substrate. The configuration shown in FIG.2A also includes an electrode 210 of capacitor 202 and a substrate 212 upon which capacitor 202 is mounted. For 2D layers, materials including but not limited to semimetals (e.g., 2D semimetals), insulators (e.g., 2D insulators), and / or magnetic materials (e.g., 2D magnetic materials) may be implemented. For example, a user can choose the type of 2D layer according to their specific situation, with options including but not limited to 2D semimetals such as graphene, 2D insulators such as hexagonal Boron Nitride (h-BN), and 2D magnetic materials such as Fe3GeTe2. Additionally, transition metal dichalcogenides (TMDs) and transition metal oxides (TMOs), and so on, may be implemented as materials for 2D layers. The amount of 2D layers may range anywhere from 0 to 10,000 layers. This approach provides higher energy storage than the conventional approaches that include the dielectric / ferroelectric / dielectric layer structure, as the reduction in the dielectric constant and polarization density is much smaller than that of the ferroelectric layer, aspects of which are illustrated in plot 220 shown in FIG.2B.CT

[0066] With reference to FIGS. 1A-1C, a high-efficiency capacitor layer with unprecedented energy storage characteristics as described herein serves as a key component material integrated into electronic components and circuits, serving various fields such as biology, artificial intelligence (AI), military, and neuromorphic systems. Moreover, high-efficiency capacitor layers enable the implementation of high-efficiency computing devices and circuits by integrating into FETs. Capacitor layers with high energy storage and low energy loss also serve as a key component for implementing high-frequency, high- power, and miniaturized electronics integrated into various electronic components and circuits. FIG.2C is a diagram illustrating example applications of high-efficiency capacitor layers including but not limited to capacitors 242 (e.g., including high energy storage and band pass filters), dielectric layers 244 (e.g., for MOSFETs), piezoelectric applications 246 such as nanogenerators and sensors, and electromechanical applications 248 such as transducers and stimulators.

[0067] With reference to FIGS. 1D and 1E, described herein is a new approach to manufacturing MLCC with nearly zero energy loss and ultrahigh energy density by sandwiching materials between a freestanding FE and DE nanomembrane, aspects of which are shown in FIG. 3. By way of the layer transfer techniques and / or other methods 302 (e.g., vertical heterointegration) and lift-off techniques 304 described herein, capacitor devices 306 are fabricated by sequentially stacking (e.g., single) crystalline FE and DE materials produced by the lift-off and layer transfer methods. After fabricating the DE / FE / DE structure, electrodes can be deposited, or freestanding metal can be transferred. There are no restrictions on the formation method of the electrode. Lift-off technologies 304 include all methods that can produce freestanding nanomembranes, such as mechanical lift-off, mechanical exfoliation, chemical lift-off (e.g., freestanding film), optical lift-off, and 2D layer-assisted layer transfer (2DLT). FE and DE materials may include 2D layers as well as 3D materials.2D layers include from 1 layer to 10,000 layers. The number of layers in the Metal / DE / FE / DE / metal structure can be stacked from 1 layer to 1,000,000 layers. For example, multiple arrangements / combinations of layers such as 204, 206, and / or 208 shown in FIG. 2A may be implemented for a given capacitor device 306. In one embodiment, capacitor device 306 may include a DE / FE / DE configuration 308, an electrode configuration 310, a plating configuration 312, a termination configuration 314, and plating configuration 316, as shown in FIG.3.CT

[0068] As shown in diagram 400 of FIG.4, MLCCs have been utilized for various applications such as displays (e.g., televisions), personal computers, communications, integrated circuits, satellite and aerospace, mobile phones, and electric vehicles. Interface engineering, electrochemical kinetics and thermodynamics, micro / nanostructure control, defect engineering, and / or tailored composition and doping are utilized to manufacture MLCCs that have characteristics including but not limited to high voltage stability and output, tolerance to high frequency, large volumetric capacitance, high thermal stability, and suppressed IR degradation. Furthermore, with the advent of the Internet of Things (IoT), their application has become much broader. The high-efficiency MLCC and its manufacturing method described herein is applicable to these industries and key electronics in next-generation high-frequency and high-power devices.

[0069] Managing high energy density has become increasingly important in applications ranging from electric power systems to portable electronic devices. Electrostatic capacitors have been widely used for high-energy storage and release due to their ultrafast charge and discharge rate, but their performance is limited by the low maximum polarization (Pm) of conventional dielectric materials. In contrast, ferroelectric materials such as HfO2, ZrO2, and BaTiO3 (BTO) can achieve higher maximum polarization due to their higher electric susceptibilities related to dielectric constants. However, their high remnant polarization (Pr) limits the effectiveness of energy storage and release during the discharging process. To overcome this limitation, relaxor-ferroelectric materials have been studied for their ability to achieve high energy densities with low remnant polarization. Through compositional and defect design, nanodomains have been introduced into ferroelectric materials to realize relaxor ferroelectricity, offering a potential avenue for developing high-performance electrostatic capacitors. These methodologies lead to a redistribution of domain walls that can serve as effective relaxor-like defects to suppress the formation of large polar domains and reduce the remnant polarization. Although recent advances have shown great promise in realizing relaxor ferroelectricity by inducing nanodomains in ferroelectric materials through composition and defect engineering, these approaches result in the loss of crystallinity, leading to reduced permittivity and sacrificing the maximum polarization. Moreover, some approaches have shown a restriction in achieving a high polarization saturation limit, resulting in polarization saturation at a low electric field and leading to low energy density (Ue), despite substantial breakthroughCT otherwise. These limitations highlight the need for a different approach that can supplement previous methods and lead to the development of electrostatic capacitors with extremely high energy density.

[0070] The present disclosure further describes herein a strategy for precise control of the relaxation time of polarization that maintains minimal energy loss by using monolayer 2D materials produced by a layer splitting technique. In some embodiments, this is achieved by using artificially designed 2D / crystalline (e.g., single crystalline) 3D / 2D (2D / C-3D / 2D) heterostructures. The layer transfer technique described herein is used to produce freestanding crystalline (e.g., single-crystalline) BaTiO3 (C-BTO) where both interfaces can be manipulated, and 2D / C-3D / 2D heterostructures are formed by addition of various 2D materials. Unlike previous approaches that deteriorate ferroelectric materials by involving structural changes, the approach described herein preserves the crystalline(e.g., single-crystal) nature of the BTO. Instead, as described herein, a C-BTO layer is sandwiched with 2D materials in the form of a freestanding membrane, such that a Maxwell-Wagner (MW) effect, a relaxation by charge accumulation at heterogeneous interfaces, takes place at the interfaces to change the relaxation time. Thickness control of 2D materials with atomic precision by a layer-resolved splitting technique enables minimal energy loss and tangent delta (tan δ), a dielectric loss due to electrical phase difference, while controlling relaxation time. Using this strategy, the remnant polarization of ferroelectric materials can be effectively suppressed while maintaining the maximum polarization. As shown in the figures and as described herein, this allows for an energy density of 191.7 J / cm3with an efficiency of over 90%. The approach described herein enhances the performance of dielectric materials and other related applications that require high-energy storage systems.

[0071] Disclosed herein are systems, devices, and methods to precisely control relaxation time using 2D materials while minimizing energy loss in artificially designed 2D / 3D / 2D heterostructures, while preserving the crystallinity of ferroelectric 3D materials. In some embodiments, and as described above and in greater detail herein, this approach has led to the achievement of an energy density of 191.7 J / cm3, much higher than prior achieved energy densities, coupled with an efficiency over 90%. This precise control over relaxation time has significant applicability for a wide array of applications, including but not limited to developing highly efficient energy storage systems, and represents a significant improvement over conventional energy storage systems.CT

[0072] Additionally, disclosed herein are systems, devices, and methods for fabricating and / or manufacturing capacitors with nearly zero energy loss and ultrahigh energy density by sandwiching atomically thin 2D layers between a freestanding ferroelectric nanomembrane and the outer electrodes. In some embodiments, a highly efficient capacitor layer is fabricated by transferring 2D layers onto a top surface and a bottom surface of the ferroelectric nanomembrane by lifting the 2D layers off from host substrates.

[0073] The disclosed fabrication methods provide for vertical heterointegration of several components that together overcome several limitations of previous fabrication methods to produce a capacitor characterized by high energy intensity and low energy loss. The disclosed fabrication methods, described in additional detail herein, also include exfoliating a thin (e.g., single) 3D crystalline freestanding ferroelectric nanomembrane from a substrate and transferring thin 2D semiconductor layers onto the upper and lower faces of the 3D ferroelectric nanomembrane. In some embodiments, the 3D layer may be fabricated as a freestanding thin film independent of any substrates, such as films fabricated via powder sintering in connection with conventional MLCC fabrication. The depth of the 2D layers, which may vary between 1 to 10,000 molecules, minimizes the reduction of the dielectric constant of the ferroelectric layer, thus preserving the high energy density of the ferroelectric material. Further, the complex and sophisticated electrical interactions including, but not limited to dielectric relaxation at the 2D layer / ferroelectric nanomembrane interfaces effectively reduce the energy loss of the capacitor, as described in additional detail herein. The disclosed capacitors and methods of fabrication provide for potentially significant enhancements in various electrical devices requiring capacitor layers including, but not limited to, field effect transistors (FETs), energy storage devices, piezoelectric devices, electromechanical devices, and the like.

[0074] Among the various aspects of the present disclosure is the provision of a capacitor device or layer that includes a 3D single ferroelectric crystal layer sandwiched between upper and lower 2D monolayers of a semiconductor material. In one aspect, a capacitor device or layer is disclosed that includes a 3D layer with opposed upper and lower faces, as well as an upper 2D layer and a lower 2D layer positioned over the upper and lower faces of the 3D layer, respectively. The 3D layer includes a single crystal of a ferroelectric material. The upper and lower 2D layers each include a semiconductor material. In some aspects, the ferroelectric material is a freestanding single crystal. In some aspects, theCT ferroelectric material includes crystalline BTO (BaTiO3). In some aspects, the ferroelectric material includes a thickness ranging from about 25 nm to about 50 nm. In some aspects, the ferroelectric material has a thickness of about 30 nm. In other aspects, the ferroelectric material includes a thickness ranging from about 200 nm to about 5 μm. In some aspects, the upper and lower 2D layers are freestanding membranes. In some aspects, the upper and lower 2D layers each have a layer thickness ranging from 1 monolayer (ML) to about 1000 ML. In some aspects, the upper and lower 2D layers each have a layer thickness or 1 monolayer (ML) or 2 ML. In some aspects, the upper and lower 2D layers each have a layer thickness of about 2 ML. In some aspects, the upper and lower 2D layers each comprise MoS2. In some aspects, the upper and lower 2D layers are positioned over the upper and lower faces of the 3D layer in a weakly bonded interface. In some aspects, the upper and lower 2D layers are positioned over the upper and lower faces of the 3D layer in a weakly bonded interface with an average gap ranging from about 0.1 nm to about 2 nm. In some aspects, the upper and lower 2D layers are positioned over the upper and lower faces of the 3D layer in a weakly bonded interface with an average gap of about 0.8 nm. In some aspects, the capacitor device or layer is configured to perform at an energy density of at least about 190 J / cm3 and an efficiency of at least about 90%. In another aspect, a method of fabricating the capacitor device or layer described above that includes growing first and second sacrificial layers (1S and 2S) on first and second substrates, respectively; growing upper and lower 2D layers (2DU and 2DL) on the first and second sacrificial layers to form 2DU / 1S and 2DL / 2S structures on the first and second substrates, respectively; placing (e.g., depositing) first and second handling layers (1H and 2H) over the 2DU and 2DL of the 2DU / 1S and 2DL / 2S structures, respectively, to form 1H / 2DU / 1S and 2H / 2DL / 2S structures on the first and second substrates, respectively; etching the 1S and 2S layers to release a 1H / 2DU structure and a 2H / 2DL structure from the first and second substrates, respectively; depositing a third sacrificial layer (3S) on a growth substrate (which in some embodiments may be an epitaxial growth substrate); growing (which in some embodiments may include epitaxially growing) a single crystal of a 3D ferromagnetic material (3D) on the first sacrificial layer to form a 3D / 3S structure on the (e.g., epitaxial) substrate; depositing a third handling layer (3H) over the single crystal of the ferromagnetic material to form a 3H / 3D / 3S structure on the (e.g., epitaxial) substrate; etching the third sacrificial layer to separate a 3H / 3D structure from the (e.g., epitaxial) substrate; scooping the 3H / 3D structure onto a fourth handling layer (4H) to form a freestanding 4H / 3H / 3D structure; contacting an exposedCT ferromagnetic crystal surface of the 4H / 3H / 3D structure with an exposed lower 2D surface of the 2L / 2DL structure to form a 2L / 2DL / 3D / 3H / 4H structure; etching the first and fourth handling layers of the 2L / 2DL / 3D / 3H structure and contacting the exposed surface of the lower 2D layer with a target substrate (TS) to form a 3H / 3D / 2DL / TS structure; etching the third handling layer and contacting the exposed ferromagnetic crystal surface of the resulting 3D / 2DL / TS structure with the exposed upper 2D layer of the 2DU / 1S structure to form a 1S / 2DU / 3D / 2DL / TS structure; etching the first handling layer to form the capacitor device or layer including a 2DU / 3D / 2DL / TS structure. In some aspects, the first and second sacrificial layers comprise SiO2; the first and second substrates comprise Si; the upper and lower 2D layers comprise MoS2; the first and second handling layers comprise PMMA; the third sacrificial layer includes Sr3AlO6(SAO); the (e.g., epitaxial) substrate includes SrTiO3(100) (STO); the 3D ferromagnetic material includes BTO; the third handling layer includes Ni; and the fourth handling layer includes PDMS.

[0075] As referred to herein, the “first experiment” generally relates to MLCCs, including techniques and methods for the fabrication thereof, and the “second experiment” generally relates to high-efficiency capacitor layers with 2D / 3D structure, including techniques and methods for the fabrication thereof. In some embodiments, certain techniques and methods associated with the “second experiment” are utilized for fabrication of highly efficient MLCCs in connection with the “first experiment.” In some aspects, the MLCCs of the “first experiment” may be considered as an implementation and / or application of the techniques and methods of the “second experiment.” For example, and without limitation, for MLCC 2D layers, materials including but not limited to 2D semimetals, 2D insulators, and / or 2D magnetic materials may be implemented.

[0076] Additional description of the disclosed system, devices, and methods are provided below. The following non-limiting examples are provided to further illustrate the present disclosure. It should be appreciated by those of skill in the art that the techniques disclosed in the examples that follow represent approaches the inventors have found function well in the practice of the present disclosure, and thus can be considered to constitute examples of modes for its practice. However, those of skill in the art should, in light of the present disclosure, appreciate that many changes can be made in the specific embodiments that are disclosed and still obtain a like or similar result without departing from the spirit and scope of the present disclosure.CT

[0077] FIGs. 5A-37C and their accompanying descriptions show and describe aspects of high energy density in 2D / 3D / 2D heterostructures that combine low relaxation time and low energy loss in connection with first and second experiments that were performed and are described herein.

[0078] FIGs. 5A-5D and 6A-6D illustrate management of spontaneous polarization via Miller model inspired from classic Debye relaxation, where FIGs. 5A-5D illustrate results of the first experiment, and FIGS. 6A-6D illustrate results of the second experiment. FIGs. 5A and 6A each illustrate via diagrams 500 and 600, respectively, polarizability vs. ωτ curve of the Miller model. FIGs.5B and 6B each illustrate via diagrams 520 and 620, respectively, a summary of the conductivity vs. dielectric constant curve of several 2D materials. FIGs.5C and 6C each illustrate via diagrams 540 and 640, respectively, dielectric Cole-Cole plots. FIGs. 5D and 6D each illustrate via diagrams 560 and 660, respectively, Tan δ vs. frequency curves of the C-BTO, 2D / C-3D / 2D, and 3D / C-3D / 3D structures.

[0079] FIGs. 7A-7E illustrate polarization of the C-BTO, 3D / 3D / 3D, and 2D / 3D / 2D heterostructures for each of the first and second experiments. FIG.7A illustrates plot 700 of a P-E loop of C-BTO. Plot 720 of FIG.7B illustrates a comparison of P-E loops of Al2O3 / C-BTO / Al2O3with strongly and weakly bonded interfaces. Plot 740 of FIG. 7C illustrates a P-E loop of the 2D / 3D / 2D heterostructure. The P-E loops were measured at 10 kHz. Plot 760 of FIG.7D illustrates Pm- Pr. Plot 780 of FIG.7E illustrates Pm / Pr calculated from the P-E loops.

[0080] FIGs. 8A-8E and 9A-9E illustrate atomic-scale polarization distribution and additional electrical performance under bias, where FIGs. 8A-8E illustrate results of the first experiment, and FIGs.9A-9E illustrate results of the second experiment. FIGs.8A and 9A each illustrate a STEM-HAADF image 800 and 900, respectively (portion A, left, in each of FIGs.8A and 9A) and an iDPC image 802 and 902, respectively (portion B, right, in each of FIGs.8A and 9A) of 2ML-MoS2 / C-BTO / 2ML-MoS2. Separation between the MoS2and BTO and interface roughness of the BTO are visible. FIGs. 8B and 9B each illustrate in plots 820 and 920, respectively, a P-E loop of the C-BTO, 2ML-MoS2 / C- BTO / 2ML-MoS2, and 2ML-MoS2 / C-BTO / 2ML-MoS2 after mechanically exfoliating the MoS2layers. FIGs.8C, 9C and 8D, 9D illustrate dielectric Cole-Cole plots, including plotsCT 840 and 940 in FIGs.8C, 9C, respectively, for C-BTO, and plots 860 and 960 in FIGs.8D, 9D, respectively, for 2ML-MoS2 / C-BTO / 2ML-MoS2, under DC bias from 0 to 5 MV / cm. FIGs.8E and 9E each illustrate respective plots 880 and 980 showing the ωτ under electric field of C-BTO, 1ML-MoS2 / C-BTO / 1ML-MoS2, and 2ML-MoS2 / C-BTO / 2ML-MoS2.

[0081] FIGs.10A-10F and 11A-11D illustrate energy storage performance of C-BTO and MoS2 / C-BTO / MoS2 with respect to the number of MoS2 layers, where FIGs. 10A-10F illustrate results of the first experiment, and FIGs.11A-11D illustrate results of the second experiment. FIGs. 10A and 11A each illustrate respective plots 1000 and 1100 for two-parameter Weibull distribution analysis of the characteristic breakdown fields and FIGs. 10B and 11B each illustrate respective plots 1010 and 1110 for voltage-dependent energy density and efficiency of the C-BTO and MoS2 / C-BTO / MoS2heterostructures. FIGs. 10C and 11C each illustrate respective plots 1020 and 1120 for temperature-dependence of energy densities and efficiencies at the temperature range from 250 to 400K. Also illustrated are plots for P-E loops of C-BTO (FIGs.10D and 11D), 1ML-MoS2 / C-BTO / 1ML-MoS2(FIG. 10E), and 2ML-MoS2 / C-BTO / 2ML-MoS2(FIG. 10F) at temperatures ranging from 250 to 400K. FIG.10D shows plot 1030, FIG.10E shows plot 1040, and FIG.10F shows plot 1050. FIG.11D shows plot 1130.

[0082] FIGs. 12A and 12B illustrate atomic-force microscopy (AFM) images of the as-grown BTO used in the first and second experiments. FIG.12A illustrates plan-view 1200 and FIG.12B illustrates three-dimensional AFM image 1220 of the as-grown BTO.

[0083] FIG. 13 illustrates a plot 1300 of an XRD rocking curve of the as- grown BTO used in the first and second experiments, and, more specifically, a theta-2theta XRD rocking curve of the as-grown BTO. The full width at half maximum value of BTO was calculated to be ~0.2°.

[0084] FIG. 14 illustrates electron back-scattering diffraction (EBSD) mapping 1400 of the as-grown BTO, specifically plan-view EBSD mapping (scale = 5 μm) of the as-grown C-BTO used in the first and second experiments. Only (001) plane is observed at the surface, indicating the C-BTO was grown with single-crystalline.CT

[0085] FIGs.15 and 16 each illustrate a capacitance vs. voltage (CV) curve of the C-BTO, where FIG.15 includes plot 1500 showing results of the first experiment and FIG.16 includes plot 1600 showing results of the second experiment. Each plot 1500, 1600 illustrates a CV curve and dielectric constant calculated from capacitance of the Au / C- BTO / Au structure at 10 kHz.

[0086] FIG.17 illustrates a 2D / C-BTO / 2D fabrication process. FIG.17 is a schematic illustration 1700 of 14 steps (Step 1 through Step 14) of the fabrication process for 2D / C-BTO / 2D structure in each of the first and second experiments. In this process, 1ML-MoS2 was used as an example. (Step 1) the single-domain MoS2 was grown onto an SiO2 / Si substrate via chemical vapor deposition. (Step 2) Poly(methyl methacrylate) (PMMA) was placed on the MoS2layer as a handling layer. (Step 3) SiO2sacrificial layer has been etched using buffered oxide etchant (BOE). (Step 4) the PMMA / MoS2 layer was rinsed by using deionized (DI) water. (Step 5) To prepare the freestanding BTO nanomembrane, the BTO / SAO was grown onto STO and (Step 6) deposited an Ni handling layer by using DC plasma for 12 minutes in physical vapor deposition (PVD). (Step 7) The sample is left to float onto DI water for 6 hours to etch the SAO sacrificial layer. (Step 8) the freestanding Ni / BTO layer was scooped onto the Polydimethylsiloxane (PDMS) and dried overnight. (Step 9) By using standard wet transfer, PMMA / MoS2layers were formed on the BTO surface. (Step 10) the PMMA layer was etched into acetone at 40°C for 30 minutes. The PDMS handling layer is automatically detached from Ni / BTO. (Step 11) For the 2ML- MoS2 / C-BTO / 2ML-MoS2, steps 2 to 4 were repeatedly performed, then the layer transfer method was employed to transfer another PMMA / MoS2 layer onto the MoS2 / BTO / Ni / PDMA surface. The freestanding Ni / BTO / MoS2 layer was scooped onto the target substrate and dried overnight. (Step 12). To etch the Ni handling layer, the sample was dipped into FeCl3solution for 1 minute. (Step 13) For the 2D / C-BTO / 2D sandwich structure, the PMMA / MoS2 layer was transferred onto the BTO surface. (Step 14) PMMA layer has been etched as in Step 10.

[0087] FIG. 18 illustrates a strongly chemically-bonded 3D / C-BTO / 3D fabrication process including steps 1-9 (Step 1 through Step 9). FIG. 18 is a schematic illustration 1800 of the fabrication process for a 3D / C-BTO / 3D structure with a strongly chemically bonded interface used for each of the first and second experiments. (Step 1) to prepare the freestanding BTO nanomembrane, the BTO / SAO was grown onto STO and (StepCT 2) the 3-nm thick Al2O3was deposited by using atomic layer deposition (ALD) to form the chemical bonded interface (58). (Step 3) Ni handling layer was deposited using DC plasma for 12 minutes in PVD. (Step 4) The sample has been left to float onto DI water for 6 hours to etch the SAO sacrificial layer. (Step 5) the freestanding Ni / Al2O3 / BTO layer was scooped onto the cover glass and dried overnight. Thereafter, the Al2O3was deposited with a thickness of 3 nm using ALD at 175°C. (Step 6) the Al2O3 / BTO / Al2O3 / Ni layer was exfoliated from the glass into acetone. (Step 7) the freestanding layer was scooped onto the target substrate and dried overnight. (Step 8) To etch the Ni handling layer, the sample was dipped into FeC13 solution for 1 minute. (Step 9) For cleaning, the sample was rinsed in acetone at 40 °C for 30 minutes.

[0088] FIG. 19 illustrates a weakly bonded 3D / C-BTO / 3D fabrication process including steps 1-15 (Step 1 through Step 15). FIG. 19 is a schematic illustration 1900 of the fabrication process for 3D / C-BTO / 3D structure without strong chemical bonds at the interface used for each of the first and second experiments. (Step 1) the 3-nm thick Al2O3was deposited on SiO2 / Si substrate by ALD. (Step 2) Ni handling layer was deposited using DC plasma for 12 minutes in PVD on the top of the Al2O3. To prepare the freestanding Al2O3 nanomembrane, the SiO2 layer was etched onto BOE and (Step 4) immediately rinsed the Ni / Al2O3freestanding layer in DI water. (Step 5) the freestanding layer was transferred onto the target substrate and dried it overnight. (Step 6) To etch the Ni handling layer, the sample was dipped into FeCl3 solution for 1 minute. (Step 7) the sample was rinsed in acetone at 40°C for 30 minutes. (Step 8) To prepare the freestanding BTO nanomembrane, Ni was deposited on the surface of the BTO for 12 minutes. (Step 9) the SAO sacrificial layer was etched in DI water for 6 hours and (Step 10) transferred to the surface of the Al2O3. (Step 11) Thereafter, the Ni was etched and (Step 12) the sample was rinsed. The formation process of top Al2O3(Step 13 - Step 15) used the same method as the bottom Al2O3(Step 5 - Step 7). During the process, any additional thermal annealing process was avoided, which would lead to stronger chemical bonds at the interface.

[0089] FIG. 20 illustrates a Cole-Cole plot 2000 for each of the first and second experiments. FIG.20 is a schematic illustration of the Cole-Cole plot 2000 where the ^ relaxation time is calculated as follows:^^^^ (^^) , where u is the distance from a particular data point in the Cole-Cole plot from point ^^, v is the distance of the same data point fromCT point ^^, and α is the distribution parameter that ranges from 0 to 1. For calculations, the relaxation time was calculated at 10 kHz.

[0090] FIG.21 is a plot 2100 illustrating P-E loops of C-BTO with different thicknesses for the first experiment. P-E loop of BTO according to the thickness: for the 10 nm C-BTO sample, a round shape indicates high electrical leakage, while 50 nm thick C- BTO exhibits substantial energy loss attributed to its large Pr. Considering these results, C- BTO with a thickness of 30 nm was selected for all other measurements.

[0091] FIGs. 22A and 22B illustrate an electronic structure of the 1ML- MoS2 / C-BTO / 1ML-MoS2heterostructure from density-functional theory (DFT) for each of the first and second experiments. FIG. 22A is a diagram 2200 illustrating an atomic configuration (top) and layer-projected density of states (bottom) across the ‘Au / lML- MoS2 / BaTiO3 / 1ML-MoS2 / Au’ heterostructure. Color legends: Au — orange, Mo — light purple, S — yellow, O — red, Ti — sky blue, Ba — dark blue. Red line shows the polarization-induced band bending within the BaTiO3 layer. FIG. 22B is a diagram 2220 illustrating laterally averaged charge density difference along the c-axis of the ‘Au / lML- MoS2 / BaTiO3 / 1ML-MoS2 / Au’ heterostructure. The shaded blue and green areas represent the interface regions of MoS2 / BaTiO3 and MoS2 / Au contacts, respectively.

[0092] FIGs. 23A and 23B illustrate an electronic structure of the 2ML- MoS2 / C-BTO / 2ML-MoS2heterostructure for each of the first and second experiments. FIG. 23A is a diagram 2300 illustrating an atomic configuration (top) and layer-projected density of states (bottom) across the ‘Au / 2ML-MoS2 / BaTiO3 / 2ML-MoS2 / Au’ heterostructure. Color legends: Au — orange, Mo — light purple, S — yellow, O — red, Ti — sky blue, Ba — dark blue. Red line shows the polarization-induced band bending within the BaTiO3layer. FIG. 23B is a diagram 2320 illustrating laterally averaged charge density difference along the c-axis (bottom) of the ‘Au / 2ML-MoS2 / BaTiO3 / 2ML-MoS2 / Au’ heterostructure. The shaded blue, orange, and green areas represent the interface regions of MoS2 / BaTiO3, MoS2 / MoS2, and MoS2 / Au contacts, respectively.

[0093] FIGs. 24 and 25 each illustrate a Dielectric Cole-Cole plot, where FIG.24 is a plot 2400 illustrating results of the first experiment and FIG.25 is a plot 2500 illustrating results of the second experiment. Dielectric Cole-Cole plots of the 2ML-MoS2 / C-CT BTO / 2ML-MoS2over the frequency range from 102to 106are shown for each. The ωτ and relaxation time are calculated to be 3.7 and 59.5 µs.

[0094] FIG. 26 illustrates high-angle annular dark field (HAADF) images 2600 of the 2ML-MoS2 / C-BTO / 2ML-MoS2for each of the first and second experiments, and specifically HAADF images of the 2ML-MoS2 / C-BTO / 2ML-MoS2obtained from several different regions of the sample. The average gap between BTO and MoS2 in the images is calculated to be 0.8 + / - 0.08 nm with a standard deviation of 0.45 in nine samples. This variability is related to the roughness visible at the BTO surface.

[0095] FIGs. 27A-27C and 28A-28C illustrate frequency dependent dielectric constant curves, where FIGs.27A-27C illustrate results of the first experiment, and FIGS. 28A-28C illustrate results of the second experiment. Frequency dependent real dielectric constant and imaginary dielectric constant curves of the C-BTO (plot 2700 in FIG. 27A, plot 2800 in FIG.28A), 1ML-MoS2 / C-BTO / 1ML-MoS2 (plot 2720 in FIG.27B, plot 2820 in FIG.28B), and 2ML-MoS2 / C-BTO / 2ML-MoS2(plot 2740 in FIG.27C, plot 2840 in FIG. 28C). Gaussian curves in 1ML-MoS2 / C-BTO / 1ML-MoS2and 2ML-MoS2 / C- BTO / 2ML-MoS2 are shifted with increasing the DC electric field, indicating the point shift in dielectric Cole-Cole plots.

[0096] FIGs.29 and 30 each illustrate a DC electric field dependent Cole- Cole plot, where FIG. 29 illustrates results of the first experiment and FIG. 30 illustrates results of the second experiment. Dielectric Cole-Cole plot of the MoS2 / C-BTO / MoS2 with respect to the DC electric field at the AC field of 100 mV at 10 kHz.

[0097] FIG. 31 is a plot 3100 illustrating a two-parameter Weibull distribution analysis of breakdown strengths for each of the first and second experiments. Two-parameter Weibull distribution analysis of breakdown strengths of the C-BTO, 1ML- MoS2 / C-BTO / 1ML-MoS2, and 2ML-MoS2 / C-BTO / 2ML MoS2. Ten different samples were investigated for each composition for the analysis.

[0098] FIGs.32A-32C illustrate leakage current densities of the C-BTO and MoS2 / C-BTO / MoS2for each of the first and second experiments. The leakage current density vs. electric field is shown for C-BTO (plot 3200 in FIG. 32A), 1ML-MoS2 / C-CT BT0 / 1ML-MoS2(plot 3220 in FIG.32B), and 2ML-MoS2 / C-BTO / 2ML-MoS2(plot 3240 in FIG.32C).

[0099] FIG.33 is a diagram 3300 illustrating comparative energy densities of different structural configurations for each of the first and second experiments. Specifically, a comparison of the energy densities of representative electrostatic capacitors in previous studies with the 2D / C-3D / 2D heterostructure-based capacitor described herein.

[0100] FIG. 34 illustrates frequency dependent energy storage performance of the 2ML-MoS2 / BTO / 2ML-MoS2for the first experiment. FIG.34 shows a plot 3400 of the P-E loop of the 2ML-MoS2 / BTO / 2ML-MoS2 sample with frequencies of 10, 5, 3, and 1 kHz.

[0101] FIGs. 35A-35C illustrate cyclic tests of the C-BTO and MoS2 / C- BTO / MoS2 samples for the second experiment. Shown are P-E loops of C-BTO (plot 3500 in FIG.35A), 1ML-MoS2 / C-BTO / 1ML-MoS2 (plot 3520 in FIG.35B), and 2ML-MoS2 / C- BTO / 2ML-MoS2(plot 3540 in FIG.35C) measured at 10 kHz regarding the charging-and- discharging cycle of 20 kHz.

[0102] FIGs.36A-36C illustrate temperature-dependent P-E loops of the C-BTO and MoS2 / C-BTO / MoS2 samples for each of the first and second experiments. Shown are P-E loops of C-BTO (plot 3600 in FIG. 36A), 1ML-MoS2 / C-BTO / 1ML-MoS2(plot 3620 in FIG. 36B), and 2ML-MoS2 / C-BTO / 2ML-MoS2 (plot 3640 in FIG. 36C) at temperatures ranging from 250 to 400K.

[0103] FIGs. 37A-37C illustrate aspects of a 2ML-MoS2 / C-BTO / 2ML- MoS2 array, including a photograph 3700 (FIG.37A, left portion “A”) and a light microscope image 3702 (FIG.37A, right portion “B”), and P-E loops of 2ML-MoS2 / C-BTO / 2ML-MoS2 (plot 3720 in FIG.37B) heterostructures in an array. Graph 3740 in FIG.37C illustrates a Pmhistogram of the 2ML-MoS2 / BTO / 2ML-MoS2heterostructures in the array, where the Pmvalues are calculated rounded to the nearest whole number.

[0104] Additional description and aspects of the disclosed system, devices, methods, and experiments are provided below. MW relaxation at 2D / 3D interfacesCT

[0105] The Miller model inspired by classic Debye relaxation provides a theoretical framework for controlling spontaneous polarization by manipulating the relaxation time (FIGs.5A, 6A). One approach for regulating the relaxation time involves the creation of heterostructures including two distinct materials, typically a ferroelectric material and a dielectric material, due to their disparities in electrical conductivity and permittivity. These heterostructures enable the accumulation of charge at the interfaces between the phases when subjected to an alternating electric field, a phenomenon known as the MW relaxation effect. This effect offers a means to influence and modulate the relaxation time within the heterostructures. However, effective modulation of the relaxation time has been difficult while conserving maximum polarization in conventional heterostructures through the MW effect for two reasons: (i) previous attempts mainly led to the deterioration of ferroelectricity, generating strain or creating multi-domain structures by the additional layers forming chemical bonds with the ferroelectric material; (ii) as the thickness increases due to the additional layers needed for the MW effect, this inevitably leads to additional energy loss and higher tan δ, which is closely associated with dielectric loss. These problems were circumvented herein through the use of 2D / C-3D / 2D heterostructures, formed using a layer transfer technique. A freestanding C-BTO of 30 nm thickness was first produced. The film is sufficiently high quality that only the (001) orientation was observed in electron back- scattering diffraction mapping. A variety of characterization techniques were used to show the C-BTO quality (FIGs.12A, 12B, 13, 14, 15, 16). A schematic representation of the 2D / C- BTO / 2D fabrication process is shown in FIG. 17. The freestanding nature of these C-BTO nanomembranes then allows for coating both sides with other materials to produce artificial heterostructures.

[0106] It was anticipated that the choice of 2D materials for the coating layer would induce an efficient MW effect while avoiding substantial energy loss, because of both the atomically thin nature of the 2D layers and the lack of strong chemical bonding at the heterointerfaces. To aid in 2D materials choice, a summary of the conductivity vs. dielectric constant of representative 2D materials is shown in FIGs.5B, 6B. The higher the dielectric constant and the lower the conductivity, the stronger MW relaxation induced at the interface. From the 2D candidates, graphene (a 2D semimetal) was selected, MoS2 (a 2D semiconductor), and h-BN (a 2D insulator). Although some studies of MoS2have shown ferroelectricity due to structural deformation, previous measurements of the presentCT disclosure of devices that included similar MoS2did not show such behavior, no ferroelectric behavior of the MoS2 layer was expected or included in the analysis herein. Selection of these materials is based on anticipation of the possibility of observing diverse variations in relaxation time and tan δ within different artificial heterostructures. For comparison purposes, two different heterostructures of 3 nm Al2O3 / C-BTO / Al2O3were fabricated. One heterostructure was formed by atomic layer deposition, for which strong chemically bonded BTO / Al2O3 interfaces were anticipated (FIG.18). The other heterostructure was formed by layer transfer without an annealing process and was anticipated to lack strong chemically bonded interfaces (FIG.19).

[0107] After fabrication of this set of heterostructures, the dielectric Cole- Cole plot at the frequency range 102- 106Hz (FIGs.5C, 6C) was measured and the relaxation times at 10 kHz were calculated (FIG.20). In the bare freestanding C-BTO nanomembranes, a value of ~0.09 for ωτ was obtained, which is defined as the product of angular frequency (ω) of 10 kHz and relaxation time (τ). The ωτ values of Al2O3 / C-BTO / Al2O3samples were calculated to be 0.95 and 16.4 for the strongly bonded and weakly bonded samples, respectively. Some internal strain in the Al2O3 and C-BTO may be present and expected, due to the difference in thermal expansion coefficients, and any such effects are included in the relaxation times. This result indicates that the weakly bonded and discontinuous interface provides a higher relaxation time than that of a strongly chemically bonded interface. However, the tan δ values of the strongly and weakly bonded Al2O3 / C-BTO / Al2O3 were measured to be 7.4 x 10-3and 31.0 x 10-3at 10 kHz, which are much higher than those of bare C-BTO (FIGs. 5D, 6D). Substantial energy loss and decrease in the maximum polarization density based on these values were expected. In contrast, the heterostructures fabricated using layer-resolved splitting of 2D materials, enabling thickness control of 2D materials at atomic precision, yielded lower tan δ and ωτ values. One monolayer h-BN (1ML- h-BN) / C-BTO / 1ML-h-BN had a ωτ = 9.5 and tan δ = 3.7 x 10-3at 10 kHz. More effective control of relaxation time is clearly achievable using h-BN compared to conventional dielectric materials such as Al2O3. Additionally, the lower tan δ with h-BN suggests the potential for relatively smaller energy loss using 2D materials. The benefits of the 2D material were attributed to be its atomic thickness, compared to the relatively large Al2O3 layer thickness. To further explore this hypothesis, the experiment was repeated by creating an artificial heterostructure using MoS2, known for its lower carrier density and dielectricCT constant, as well as graphene, which exhibits much lower values. The one monolayer MoS2(1ML-MoS2) / C-BTO / 1ML-MoS2 heterostructure had a ωτ value of 1.2 and a tan δ of 1.61 x 10-3, while the one monolayer graphene (1ML-Gr) / C-BTO / 1ML-Gr heterostructure had a ωτ value of 0.2 and an even lower tan δ of 7.6 x 10-5. Unlike the 1ML-h-BN / C-BTO / 1ML-h- BN heterostructure, which displayed two distinct peaks indicating the presence of MW relaxation, the 1ML-MoS2 / C-BTO / 1ML-MoS2 heterostructure did not exhibit clear peak separation, instead displaying an asymmetric Gaussian distribution. This still proves the presence of MW relaxation. However, the 1ML-Gr / C-BTO / 1ML-Gr heterostructure did not show similar behavior in the tan δ measurement despite its extremely low tan δ. These findings highlight the role of the 2D materials in influencing and modulating relaxation time and tan δ within the heterostructures. Polarization of artificial heterostructures

[0108] It is expected that the large ωτ values caused by the large relaxation time induce a strong reduction in the remnant polarization. The polarization-electric field (P- E) loop of the unmodified C-BTO and the strongly and weakly chemically bonded Al2O3 / C- BTO / Al2O3 heterostructures were measured, all at10 kHz (FIGs. 7A and 7B). 30-nm thick BTO was chosen because it has higher Pm, lower Pr, and lower electrical leakage than other thicknesses tested (FIG. 21). The maximum polarizations of both Al2O3 / C-BTO / Al2O3samples were dramatically decreased because of the tan δ. However, the remnant polarization of the strongly bonded sample is much higher than the weakly bonded sample. These results agree with expectations, driven by the tan δ and relaxation time values. Nevertheless, the Al2O3 / C-BTO / Al2O3 with weakly bonded interfaces still provide low maximum polarization and thus poor energy storage performance, because of the high tan δ attributed to the thick nature of Al2O3.

[0109] Based on an understanding that relaxation time can be effectively controlled while minimizing tan δ, P-E loop measurements were conducted on the various 2D / C-BTO / 2D heterostructures (FIG. 7C). First, h-BN / C-BTO / h-BN structures were examined and a reduction in remnant polarization was observed. However, this reduction also led to a decrease in maximum polarization, resulting in a notable decline in energy storage density and efficiency. To mitigate the decrease in maximum polarization, MoS2 was employed, which possesses a higher conductivity than h-BN and is thus expected toCT minimize the MW relaxation. Indeed, when C-BTO was coated with 1ML-MoS2, a smaller decrease in maximum polarization was observed. However, an insufficient decrease in remnant polarization, leading to energy loss was also noted. This insufficient decrease is attributed to the increase in conductivity of 1ML-MoS2, in which the Fermi level shift due to the metal contact through density functional theory calculations was confirmed (FIGs. 22A, 22B). Meanwhile, the successful suppression of the remnant polarization is observed in heterostructures using bilayer (2ML)-MoS2, formed by sequentially transferring 1ML- MoS2twice, and C-BTO. It is proposed that free electrons of the electrodes do not affect the MoS2 layer adjacent to the C-BTO, providing a sufficiently low conductivity to allow for screening of the dielectric polarization (FIGs. 23A, 23B). Heterostructures containing graphene, which has a smaller dielectric constant, were further investigated. However, due to its high charge density, it was not possible to induce an effective relaxation time delay. Instead, the P-E loop slightly decreased because of the small increase in the dielectric loss at the non-chemically bonded interface of the graphene / C-BTO. Such performance, with small remnant polarization and high maximum polarization, is attributed to several factors: (i) the artificial heterostructures do not sacrifice the crystallinity of single crystalline ferroelectric materials, unlike conventional heterostructures that experience lattice and thermal mismatch issues; (ii) the atomically thin 2D layers provide extremely low tan δ, preventing a high dielectric loss and decrease in the dielectric constant; and (iii) the weakly bonded interface facilitates a substantial increase in dielectric relaxation even when the layer is atomically thin, effectively decreasing the remnant polarization. Together, the small remnant polarization and large maximum polarization are expected to lead to high energy density and high efficiency. To analyze which of the artificial heterostructures are most suitable for high energy density (FIGs.7D and 7E), the maximum polarization is subtracted from the remnant polarization (Pm- Pr) - related to the energy density - and divide the maximum polarization by the remnant polarization (Pm / Pr) - related to the efficiency, according to the ωτ. Up to a ωτ value of 3.4, the Pm - Pr and Pm / Pr values increased, indicating improved energy density and efficiency. For ωτ > 3.4, even though Pm / Princreased, Pm- Prrapidly decreased. Considering these results, it is anticipated that the 2D / C-BTO / 2D heterostructures with an- around 3.4 (1ML-MoS2 / C-BTO / 1ML-MoS2 and 2ML-MoS2 / C-BTO / 2ML-MoS2) provide the largest energy storage system in the samples (Cole-Cole plot of 2ML-MoS2 / C- BTO / 2ML-MoS2; FIG.24).CT Atomic scale polarization distribution

[0110] To gain a more comprehensive understanding of polarization behavior in the artificially designed 2D / C-3D / 2D structures, additional electrical measurements were conducted and atomic-scale structural information for the most effective structure, MoS2 / C-BTO / MoS2. was obtained. FIG. 8A shows high-angle annular dark field (HAADF) and integrated differential phase contrast (iDPC) images of this sample measured by scanning transmission electron microscopy (STEM). The sample after hysteresis tests for 10 cycles under an electric field of -5 to 5 MV / cm at 10 kHz was characterized. The lattice spacings of the C-BTO in all samples to be about 0.409 nm was measured, corresponding to the (001) lattice plane of the BTO perovskite structure and indicating preferred growth along the

[0001] direction. HAADF and iDPC images clearly showed the gap between the lattice structures of the 2ML-MoS2and C-BTO and some interfacial roughness (further example images are shown in FIG. 26). Thus, structural discontinuity at the top and bottom surfaces of the C-BTO can work as a screener for dielectric polarization in the C-BTO crystal, leading to a relatively small remnant polarization. To further confirm the role of the 2D layer, the P- E curve after mechanically exfoliating both the top and bottom MoS2 layers from the 2ML- MoS2 / C-BTO / 2ML-MoS2 heterostructure was measured. The hysteresis after removing the MoS2layers is similar to that of bare C-BTO (see the comparison in FIG.8B), indicating that the pseudo-relaxor ferroelectric behavior exhibited by the 2D / 3D / 2D heterostructure is driven by charge compensation rather than relaxor ferroelectricity, and that the 2D layers did not directly affect the dipoles inside the C-BTO crystal, preserving the high polarization.

[0111] Another intriguing aspect of the artificial 2D / 3D / 2D heterostructure described herein is the observation that as the DC electric field increases, the polarization correspondingly increases, with the maximum polarization approaching that of C-BTO. This phenomenon indicates a strong correlation between the applied electric field and the relaxation time within the artificial heterostructure. The dielectric Cole-Cole plots of the C-BTO and 2ML-MoS2 / C-BTO / 2ML-MoS2samples at a DC electric field of 0 - 5 MV / cm are shown in FIGs. 8C, 9C and 8D, 9D, where the frequency-dependent dielectric constants are described in FIGS. 27A, 28A and 27B, 28B. In the C-BTO sample, the ωτ measured at 10 kHz is observed at the right side of the center of the semicircle regardless of the electric field. In contrast, the ωτ of 2ML-MoS2 / C-BTO / 2ML-MoS2 measured at 10 kHz were shifted to theright with increased field, indicating the increase in the relaxation time. The ωτ calculatedfrom dielectric Cole-Cole plot is summarized as a function of electric field for the C-BTO,CT 1ML-MoS2 / C-BTO / 1ML-MoS2, and 2ML-MoS2 / C-BTO / 2ML-MoS2 samples in FIGs. 8E, 9E. The DC field-dependent Cole-Cole plot of MoS2 / C-BTO / MoS2 is described in FIG. 29. With increasing field, the relaxation times of the 2D / C-3D / 2D become similar to that of the bare C-BTO. This result is attributed to the decrease in the accumulated charge by MW relaxation due to the electric field. This interplay between the electric field and relaxation time provides useful insights into the ferroelectric properties of the artificial 2D / 3D / 2D heterostructures. Performance MoS2 / C-BTO / MoS2

[0112] To investigate the complete energy storage performance of the C- BTO and MoS2 / C-BTO / MoS2 heterostructures, their statistical breakdown strengths (Eb) were measured via Weibull distribution fitting (FIGs. 10A, 11A and FIG.31). The Ebvalues of the MoS2 / C-BTO / MoS2structures were calculated to be 5.62 and 5.61 MV / cm, which are comparable with that of C-BTO (5.81 MV / cm) due to the low thicknesses of the C-BTO. Furthermore, the result is consistent with the negligible effective permittivity change arising from the atomically thin 2D layers. Non-zero leakage currents were observed in the C-BTO and MoS2 / C-BTO / MoS2 heterostructures (FIGs. 32A, 32B, 32C), attributed to the narrow band gap nature of BTO and probability of oxygen vacancies. Nevertheless, the leakage current values are comparable to that of previously reported capacitors with high energy capability, indicating high reliability and Ebunder high electric field conditions. From the P- E loops at 10 kHz the Ueand efficiencies of the samples at an electric field of ~5.6 MV / cm (close to their Eb) were further calculated (FIGs. 10B, 11B). As expected, a higher energy density from the 2ML-MoS2 / C-BTO / 2ML-MoS2 samples (191.7 J / cm3) was obtained than those of the C-BTO (96.9 J / cm3) and 1ML-MoS2 / C-BTO / 1ML-MoS2 (152.4 J / cm3) samples. The energy density observed in the 2ML-MoS2 / C-BTO / 2ML-MoS2heterostructure exhibits a high value (FIG. 33). These ultrahigh Uevalues are the combined results of high polarization density, low hysteresis, and high efficiency (over 90%). The high efficiency is critical to address the energy dissipation of dielectrics for high-power applications, facilitating reliable operation. At higher frequency, smaller Pm and Pr were observed because there is insufficient time to align the dipoles at the higher frequency (FIG.34). Nevertheless, high energy storage performance is still achieved. Stability and reliability tests were also conducted, crucial for electrostatic energy storage. For a thermal stability test, the P-E loops of the MoS2 / C- BTO / MoS2 structures were measured, which showed good stability of the polarization (FIGs. 36A, 36B, and 36C) and energy storage performance (FIGs. 10C, 11C) under a wideCT temperature range (250 to 400 K) with a small degradation in Ue (< 6%) and efficiency (< 6%). This Ue and efficiency reduction was attributed to the complex thermal scattering of charges accumulated at the non-chemically bonded interfaces. Nevertheless, the degradation rates are similar to previously reported results, indicating good thermal stability. During an accelerated charge-and-discharge test shown in FIGs. 10D, 11D and 10E, 10F, they survived over 108cycles. Moreover, the degradation rate of 2ML-MoS2 / C-BTO / 2ML-MoS2 is < 5% after 108cycles, indicating that the samples are stable during the cycling test. To assess the practical feasibility of this approach, a 2ML-MoS2 / C-BTO / 2ML-MoS2 array was fabricated (FIGs.37A, 37B, 37C). The average Pmhas 36.3 ± 9.3 µC / cm2at 2.7 MV / cm with suppressed Pr, indicating the potential for practical application.

[0113] These findings highlight the complex interplay between different materials in artificially designed 2D / C-3D / 2D heterostructures and their impact on remnant polarization, maximum polarization, energy loss, and efficiency. These insights contribute to the understanding of how to optimize the design and performance of high-energy electrostatic capacitors using ferroelectric materials. Utilizing this approach results in advances in the development of more efficient and large energy storage systems. Materials and Methods

[0114] Materials and methods, such as used for the first and second experiments described herein, are discussed in greater detail below.

[0115] Single-crystalline BaTiO3(BTO) growth

[0116] Before the growth of the single-crystalline BTO, the native oxide on the SrTiO3(100) (STO) substrate with a size of 10 x 10 x 0.5 mm was removed by chemical wet etching into buffered oxide etchant (6:1; Sigma-Aldrich) for 30 seconds and rinsed into DI water for 5 minutes. Thereafter, subsequent thermal annealing was conducted at 900°C by using pulsed-laser deposition for 90 minutes. The Sr3AlO6 (SAO) water-soluble sacrificial layer was grown by using a KrF excimer laser (248 nm, COMPex 205F, Coherent) at 780°C for 40 min. The laser power and frequency are 2 W and 2 Hz, respectively. Afterward, single- crystalline BTO with a thickness of 30 nm was grown on the SAO surface at 100 mTorr. The laser power and frequency are 2 W and 10 Hz, respectively. Due to the small lattice mismatch (less than 0.5%), single-crystalline BTO could be grown with a smooth surface and narrow full width at half maximum of X-ray diffraction (XRD) (FIGs. 12A, 12B, 13, 14),CT demonstrating low defect density. Moreover, high capacitance (FIGs. 15 and 16) and dielectric constant (FIGs. 15, 16, 26, 27A-27C) were observed in the single-crystalline BTO, demonstrating the possibility of a high polarization density.

[0117] Synthesis of MoS2

[0118] A customized hot-wall asymmetric three-zone metal-organic chemical vapor deposition (MOCVD) system was used to synthesize monolayer MoS2 continuous films. After cleaning with acetone, isopropanol, and deionized water, thermally grown 300-nm-thick SiO2 on 4-inch Si wafer was placed in a quartz tube. 60 mg of Molybdenum hexacarbonyl (MHC, Sigma Aldrich, purity ≥ 99.9%) and 12.5 mL of dimethyl sulfide anhydrous (DMS, Sigma Aldrich, purity ≥ 99.0%) were used as precursors for Mo and S respectively and introduced into the quartz tube using 5.0 sccm for H2 and 310 sccm for Ar as carrier gases. The amounts of precursors injected into the chamber are precisely controlled with mass flow controllers (MFCs), with NaCl plates placed in front of the substrate where the upstream of the furnace. The optimized conditions for synthesizing the continuous films for monolayer MoS2included pressure of 12.5 Torr, growth temperature of 580 °C, growth time of 23 hours, MHC flow of 1.0 sccm, and DMS flow of 0.6 sccm with optimized the reacting zone positions.

[0119] Synthesis of h-BN

[0120] The growth of h-BN was performed in a metal-organic vapor phase epitaxy (Aixtron) close-coupled showerhead (CCS) reactor on the 2-inch sapphire substrate at 1280 °C and 90 mbar pressure. Triethylboron (TEB) and ammonia (NH3) were used as B and N precursors, respectively. The hydrogen was used as carrier gas. The growth rate is 15 nm / hour.

[0121] Characterization

[0122] To evaluate the structural performance of as-grown BTO, an environmental scanning electron microscopy (SEM) measurement was conducted with a Thermo Fisher Scientific Quottro, operated at an accelerating voltage 10 kV. XRD and atomic force microscopy (AFM) measurements were conducted to measure the 3D material quality. XRD rocking curves of the samples were obtained using a Rigaku D-Max-B with Cu Kαradiation. The AFM images were obtained using a VEECO Nanoscope IIIA AFM. Transmission electron microscopy (TEM) using a Thermo Fisher Scientific Themis Z atCT 200kV was used to investigate the crystallinity and record integrated differential phase contrast (iDPC) data from the BTO and 2D / 3D / 2D heterostructures.

[0123] For analysis of the electrical performance, capacitor structures were fabricated using the C-BTO, 2D / C-BTO / 2D, 3D / C-BTO / 3D with chemically bonded interfaces, and 3D / C-BTO / 3D without chemically bonded interface, using symmetric 30 nm Au top and bottom electrodes with a width of 5 μm. These electrodes were formed using photolithography with LOR10B resist, S1805 positive photoresist, developer 319 and remover PG with the fabrication processes described in FIGs.15, 16, 18, and 19. Frequency- dependent dielectric constant measurements were performed using a potentiostat (Biologic, SP-300). Polarization versus vs. electric field loops were measured at a frequency of 10 kHz using a high-voltage dielectric & ferroelectric test system (PolyK) with a probe station.

[0124] Density-functional theory calculations

[0125] Density-functional theory (DFT) calculations were performed using the Vienna Ab initio Simulation Package (VASP). Projector augmented wave (PAW) potentials and the spin-polarized generalized gradient approximation (GGA) within the Perdew-Burke- Ernzerhof (PBE) functional for the exchange-correlation energy were used. The PAW potentials explicitly included the valence electrons as follows: 5d106s1for Au, 4p64d55s1for Mo, 3s23p4for S, 5s25p66s2for Ba, 3p63d24s2for Ti, 2s22p4for O, respectively. The plane-wave cutoff energy was set to 600 eV. The Brillouin zone was sampled with Γ-centered 4 x 1 x 1 k-point meshes. To obtain more accurate layer spacing in the slab models, the Grimme-D3 dispersion correction was employed, as implemented in the VASP. In addition, dipole correction with a large vacuum thickness (~20 Å) along the c-axis was employed in the slab calculations to remove any fictitious dipole interactions between the periodic images. The convergence criteria were set to 10-7eV for energy and 0.01 eV / Å2for forces, respectively.

[0126] Using this approach, a sandwich-type heterostructure(‘Au / MoS2 / BTO / MoS2 / Au’) was constructed, using the following materials: √3 x 7 x 1supercell of 2H-MoS2, √2 x 4√2 x 1 supercell of P4mm-BTO (001), and √2 x 4√2 x 1 supercellof Au (001), respectively. This gives less than 1% of lattice mismatch for BTO and MoS2layers along the ab-plane. To find the optimal lattice spacing between MoS2and ferroelectric BTO layers, the atomic positions of the BTO were kept at its bulk configuration of tetragonal phase (P4mm), and the MoS2 layers were fully relaxed using the conjugated gradient algorithm. TheCT interlayer distance between Au and MoS2 was fixed as 3 Å, which is comparable to other reported metal-MoS2 contact distances.

[0127] Weibull distribution analysis

[0128] The dielectric breakdown behavior of the samples was statistically analyzed with a two-parameter Weibull distribution function:

[0129] Here Ei is the measured breakdown field, P(Ei) is the cumulative probability of electric breakdown at Ei, Ebis the statistical breakdown strength at which P (Ei) equals 63.2%, and the Weibull parameter β evaluates the distribution of Ei. Ten different samples were investigated for each composition for the analysis.

[0130] Miller model

[0131] The Miller model can be derived from the classical damping theory for ferroelectric capacitors. From the damping theory, the damping response of the spontaneous polarization can be effectively modeled by Debye's dielectric relaxation model. Due to the lagging response of the spontaneous dipole moment, the rate at which the dipole moment change is as follows:

[0132] Here, ps is an instantaneous spontaneous dipole moment, αf (0) is the direct current (DC) polarizability for spontaneous polarization in ferroelectric materials,E(t) is an external electric field, and τ is the relaxation time of the dipole. For an alternatingcurrent (AC) condition, the external field can be expressed by an exponential representation as follows: ^(^) = ^^exp (^^^) (S2)

[0133] Here E0is the amplitude of the field, j is an imaginary number, and ω is the angular frequency of the AC condition. If the field is substituted into Equation (S1), an ordinary differential equation that describes the lagging response is obtained as follows:CT

[0134] Solving the differential equation for the ps, the Equation (S3) is expressed as follows:

[0135] where αf (ω) is the AC polarizability of the ps, and αf (ω) can be described as follows:

[0136] According to Equation (S5), αf (ω) at low τ is nearly equal to αf (0) at a certain frequency. This result indicates that the ps, closely follows the external field. At the high τ, the τ is larger than the AC period of the field and the psdoes not follow the field. That is, the large τ suppresses the AC polarizability depending on the external AC bias, providing relatively low remnant polarization.

[0137] Maxwell-Wagner (MW) relaxation

[0138] MW relaxation (or Maxwell-Wagner-Sillars relaxation) is the phenomenon of charge accumulation at the heterogeneous interfaces of the dielectric materials with different permittivity and conductivity. This relaxation is equivalent to the charging two series capacitors when the current flows across the heterogeneous interface. The conduction current through each material is given bywhere E represents the electric field and σ is the conductivity of the two different materials. Before reaching the steady state, the conduction currents in each material are not equal. The electric field can be expressed as follows:CT where U is the polarization voltage applied on the heterostructure, d is thickness, εr is the relative permittivity, and t is time.

[0139] Electronic structure of MoS2 / C-BTO / MoS2heterostructures

[0140] To gain a comprehensive understanding of the polarization behavior within the 2D / 3D / 2D heterostructures, their electronic structure was calculated using DFT. A series of sandwich-type heterostructures (‘Au / MoS2 / BTO / MoS2 / Au’) were created including either 1 or 2 monolayers (ML) of MoS2, 3-unit cells-thick BTO, and 3 layers of Au as contacts (as described in the details in the “Materials and Methods” section). FIGs. 22A, 22B, 23A, 23B, and 25 show the layer-projected density of states for the heterostructures with one monolayer (1ML)- and two monolayer (2ML)-MoS2, respectively. In both cases, the intrinsic electric field within the ferroelectric BTO layers induces a potential gradient and band bending indicated by the red lines. This leads to a charge transfer, from the valence band of the top BTO layer to the conduction band of the bottom BTO layer. It is noted that the middle BTO layer, corresponding to the bulk region, remained insulating. These polarization- induced charges impact the adjacent MoS2 layer, transitioning it to a metallic state, as shown in FIGs.22A, 22B, 23A, 23B, and 25. However, with 2ML-MoS2, the MoS2 layers away from BTO (e.g., in contact with the Au electrode) show only a small density of states at the Fermi energy due to transfer of electrons from the Au contact (and do not follow the trend in band shift observed in BTO), indicating that the polarization-induced charges can be screened completely by 1ML-MoS2. These results are in excellent agreement with the experimental PE measurements wherein a significant reduction in the remnant polarization of 2ML-MoS2 / C- BTO / 2ML-MoS2 is observed.

[0141] The laterally averaged charge density difference along the c-axis (Δρ) for the heterostructures (FIGs. 22A, 22B, 23A, 23B, and 25) was also investigated, which is defined as the difference of charge density of the heterostructure (‘MoS2 / BTO / Au’) after subtracting the superposed charge density of two isolated systems (‘MoS2 / Au’ and ‘BTO’). In common, the spontaneous polarization within the BTO layers results in the charge accumulation at the interface between BTO and adjacent MoS2layers (blue shaded area). Meanwhile, the charge transfer into the non-adjacent MoS2 layer is negligible (orange shaded area). Consequently, the aggregated electrons and holes are confined within the adjacent MoS2 layers to the interface, which suggests that 1 ML-MoS2 can effectively screen the negative or positive polarization bound charges.CT

[0142] Additional description and aspects of the disclosed system, devices, and methods are provided below.

[0143] FIG. 38 illustrates a fabrication configuration 3800 according to one embodiment of the present disclosure. Fabrication configuration 3800 includes the providing / formulation of materials 3802, device designs 3804, and variety of fabrication equipment 3806 needed for device (e.g., capacitor) fabrication. Fabrication equipment 3806 may be controlled by one or more computers 3808 operatively connected thereto. From this, a fabricated device 3810 results. Fabrication equipment 3806 may include but is not limited to equipment for pulsed-laser deposition, various lasers (e.g., KrF excimer laser), chemical vapor deposition (CVD) systems, mass flow controllers (MFCs), close-coupled showerhead (CCS) reactors.

[0144] FIG. 39 illustrates a testing configuration 3900 for testing of fabricated devices 3810. Testing configuration 3900 may include a plurality of testing equipment 3904 operatively connected to one or more computers 3906. One or both of testing equipment 3904 and / or computers 3906 may output results 3908 from testing of devices 3810, and these results may be analyzed for device performance, structural and electrical integrity, and the like. Testing equipment 3904 may include but is not limited to scanning electron microscopes, atomic force microscopes, nanoscopes, transmission electron microscopes, cameras, a high- voltage dielectric & ferroelectric test system (e.g., PolyK) with a probe station, Vienna Ab initio Simulation Package (VASP), and more. Each of computers 3808, 3906, and equipment 3806 and 3904 may be connected to a computer network or a communications network such as the Internet, and may use wired or wireless connections. Additionally, computers 3808 and 3906 may be remote from the location equipment 3806 and 3904 are located, but still in operative communication to provide control and / or receive data from the equipment or vice versa. Computers 3808 and 3906 may include hardware and software including but not limited to processors and non-transitory memory devices in operative communication with one another. Additional fabrication details are described in the “Materials and Methods” section herein.

[0145] FIG. 40 illustrates a flow chart of an example method 4000 according to one embodiment of the present disclosure. Method 4000 includes selecting 4002 materials, as described herein. Method 4000 includes selecting 4004 a layer / device design, as described herein, such as a desired amount of layers. Method 4000 includes fabricating 4006 the device (e.g., capacitor layer(s), entire capacitor, etc.), such as via equipment 3806CT shown in and described in connection with FIG.38, or as otherwise described herein. Method 4000 includes evaluating the fabricated device, such as with testing equipment 3904 shown in and described in connection with FIG.39, or as otherwise described herein. Method 4000 includes using 4010 the fabricated and tested device, such as for any of the applications described herein, such as those shown in and described in connection with FIGs.2C and 4, or as otherwise described herein.

[0146] FIG. 41 illustrates a flow chart of an example method 4100 according to one embodiment of the present disclosure. Method 4100 includes growing 4102 one or more sacrificial layers. Method 4100 includes growing 4104 one or more 2D layers. As described herein, 3D layers may be used in place of 2D layers, and as such growing 4104 may alternatively or additionally include growing 3D layers. Method 4100 includes placing 4106 one or more handling layers to form an initial device structure. Method 4100 includes etching 4108 one or more sacrificial layers. Method 4100 includes depositing 4110 one or more additional sacrificial layers. Method 4100 includes growing 41123D material. Method 4100 includes depositing 4114 one or more additional handling layers to form a 3D structure. Method 4100 includes etching 4116 one or more of the additional sacrificial layers. Method 4100 includes scooping 4118 the 3D structure. Method 4100 includes contacting 4120 surfaces to form a structure. Method 4100 includes etching 4122 the handling layer(s). Method 4100 includes contacting 4124 to form a structure. Method 4100 includes etching 4126 handling layers to form the device. In one embodiment, this includes: a. growing (e.g., 4102) first and second sacrificial layers (1S and 2S) on first and second substrates, respectively; b. growing (e.g., 4104) upper and lower 2D layers (2DU and 2DL) on the first and second sacrificial layers to form 2DU / 1S and 2DL / 2S structures on the first and second substrates, respectively; c. placing (e.g., 4106) first and second handling layers (1H and 2H) over the 2DU and 2DL of the 2DU / 1S and 2DL / 2S structures, respectively, to form 1H / 2DU / 1S and 2H / 2DL / 2S structures on the first and second substrates, respectively; d. etching (e.g., 4108) the 1S and 2S layers to release a 1H / 2DU structure and a 2H / 2DL structure from the first and second substrates, respectively; e. depositing a third sacrificial layer (3S) on an (e.g., epitaxial) substrate; f. growing (e.g., 4112, such as epitaxially growing) a single crystal of a 3D ferromagnetic material (3D) on the first sacrificial layer to form a 3D / 3S structure on the (e.g., epitaxial) substrate; g. depositing (e.g., 4114) a third handling layer (3H) over the single crystal of the ferromagnetic material to form a 3H / 3D / 3S structureCT on the (e.g., epitaxial) substrate; h. etching (e.g., 4116) the third sacrificial layer to separate a 3H / 3D structure from the (e.g., epitaxial) substrate; i. scooping (e.g., 4118) the 3H / 3D structure onto a fourth handling layer (4H) to form a freestanding 4H / 3H / 3D structure; j. contacting (e.g., 4120) an exposed ferromagnetic crystal surface of the 4H / 3H / 3D structure with an exposed lower 2D surface of the 2L / 2DL structure to form a 2L / 2DL / 3D / 3H / 4H structure; k. etching (e.g., 4122) the first and fourth handling layers of the 2L / 2DL / 3D / 3H structure and contacting (e.g., 4120) the exposed surface of the lower 2D layer with a target substrate (TS) to form a 3H / 3D / 2DL / TS structure; l. etching (e.g., 4122) the third handling layer and contacting (e.g., 4124) the exposed ferromagnetic crystal surface of the resulting 3D / 2DL / TS structure with the exposed upper 2D layer of the 2DU / 1S structure to form a 1S / 2DU / 3D / 2DL / TS structure; m. etching (e.g., 4126) the first handling layer to form the capacitor device or layer including a 2DU / 3D / 2DL / TS structure.

[0147] FIG.42 illustrates an example configuration of a computer system 4200. Computer system 4200 may be an implementation of computer 3808 shown in FIG. 38 and / or computer 3906 shown in FIG.39. Computer system 4200 may include a processor 4202 for executing instructions. Instructions may be stored in a memory area of memory 4204, for example. Processor 4202 may include one or more processing units (e.g., in a multi- core or parallel processing configuration).

[0148] Processor 4202 may be operatively coupled to a communication interface 4206 such that computer system 4200 may be capable of communicating with a remote device such as equipment 3806 / 3906 (shown in FIG.43) or another computer system 4200 or a user computing device 4300 shown in FIG. 43. For example, communication interface 4206 may receive requests from a user computing device (e.g., 3808 and / or 3906) via a network (e.g., local area or wide area).

[0149] Processor 4202 may also be operatively coupled to a storage device 4208. Storage device 4208 may be any computer-operated hardware suitable for storing and / or retrieving data. In some aspects, storage device 4208 may be integrated in computer system 4200. For example, computer system 4200 may include one or more hard disk drives as storage device 4208. In other aspects, storage device 4208 may be external to computer system 4200 and may be accessed by a plurality of computer systems 4200. For example, storage device 4208 may include multiple storage units such as hard disks or solid state disksCT in a redundant array of inexpensive disks (RAID) configuration. Storage device 4208 may include a storage area network (SAN) and / or a network attached storage (NAS) system. In some aspects, processor 4202 may be operatively coupled to storage device 4208 via a storage interface 4210. Storage interface 4210 may be any component capable of providing processor 4202 with access to storage device 4208. Storage interface 4210 may include, for example, an Advanced Technology Attachment (ATA) adapter, a Serial ATA (SATA) adapter, a Small Computer System Interface (SCSI) adapter, a RAID controller, a SAN adapter, a network adapter, and / or any component providing processor 4202 with access to storage device 4208. Storage device 4208 may include computer files such as digital data from prior device testing, device designs, and other software and / or files.

[0150] FIG. 43 depicts a configuration of a remote or user computing device 4300. Computing device 4200 may be an implementation of computer 3808 shown in FIG.38 and / or computer 3906 shown in FIG.39. Computing device 4300 may include a processor 4302 for executing computer-readable / -executable instructions. In some aspects, executable instructions may be stored in a memory area of memory 4304. Processor 4302 may include one or more processing units (e.g., in a multi-core or parallel processing configuration). Memory 4304 may be any device allowing information such as executable instructions and / or other data to be stored and retrieved. Memory 4304 may include one or more computer-readable media (e.g., hard drive, RAM, ROM, and the like).

[0151] Computing device 4300 may also include at least one media output component 4306 for presenting information to a user 4308. Media output component 4306 may be any component capable of conveying information to a user 4308. In some aspects, media output component 4306 may include an output adapter, such as a video adapter and / or an audio adapter. An output adapter may be operatively coupled to processor 4302 and operatively coupled to an output device such as a display device (e.g., a liquid crystal display (LCD), organic light emitting diode (OLED) display, cathode ray tube (CRT), or “electronic ink” display) or an audio output device (e.g., a speaker or headphones). In some aspects, media output component 4306 may be configured to present an interactive user interface (e.g., a web browser or client application) to user 4308.

[0152] In some aspects, computing device 4300 may include an input device 4310 for receiving input from user 4308. Input device 4310 may include, for example,CT a keyboard, a pointing device, a mouse, a stylus, a touch sensitive panel (e.g., a touch pad or a touch screen), a camera, a gyroscope, an accelerometer, a position detector, and / or an audio input device. A single component such as a touch screen may function as both an output device of media output component 4306 and input device 4310.

[0153] Computing device 4300 may also include a communication interface 4312, which may be communicatively coupled to a remote device. Communication interface 4312 may include, for example, a wired or wireless network adapter or a wireless data transceiver for use with the Internet (e.g., via WiFi), a mobile phone network (e.g., Global System for Mobile communications (GSM), 3G, 4G or Bluetooth) or other mobile data network (e.g., Worldwide Interoperability for Microwave Access (WIMAX)).

[0154] Stored in memory 4304 are, for example, computer-readable / - executable instructions for providing a user interface to user 4308 via media output component 4306 and, optionally, receiving and processing input from input device 4310. A user interface may include, among other possibilities, a web browser and client application. Web browsers enable users 4308 to display and interact with media and other information typically embedded on a web page or a website from a web server. A client application allows users 4308 to interact with a server application associated with, for example, a vendor or business.

[0155] Memory 4304 (shown in FIG. 43) and 4204 (shown in FIG. 42) may include, but are not limited to, random access memory (RAM) such as dynamic RAM (DRAM) or static RAM (SRAM), read-only memory (ROM), erasable programmable read- only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), and non-volatile RAM (NVRAM). The above memory types are example only, and are thus not limiting as to the types of memory usable for storage of a computer program.

[0156] Each of computer system 4200 and user computing device 4300 may be connected to a respective network 4212 and 4314, which may be the same network. A plurality of computer systems 4200 and user computing devices 4300 may be used together, such as in a distributed computing configuration. In one embodiment, a researcher or fabricator / manufacturer may use a user computing device 4300 as a control device to control equipment 3806 and / or 3904.CT

[0157] Processors described herein may also be operatively coupled via a storage interface to a storage device, which may be cloud-based and accessible via a network Storage device is any computer-operated hardware suitable for storing and / or retrieving data. Storage device may be accessed by a plurality of server systems. Storage interface is any component capable of providing processor with access to storage device. Storage interface may include, for example, an Advanced Technology Attachment (ATA) adapter, a Serial ATA (SATA) adapter, a Small Computer System Interface (SCSI) adapter, a RAID controller, a SAN adapter, a network adapter, and / or any component providing processor with access to storage device.

[0158] Memory area may include, but are not limited to, random access memory (RAM) such as dynamic RAM (DRAM) or static RAM (SRAM), read-only memory (ROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), non-volatile RAM (NVRAM), registers, hard disk memory, a removable disk, a CD-ROM, or any other form of computer-readable storage medium known in the art. The above memory types are exemplary only, and are thus not limiting as to the types of memory usable for storage of a computer program.

[0159] Stored in memory are, for example, computer-readable instructions for providing a user interface to user via media output component and, optionally, receiving and processing input from input device. A user interface may include, among other possibilities, a web browser and an application. Web browsers enable users to display and interact with media and other information typically embedded on a web page or a website from a web server. An application allows users to interact with a server application.

[0160] As will be appreciated based upon the foregoing specification, the above-described aspects of the disclosure may be implemented using computer programming or engineering techniques including computer software, firmware, hardware or any combination or subset thereof. Any such resulting program, having computer-readable code means, may be embodied or provided within one or more non-transitory computer-readable media, thereby making a computer program product, e.g., an article of manufacture, according to the discussed aspects of the disclosure. The computer-readable media may be, for example, but is not limited to, a fixed (hard) drive, diskette, optical disk, magnetic tape, semiconductor memory such as read-only memory (ROM), and / or anyCT transmitting / receiving medium, such as the Internet or other communication network or link. The article of manufacture containing the computer code may be made and / or used by executing the code directly from one medium, by copying the code from one medium to another medium, or by transmitting the code over a network.

[0161] These computer programs (also known as programs, software, software applications, “apps”, or code) include machine instructions for a programmable processor, and can be implemented in a high-level procedural and / or object-oriented programming language, and / or in assembly / machine language. As used herein, the terms “machine-readable medium” “computer-readable medium” refers to any computer program product, apparatus and / or device (e.g., magnetic discs, optical disks, memory, Programmable Logic Devices (PLDs)) used to provide machine instructions and / or data to a programmable processor, including a machine-readable medium that receives machine instructions as a machine-readable signal. The “machine-readable medium” and “computer-readable medium,” however, do not include transitory signals. The term “machine-readable signal” refers to any signal used to provide machine instructions and / or data to a programmable processor.

[0162] As used herein, a “processor” may include any programmable system including systems using micro-controllers, reduced instruction set circuits (RISC), application specific integrated circuits (ASICs), logic circuits, and any other circuit or processor capable of executing the functions described herein. The above examples are examples only, and are thus not intended to limit in any way the definition and / or meaning of the term “processor.”

[0163] As used herein, the terms “software” and “firmware” are interchangeable, and include any computer program stored in memory for execution by a processor, including RAM memory, ROM memory, EPROM memory, EEPROM memory, and non-volatile RAM (NVRAM) memory. The above memory types are example only, and are thus not limiting as to the types of memory usable for storage of a computer program.

[0164] As used herein, the term "database" may refer to either a body of data, a relational database management system (RDBMS), or to both. As used herein, a database may include any collection of data including hierarchical databases, relational databases, flat file databases, object-relational databases, object oriented databases, and anyCT other structured collection of records or data that is stored in a computer system. The above examples are example only, and thus are not intended to limit in any way the definition and / or meaning of the term database. Examples of RDBMS's include, but are not limited to including, Oracle® Database, MySQL, IBM® DB2, Microsoft® SQL Server, Sybase®, and PostgreSQL. However, any database may be used that enables the systems and methods described herein. (Oracle is a registered trademark of Oracle Corporation, Redwood Shores, California; IBM is a registered trademark of International Business Machines Corporation, Armonk, New York; Microsoft is a registered trademark of Microsoft Corporation, Redmond, Washington; and Sybase is a registered trademark of Sybase, Dublin, California.).

[0165] In some aspects, the system includes multiple components distributed among a plurality of computing devices. One or more components may be in the form of computer-executable instructions embodied in a computer-readable medium. The systems and processes are not limited to the specific aspects described herein.

[0166] In addition, components of each system and each process can be practiced independent and separate from other components and processes described herein. Each component and process can also be used in combination with other assembly packages and processes. The present aspects may enhance the functionality and functioning of computers and / or computer systems.

[0167] Although the present disclosure is described in connection with an exemplary fabrication / manufacturing environment, embodiments of the invention are operational with numerous other general purpose or special purpose fabrication / manufacturing system environments or configurations. The fabrication / manufacturing system environment is not intended to suggest any limitation as to the scope of use or functionality of any aspect of the invention. Moreover, the fabrication / manufacturing system environment should not be interpreted as having any dependency or requirement relating to any one or combination of components illustrated in the exemplary operating environment. Examples of well-known fabrication / manufacturing systems, environments, and / or configurations that may be suitable for use with aspects of the invention include, but are not limited to, personal computers, server computers, hand-held or laptop devices, multiprocessor systems, microprocessor-based systems, set top boxes, programmable consumer electronics, mobile telephones, network PCs, minicomputers,CT mainframe computers, distributed computing environments that include any of the above systems or devices, and the like.

[0168] Computer systems, as described herein, refer to any known computing device and computer system. As described herein, all such computer systems include a processor and a memory. However, any processor in a computer system referred to herein may also refer to one or more processors wherein the processor may be in one computing device or a plurality of computing devices acting in parallel. Additionally, any memory in a computer device referred to herein may also refer to one or more memories wherein the memories may be in one computing device or a plurality of computing devices acting in parallel. Each of the memories described herein may be non-transitory storage mediums.

[0169] In one embodiment, a computer program is provided to enable the data processing of the methods as described herein above, and this program is embodied on a computer readable medium. In an example embodiment, the computer system is executed on a single computer system, without requiring a connection to a server computer. In a further embodiment, the computer system is run in a Windows® environment (Windows is a registered trademark of Microsoft Corporation, Redmond, Washington). In yet another embodiment, the computer system is run on a mainframe environment and a UNIX® server environment (UNIX is a registered trademark of X / Open Company Limited located in Reading, Berkshire, United Kingdom). Alternatively, the computer system is run in any suitable operating system environment. The computer program is flexible and designed to run in various different environments without compromising any major functionality. In some embodiments, the computer system includes multiple components distributed among a plurality of computing devices. One or more components may be in the form of computer- executable instructions embodied in a computer-readable medium.

[0170] The computer systems and processes are not limited to the specific embodiments described herein. In addition, components of each computer system and each process can be practiced independent and separate from other components and processes described herein. Each component and process also can be used in combination with other assembly packages and processes.CT

[0171] Exemplary embodiments of methods, systems, and apparatus for use in producing high-efficiency ferroelectric capacitors including MLCCs with 2D / 3D structures are described above in detail. The methods, systems, and apparatus are not limited to the specific embodiments described herein but, rather, operations of the methods and / or components of the systems and / or apparatus may be utilized independently and separately from other operations and / or components described herein. Further, the described operations and / or components may also be defined in, or used in combination with, other systems, methods, and / or apparatus, and are not limited to practice with only the systems, methods, and apparatus described herein.

[0172] The order of execution or performance of the operations in the embodiments of the invention illustrated and described herein is not essential, unless otherwise specified. That is, the operations may be performed in any order, unless otherwise specified, and embodiments of the invention may include additional or fewer operations than those disclosed herein. For example, it is contemplated that executing or performing a particular operation before, contemporaneously with, or after another operation is within the scope of aspects of the invention.

[0173] It will be understood by those of skill in the art that information and signals may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and / or chips may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof. Similarly, the various illustrative logical blocks, modules, circuits, and algorithm operations described herein may be implemented as electronic hardware, computer software, or a combination of both, depending on the application and the functionality. Moreover, the various logical blocks, modules, and circuits described herein may be implemented or performed with a general purpose computer, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. Exemplary general purpose processors include, but are not limited to only including, microprocessors, conventional processors, controllers, microcontrollers, state machines, or a combination of computing devices.CT

[0174] Definitions and methods described herein are provided to better define the present disclosure and to guide those of ordinary skill in the art in the practice of the present disclosure. Unless otherwise noted, terms are to be understood according to conventional usage by those of ordinary skill in the relevant art. In some embodiments, numbers expressing quantities of ingredients, properties such as molecular weight, reaction conditions, and so forth, used to describe and claim certain embodiments of the present disclosure are to be understood as being modified in some instances by the term “about.” In some embodiments, the term “about” is used to indicate that a value includes the standard deviation of the mean for the device or method being employed to determine the value. In some embodiments, the numerical parameters set forth in the written description and attached claims are approximations that can vary depending upon the desired properties sought to be obtained by a particular embodiment. In some embodiments, the numerical parameters should be construed in light of the number of reported significant digits and by applying ordinary rounding techniques. Notwithstanding that the numerical ranges and parameters setting forth the broad scope of some embodiments of the present disclosure are approximations, the numerical values set forth in the specific examples are reported as precisely as practicable. The numerical values presented in some embodiments of the present disclosure may contain certain errors necessarily resulting from the standard deviation found in their respective testing measurements. The recitation of ranges of values herein is merely intended to serve as a shorthand method of referring individually to each separate value falling within the range. Unless otherwise indicated herein, each individual value is incorporated into the specification as if it were individually recited herein. The recitation of discrete values is understood to include ranges between each value. In some embodiments, the terms “a” and “an” and “the” and similar references used in the context of describing a particular embodiment (especially in the context of certain of the following claims) can be construed to cover both the singular and the plural, unless specifically noted otherwise. In some embodiments, the term “or” as used herein, including the claims, is used to mean “and / or” unless explicitly indicated to refer to alternatives only or the alternatives are mutually exclusive.

[0175] The terms “comprise,” “have” and “include” are open-ended linking verbs. Any forms or tenses of one or more of these verbs, such as “includes,” “including,” “has,” “having,” “includes” and “including,” are also open-ended. ForCT example, any method that “includes,” “has” or “includes” one or more steps is not limited to possessing only those one or more steps and can also cover other unlisted steps. Similarly, any composition or device that “includes,” “has” or “includes” one or more features is not limited to possessing only those one or more features and can cover other unlisted features.

[0176] All methods described herein can be performed in any suitable order unless otherwise indicated herein or otherwise clearly contradicted by context. The use of any and all examples, or exemplary language (e.g., “such as”) provided with respect to certain embodiments herein is intended merely to better illuminate the present disclosure and does not pose a limitation on the scope of the present disclosure otherwise claimed. No language in the specification should be construed as indicating any non-claimed element essential to the practice of the present disclosure.

[0177] Groupings of alternative elements or embodiments of the present disclosure disclosed herein are not to be construed as limitations. Each group member can be referred to and claimed individually or in any combination with other members of the group or other elements found herein. One or more members of a group can be included in, or deleted from, a group for reasons of convenience or patentability. When any such inclusion or deletion occurs, the specification is herein deemed to contain the group as modified thus fulfilling the written description of all Markush groups used in the appended claims.

[0178] Any publications, patents, patent applications, and other references cited in this application are incorporated herein by reference in their entirety for all purposes to the same extent as if each individual publication, patent, patent application, or other reference was specifically and individually indicated to be incorporated by reference in its entirety for all purposes. Citation of a reference herein shall not be construed as an admission that such is prior art to the present disclosure.

[0179] Having described the present disclosure in detail, it will be apparent that modifications, variations, and equivalent embodiments are possible without departing from the scope of the present disclosure defined in the appended claims. Furthermore, it should be appreciated that all examples in the present disclosure are provided as non-limiting examples.CT

[0180] When introducing elements of aspects of the invention or embodiments thereof, the articles “a,” “an,” “the,” and “said” are intended to mean that there are one or more of the elements. The terms “including,” including,” and “having” are intended to be inclusive and mean that there may be additional elements other than the listed elements.

[0181] This written description uses examples to disclose the invention, including the best mode, and also to enable any person skilled in the art to practice the invention, including making and using any devices or systems and performing any incorporated methods. The patentable scope of the invention is defined by the claims, and may include other examples that occur to those skilled in the art. Such other examples are intended to be within the scope of the claims if they have structural elements that do not differ from the literal language of the claims, or if they include equivalent structural elements with insubstantial differences from the literal language of the claims.

Claims

CT WHAT IS CLAIMED IS:

1. A capacitor device including: a 3D layer including a crystalline ferroelectric material, the 3D layer including a first surface and a second surface, the first surface being opposite the second surface; a first 2D layer on the first surface of the 3D layer; and a second 2D layer on the second surface of the 3D layer, wherein application of (i) the first 2D layer on the first surface and (ii) the second 2D layer on the second surface does not disrupt a crystalline structure of the crystalline ferroelectric material.

2. The device of claim 1, wherein the crystalline ferroelectric material is a freestanding membrane and dielectric relaxation occurs at heterogeneous interfaces between the freestanding membrane and the first and second 2D layers.

3. The device of claim 2, wherein a remnant polarization of the crystalline ferroelectric material is suppressed while maintaining a polarization threshold.

4. The device of claim 1, wherein the first 2D layer being on the first surface and the second 2D layer being on the second surface includes lifting the first and second 2D layers off from respective host substrates, and the 3D layer is a freestanding membrane formed independent of a substrate.

5. The device of claim 4, wherein the crystalline ferroelectric material is exfoliated from a substrate.

6. The device of claim 1, wherein the crystalline ferroelectric material includes crystalline BaTiO3.

7. The device of claim 1, wherein the crystalline ferroelectric material includes a thickness ranging from about 10 nm to about 5 μm.

8. The device of claim 1, wherein each of the first and second 2D layers is a freestanding membrane, and the 3D layer is a freestanding membrane formed independent of a substrate.CT 9. The device of claim 1, wherein each of the first and second 2D layers comprise a layer thickness ranging from 1 monolayer (ML) to about 1,000 ML.

10. The device of claim 1, wherein each of the first and second 2D layers comprises MoS2.

11. The device of claim 1, wherein a weakly bonded interface is present between each of (i) the first 2D layer and the first surface and (ii) the second 2D layer and the second surface.

12. The device of claim 1, wherein each of the first 2D layer and the second 2D layer is a dielectric layer.

13. A method of fabricating a capacitor device including: forming, on a first substrate, a 3D layer on a sacrificial layer, the 3D layer comprising a 3D ferromagnetic material; forming a 3D layer structure from at least the 3D layer and the first substrate; forming a freestanding 3D layer from at least the 3D layer structure; forming at least one 2D layer; forming a 2D layer structure from at least the at least one 2D layer; contacting an exposed surface of the at least one 2D layer with a target substrate; forming a structure comprising the 3D layer, the 2D layer, and the target substrate; and forming the capacitor device with the structure comprising the 3D layer, the 2D layer, and the target substrate.

14. The method of claim 13, wherein: wherein the forming of the capacitor device with the structure comprising the 3D layer, the 2D layer, and the target substrate includes etching the structure comprising the 3D layer, the 2D layer, and the target substrate.CT 15. The method of claim 13, wherein: the forming of the at least one 2D layer includes lifting-off the at least one 2D layer from a substrate, and the lifting-off includes a lift-off technique comprising one of: (i) mechanical lift-off; (ii) mechanical exfoliation; (iii) chemical lift-off; (iv) optical lift-off; and (v) 2D layer-assisted layer transfer.

16. The method of claim 13, wherein: the first substrate is a growth substrate; the 3D ferromagnetic material comprises BaTiO3. the sacrificial layer comprises SiO2; and the 2D layer comprise MoS2.

17. The method of claim 16, wherein: the growth substrate comprises SrTiO3.

18. The method of claim 13, wherein: the capacitor device includes one of (i) strongly bonded interfaces and (ii) weakly bonded interfaces.

19. A method of fabricating a capacitor device including: growing (i) a first sacrificial layer on a first substrate and (ii) a second sacrificial layer on a second substrate; growing (i) a first 2D layer on the first sacrificial layer and (ii) a second 2D layer on the second sacrificial layer, thereby forming a first 2D layer / first sacrificial layer structure on the first substrate and a second 2D layer / second sacrificial layer structure on the second substrate; depositing (i) a first handling layer on the first 2D layer of the first 2D layer / first sacrificial layer structure and (i) a second handling layer on the second 2D layer of the second 2D layer / second sacrificial layer structure, thereby forming (i) a first handling layer / first 2DCT layer / first sacrificial layer structure on the first substrate and (ii) a second handling layer / second 2D layer / second sacrificial layer structure on the second substrate; etching (i) the first sacrificial layer to release a first handling layer / first 2D layer structure from the first substrate and (ii) the second sacrificial layer to release a second handling layer / second 2D layer structure from the second substrate; depositing a third sacrificial layer on a growth substrate; growing a single crystal of a 3D ferromagnetic material on the first sacrificial layer, thereby forming a 3D layer / third sacrificial layer structure on the growth substrate; depositing a third handling layer on the single crystal of the 3D ferromagnetic material, thereby forming a third handling layer / 3D layer / third sacrificial layer structure on the growth substrate; etching the third sacrificial layer to separate a third handling layer / 3D layer structure from the growth substrate; scooping the third handling layer / 3D layer structure onto a fourth handling layer to form a freestanding fourth handling layer / third handling layer / 3D layer structure; contacting an exposed ferromagnetic crystal surface of the fourth handling layer / third handling layer / 3D layer structure with an exposed 2D surface of the second 2D layer, thereby forming a second 2D layer / 3D layer / third handling layer / fourth handling layer structure; etching the first and fourth handling layers of a second 2D layer / 3D layer / third handling layer structure and contacting the exposed surface of the second 2D layer with a target substrate to form a third handling layer / 3D layer / second 2D layer / target substrate structure; etching the third handling layer and contacting the exposed ferromagnetic crystal surface of a resulting 3D layer / second 2D layer / target substrate structure with the exposed first 2D layer of the first 2D layer / first sacrificial layer structure to form a first sacrificial layer / first 2D layer / 3D layer / second 2D layer / target substrate structure; andCT etching the first handling layer to form the capacitor device including a first 2D layer / 3D layer / second 2D layer / target substrate structure.

20. The method of claim 19, wherein: the first and second sacrificial layers comprise SiO2; the first and second substrates comprise Si; the upper and lower 2D layers comprise MoS2; the first and second handling layers comprise PMMA; the third sacrificial layer comprises SAO; the 3D layer / third sacrificial layer structure on the growth substrate comprises STO; the 3D ferromagnetic material comprises BTO; the third handling layer comprises Ni; and the fourth handling layer comprises PDMS.

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