Gate driving circuit, display substrate, and display apparatus

Abstract

A gate driving circuit, a display substrate, and a display apparatus. The gate driving circuit comprises a logic operation circuit (200) disposed on a silicon substrate, the logic operation circuit (200) comprising at least a first operation circuit that generates a write-in switching signal, a second operation circuit that generates a display switching signal, and a third operation circuit that generates a display reset signal, and the write-in switching signal, the display switching signal, and the display reset signal being configured to be outputted to a display area. Among the first operation circuit, the second operation circuit, and the third operation circuit, at least two operation circuits have at least one same input signal. At least one input signal of the second operation circuit is provided by the first operation circuit, and the second operation circuit or the third operation circuit is disposed on the side of the first operation circuit close to the display area.

Description

Gate driving circuit, display substrate and display device Technical Field

[0001] The present disclosure relates to, but is not limited to, the field of display technology, and in particular to a gate driving circuit, a display substrate, and a display device. Background Art

[0002] Micro-OLEDs (Micro Organic Light-Emitting Diodes) are a type of microdisplay that has been developed in recent years, with silicon-based OLEDs being one of them. Silicon-based OLEDs are a novel display technology that combines semiconductor manufacturing processes with OLED display technology, using wafers as substrates for manufacturing OLED devices. By combining the advantages of both semiconductor manufacturing processes and OLED display technology, silicon-based OLEDs not only offer a high pixel density (PPI), but also high brightness, low power consumption, fast response time, a wide color gamut, and excellent thermal stability.

[0003] Summary of the Invention

[0004] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0005] On the one hand, an embodiment of the present disclosure provides a gate drive circuit, including a logic operation circuit arranged on a silicon substrate, the logic operation circuit including at least a first operation circuit for generating a write switch signal, a second operation circuit for generating a display switch signal, and a third operation circuit for generating a display reset signal, the write switch signal, the display switch signal, and the display reset signal are configured to be output to a display area; at least two operation circuits of the first operation circuit, the second operation circuit, and the third operation circuit have at least one identical input signal, at least one input signal of the second operation circuit is provided by the first operation circuit, and the second operation circuit or the third operation circuit is arranged on a side of the first operation circuit close to the display area.

[0006] In an exemplary embodiment, the second operational circuit is arranged on a side of the first operational circuit close to the display area, the third operational circuit is arranged on a side of the second operational circuit close to the display area, the output end of the first operational circuit is connected to an input end of the second operational circuit, and the input end of the second operational circuit is arranged on a side of the output end of the first operational circuit close to the display area.

[0007] In an exemplary embodiment, the first operation circuit, the second operation circuit, and the third operation circuit each include a plurality of transistor groups arranged in sequence along a first direction, at least one transistor group includes a P-type transistor and an N-type transistor arranged on one side of the P-type transistor in a second direction, and the first direction and the second direction intersect; the number of transistor groups in the third operation circuit is smaller than the number of transistor groups in the first operation circuit, and the number of transistor groups in the third operation circuit is smaller than the number of transistor groups in the second operation circuit.

[0008] In an exemplary embodiment, the plurality of transistor groups in the first operation circuit form a first NAND gate, a first inverter, a first NOR gate, a second inverter, a second NOR gate, a fourth inverter, a third inverter, a third NOR gate, and a two-way selector that are sequentially arranged in a direction close to the display area, wherein the first NAND gate, the first NOR gate, the second NOR gate, and the third NOR gate each include two transistor groups, the first inverter, the second inverter, the third inverter, and the fourth inverter each include one transistor group, and the two-way selector includes three transistor groups.

[0009] In an exemplary embodiment, the plurality of transistor groups in the second operational circuit form a fifth inverter, a sixth inverter, a seventh inverter, an eighth inverter, a ninth inverter, a tenth inverter, a latch, a fourth NOR gate, and a second NAND gate, which are sequentially arranged in a direction close to the display area. The fifth to tenth inverters each include one transistor group, the latch includes nine transistor groups, and the fourth NOR gate and the second NAND gate each include two transistor groups.

[0010] In an exemplary embodiment, the plurality of transistor groups in the third operational circuit form a fifth NOR gate and a third NAND gate that are sequentially arranged in a direction close to the display area, the fifth NOR gate includes a forty-first P-type transistor, a forty-first N-type transistor, a forty-second P-type transistor, a forty-second N-type transistor, a forty-third P-type transistor, and a forty-third N-type transistor, and the third NAND gate includes a forty-fourth P-type transistor, a forty-fourth N-type transistor, a forty-fifth P-type transistor, and a forty-fifth N-type transistor; and the P-type width-to-length ratio of the P-type transistor in the fifth NOR gate is greater than the P-type width-to-length ratio of the P-type transistor in the third NAND gate.

[0011] In an exemplary embodiment, the logic operation circuit includes at least a first signal line for transmitting a duty control signal, a second signal line for transmitting a third input signal, a third signal line for transmitting a second input signal, a fourth signal line and a fifth signal line for transmitting the first input signal, a sixth signal line for transmitting a first reset signal, a seventh signal line for transmitting a second reset signal, and an eighth signal line for transmitting a clock signal; the first signal line, the second signal line, the third signal line, the sixth signal line, the eighth signal line, the seventh signal line and the fifth signal line are arranged in sequence along the second direction, and the fourth signal line is arranged on the side of the fifth signal line in the opposite direction Y of the second direction.

[0012] In an exemplary embodiment, an orthographic projection of the first signal line on the silicon substrate does not overlap with orthographic projections of P-type gate electrodes of a plurality of transistor groups in the first and second operation circuits on the silicon substrate.

[0013] In an exemplary embodiment, an orthographic projection of the second signal line on the silicon substrate does not overlap with an orthographic projection of P-type gate electrodes of a plurality of inverters in the first and second operational circuits on the silicon substrate.

[0014] In an exemplary embodiment, an orthographic projection of the third signal line on the silicon substrate does not overlap with orthographic projections of P-type gate electrodes of a plurality of inverters in the first and second operational circuits on the silicon substrate.

[0015] In an exemplary embodiment, the gate drive circuit further includes a shift register circuit, a level converter, and a row drive enhancer arranged on a silicon substrate, wherein the shift register circuit is configured to generate a row-by-row shift timing according to a timing signal, the logic operation circuit is configured to generate a target timing through a logic operation, the level converter is configured to perform voltage domain conversion on the target timing, and the row drive enhancer is configured to enhance the converted signal and output it to the scan signal line of the display area.

[0016] On the other hand, an embodiment of the present disclosure provides a display substrate, including a display area and a non-display area; the display area includes a plurality of sub-pixels, at least one sub-pixel includes a pixel driving circuit and at least one scanning signal line, and the scanning signal line is configured to provide a scanning signal to the connected pixel driving circuit; the non-display area includes a plurality of cascaded gate driving circuits, at least one gate driving circuit is connected to the scanning signal line in the display area, and at least one gate driving circuit includes the aforementioned gate driving circuit.

[0017] On the other hand, embodiments of the present disclosure provide a display device including the aforementioned display substrate.

[0018] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The accompanying drawings are intended to facilitate understanding of the technical solutions of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solutions of the present disclosure and do not constitute a limitation of the technical solutions of the present disclosure. The shapes and sizes of each component in the drawings do not reflect the actual scale and are intended only to illustrate the contents of the present disclosure.

[0020] FIG1 is a schematic structural diagram of a silicon-based OLED display device;

[0021] FIG2 is a schematic diagram of a planar structure of a display area in a silicon-based OLED display device;

[0022] FIG3 is a schematic diagram of the cross-sectional structure of a display area in a silicon-based OLED display device;

[0023] FIG4 is an equivalent circuit diagram of a pixel driving circuit;

[0024] FIG5 is a driving timing diagram of the pixel driving circuit shown in FIG4 ;

[0025] FIG6 is a schematic structural diagram of a gate driving circuit according to an exemplary embodiment of the present disclosure;

[0026] FIG7 is a working principle diagram of a first operation circuit according to an exemplary embodiment of the present disclosure;

[0027] FIG8 is an equivalent circuit diagram of a first operation circuit according to an exemplary embodiment of the present disclosure;

[0028] FIG9 is a working principle diagram of a second operation circuit according to an exemplary embodiment of the present disclosure;

[0029] FIG10 is an equivalent circuit diagram of a second operation circuit according to an exemplary embodiment of the present disclosure;

[0030] FIG11 is a working principle diagram of a third operation circuit according to an exemplary embodiment of the present disclosure;

[0031] FIG12 is an equivalent circuit diagram of a third operation circuit according to an exemplary embodiment of the present disclosure;

[0032] FIG13 is a schematic structural diagram of a logic operation circuit according to an exemplary embodiment of the present disclosure;

[0033] 14A and 14B are schematic diagrams of an embodiment of the present disclosure after forming patterns of an N-well region and an active region;

[0034] 15A and 15B are schematic diagrams of an embodiment of the present disclosure after a gate conductive layer pattern is formed;

[0035] 16A and 16B are schematic diagrams of an embodiment of the present disclosure after forming a P-type doping region pattern;

[0036] 17A and 17B are schematic diagrams of an embodiment of the present disclosure after forming an N-type doping region pattern;

[0037] FIG18 is a schematic diagram of an embodiment of the present disclosure after forming a second insulating layer pattern;

[0038] 19A and 19B are schematic diagrams of an embodiment of the present disclosure after forming a first conductive layer pattern;

[0039] FIG19C is an enlarged view of the first conductive layer in the first region in FIG19A;

[0040] FIG19D is an enlarged view of the first conductive layer in the second region in FIG19A;

[0041] FIG20 is a schematic diagram of an embodiment of the present disclosure after forming a third insulating layer pattern;

[0042] 21A and 21B are schematic diagrams of an embodiment of the present disclosure after forming a second conductive layer pattern;

[0043] 22A and 22B are schematic diagrams of an embodiment of the present disclosure after patterns of a fourth insulating layer and a third conductive layer are formed.

[0044] Description of the accompanying drawings:

[0045] 10—N-well region; 31—first P-type doping region; 32—second P-type doping region;

[0046] 41—first N-type doping region; 42—second N-type doping region; 51—first power line;

[0047] 52—ground line; 61—first signal line; 62—second signal line;

[0048] 63—third signal line; 64—fourth signal line; 65—fifth signal line;

[0049] 66—sixth signal line; 67—seventh signal line; 68—eighth signal line;

[0050] 69—Ninth signal line; 71—First signal adapter line; 72—Second signal adapter line;

[0051] 73—third signal adapter cable; 74—fourth signal adapter cable; 75—fifth signal adapter cable;

[0052] 76—Sixth signal adapter cable; 77—Seventh signal adapter cable; 78—Eighth signal adapter cable;

[0053] 79—Ninth signal adapter cable; 80—Tenth signal adapter cable; 81—Eleventh signal adapter cable;

[0054] 91—first signal trace; 92—second signal trace; 93—third signal trace;

[0055] 94—Fourth signal trace; 95—Fifth signal trace; 96—Sixth signal trace;

[0056] 97—seventh signal trace; 98—eighth signal trace; 100—shift register circuit;

[0057] 101—silicon substrate; 102—driving circuit layer; 103—light-emitting structure layer;

[0058] 104—first encapsulation layer; 105—color filter structure layer; 106—second encapsulation layer;

[0059] 107—cover layer; 200—logic operation circuit; 300—level converter;

[0060] 301—first NAND gate; 302—second NAND gate; 303—third NAND gate;

[0061] 400—row driver booster; 401—first inverter; 402—second inverter;

[0062] 403 — third inverter; 404 — fourth inverter; 405 — fifth inverter;

[0063] 406 —sixth inverter; 407 —seventh inverter; 408 —eighth inverter;

[0064] 409 — ninth inverter; 410 — tenth inverter; 501 — first NOR gate;

[0065] 502—Second NOR gate; 503—Third NOR gate; 504—Fourth NOR gate;

[0066] 505—fifth NOR gate; 510—two-way selector; 520—latch. DETAILED DESCRIPTION

[0067] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. Note that the embodiments can be implemented in a variety of different forms. A person of ordinary skill in the art can easily understand the fact that the methods and contents can be transformed into various forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. Unless there is a conflict, the embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other. In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits detailed descriptions of some known functions and known components. The drawings of the embodiments of the present disclosure only involve structures related to the embodiments of the present disclosure. Other structures can refer to the general design

[0068] The scales of the figures in this disclosure can be used as a reference for actual processes, but are not limited to such. For example, the width-to-length ratio of the channel, the thickness and spacing of the various film layers, and the width and spacing of the various signal lines can be adjusted according to actual needs. The number of pixels in the display device and the number of sub-pixels in each pixel are not limited to the numbers shown in the figures. The figures described in this disclosure are merely schematic structural diagrams, and one embodiment of this disclosure is not limited to the shapes or values ​​shown in the figures.

[0069] In this specification, ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements, and are not intended to limit the number.

[0070] In this specification, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the purpose of facilitating the description of this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limiting the present disclosure. The positional relationships of constituent elements may be appropriately changed depending on the direction in which each constituent element is described. Therefore, the present disclosure is not limited to the words and phrases described in the specification and may be appropriately replaced according to the circumstances.

[0071] In this specification, unless otherwise specified or limited, the terms "mounted," "connected," and "connected" should be understood broadly. For example, they can refer to fixed, removable, or integral connections; mechanical or electrical connections; direct connections, indirect connections through intermediaries, or internal communication between two components. Those skilled in the art will understand the specific meanings of these terms in this disclosure.

[0072] In this specification, a transistor refers to a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0073] In this specification, in order to distinguish the two electrodes of a transistor other than the gate electrode, one of the electrodes is directly described as the first electrode and the other as the second electrode. The first electrode can be the drain electrode and the second electrode can be the source electrode, or the first electrode can be the source electrode and the second electrode can be the drain electrode. In cases where transistors with opposite polarity are used or where the direction of current changes during circuit operation, the functions of the "source electrode" and "drain electrode" are sometimes interchangeable. Therefore, in this specification, the terms "source electrode" and "drain electrode" can be interchanged.

[0074] In this specification, "electrically connected" includes components connected together via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables the transfer of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0075] In this specification, "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°, and thus also includes a state where the angle is greater than -5° and less than 5°. Furthermore, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°, and thus also includes a state where the angle is greater than 85° and less than 95°.

[0076] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced with "conductive film." Similarly, "insulating film" may be replaced with "insulating layer."

[0077] In this specification, the term "same-layer arrangement" refers to a structure formed by patterning two (or more) structures using the same patterning process. The materials of these structures can be the same or different. For example, the precursor materials for forming the multiple structures arranged in the same layer can be the same, and the materials of the final structures can be the same or different.

[0078] The triangles, rectangles, trapezoids, pentagons or hexagons in this specification are not in the strict sense, but may be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances, and there may be chamfers, arc edges and deformations.

[0079] The term "about" in the present disclosure refers to a numerical value that is not strictly defined and allows for process and measurement errors.

[0080] FIG1 is a schematic diagram of the structure of a silicon-based OLED display device. As shown in FIG1 , the silicon-based OLED display device may include a display area and a non-display area. The display area may include multiple scan signal lines, multiple data signal lines, and multiple sub-pixels Pxij forming multiple pixel rows and multiple pixel columns. The multiple scan signal lines are respectively arranged in the multiple pixel rows, and the multiple data signal lines are respectively arranged in the multiple pixel columns. Each sub-pixel Pxij may include at least a pixel driving circuit and a light-emitting device. The pixel driving circuit is configured to provide the current required for light emission to the connected light-emitting device. The pixel driving circuit of each sub-pixel Pxij may be connected to the scan signal line of the corresponding pixel row and the data signal line of the corresponding pixel column. The sub-pixel Pxij may refer to the sub-pixel in the i-th pixel row and the j-th pixel column. The pixel driving circuit of the sub-pixel Pxij is respectively connected to the i-th scan signal line and the j-th data signal line, where i and j may be natural numbers. The non-display area may include a display driver integrated circuit (DDIC), a gate driver (GD), and a data driver (SD). The display driver circuit may include at least a timing controller (TCON). The timing controller is configured to generate timing signals required by the gate driver, such as a start signal (STV) and a clock signal (CKV), and send the timing signals to the gate driver. The gate driver is respectively connected to a plurality of scan signal lines in the display area, and the gate driver is configured to provide the required timing signals (timing) to the connected pixel driver circuit to realize the display progressive scanning function. The data driver is respectively connected to a plurality of data signal lines in the display area, and the data driver is configured to provide the required data signals (data) to the connected pixel driver circuit to realize the switching and control of the display screen.

[0081] In one exemplary embodiment, a silicon-based OLED display device may utilize a single-chip display architecture ("One Chip"), integrating a gate driver, data driver, clock control unit, image processing unit, and storage unit on a single chip. A chip with a One Chip architecture includes both digital and analog components, making it a mixed-signal chip.

[0082] In another exemplary embodiment, the silicon-based OLED display device can be a dual-chip display architecture (Two Chip), in which the gate driving device and the data driving device are integrated in the display substrate, and the clock control unit, the image processing unit, the mobile industry processor interface (MIPI) and the storage unit are integrated in one chip, which is bonded to the display substrate through the COC process.

[0083] Figure 2 is a schematic diagram of the planar structure of a display area in a silicon-based OLED display device. As shown in Figure 2, the display area may include multiple pixel units P arranged in a matrix on a plane parallel to the display device. At least one pixel unit P may include a first sub-pixel P1 that emits a first color light, a second sub-pixel P2 that emits a second color light, and a third sub-pixel P3 that emits a third color light. Each of the three sub-pixels may include a pixel driving circuit and a light-emitting device. The pixel driving circuit in the sub-pixel is respectively connected to a scan signal line and a data signal line. The pixel driving circuit is configured to receive a data voltage transmitted by the data signal line under the control of the scan signal line and output a corresponding current to the display light-emitting device. The light-emitting device in the sub-pixel is connected to the pixel driving circuit of the sub-pixel in which it is located. The light-emitting device is configured to emit light of corresponding brightness in response to the current output by the pixel driving circuit of the sub-pixel in which it is located.

[0084] In an exemplary embodiment, the first subpixel P1 may be a red (R) subpixel emitting red light, the second subpixel P2 may be a blue (B) subpixel emitting blue light, and the third subpixel P3 may be a green (G) subpixel emitting green light.

[0085] In an exemplary embodiment, the shape of the sub-pixels can be any one or more of a triangle, square, rectangle, rhombus, trapezoid, parallelogram, pentagon, hexagon, and other polygons. The three sub-pixels can be arranged in a horizontal parallel arrangement, a vertical parallel arrangement, a herringbone arrangement, etc., which is not limited in this disclosure. In other possible embodiments, the pixel unit can include four sub-pixels, which is not limited in this disclosure.

[0086] FIG3 is a schematic diagram of the cross-sectional structure of the display area in a silicon-based OLED display device, illustrating a structure that uses white light + color filter to achieve full color. As shown in FIG3 , in a direction perpendicular to the display device, the silicon-based OLED display device may include: a silicon substrate 101, a driving circuit layer 102 disposed on the silicon substrate 101, a light-emitting structure layer 103 disposed on the side of the driving circuit layer 102 away from the silicon substrate 101, a first encapsulation layer 104 disposed on the side of the light-emitting structure layer 103 away from the silicon substrate 101, a color filter structure layer 105 disposed on the side of the first encapsulation layer 104 away from the silicon substrate 101, a second encapsulation layer 106 disposed on the side of the color filter structure layer 105 away from the silicon substrate 101, and a cover layer 107 disposed on the side of the second encapsulation layer 106 away from the silicon substrate 101. In some possible implementations, the silicon-based OLED display device may include other film layers, which are not limited in this disclosure.

[0087] In an exemplary embodiment, the silicon substrate 101 may be a bulk silicon substrate or a silicon-on-insulator (SOI) substrate. The driving circuit layer 102 may be prepared on the silicon substrate 101 by a silicon semiconductor process. The driving circuit layer 102 may include a plurality of circuit units. The circuit unit may include at least a pixel driving circuit. The pixel driving circuit is connected to a scanning signal line and a data signal line, respectively. The pixel driving circuit may include a plurality of transistors and a storage capacitor. FIG3 shows only one transistor as an example. The transistor may include a gate electrode G, a source electrode S, and a drain electrode D. The gate electrode G, the source electrode S, and the drain electrode D may be connected to corresponding connection electrodes through tungsten metal-filled vias (i.e., tungsten vias, W-vias), respectively, and may be connected to other electrical structures (such as traces, etc.) through the connection electrodes.

[0088] In an exemplary embodiment, the light-emitting structure layer 103 may include a plurality of light-emitting devices, each of which may include at least an anode, an organic light-emitting layer, and a cathode. The anode may be connected to the drain electrode D of the transistor via a connecting electrode, the organic light-emitting layer is connected to the anode, the cathode is connected to the organic light-emitting layer, and the cathode is connected to the second power line. The organic light-emitting layer emits light under the drive of the anode and the cathode. In an exemplary embodiment, the organic light-emitting layer may include a light-emitting layer (EML), and any one or more of the following: a hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), a hole blocking layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL). In an exemplary embodiment, for a light-emitting device that emits white light, the organic light-emitting layers of all sub-pixels may be a common layer connected together.

[0089] In an exemplary embodiment, the first encapsulation layer 104 and the second encapsulation layer 106 can be encapsulated using a thin film encapsulation (TFE) method to ensure that external moisture cannot enter the light-emitting structure layer. The color filter structure layer 105 can include at least a red filter unit, a blue filter unit, and a green filter unit. The red filter unit is set in the red sub-pixel to filter the white light emitted by the light-emitting device into red light. The blue filter unit is set in the blue sub-pixel to filter the white light emitted by the light-emitting device into blue light. The green filter unit is set in the green sub-pixel to filter the white light emitted by the light-emitting device into green light. The cover layer 107 can be made of glass or a flexible plastic material such as colorless polyimide.

[0090] Figure 4 is an equivalent circuit diagram of a pixel driving circuit. As shown in Figure 4, the pixel driving circuit has a 4T2C structure, which can include four transistors (a first transistor T1, a second transistor T2, a third transistor T3, and a fourth transistor T4) and two storage capacitors (a first capacitor C1 and a second capacitor C2). The pixel driving circuit is connected to six signal lines (a first scan signal line S1, a second scan signal line S2, a third scan signal line S3, a data signal line DATA, a first power line VDD, and a second power line VSS).

[0091] In an exemplary embodiment, the pixel driving circuit may include a first node N1, a second node N2, and a third node N3. The first node N1 is connected to the second electrode of the first transistor T1, the gate electrode of the third transistor T3, and the first end of the first capacitor C1, respectively. The second node N2 is connected to the second electrode of the second transistor T2, the first electrode of the third transistor T3, the second end of the first capacitor C1, and the first end of the second capacitor C2, respectively. The third node N3 is connected to the second electrode of the third transistor T3 and the second electrode of the fourth transistor T4, respectively.

[0092] In an exemplary embodiment, the first transistor T1 can be referred to as a write switch transistor, a gate electrode of the first transistor T1 is connected to the first scan signal line S1, a first electrode of the first transistor T1 is connected to the data signal line DATA, and a second electrode of the first transistor T1 is connected to the first node N1.

[0093] In an exemplary embodiment, the second transistor T2 is called a display switch transistor, a gate electrode of the second transistor T2 is connected to the second scan signal line S2, a first electrode of the second transistor T2 is connected to the first power line VDD, and a second electrode of the second transistor T2 is connected to the second node N2.

[0094] In an exemplary embodiment, the third transistor T3 may be referred to as a driver transistor, a gate electrode of the third transistor T3 is connected to the first node N1, a first electrode of the third transistor T3 is connected to the second node N2, and a second electrode of the third transistor T3 is connected to the third node N3.

[0095] In an exemplary embodiment, the fourth transistor T4 can be referred to as a reset (Auto Zero) transistor, a gate electrode of the fourth transistor T4 is connected to the third scan signal line S3, a first electrode of the fourth transistor T4 is connected to the second power line VSS, and a second electrode of the fourth transistor T4 is connected to the third node N3.

[0096] In an exemplary embodiment, a first end of the first capacitor C1 is connected to the first node N1, a second end of the first capacitor C1 is connected to the second node N2, a first end of the second capacitor C2 is connected to the second node N2, and a second end of the second capacitor C2 is connected to the first power line VDD.

[0097] In an exemplary embodiment, the light emitting device XL may be an organic light emitting diode (OLED) including a stacked first electrode (anode), an organic light emitting layer, and a second electrode (cathode). The first electrode of the light emitting device XL is connected to the third node N3, and the second electrode of the light emitting device XL is connected to the common voltage line VCOM.

[0098] In an exemplary embodiment, the signal of the first power line VDD may be a continuously provided high level signal, and the signals of the second power line VSS and the common voltage line VCOM may be continuously provided low level signals.

[0099] In an exemplary embodiment, the first to fourth transistors T1 to T4 may be P-type transistors (PMOS) or N-type transistors (NMOS). For example, the first to fourth transistors T1 to T4 are all P-type transistors. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the difficulty of manufacturing the display substrate, and improve the product yield.

[0100] In an exemplary embodiment, the first to fourth transistors T1 to T4 may include P-type transistors and N-type transistors. For example, the first to third transistors T1 to T3 may be P-type transistors, and the fourth transistor T4 may be an N-type transistor, as shown in FIG4 .

[0101] FIG5 is a driving timing diagram of the pixel driving circuit shown in FIG4. As shown in FIG5, in an exemplary embodiment, the operation process of the pixel driving circuit may include:

[0102] The first phase A1 can be called the initialization phase. The signals of the first scan signal line S1 and the second scan signal line S2 are low-level signals, and the signal of the third scan signal line S3 is a high-level signal, so that the first transistor T1, the second transistor T2 and the fourth transistor T4 are turned on. The first transistor T1 is turned on so that the bias voltage Vofs output by the data signal line DATA is written into the first capacitor C1, and the potential Vs of the first node N1 (i.e., the gate electrode of the third transistor T3) is Vofs. The second transistor T2 is turned on so that the first power supply voltage ELVDD output by the first power line VDD is written into the second node N2, and the potential Vg of the second node N2 (i.e., the first electrode of the third transistor T3) is ELVDD. At this time, the gate-source voltage Vgs of the third transistor T3 is ELVDD-Vofs, and the storage voltage V of the first capacitor C1 is V cs=ELVDD-Vofs, the potential Vd of the third node N3 (ie, the second electrode of the third transistor T3) = Vg+Vth, preparing for the next stage of discharge. ofs >|Vth|, where Vth is the threshold voltage of the third transistor T3.

[0103] The second stage A2 can be called the self-discharge stage. The signal of the third scanning signal line S3 is a high-level signal, and the fourth transistor T4 is continuously turned on. The signal of the first scanning signal line S13 changes from a low-level signal to a high-level signal, causing the first transistor T1 to be disconnected first, and the first node N1 to float. Subsequently, the signal of the second scanning signal line S2 changes from a low-level signal to a high-level signal, causing the second transistor T2 to be disconnected, and the second node N2 forms a loop through the turned-on third transistor T3, the third node N3 and the turned-on fourth transistor T4, and begins to discharge, and the potential of the second node N2 drops. Because the first node N1 is floating, the voltage difference across the first capacitor C1 remains unchanged, and thus the potential of the first node N1 drops as the potential of the second node N2 drops. Due to the back-gate effect of the third transistor T3, the gate-source voltage Vgs of the third transistor T3 remains unchanged, and thus the equivalent threshold voltage |V th_EF |As the potential of the second node N2 decreases, the equivalent threshold voltage of the third transistor T3 gradually increases. th_EF |=α(ELVDD-Vs)+|Vth|, α is the back gate coefficient. When the equivalent threshold voltage of the third transistor T3 |V th_EF When Vgs increases to the gate-source voltage Vgs of the third transistor T3, the third transistor T3 is turned off and the second node N2 stops discharging.

[0104] The third stage A3 can be called the data writing stage and the threshold compensation stage. The signal of the second scan signal line S2 is a high-level signal, and the second transistor T2 is continuously off. The signal of the third scan signal line S3 is a high-level signal, and the fourth transistor T4 is continuously on. The signal of the first scan signal line S13 changes from a high-level signal to a low-level signal, turning on the first transistor T1. Turning on the first transistor T1 causes the data voltage Vdata output by the data signal line DATA to be written to the first node N1, and the potential of the first node N1 changes from Vofs to Vdata. Because the second node N2 is floating, threshold compensation can be achieved in this stage.

[0105] The fourth phase A4 can be referred to as the light-emitting phase. The signals on the second and third scan signal lines S2 and S3 are low-level signals, while the signal on the first scan signal line S1 is high-level. This turns on the second transistor T2, while the first and fourth transistors T1 and T4 are off. Turning on the second transistor T2 causes the power supply voltage output from the first power line VDD to provide a driving voltage to the first electrode of the light-emitting device EL through the turned-on second and third transistors T2 and T3, driving the light-emitting device EL to emit light.

[0106] In the light-emitting stage, the driving current of the third transistor T3 is not affected by the threshold voltage of the third transistor T3, eliminating the influence of the threshold voltage of the third transistor T3 on the driving current, ensuring uniform display brightness of the display product and improving the display effect of the entire display product.

[0107] An exemplary embodiment of the present disclosure provides a display substrate, comprising a display area and a non-display area; the display area comprises a plurality of sub-pixels forming a plurality of pixel rows and a plurality of pixel columns, at least one sub-pixel comprising a pixel driving circuit and at least one scan signal line, the scan signal line being configured to provide a scan signal to the connected pixel driving circuit; the non-display area comprises a plurality of cascaded gate driving circuits, at least one gate driving circuit being connected to a scan signal line in a pixel row in the display area; at least one gate driving circuit comprises a shift register circuit, a logic operation circuit, a level converter, and a row drive enhancement circuit sequentially arranged in a direction close to the display area. The shift register circuit is configured to generate a row-by-row shift timing according to a timing signal, the logic operation circuit is configured to generate a target timing through a logic operation, the level converter is configured to perform voltage domain conversion on the target timing, and the row drive enhancer is configured to enhance the converted signal; the logic operation circuit includes at least a first operation circuit for generating a write switch signal, a second operation circuit for generating a display switch signal, and a third operation circuit for generating a display reset signal, the second operation circuit is arranged on a side of the first operation circuit close to the display area, and the third operation circuit is arranged on a side of the second operation circuit close to the display area.

[0108] In an exemplary embodiment, the first operation circuit includes a plurality of transistor groups arranged in sequence along a pixel row direction, at least one transistor group includes a P-type transistor and an N-type transistor arranged on one side of the P-type transistor in a pixel column direction, and the plurality of transistor groups form a first NAND gate, a first inverter, a first NOR gate, a second inverter, a second NOR gate, a fourth inverter, a third inverter, a third NOR gate, and a two-way selector arranged in sequence along a direction close to the display area.

[0109] In an exemplary embodiment, the second operation circuit includes a plurality of transistor groups sequentially arranged along a pixel row direction, at least one transistor group includes a P-type transistor and an N-type transistor arranged on one side of the P-type transistor in a pixel column direction, and the plurality of transistor groups form a fifth inverter, a sixth inverter, a seventh inverter, an eighth inverter, a ninth inverter, a tenth inverter, a latch, a fourth NOR gate, and a second NAND gate sequentially arranged along a direction close to the display area.

[0110] In an exemplary embodiment, the third operational circuit includes a plurality of transistor groups sequentially arranged along a pixel row direction, at least one transistor group includes a P-type transistor and an N-type transistor arranged on one side of the P-type transistor in a pixel column direction, and the plurality of transistor groups form a fifth NOR gate and a third NAND gate sequentially arranged in a direction close to the display area.

[0111] The technical solution of the display substrate disclosed herein is described below through exemplary embodiments.

[0112] Figure 6 is a structural schematic diagram of a gate drive circuit of an exemplary embodiment of the present disclosure. In an exemplary embodiment, the gate drive device can be arranged in a non-display area, can be located on one side of the pixel row direction of the display area, or can be located on both sides of the pixel row direction of the display area. The gate drive device can include multiple cascaded gate drive circuits, at least one gate drive circuit is connected to the scan signal line in a pixel row in the display area, and provides a scan signal to the connected scan signal line. When the gate drive device is arranged on both sides of the pixel row direction of the display area, the scan signal line in the pixel row is driven by two gate drive circuits to form a bilateral drive structure, which can ensure the driving capability of high pixel density and avoid distortion of the drive signal. As shown in Figure 6, the gate drive circuit may include a shift register circuit 100, a logical operation circuit (Logical Transition Unit) 200, a level converter (Level shifter) 300 and a line driver enhancer (Line Driver) 400.

[0113] In an exemplary embodiment, the shift register circuit 100 may be a shift register circuit composed of flip-flops (D flip-flops). The shift register circuit 100 is connected to the display driver circuit and receives timing signals generated by the display driver circuit. The timing signals may include a start signal STV and a clock signal CKV. The D flip-flops are configured to shift register the received timing signals to initially generate a timing sequence that can be shifted row by row. The logic operation circuit 200 is connected to the shift register circuit 100 and configured to perform a logic operation on the shifted signals to generate a plurality of target timing sequences with different waveforms. The level converter 300 is connected to the logic operation circuit 200 and configured to perform voltage domain conversion on the target timing sequences. The row driver booster 400 is connected to the level converter 300 and configured to boost the converted signals to enhance output capability and output scan signals to the display area.

[0114] In an exemplary embodiment, for the pixel driving circuit in the display area including a first scan signal line S1, a second scan signal line S2 and a third scan signal line S3, the output circuit 300 may include three output sub-circuits, one output sub-circuit is connected to the first scan signal line S1 of a pixel row in the display area, and is configured to output a first scan signal to the display area, another output sub-circuit is connected to the second scan signal line S2 of a pixel row in the display area, and is configured to output a second scan signal to the display area, and yet another output sub-circuit is connected to the third scan signal line S3 of a pixel row in the display area, and is configured to output a third scan signal to the display area.

[0115] In an exemplary embodiment, the first scan signal may be referred to as a write switch (WS) signal, configured to control the on / off switching of a first transistor T1 in a pixel driving circuit. The second scan signal may be referred to as a display switch (DS) signal, configured to control the on / off switching of a second transistor T2 in the pixel driving circuit. The third scan signal may be referred to as a display reset (Auto Zero, AZ) signal, configured to control the on / off switching of a fourth transistor T4 in the pixel driving circuit.

[0116] In an exemplary embodiment, since signals such as the start signal and the clock signal are output by the display driver circuit, their voltage domains are inconsistent with the voltage domains of the pixel driver circuit. By converting the voltage through a level converter, the required voltage (0V to -2V & -5V) is introduced to ensure that the voltage of the output gate drive signal matches the pixel driver circuit.

[0117] In an exemplary embodiment, the start signal STV may be referred to as a frame start signal, with a period of one frame, and the clock signal CKV may be referred to as a row driving clock signal, with a period of one row.

[0118] In an exemplary embodiment, the logic operation circuit may include at least a first operation circuit, a second operation circuit, and a third operation circuit, the first operation circuit being configured to generate a write switch signal WS, the second operation circuit being configured to generate a display switch signal DS, and the third operation circuit being configured to generate a display reset signal AZ.

[0119] FIG7 is a diagram illustrating the working principle of a first arithmetic circuit according to an exemplary embodiment of the present disclosure. The first arithmetic circuit may include nine components, namely four inverters (INVX), three NOR gates (NOR), one NAND gate (NAND), and one two-way selector (MUX2). As shown in FIG7 , the first arithmetic circuit may include a first NAND gate 301, a first inverter 401, a second inverter 402, a third inverter 403, a fourth inverter 404, a first NOR gate 501, a second NOR gate 502, a third NOR gate 503, and a two-way selector 510.

[0120] In an exemplary embodiment, a first input terminal of the first NAND gate 301 is connected to the second input terminal B_Qn of the logic operation circuit, and a second input terminal is connected to the third input terminal C_Qn of the logic operation circuit. An output terminal of the first NAND gate 301 is connected to the input terminal of the first inverter 401, an output terminal of the first inverter 401 is connected to the first input terminal of the first NOR gate 501, a second input terminal of the first NOR gate 501 is connected to the first input terminal A_Qn of the logic operation circuit, an output terminal of the first NOR gate 501 is connected to the input terminal of the second inverter 402, an output terminal of the second inverter 402 is connected to the first input terminal of the second NOR gate 502, a second input terminal of the second NOR gate 502 is connected to the clock signal terminal CKV4 of the logic operation circuit, an output terminal of the second NOR gate 502 is connected to the input terminal of the fourth inverter 404, and an output terminal of the fourth inverter 404 is connected to the second input terminal of the two-way selector 510. The input of the third inverter 403 is connected to the second reset terminal LF_pulse2 of the logic operation circuit. The output of the third inverter 403 is connected to the second input terminal of the third NOR gate 503. The first input of the third NOR gate 503 is connected to the first reset terminal LF_pulse1 of the logic operation circuit. The output of the third NOR gate 503 is connected to the control terminal of the two-way selector 510. The first input of the two-way selector 510 is connected to the first input terminal A_Qn of the logic operation circuit. The output of the two-way selector 510 serves as the output terminal of the first operation circuit and is connected to the input terminal of a level shifter, outputting the output signal WSn of the first operation circuit to the level shifter.

[0121] In the exemplary embodiment, the first operation circuit operates as follows: the first NAND gate 301 and the first inverter 401 perform an AND operation on the second input signal at the second input terminal B_Qn and the third input signal at the third input terminal C_Qn. The first NOR gate 501 and the second inverter 402 perform an OR operation on the result of the AND operation and the first input signal at the first input terminal A_Qn. The second NOR gate 502 and the fourth inverter 404 perform an OR operation on the result of the OR operation and the clock signal at the clock signal terminal CKV4, i.e., F1 = B_Qn & C_Qn + A_Qn' + CKV4. The third inverter 403 inverts the second reset signal at the second reset terminal LF_pulse2. The third NOR gate 503 performs a NOR operation on the inverted result and the first reset signal at the first reset terminal LF_pulse1, i.e., F2 = ┐(LF_pulse2' + LF_pulse1). F1 serves as a control signal of the two-way selector 510 . When F1=1, the output signal WSn of the two-way selector 510 is A_Qn. When F1=0, the output signal WSn of the two-way selector 510 is F2 .

[0122] FIG8 is an equivalent circuit diagram of a first operation circuit of an exemplary embodiment of the present disclosure. As shown in FIG8 , in the display substrate of the embodiment of the present disclosure, the first operation circuit of the logic operation circuit may include 30 transistors. Among them, the first inverter 401, the second inverter 402, the third inverter 403, and the fourth inverter 404 each include 1 P-type transistor and 1 N-type transistor, the first NAND gate 301, the first NOR gate 501, the second NOR gate 502, and the third NOR gate 503 each include 2 P-type transistors and 2 N-type transistors, and the two-way selector 510 includes 3 P-type transistors and 3 N-type transistors.

[0123] In an exemplary embodiment, the first NAND gate 301, the first inverter 401, the first NOR gate 501, the second inverter 402, the second NOR gate 502, the fourth inverter 404, the third inverter 403, the third NOR gate 503 and the two-way selector 510 can be arranged in sequence along the first direction X (the direction close to the display area).

[0124] In an exemplary embodiment, a first P-type transistor P1, a first N-type transistor N1, a second P-type transistor P2, and a second N-type transistor N2 form a first NAND gate 301. The gate electrode of the first P-type transistor P1 and the gate electrode of the first N-type transistor N1 are interconnected and connected to the third input terminal C_Qn of the logic operation circuit. The gate electrode of the second P-type transistor P2 and the gate electrode of the second N-type transistor N2 are interconnected and connected to the second input terminal B_Qn of the logic operation circuit. The first electrode of the first P-type transistor P1 and the first electrode of the second P-type transistor P2 are both connected to the first power supply line VDD. The second electrode of the first P-type transistor P1 and the second electrode of the second P-type transistor P2 are interconnected and connected to the second electrode of the second N-type transistor N2, the gate electrode of the third P-type transistor P3, and the gate electrode of the third N-type transistor N3, respectively. The first electrode of the first N-type transistor N1 is connected to the ground line GND, and the second electrode of the first N-type transistor N1 is connected to the first electrode of the second N-type transistor N2.

[0125] In an exemplary embodiment, a third P-type transistor P3 and a third N-type transistor N3 form a first inverter 401. A gate electrode of the third P-type transistor P3 and a gate electrode of the third N-type transistor N3 are connected to each other and are connected to the second electrode of the first P-type transistor P1, the second electrode of the second P-type transistor P2, and the second electrode of the second N-type transistor N2, respectively. A first electrode of the third P-type transistor P3 is connected to a first power supply line VDD, a first electrode of the third N-type transistor N3 is connected to a ground line GND, and a second electrode of the third P-type transistor P3 and a second electrode of the third N-type transistor N3 are connected to each other and are connected to the gate electrode of the fifth P-type transistor P5 and the gate electrode of the fifth N-type transistor N5, respectively.

[0126] In an exemplary embodiment, a fourth P-type transistor P4, a fourth N-type transistor N4, a fifth P-type transistor P5, and a fifth N-type transistor N5 form a first NOR gate 501. The gate electrode of the fourth P-type transistor P4 and the gate electrode of the fourth N-type transistor N4 are connected to each other and to the first input terminal A_Qn of the logic operation circuit. The gate electrode of the fifth P-type transistor P5 and the gate electrode of the fifth N-type transistor N5 are connected to each other and to the second electrode of the third P-type transistor P3 and the second electrode of the third N-type transistor N3, respectively. A first electrode of the fourth P-type transistor P4 is connected to the first power supply line VDD. A second electrode of the fourth P-type transistor P4 is connected to the first electrode of the fifth P-type transistor P5. A first electrode of the fourth N-type transistor N4 and a first electrode of the fifth N-type transistor N5 are both connected to the ground line GND. A second electrode of the fourth N-type transistor N4 and a second electrode of the fifth N-type transistor N5 are connected to each other and to the second electrode of the fifth P-type transistor P5, the gate electrode of the sixth P-type transistor P6, and the gate electrode of the sixth N-type transistor N6, respectively.

[0127] In an exemplary embodiment, the sixth P-type transistor P6 and the sixth N-type transistor N6 constitute the second inverter 402. The gate electrode of the sixth P-type transistor P6 and the gate electrode of the sixth N-type transistor N6 are connected to each other and are respectively connected to the second electrode of the fifth P-type transistor P5, the second electrode of the fourth N-type transistor N4, and the second electrode of the fifth N-type transistor N5. A first electrode of the sixth P-type transistor P6 is connected to the first power supply line VDD, a first electrode of the sixth N-type transistor N6 is connected to the ground line GND, and a second electrode of the sixth P-type transistor P6 and the second electrode of the sixth N-type transistor N6 are connected to each other and are respectively connected to the gate electrode of the eighth P-type transistor P8 and the gate electrode of the eighth N-type transistor N8.

[0128] In an exemplary embodiment, a seventh P-type transistor P7, a seventh N-type transistor N7, an eighth P-type transistor P8, and an eighth N-type transistor N8 form a second NOR gate 502. The gate electrode of the seventh P-type transistor P7 and the gate electrode of the seventh N-type transistor N7 are connected to each other and to the clock signal terminal CKV4 of the logic operation circuit. The gate electrode of the eighth P-type transistor P8 and the gate electrode of the eighth N-type transistor N8 are connected to each other and to the second electrode of the sixth P-type transistor P6 and the second electrode of the sixth N-type transistor N6, respectively. A first electrode of the seventh P-type transistor P7 is connected to the first power supply line VDD. A second electrode of the seventh P-type transistor P7 is connected to the first electrode of the eighth P-type transistor P8. A first electrode of the seventh N-type transistor N7 and a first electrode of the eighth N-type transistor N8 are both connected to the ground line GND. A second electrode of the seventh N-type transistor N7 and a second electrode of the eighth N-type transistor N8 are connected to each other and to the second electrode of the eighth P-type transistor P8, the gate electrode of the ninth P-type transistor P9, and the gate electrode of the ninth N-type transistor N9, respectively.

[0129] In an exemplary embodiment, a ninth P-type transistor P9 and a ninth N-type transistor N9 form a fourth inverter 404. The gate electrode of the ninth P-type transistor P9 and the gate electrode of the ninth N-type transistor N9 are connected to each other and are connected to the second electrode of the seventh N-type transistor N7, the second electrode of the eighth N-type transistor N8, and the second electrode of the eighth P-type transistor P8, respectively. A first electrode of the ninth P-type transistor P9 is connected to the first power supply line VDD, a first electrode of the ninth N-type transistor N9 is connected to the ground line GND, and a second electrode of the ninth P-type transistor P9 and the second electrode of the ninth N-type transistor N9 are connected to each other and are connected to the first electrode of the fifteenth P-type transistor P15 and the first electrode of the fifteenth N-type transistor N15, respectively.

[0130] In an exemplary embodiment, the tenth P-type transistor P10 and the tenth N-type transistor N10 form a third inverter 403. The gate electrode of the tenth P-type transistor P10 and the gate electrode of the tenth N-type transistor N10 are connected to each other and to the second reset terminal LF_pulse2 of the logic operation circuit. The first electrode of the tenth P-type transistor P10 is connected to the first power line VDD. The first electrode of the tenth N-type transistor N10 is connected to the first power line VDD. The second electrode of the tenth P-type transistor P10 and the second electrode of the tenth N-type transistor N10 are connected to each other and to the gate electrode of the eleventh P-type transistor P11 and the gate electrode of the eleventh N-type transistor N11, respectively.

[0131] In an exemplary embodiment, the eleventh P-type transistor P11, the eleventh N-type transistor N11, the twelfth P-type transistor P12, and the twelfth N-type transistor N12 constitute a third NOR gate 503. The gate electrode of the eleventh P-type transistor P11 and the gate electrode of the eleventh N-type transistor N11 are connected to each other and are connected to the second electrode of the tenth P-type transistor P10 and the second electrode of the tenth N-type transistor N10, respectively. The gate electrode of the twelfth P-type transistor P12 and the gate electrode of the twelfth N-type transistor N12 are connected to each other and are connected to the first reset terminal LF_pulse1 of the logic operation circuit. The first electrode of the eleventh P-type transistor P11 is connected to the first power line VDD, and the second electrode of the eleventh P-type transistor P11 is connected to the tenth P-type transistor P10. The first electrode of the second P-type transistor P12 is connected, the first electrode of the eleventh N-type transistor N11 and the first electrode of the twelfth N-type transistor N12 are both connected to the ground line GND, the second electrode of the eleventh N-type transistor N11 and the second electrode of the twelfth N-type transistor N12 are connected to each other, and are respectively connected to the second electrode of the twelfth P-type transistor P12, the gate electrode of the thirteenth P-type transistor P13, the gate electrode of the thirteenth N-type transistor N13, the gate electrode of the fourteenth N-type transistor N14 and the gate electrode of the fifteenth P-type transistor P15.

[0132] In an exemplary embodiment, the thirteenth P-type transistor P13, the thirteenth N-type transistor N13, the fourteenth P-type transistor P14, the fourteenth N-type transistor N14, the fifteenth P-type transistor P15, and the fifteenth N-type transistor N15 constitute a two-way selector 510. The gate electrode of the thirteenth P-type transistor P13 and the gate electrode of the thirteenth N-type transistor N13 are connected to each other, and are respectively connected to the second electrode of the eleventh N-type transistor N11, the second electrode of the twelfth N-type transistor N12, the second electrode of the twelfth P-type transistor P12, the gate electrode of the fourteenth N-type transistor N14, and the gate electrode of the fifteenth P-type transistor P15. A first electrode of the thirteenth P-type transistor P13 is connected to the first power supply line VDD, a first electrode of the thirteenth N-type transistor N13 is connected to the ground line GND, a second electrode of the thirteenth P-type transistor P13 and the second electrode of the thirteenth N-type transistor N13 are connected to each other, and are respectively connected to the gate electrode of the fourteenth P-type transistor P14 and the gate electrode of the fifteenth N-type transistor N15. The first electrode of the fourteenth P-type transistor P14 and the first electrode of the fourteenth N-type transistor N14 are connected to each other and to the first input terminal A_Qn of the logic operation circuit. The first electrode of the fifteenth P-type transistor P15 and the first electrode of the fifteenth N-type transistor N15 are connected to each other and to the second electrode of the ninth P-type transistor P9 and the second electrode of the ninth N-type transistor N9, respectively. The second electrode of the fourteenth P-type transistor P14, the second electrode of the fourteenth N-type transistor N14, the second electrode of the fifteenth P-type transistor P15 and the second electrode of the fifteenth P-type transistor P15 are connected to each other and, as the output terminal of the first operation circuit, are connected to the input terminal of a level converter and output the output signal WSn of the first operation circuit to the level converter.

[0133] FIG9 is a diagram illustrating the working principle of a second arithmetic circuit according to an exemplary embodiment of the present disclosure. The second arithmetic circuit may include nine components, each of which is composed of six inverters, one NOR gate, one NAND gate, and one latch (D-Latch). As shown in FIG9 , the second arithmetic circuit may include a second NAND gate 302, a fifth inverter 405, a sixth inverter 406, a seventh inverter 407, an eighth inverter 408, a ninth inverter 409, a tenth inverter 410, a fourth NOR gate 504, and a latch 520.

[0134] In an exemplary embodiment, an input terminal of the fifth inverter 405 is connected to an output terminal of the first operation circuit to receive an output signal WSn of the first operation circuit. An output terminal of the fifth inverter 405 is connected to an input terminal of the sixth inverter 406. An output terminal of the sixth inverter 406 is connected to an input terminal of the seventh inverter 407. An output terminal of the seventh inverter 407 is connected to an input terminal of the eighth inverter 408. An output terminal of the eighth inverter 408 is connected to an input terminal of the ninth inverter 409. An output terminal of the ninth inverter 409 is connected to an input terminal of the tenth inverter 410. An output terminal of the tenth inverter 410 is connected to an enable signal terminal EN of the latch 520. The input end of the register 520 is connected to the second input end B_Qn of the logic operation circuit, the output end of the latch 520 is connected to the second input end of the fourth NOR gate 504, the first input end of the fourth NOR gate 504 is connected to the proportion control end D_Qn of the logic operation circuit, the output end of the fourth NOR gate 504 is connected to the first input end of the second NAND gate 302, the second input end of the second NAND gate 302 is connected to the second reset end LF_pulse2 of the logic operation circuit, and the output end of the second NAND gate 302 serves as the output end of the second operation circuit and is connected to the input end of another level converter, outputting the output signal DSn of the second operation circuit to the level converter.

[0135] In an exemplary embodiment, the second operation circuit operates as follows: the fifth inverter 405 to the tenth inverter 410 delay the input signal WSn of the second operation circuit and then input it to the enable signal terminal EN of the latch 520, which serves as the enable signal for the latch 520. The second input signal at the second input terminal B_Qn of the logic operation circuit serves as the input signal for the latch 520. When the enable signal at the enable signal terminal EN is low, the output of the latch 520 remains unchanged. When the enable signal at the enable signal terminal EN is high, the output of the latch 520 changes with the second input signal. Subsequently, the fourth NOR gate 504 performs a NOR operation on the duty control signal at the duty control terminal D_Qn and the output signal of the latch 520. The second NAND gate 302 performs a NAND operation on the NOR operation result and the second reset signal at the second reset terminal LF_pulse2. The logical expression is: DSn = ┐(┐(D_Qn+Q) & LF_pulse2). Where Q is the output signal of latch 520, LF_pulse2 is the reset signal, and during normal operation, the output signal of the second arithmetic circuit, DSn, equals D_Qn + Q. When a global reset is required, DSn = 0, indicating a global reset. D_Qn is the emission duty control signal. When the emission duty is 100%, D_Qn remains low, and DSn = Q. To adjust the emission duty, adjust the duty cycle of D_Qn.

[0136] FIG10 is an equivalent circuit diagram of a second operation circuit of an exemplary embodiment of the present disclosure. As shown in FIG10 , in the display substrate of the embodiment of the present disclosure, the second operation circuit of the logic operation circuit may include 38 transistors. Among them, the second NAND gate 302 includes 2 P-type transistors and 2 N-type transistors, the fifth inverter 405, the sixth inverter 406, the seventh inverter 407, the eighth inverter 408, the ninth inverter 409, and the tenth inverter 410 each include 1 P-type transistor and 1 N-type transistor, the fourth NOR gate 504 includes 2 P-type transistors and 2 N-type transistors, and the latch 520 includes 9 P-type transistors and 9 N-type transistors.

[0137] In an exemplary embodiment, the fifth inverter 405, the sixth inverter 406, the seventh inverter 407, the eighth inverter 408, the ninth inverter 409, the tenth inverter 410, the latch 520, the fourth NOR gate 504 and the second NAND gate 302 can be arranged in sequence along the first direction X (the direction close to the display area).

[0138] In the exemplary embodiment, the twenty-first P-type transistor P21 and the twenty-first N-type transistor N21 constitute a fifth inverter 405. The gate electrode of the twenty-first P-type transistor P21 and the gate electrode of the twenty-first N-type transistor N21 are connected to each other and to the write switch signal terminal WSn′ of the logic operation circuit. A first electrode of the twenty-first P-type transistor P21 is connected to the first power supply line VDD, a first electrode of the twenty-first N-type transistor N21 is connected to the ground line GND, and a second electrode of the twenty-first P-type transistor P21 and the second electrode of the twenty-first N-type transistor N21 are connected to each other and to the gate electrode of the twenty-second P-type transistor P22 and the gate electrode of the twenty-second N-type transistor N22, respectively.

[0139] In the exemplary embodiment, the twenty-second P-type transistor P22 and the twenty-second N-type transistor N22 constitute the sixth inverter 406. The gate electrode of the twenty-second P-type transistor P22 and the gate electrode of the twenty-second N-type transistor N22 are connected to each other and to the second electrode of the twenty-first P-type transistor P21 and the second electrode of the twenty-first N-type transistor N21, respectively. The first electrode of the twenty-second P-type transistor P22 is connected to the first power supply line VDD, the first electrode of the twenty-second N-type transistor N22 is connected to the ground line GND, the second electrode of the twenty-second P-type transistor P22 and the second electrode of the twenty-second N-type transistor N22 are connected to each other and to the gate electrode of the twenty-third P-type transistor P23 and the gate electrode of the twenty-third N-type transistor N23, respectively.

[0140] In the exemplary embodiment, the twenty-third P-type transistor P23 and the twenty-third N-type transistor N23 constitute the seventh inverter 407. The gate electrode of the twenty-third P-type transistor P23 and the gate electrode of the twenty-third N-type transistor N23 are connected to each other and to the second electrode of the twenty-second P-type transistor P22 and the second electrode of the twenty-second N-type transistor N22, respectively. A first electrode of the twenty-third P-type transistor P23 is connected to the first power supply line VDD, a first electrode of the twenty-third N-type transistor N23 is connected to the ground line GND, and a second electrode of the twenty-third P-type transistor P23 and the second electrode of the twenty-third N-type transistor N23 are connected to each other and to the gate electrode of the twenty-fourth P-type transistor P24 and the gate electrode of the twenty-fourth N-type transistor N24, respectively.

[0141] In the exemplary embodiment, the twenty-fourth P-type transistor P24 and the twenty-fourth N-type transistor N24 constitute the eighth inverter 408. The gate electrode of the twenty-fourth P-type transistor P24 and the gate electrode of the twenty-fourth N-type transistor N24 are connected to each other and to the second electrode of the twenty-third P-type transistor P23 and the second electrode of the twenty-third N-type transistor N23, respectively. The first electrode of the twenty-fourth P-type transistor P24 is connected to the first power supply line VDD, the first electrode of the twenty-fourth N-type transistor N24 is connected to the ground line GND, the second electrode of the twenty-fourth P-type transistor P24 and the second electrode of the twenty-fourth N-type transistor N24 are connected to each other and to the gate electrode of the twenty-fifth P-type transistor P25 and the gate electrode of the twenty-fifth N-type transistor N25, respectively.

[0142] In the exemplary embodiment, the twenty-fifth P-type transistor P25 and the twenty-fifth N-type transistor N25 constitute a ninth inverter 409. The gate electrode of the twenty-fifth P-type transistor P25 and the gate electrode of the twenty-fifth N-type transistor N25 are connected to each other and to the second electrode of the twenty-fourth P-type transistor P24 and the second electrode of the twenty-fourth N-type transistor N24, respectively. A first electrode of the twenty-fifth P-type transistor P25 is connected to the first power supply line VDD, a first electrode of the twenty-fifth N-type transistor N25 is connected to the ground line GND, and a second electrode of the twenty-fifth P-type transistor P25 and the second electrode of the twenty-fifth N-type transistor N25 are connected to each other and to the gate electrode of the twenty-sixth P-type transistor P26 and the gate electrode of the twenty-sixth N-type transistor N26, respectively.

[0143] In the exemplary embodiment, the twenty-sixth P-type transistor P26 and the twenty-sixth N-type transistor N26 constitute the tenth inverter 410. The gate electrode of the twenty-sixth P-type transistor P26 and the gate electrode of the twenty-sixth N-type transistor N26 are connected to each other and to the second electrode of the twenty-fifth P-type transistor P25 and the second electrode of the twenty-fifth N-type transistor N25, respectively. The first electrode of the twenty-sixth P-type transistor P26 is connected to the first power supply line VDD, the first electrode of the twenty-sixth N-type transistor N26 is connected to the ground line GND, and the second electrode of the twenty-sixth P-type transistor P26 and the second electrode of the twenty-sixth N-type transistor N26 are connected to each other and to the gate electrode of the twenty-ninth P-type transistor P29, the gate electrode of the twenty-ninth N-type transistor N29, the gate electrode 232P of the thirty-second P-type transistor P32, and the gate electrode of the thirty-second N-type transistor N32, respectively.

[0144] In an exemplary embodiment, the twenty-seventh to thirty-fifth P-type transistors P27 to P35 and the twenty-seventh to thirty-fifth N-type transistors N27 to N35 constitute the latch 520 .

[0145] In an exemplary embodiment, the gate electrode of the twenty-seventh P-type transistor P27 and the gate electrode of the twenty-seventh N-type transistor N27 are interconnected and respectively connected to the second input terminal B_Qn of the logic operation circuit, the gate electrode of the thirty-third P-type transistor P33 and the gate electrode of the thirty-third N-type transistor N33, the first electrode of the twenty-seventh P-type transistor P27 is connected to the first power supply line VDD, the first electrode of the twenty-seventh N-type transistor N27 is connected to the ground line GND, the second electrode of the twenty-seventh P-type transistor P27 and the second electrode of the twenty-seventh N-type transistor N27 are interconnected and respectively connected to the gate electrode of the twenty-eighth P-type transistor P28 and the gate electrode of the twenty-eighth N-type transistor N28.

[0146] In the exemplary embodiment, the gate electrode of the twenty-eighth P-type transistor P28 and the gate electrode of the twenty-eighth N-type transistor N28 are connected to each other and are respectively connected to the second electrode of the twenty-seventh P-type transistor P27 and the second electrode of the twenty-seventh N-type transistor N27. The gate electrode of the twenty-ninth P-type transistor P29 and the gate electrode of the twenty-ninth N-type transistor N29 are connected to each other and are respectively connected to the second electrode of the twenty-sixth P-type transistor P26, the second electrode of the twenty-sixth N-type transistor N26, the gate electrode 232P of the thirty-second P-type transistor P32, and the gate electrode of the thirty-second N-type transistor N32. In addition, the first electrode of the twenty-eighth P-type transistor P28 and the first electrode of the twenty-ninth P-type transistor P29 are both connected to the first power supply line VDD, the second electrode of the twenty-eighth P-type transistor P28 and the second electrode of the twenty-ninth P-type transistor P29 are connected to each other, and are respectively connected to the second electrode of the twenty-eighth N-type transistor N28, the gate electrode of the thirtieth P-type transistor P30 and the gate electrode of the thirtieth N-type transistor N30, the first electrode of the twenty-ninth N-type transistor N29 is connected to the ground line GND, and the second electrode of the twenty-ninth N-type transistor N29 is connected to the first electrode of the twenty-eighth N-type transistor N28.

[0147] In the exemplary embodiment, the gate electrode of the 30th P-type transistor P30 and the gate electrode of the 30th N-type transistor N30 are connected to each other and are respectively connected to the second electrode of the 28th P-type transistor P28, the second electrode of the 28th N-type transistor N28, and the second electrode of the 29th P-type transistor P29. The gate electrode of the 31st P-type transistor P31 and the gate electrode of the 31st N-type transistor N31 are connected to each other and are respectively connected to the second electrode of the 34th P-type transistor P34, the second electrode of the 34th N-type transistor N34, the second electrode of the 35th P-type transistor P35, the gate electrode of the 36th P-type transistor P36, and the gate electrode of the 37th P-type transistor P37. The gate electrode of the sixteenth N-type transistor N36 is connected, the first electrode of the thirtieth P-type transistor P30 and the first electrode of the thirty-first P-type transistor P31 are both connected to the first power supply line VDD, the second electrode of the thirtieth P-type transistor P30 and the second electrode of the thirty-first P-type transistor P31 are connected to each other, and are respectively connected to the second electrode of the thirty-first N-type transistor N31, the gate electrode of the thirty-fifth P-type transistor P35 and the gate electrode of the thirty-fifth N-type transistor N35, the first electrode of the thirtieth N-type transistor N30 is connected to the ground line GND, and the second electrode of the thirtieth N-type transistor N30 is connected to the first electrode of the thirty-first N-type transistor N30.

[0148] In an exemplary embodiment, the gate electrode of the thirty-second P-type transistor P32 and the gate electrode of the thirty-second N-type transistor N32 are connected to each other, and are respectively connected to the second electrode of the twenty-sixth P-type transistor P26, the second electrode of the twenty-sixth N-type transistor N26, the gate electrode of the twenty-ninth P-type transistor P29, and the gate electrode of the twenty-ninth N-type transistor N29. The gate electrode of the thirty-third P-type transistor P33 and the gate electrode of the thirty-third N-type transistor N33 are connected to each other, and are respectively connected to the second input terminal B_Qn of the logic operation circuit, the gate electrode of the twenty-seventh P-type transistor P27, and the gate electrode of the twenty-seventh N-type transistor N27. The first electrode of the thirty-second P-type transistor P32 and the first electrode of the thirty-third P-type transistor P33 are both connected to the first power supply line VDD, the second electrode of the thirty-second P-type transistor P32 and the second electrode of the thirty-third P-type transistor P33 are connected to each other, and are respectively connected to the second electrode of the thirty-third N-type transistor N33, the gate electrode of the thirty-fourth P-type transistor P34 and the gate electrode of the thirty-fourth N-type transistor N34, the first electrode of the thirty-second N-type transistor N32 is connected to the ground line GND, and the second electrode of the thirty-second N-type transistor N32 is connected to the first electrode of the thirty-third N-type transistor N33.

[0149] In the exemplary embodiment, the gate electrode of the thirty-fourth P-type transistor P34 and the gate electrode of the thirty-fourth N-type transistor N34 are connected to each other and are respectively connected to the second electrode of the thirty-second P-type transistor P32, the second electrode of the thirty-third P-type transistor P33, and the second electrode of the thirty-third N-type transistor N33. The gate electrode of the thirty-fifth P-type transistor P35 and the gate electrode of the thirty-fifth N-type transistor N35 are connected to each other and are respectively connected to the second electrode of the thirtieth P-type transistor P30, the second electrode of the thirty-first P-type transistor P31, and the second electrode of the thirty-first N-type transistor N31. The first electrode of the thirty-fourth P-type transistor P34 and the first electrode of the thirty-fifth P-type transistor P35 are both connected to the first electrode. The source line VDD is connected, the second electrode of the thirty-fourth P-type transistor P34 and the second electrode of the thirty-fifth P-type transistor P35 are connected to each other, and are respectively connected to the second electrode of the thirty-fourth N-type transistor N34, the gate electrode of the thirty-first P-type transistor P31, the gate electrode of the thirty-first N-type transistor N31, the gate electrode of the thirty-sixth P-type transistor P36 and the gate electrode of the thirty-sixth N-type transistor N36, the first electrode of the thirty-fifth N-type transistor N35 is connected to the ground line GND, and the second electrode of the thirty-fifth N-type transistor N35 is connected to the first electrode of the thirty-fourth N-type transistor N34.

[0150] In the exemplary embodiment, the thirty-sixth P-type transistor P36, the thirty-sixth N-type transistor N36, the thirty-seventh P-type transistor P37, and the thirty-seventh N-type transistor N37 constitute a fourth NOR gate 504. The gate electrode of the thirty-sixth P-type transistor P36 and the gate electrode of the thirty-sixth N-type transistor N36 are connected to each other, and are respectively connected to the second electrode of the thirty-fourth P-type transistor P34, the second electrode of the thirty-fourth N-type transistor N34, the second electrode of the thirty-fifth P-type transistor P35, the gate electrode of the thirty-first P-type transistor P31, and the gate electrode of the thirty-first N-type transistor N31. The gate electrode of the thirty-seventh P-type transistor P37 and the gate electrode of the thirty-seventh N-type transistor N37 are connected to each other and are connected to the ratio control terminal D_Qn of the logic operation circuit. The thirty-sixth P-type transistor P36 and the gate electrode of the thirty-sixth N-type transistor N36 are connected to each other, and are respectively connected to the second electrode of the thirty-fourth P-type transistor P34, the second electrode of the thirty-fourth N-type transistor N34, the second electrode of the thirty-fifth P-type transistor P35, the gate electrode of the thirty-first P-type transistor P31, and the gate electrode of the thirty-first N-type transistor N31. The gate electrode of the thirty-seventh P-type transistor P37 and the gate electrode of the thirty-seventh N-type transistor N37 are connected to each other, and are connected to the ratio control terminal D_Qn of the logic operation circuit. The first electrode of the thirty-sixth P-type transistor P36 is connected to the first power supply line VDD, the second electrode of the thirty-sixth P-type transistor P36 is connected to the first electrode of the thirty-seventh P-type transistor P37, the first electrode of the thirty-sixth N-type transistor N36 and the first electrode of the thirty-seventh N-type transistor N37 are both connected to the ground line GND, the second electrode of the thirty-sixth N-type transistor N36 and the second electrode of the thirty-seventh N-type transistor N37 are connected to each other, and are respectively connected to the second electrode of the thirty-seventh P-type transistor P37, the gate electrode of the thirty-ninth P-type transistor P39 and the gate electrode of the thirty-ninth N-type transistor N39.

[0151] In an exemplary embodiment, the thirty-eighth P-type transistor P38 , the thirty-eighth N-type transistor N38 , the thirty-ninth P-type transistor P39 , and the thirty-ninth N-type transistor N39 constitute the second NAND gate 302 . The gate electrode of the thirty-eighth P-type transistor P38 and the gate electrode of the thirty-eighth N-type transistor N38 are connected to each other and to the second reset terminal LF_pulse2 of the logic operation circuit. The gate electrode of the thirty-ninth P-type transistor P39 and the gate electrode of the thirty-ninth N-type transistor N39 are connected to each other and to the second electrode of the thirty-sixth N-type transistor N36, the second electrode of the thirty-seventh P-type transistor P37, and the second electrode of the thirty-seventh N-type transistor N37, respectively. The first electrode of the thirty-eighth P-type transistor P38 and the first electrode of the thirty-ninth P-type transistor P39 are both connected to the first power supply line VDD, the first electrode of the thirty-ninth N-type transistor N39 is connected to the ground line GND, the second electrode of the thirty-ninth N-type transistor N39 is connected to the first electrode of the thirty-eighth N-type transistor N38, the second electrode of the thirty-eighth P-type transistor P38, the second electrode of the thirty-eighth N-type transistor N38, and the second electrode of the thirty-ninth P-type transistor P39 are connected to each other and, as the output terminal of the second operation circuit, are connected to the input terminal of another level converter, and output the output signal DSn of the second operation circuit to the level converter.

[0152] Figure 11 is a schematic diagram illustrating the operation of a third arithmetic circuit according to an exemplary embodiment of the present disclosure. The third arithmetic circuit may include two components: a NOR gate and a NAND gate. As shown in Figure 9 , the third arithmetic circuit may include a fifth NOR gate 505 and a third NAND gate 303.

[0153] In an exemplary embodiment, a first input terminal of the fifth NOR gate 505 is connected to the third input terminal C_Qn of the logic operation circuit, a second input terminal of the fifth NOR gate 505 is connected to the second input terminal B_Qn of the logic operation circuit, a third input terminal of the fifth NOR gate 505 is connected to the duty ratio control terminal D_Qn of the logic operation circuit, an output terminal of the fifth NOR gate 505 is connected to the first input terminal of the third NAND gate 303, a second input terminal of the third NAND gate 303 is connected to the second reset terminal LF_pulse2 of the logic operation circuit, and an output terminal of the third NAND gate 303 serves as the output terminal of the third operation circuit and is connected to the input terminal of another level converter, thereby outputting the output signal AZn of the third operation circuit to the level converter.

[0154] In an exemplary embodiment, the third arithmetic circuit operates as follows: the fifth NOR gate 505 performs a NOR operation on the third input signal of the third input terminal C_Qn, the second input signal of the second input terminal B_Qn, and the duty control signal of the duty control terminal D_Qn. The third NAND gate 303 performs a NAND operation on the NOR operation result and the second reset signal of the second reset terminal LF_pulse2. The logical expression is: AZn = ┐(┐(B_Qn + C_Qn + D_Qn) & LF_pulse2'). LF_pulse2' is an initialization signal that remains high during normal operation. Thus, AZn = B_Qn + C_Qn + D_Qn. When LF_pulse2' is low, AZn = 1, and AZn outputs a high level. When the light-emission time duty ratio reaches 100%, D_Qn remains low, and AZn = B_Qn + C_Qn. To adjust the light-emission time duty ratio, the duty cycle of D_Qn can be adjusted.

[0155] Figure 12 is an equivalent circuit diagram of a third arithmetic circuit according to an exemplary embodiment of the present disclosure. As shown in Figure 12, the third arithmetic circuit of the logic arithmetic circuit of the gate driver circuit in the display substrate of the present embodiment may include 10 transistors. The fifth NOR gate 505 includes three P-type transistors and three N-type transistors, and the third NAND gate 303 includes two P-type transistors and two N-type transistors.

[0156] In an exemplary embodiment, the fifth NOR gate 505 and the third NAND gate 303 may be sequentially disposed along the first direction X (a direction approaching the display area).

[0157] In the exemplary embodiment, the forty-first P-type transistor P41, the forty-first N-type transistor N41, the forty-second P-type transistor P42, the forty-second N-type transistor N42, the forty-third P-type transistor P43, and the forty-third N-type transistor N43 form a fifth NOR gate 505. The gate electrode of the forty-first P-type transistor P41 and the gate electrode of the forty-first N-type transistor N41 are connected to each other and to the duty control terminal D_Qn of the logic operation circuit. The gate electrode of the forty-second P-type transistor P42 and the gate electrode of the forty-second N-type transistor N42 are connected to each other and to the second input terminal B_Qn of the logic operation circuit. The gate electrode of the forty-third P-type transistor P43 and the gate electrode of the forty-third N-type transistor N43 are connected to each other and to the third input terminal C_Qn of the logic operation circuit. The first electrode of the forty-first P-type transistor P41 is connected to the first power supply line VDD, and the second electrode of the forty-first P-type transistor P41 is connected to the forty-first P-type transistor P41. The first electrode of the forty-second P-type transistor P42 is connected, the second electrode of the forty-second P-type transistor P42 is connected to the first electrode of the forty-third P-type transistor P43, the first electrode of the forty-first N-type transistor N41, the first electrode of the forty-second N-type transistor N42 and the first electrode of the forty-third N-type transistor N43 are all connected to the ground line GND, the second electrode of the forty-first N-type transistor N41, the second electrode of the forty-second N-type transistor N42 and the second electrode of the forty-third N-type transistor N43 are connected to each other, and are respectively connected to the second electrode of the forty-third P-type transistor P43, the gate electrode of the forty-fifth P-type transistor P45 and the gate electrode of the forty-fifth N-type transistor N45.

[0158] In the exemplary embodiment, the forty-fourth P-type transistor P44, the forty-fourth N-type transistor N44, the forty-fifth P-type transistor P45, and the forty-fifth N-type transistor N45 constitute a third NAND gate 303. The gate electrode of the forty-fourth P-type transistor P44 and the gate electrode of the forty-fourth N-type transistor N44 are connected to each other and to the second reset terminal LF_pulse2 of the logic operation circuit. The gate electrode of the forty-fifth P-type transistor P45 and the gate electrode of the forty-fifth N-type transistor N45 are connected to each other and to the second electrode of the forty-first N-type transistor N41, the second electrode of the forty-second N-type transistor N42, the second electrode of the forty-third N-type transistor N43, and the second electrode of the forty-third P-type transistor P43, respectively. The first electrode of the forty-fourth P-type transistor P44 and the first electrode of the forty-second N-type transistor N42 are connected to the second electrode of the forty-third N-type transistor N43. The first electrodes of the five P-type transistors P45 are all connected to the first power supply line VDD, the first electrode of the forty-fourth N-type transistor N44 is connected to the ground line GND, the second electrode of the forty-fourth N-type transistor N44 is connected to the first electrode of the forty-fifth N-type transistor N45, the second electrode of the forty-fourth P-type transistor P44, the second electrode of the forty-fifth P-type transistor P45 and the second electrode of the forty-fifth N-type transistor N45 are connected to each other and serve as the output end of the third operation circuit, connected to the input end of another level converter, and output the output signal AZn of the third operation circuit to the level converter.

[0159] FIG13 is a schematic diagram of the structure of a logic operation circuit according to an exemplary embodiment of the present disclosure. In an exemplary embodiment, the display substrate of the exemplary embodiment of the present disclosure may include at least a display area and a non-display area. The display area may include a plurality of sub-pixels forming a plurality of pixel rows and a plurality of pixel columns, at least one sub-pixel including a pixel driver circuit and at least one scan signal line, the scan signal line being configured to provide a scan signal to the connected pixel driver circuit. The non-display area may include a plurality of cascaded gate driver circuits, at least one gate driver circuit being connected to a scan signal line in a pixel row in the display area. The at least one gate driver circuit may include a shift register circuit, a logic operation circuit, a level shifter, and a row driver booster disposed on a silicon substrate. The shift register circuit is configured to generate a row-by-row shifted timing based on a timing signal, the logic operation circuit is configured to generate a target timing through a logic operation, the level shifter is configured to perform voltage domain conversion on the target timing, and the row driver booster is configured to amplify the converted signal and output it to the scan signal line of the display area.

[0160] In an exemplary embodiment, at least two of the first, second, and third arithmetic circuits may have at least one common input signal. For example, the first and second arithmetic circuits are both connected to the second input terminal B_Qn and receive the same second input signal. In another example, the second and third arithmetic circuits are both connected to the duty ratio control terminal D_Qn and receive the same duty ratio control signal.

[0161] In an exemplary embodiment, at least one input signal of the second arithmetic circuit is provided by the first arithmetic circuit, i.e., the second arithmetic circuit is triggered based on a signal from the first arithmetic circuit. For example, an input terminal of the second arithmetic circuit is connected to an output terminal of the first arithmetic circuit to receive the output signal WSn of the first arithmetic circuit.

[0162] In an exemplary embodiment, the second operation circuit or the third operation circuit is arranged on a side of the first operation circuit close to the display area, that is, the first operation circuit is arranged on a side away from the display area, which can reduce wiring and optimize layout design.

[0163] In an exemplary embodiment, the logic operation circuit may include at least a first operation circuit that generates a write switch signal WS, a second operation circuit that generates a display switch signal DS, and a third operation circuit that generates a display reset signal AZ. As shown in FIG13 , the silicon substrate of the logic operation circuit may include at least a first region LW, a second region LD, and a third region LZ. The second region LD may be disposed on one side of the first region LW in a first direction X (a direction close to the display area), and the third region LZ may be disposed on one side of the second region LD in the first direction X. The first region LW is configured to house the first operation circuit that generates the write switch signal WS, the second region LD is configured to house the second operation circuit that generates the display switch signal DS, and the third region LZ is configured to house the third operation circuit that generates the display reset signal AZ. The second operation circuit is disposed on the side of the first operation circuit close to the display area, and the third operation circuit is disposed on the side of the second operation circuit close to the display area, forming a compact, elongated strip-shaped layout extending along the first direction X.

[0164] In an exemplary embodiment, the first operational circuit, the second operational circuit, and the third operational circuit may each include a plurality of transistor groups sequentially arranged along a first direction X (a pixel row direction in a display area), and at least one transistor group may include a P-type transistor and an N-type transistor arranged on one side of the P-type transistor in a second direction Y (a pixel column direction in a display area).

[0165] In an exemplary embodiment, the plurality of transistor groups of the first operation circuit may form a first NAND gate 301, a first inverter 401, a first NOR gate 501, a second inverter 402, a second NOR gate 502, a fourth inverter 404, a third inverter 403, a third NOR gate 503, and a two-way selector 510, which are sequentially arranged along the first direction X. The plurality of transistor groups of the second operation circuit may form a fifth inverter 405, a sixth inverter 406, a seventh inverter 407, an eighth inverter 408, a ninth inverter 409, a tenth inverter 410, a latch 520, a fourth NOR gate 504, and a second NAND gate 302, which are sequentially arranged along the first direction X. The plurality of transistor groups of the third operation circuit may form a fifth NOR gate 505 and a third NAND gate 303, which are sequentially arranged along the first direction X.

[0166] In an exemplary embodiment, the number of transistor groups in the third operation circuit can be smaller than the number of transistor groups in the first operation circuit, and the number of transistor groups in the third operation circuit can be smaller than the number of transistor groups in the second operation circuit, which can reduce the impact of the operation circuit on the display area.

[0167] In an exemplary embodiment, the first operation circuit may include 15 transistor groups, the second operation circuit may include 19 transistor groups, and the third operation circuit may include 5 transistor groups.

[0168] In an exemplary embodiment, the first NAND gate, the first NOR gate, the second NOR gate, and the third NOR gate each include two transistor groups, the first inverter, the second inverter, the third inverter, and the fourth inverter each include one transistor group, and the two-way selector includes three transistor groups. The fifth to tenth inverters each include one transistor group, the latch includes nine transistor groups, the fourth NOR gate and the second NAND gate each include two transistor groups, the fifth NOR gate includes three transistor groups, and the third NAND gate includes two transistor groups.

[0169] In an exemplary embodiment, the logic operation circuit may further include a plurality of signal lines, which may be in the shape of bars extending along the second direction Y and arranged sequentially along the first direction X, and the plurality of signal lines may be configured to transmit power signals or ground signals.

[0170] In an exemplary embodiment, the plurality of signal lines may include at least a first signal line 91, a second signal line 92, a third signal line 93, a fourth signal line 94, a fifth signal line 95, a sixth signal line 96, a seventh signal line 97, and an eighth signal line 98, which are sequentially arranged in a direction close to the display area. In an exemplary embodiment, the second signal line 92, the fifth signal line 95, and the seventh signal line 97 are configured to transmit power signals, and the first signal line 91, the third signal line 93, the fourth signal line 94, the sixth signal line 96, and the eighth signal line 98 are configured to transmit ground signals.

[0171] In an exemplary embodiment, the first signal trace 91, the second signal trace 92, and the third signal trace 93 can be arranged in the first region LW. The orthographic projection of the first signal trace 91 on the silicon substrate at least partially overlaps with the orthographic projections of the first NAND gate 301 and the first inverter 401 in the first arithmetic circuit on the silicon substrate. The orthographic projection of the second signal trace 92 on the silicon substrate at least partially overlaps with the orthographic projections of the first NOR gate 501 and the second inverter 402 in the first arithmetic circuit on the silicon substrate. The orthographic projection of the third signal trace 93 on the silicon substrate at least partially overlaps with the orthographic projection of the two-way selector 510 in the first arithmetic circuit on the silicon substrate. In an exemplary embodiment, the first signal trace 91, the second signal trace 92, and the third signal trace 93 have the same first trace width LZ1, which can be the dimension in the first direction X (pixel row direction).

[0172] In an exemplary embodiment, the fourth signal line 94, the fifth signal line 95, the sixth signal line 96, and the seventh signal line 97 may be disposed in the second region LD, the orthographic projection of the fourth signal line 94 on the silicon substrate at least partially overlaps with the orthographic projections of the fifth inverter 405 and the sixth inverter 406 in the second arithmetic circuit on the silicon substrate, the orthographic projection of the fifth signal line 95 on the silicon substrate at least partially overlaps with the orthographic projections of the seventh inverter 407, the eighth inverter 408, and the ninth inverter 409 in the second arithmetic circuit on the silicon substrate, the orthographic projection of the sixth signal line 96 on the silicon substrate at least partially overlaps with the orthographic projection of the latch 520 in the second arithmetic circuit on the silicon substrate, and the orthographic projection of the seventh signal line 97 on the silicon substrate at least partially overlaps with the orthographic projections of the fourth NOR gate 504 and the second NAND gate 302 in the second arithmetic circuit on the silicon substrate. In an exemplary embodiment, the fourth signal line 94 and the fifth signal line 95 have the same first line width LZ1, and the sixth signal line 96 and the seventh signal line 97 have the same second line width LZ2. The second line width LZ2 can be the dimension in the first direction X (pixel row direction).

[0173] In an exemplary embodiment, the eighth signal trace 98 may be disposed in the third zone LZ, and an orthographic projection of the eighth signal trace 98 on the silicon substrate at least partially overlaps with an orthographic projection of the fifth NOR gate 505 and the third NAND gate 303 in the third arithmetic circuit on the silicon substrate. In an exemplary embodiment, the eighth signal trace 98 may have a second trace width LZ2.

[0174] In an exemplary embodiment, the second trace width LZ2 may be greater than the first trace width LZ1 .

[0175] In an exemplary embodiment, among the multiple transistor groups overlapping with the fourth signal routing 94 or the fifth signal routing 95, the P-type transistors in at least one transistor group have a first P-type width-to-length ratio, and among the multiple transistor groups overlapping with the sixth signal routing 96 or the seventh signal routing 97, the P-type transistors in at least one transistor group have a second P-type width-to-length ratio, and the second P-type width-to-length ratio may be greater than the first P-type width-to-length ratio.

[0176] In an exemplary embodiment, among the multiple transistor groups overlapping with the fourth signal routing 94 or the fifth signal routing 95, the N-type transistors in at least one transistor group have a first N-type width-to-length ratio, and among the multiple transistor groups overlapping with the sixth signal routing 96 or the seventh signal routing 97, the N-type transistors in at least one transistor group have a second N-type width-to-length ratio, and the second N-type width-to-length ratio may be greater than the first N-type width-to-length ratio.

[0177] In an exemplary embodiment, the logic operation circuit may further include a first power line 51 and a ground line 52. The shapes of the first power line 51 and the ground line 52 may be line shapes extending along the first direction X. The first power line 51 may be arranged on a side opposite to the second direction Y of the plurality of transistor groups. The first power line 51 is configured to transmit a power signal. The ground line 52 may be arranged on a side of the second direction Y of the plurality of transistor groups. The ground line 52 is configured to transmit a ground signal.

[0178] In an exemplary embodiment, in at least one transistor group of the first operational circuit, the P-type transistor may include at least a P-type active area, a P-type source electrode, and a P-type drain electrode, the first end of the P-type source electrode is connected to the first power line 51, and the second end of the P-type source electrode is connected to the first area of ​​the P-type active area through a via; the N-type transistor may include at least an N-type active area, an N-type source electrode, and an N-type drain electrode, the first end of the N-type source electrode is connected to the ground line 52, and the second end of the N-type source electrode is connected to the first area of ​​the N-type active area through a via.

[0179] In an exemplary embodiment, the P-type source electrode in at least one transistor group has a first P-type length, and the P-type source electrode in at least another transistor group has a second P-type length. The ratio of the first P-type length to the second P-type length can be approximately 0.95 to 1.05, and the first P-type length and the second P-type length can be dimensions in the second direction Y.

[0180] In example embodiments, lengths of P-type source electrodes in the plurality of transistor groups may be substantially equal.

[0181] In an exemplary embodiment, the N-type source electrode in at least one transistor group has a first N-type length, and the N-type source electrode in at least another transistor group has a second N-type length. The ratio of the first N-type length to the second N-type length can be approximately 0.95 to 1.05, and the first N-type length and the second N-type length can be dimensions in the second direction Y.

[0182] In example embodiments, lengths of N-type source electrodes in the plurality of transistor groups may be substantially equal.

[0183] In an exemplary embodiment, the fifth inverter 405 to the tenth inverter 410 each include a transistor group, and at least one transistor group may include at least a gate connection electrode and a common drain electrode, the gate connection electrode may be connected to the P-type gate electrode of the P-type transistor and the N-type gate electrode of the N-type transistor, and the common drain electrode may serve as the P-type drain electrode of the P-type transistor and the N-type drain electrode of the N-type transistor at the same time.

[0184] In an exemplary embodiment, the common drain electrode in the fifth inverter 405 is connected to the gate connection electrode in the sixth inverter 406, the common drain electrode in the sixth inverter 406 is connected to the gate connection electrode in the seventh inverter 407, the common drain electrode in the seventh inverter 407 is connected to the gate connection electrode in the eighth inverter 408, the common drain electrode in the eighth inverter 408 is connected to the gate connection electrode in the ninth inverter 409, and the common drain electrode in the ninth inverter 409 is connected to the gate connection electrode in the tenth inverter 410.

[0185] In an exemplary embodiment, the common drain electrode in at least one inverter has a first drain length, and the common drain electrode in at least another inverter has a second drain length, and a ratio of the first drain length to the second drain length may be approximately 0.95 to 1.05, and the first drain length and the second drain length may be dimensions in the second direction Y.

[0186] In example embodiments, lengths of the common drain electrodes in the plurality of transistor groups may be substantially equal.

[0187] In an exemplary embodiment, the gate connection electrode in at least one inverter has a first gate length, and the gate connection electrode in at least another inverter has a second gate length. The ratio of the first gate length to the second gate length can be approximately 0.95 to 1.05, and the first gate length and the second gate length can be dimensions in the first direction X.

[0188] In example embodiments, lengths of gate connection electrodes in the plurality of transistor groups may be substantially equal.

[0189] The following is an illustrative explanation through the preparation process of the display device. The "patterning process" mentioned in the present disclosure includes the deposition of film layers, coating of photoresist on the film layers, mask exposure, development, etching, stripping of photoresist and other processes for metal materials, inorganic materials or transparent conductive materials, and includes the coating of organic materials, mask exposure and development and other processes for organic materials. Deposition can be carried out by any one or more of sputtering, evaporation, and chemical vapor deposition, coating can be carried out by any one or more of spraying, spin coating and inkjet printing, and etching can be carried out by any one or more of dry etching and wet etching, and the present disclosure does not limit this. "Thin film" refers to a thin film made by deposition, coating or other processes of a certain material on a substrate. If the "thin film" does not require a patterning process during the entire production process, the "thin film" can also be called a "layer". If the "thin film" requires a patterning process during the entire production process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern". As used in this disclosure, "A and B are disposed in the same layer" means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer refers to the dimension of the film layer in a direction perpendicular to the display device. In exemplary embodiments of this disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A contains the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or that the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0190] In an exemplary embodiment, a process of preparing a display substrate may include the following steps.

[0191] (1) Provide a silicon substrate. In an exemplary embodiment, the silicon substrate may be a P-type silicon substrate. In an exemplary embodiment, the P-type silicon substrate may serve as a channel region of an N-type transistor.

[0192] In an exemplary embodiment, the P-type silicon substrate may include a first region LW, a second region LD, and a third region LZ. The second region LD may be arranged on one side of the first region LW in a first direction X (a direction close to the display area), and the third region LZ may be arranged on one side of the second region LD in the first direction X. The first region LW is configured to set a first operation circuit, the second region LD is configured to set a second operation circuit, and the third region LZ is configured to set a third operation circuit.

[0193] In some possible implementations, the silicon substrate may be an N-type silicon material, which may serve as a channel region of a P-type transistor, and this disclosure does not limit this.

[0194] (2) Sequentially forming N-type well (NW) region and active area (AA) patterns. In an exemplary embodiment, a photoresist pattern including an opening region can be formed by coating a photoresist on a P-type silicon substrate, exposing and developing the photoresist, removing the photoresist in the opening region to expose the surface of the P-type silicon substrate, and implanting n-type dopant ions in the opening region by ion implantation. The remaining photoresist is stripped off to form an N-type well region 10 pattern on the P-type silicon substrate. Subsequently, an active area pattern is formed on the silicon substrate formed with the aforementioned pattern, as shown in FIG14A and FIG14B , FIG14B being a schematic diagram of the active area in FIG14A .

[0195] In an exemplary embodiment, the N-well region 10 is configured to form a P-type transistor and a P-type device, and the region other than the N-well region 10 is configured to form an N-type transistor and an N-type device.

[0196] In an exemplary embodiment, n-type dopant ions may be implanted using ion implanters such as phosphorus or arsenic. The depth and doping concentration of the ion implantation can be controlled by controlling the implantation energy and dose. The process for forming the N-well region may also include annealing and other processes to allow the ion implanter to diffuse into the P-type silicon substrate, forming a stable N-well structure.

[0197] In an exemplary embodiment, the active area pattern may include at least: a first P-type active region 101P to a fifteenth P-type active region 115P, a twenty-first P-type active region 121P to a thirty-ninth P-type active region 139P, a forty-first P-type active region 141P to a forty-fifth P-type active region 145P, a first N-type active region 101N to a fifteenth N-type active region 115N, a twenty-first N-type active region 121N to a thirty-ninth N-type active region 139N, a forty-first N-type active region 141N to a forty-fifth N-type active region 145N, a power active region 100P and a ground active region 100N.

[0198] In an exemplary embodiment, the first to fifteenth P-type active regions 101P to 115P may be disposed in the first region LW and serve as P-type active regions for a plurality of P-type transistors in the first operation circuit. The first to fifteenth N-type active regions 101N to 115N may be disposed in the first region LW and serve as N-type active regions for a plurality of N-type transistors in the first operation circuit.

[0199] In an exemplary embodiment, the first P-type active region 101P may be located within the region where the N-well region 10 is located, and the orthographic projection of the first P-type active region 101P on the silicon substrate is located within the range of the orthographic projection of the N-well region 10 on the silicon substrate. The first P-type active region 101P may be in the shape of a strip extending along the first direction X, and the first P-type active region 101P may serve as the active region of the first P-type transistor P1.

[0200] In an exemplary embodiment, the first N-type active region 101N may be located outside the region where the N-well region 10 is located, and the orthographic projection of the first N-type active region 101N on the silicon substrate does not overlap with the orthographic projection of the N-well region 10 on the silicon substrate. The first N-type active region 101N may be in the shape of a strip extending along a first direction X and located on one side of the first P-type active region 101P in the second direction Y. The first N-type active region 101N may serve as the active region of the first N-type transistor N1.

[0201] In an exemplary embodiment, the second P-type active region 102P may be located within the region where the N-well region 10 is located, and the orthographic projection of the second P-type active region 102P on the silicon substrate is located within the range of the orthographic projection of the N-well region 10 on the silicon substrate. The second P-type active region 102P may be in the shape of a strip extending along the first direction X, and the second P-type active region 102P may serve as the active region of the second P-type transistor P2.

[0202] In an exemplary embodiment, the first P-type active region 101P and the second P-type active region 102P may be an integral structure connected to each other.

[0203] In an exemplary embodiment, the second N-type active region 102N may be located outside the region where the N-well region 10 is located, and the orthographic projection of the second N-type active region 102N on the silicon substrate does not overlap with the orthographic projection of the N-well region 10 on the silicon substrate. The second N-type active region 102N may be in the shape of a strip extending along the first direction X and located on one side of the second P-type active region 102P in the second direction Y. The second N-type active region 102N may serve as the active region of the second N-type transistor N2.

[0204] In an exemplary embodiment, the first N-type active region 101N and the second N-type active region 102N may be an integral structure connected to each other.

[0205] In an exemplary embodiment, the third P-type active region 103P may be located within the region where the N-well region 10 is located, and the orthographic projection of the third P-type active region 103P on the silicon substrate may be located within the range of the orthographic projection of the N-well region 10 on the silicon substrate. The third P-type active region 103P may be in the shape of a strip extending along the first direction X, and the third P-type active region 103P may serve as the active region of the third P-type transistor P3.

[0206] In an exemplary embodiment, the third N-type active region 103N may be located outside the region where the N-well region 10 is located, and the orthographic projection of the third N-type active region 103N on the silicon substrate does not overlap with the orthographic projection of the N-well region 10 on the silicon substrate. The third N-type active region 103N may be in the shape of a strip extending along the first direction X and located on one side of the third P-type active region 103P in the second direction Y. The third N-type active region 103N may serve as the active region of the third N-type transistor N3.

[0207] In an exemplary embodiment, the fourth P-type active region 104P may be located within the region where the N-well region 10 is located, and the orthographic projection of the fourth P-type active region 104P on the silicon substrate may be located within the range of the orthographic projection of the N-well region 10 on the silicon substrate. The fourth P-type active region 104P may be in the shape of a strip extending along the first direction X, and the fourth P-type active region 104P may serve as the active region of the fourth P-type transistor P4.

[0208] In an exemplary embodiment, the fourth N-type active region 104N may be located outside the region where the N-well region 10 is located, and the orthographic projection of the fourth N-type active region 104N on the silicon substrate does not overlap with the orthographic projection of the N-well region 10 on the silicon substrate. The fourth N-type active region 104N may be in the shape of a strip extending along the first direction X and located on one side of the fourth P-type active region 104P in the second direction Y. The fourth N-type active region 104N may serve as the active region of the fourth N-type transistor N4.

[0209] In an exemplary embodiment, the fifth P-type active region 105P may be located within the region where the N-well region 10 is located, and the orthographic projection of the fifth P-type active region 105P on the silicon substrate may be located within the range of the orthographic projection of the N-well region 10 on the silicon substrate. The fifth P-type active region 105P may be in the shape of a strip extending along the first direction X, and the fifth P-type active region 105P may serve as the active region of the fifth P-type transistor P5.

[0210] In an exemplary embodiment, the fourth P-type active region 104P and the fifth P-type active region 105P may be an integral structure connected to each other.

[0211] In an exemplary embodiment, the fifth N-type active region 105N may be located outside the region where the N-well region 10 is located, and the orthographic projection of the fifth N-type active region 105N on the silicon substrate does not overlap with the orthographic projection of the N-well region 10 on the silicon substrate. The fifth N-type active region 105N may be in the shape of a strip extending along the first direction X and located on one side of the fifth P-type active region 105P in the second direction Y. The fifth N-type active region 105N may serve as the active region of the fifth N-type transistor N5.

[0212] In an exemplary embodiment, the fourth N-type active region 104N and the fifth N-type active region 105N may be an integral structure connected to each other.

[0213] In an exemplary embodiment, the sixth P-type active region 106P may be located within the region where the N-well region 10 is located, and the orthographic projection of the sixth P-type active region 106P on the silicon substrate may be located within the range of the orthographic projection of the N-well region 10 on the silicon substrate. The sixth P-type active region 106P may be in the shape of a strip extending along the first direction X, and the sixth P-type active region 106P may serve as the active region of the sixth P-type transistor P6.

[0214] In an exemplary embodiment, the sixth N-type active region 106N may be located outside the region where the N-well region 10 is located, and the orthographic projection of the sixth N-type active region 106N on the silicon substrate does not overlap with the orthographic projection of the N-well region 10 on the silicon substrate. The sixth N-type active region 106N may be in the shape of a strip extending along the first direction X and located on one side of the sixth P-type active region 106P in the second direction Y. The sixth N-type active region 106N may serve as the active region of the sixth N-type transistor N6.

[0215] In an exemplary embodiment, the seventh P-type active region 107P may be located within the region where the N-well region 10 is located, and the orthographic projection of the seventh P-type active region 107P on the silicon substrate may be located within the range of the orthographic projection of the N-well region 10 on the silicon substrate. The seventh P-type active region 107P may be in the shape of a strip extending along the first direction X, and the seventh P-type active region 107P may serve as the active region of the seventh P-type transistor P7.

[0216] In an exemplary embodiment, the seventh N-type active region 107N may be located outside the region where the N-well region 10 is located, and the orthographic projection of the seventh N-type active region 107N on the silicon substrate does not overlap with the orthographic projection of the N-well region 10 on the silicon substrate. The seventh N-type active region 107N may be in the shape of a strip extending along the first direction X and located on one side of the seventh P-type active region 107P in the second direction Y. The seventh N-type active region 107N may serve as the active region of the seventh N-type transistor N7.

[0217] In an exemplary embodiment, the eighth P-type active region 108P may be located within the region where the N-well region 10 is located, and the orthographic projection of the eighth P-type active region 108P on the silicon substrate may be located within the range of the orthographic projection of the N-well region 10 on the silicon substrate. The eighth P-type active region 108P may be in the shape of a strip extending along the first direction X, and the eighth P-type active region 108P may serve as the active region of the eighth P-type transistor P8.

[0218] In an exemplary embodiment, the seventh P-type active region 107P and the eighth P-type active region 108P may be an integral structure connected to each other.

[0219] In an exemplary embodiment, the eighth N-type active region 108N may be located outside the region where the N-well region 10 is located, and the orthographic projection of the eighth N-type active region 108N on the silicon substrate does not overlap with the orthographic projection of the N-well region 10 on the silicon substrate. The eighth N-type active region 108N may be in the shape of a strip extending along the first direction X and located on one side of the eighth P-type active region 108P in the second direction Y. The eighth N-type active region 108N may serve as the active region of the eighth N-type transistor N8.

[0220] In exemplary embodiments, the seventh N-type active region 107N and the eighth N-type active region 108N may be an integral structure connected to each other.

[0221] In an exemplary embodiment, the ninth P-type active region 109P may be located within the region where the N-well region 10 is located, and the orthographic projection of the ninth P-type active region 109P on the silicon substrate may be located within the range of the orthographic projection of the N-well region 10 on the silicon substrate. The ninth P-type active region 109P may be in the shape of a strip extending along the first direction X, and the ninth P-type active region 109P may serve as the active region of the ninth P-type transistor P9.

[0222] In an exemplary embodiment, the ninth N-type active region 109N may be located outside the region where the N-well region 10 is located, and the orthographic projection of the ninth N-type active region 109N on the silicon substrate does not overlap with the orthographic projection of the N-well region 10 on the silicon substrate. The ninth N-type active region 109N may be in the shape of a strip extending along the first direction X and located on one side of the ninth P-type active region 109P in the second direction Y. The ninth N-type active region 109N may serve as the active region of the ninth N-type transistor N9.

[0223] In an exemplary embodiment, the tenth P-type active region 110P may be located within the region where the N-well region 10 is located, and the orthographic projection of the tenth P-type active region 110P on the silicon substrate is located within the range of the orthographic projection of the N-well region 10 on the silicon substrate. The tenth P-type active region 110P may be in the shape of a strip extending along the first direction X, and the tenth P-type active region 110P may serve as the active region of the tenth P-type transistor P10.

[0224] In an exemplary embodiment, the tenth N-type active region 110N may be located outside the region where the N-well region 10 is located, and the orthographic projection of the tenth N-type active region 110N on the silicon substrate does not overlap with the orthographic projection of the N-well region 10 on the silicon substrate. The tenth N-type active region 110N may be in the shape of a strip extending along the first direction X and located on one side of the tenth P-type active region 110P in the second direction Y. The tenth N-type active region 110N may serve as the active region of the tenth N-type transistor N10.

[0225] In an exemplary embodiment, the eleventh P-type active region 111P may be located within the region where the N-well region 10 is located, and the orthographic projection of the eleventh P-type active region 111P on the silicon substrate is located within the range of the orthographic projection of the N-well region 10 on the silicon substrate. The eleventh P-type active region 111P may be in the shape of a strip extending along the first direction X. The eleventh P-type active region 111P may serve as the active region of the eleventh P-type transistor P11.

[0226] In an exemplary embodiment, the eleventh N-type active region 111N may be located outside the region where the N-well region 10 is located, and the orthographic projection of the eleventh N-type active region 111N on the silicon substrate does not overlap with the orthographic projection of the N-well region 10 on the silicon substrate. The eleventh N-type active region 111N may be in the shape of a strip extending along the first direction X and located on one side of the eleventh P-type active region 111P in the second direction Y. The eleventh N-type active region 111N may serve as the active region of the eleventh N-type transistor N11.

[0227] In an exemplary embodiment, the twelfth P-type active region 112P may be located within the region where the N-well region 10 is located, and the orthographic projection of the twelfth P-type active region 112P on the silicon substrate may be located within the range of the orthographic projection of the N-well region 10 on the silicon substrate. The twelfth P-type active region 112P may be in the shape of a strip extending along the first direction X, and the twelfth P-type active region 112P may serve as the active region of the twelfth P-type transistor P12.

[0228] In an exemplary embodiment, the eleventh P-type active region 111P and the twelfth P-type active region 112P may be an integral structure connected to each other.

[0229] In an exemplary embodiment, the twelfth N-type active region 112N may be located outside the region where the N-well region 10 is located, and the orthographic projection of the twelfth N-type active region 112N on the silicon substrate does not overlap with the orthographic projection of the N-well region 10 on the silicon substrate. The twelfth N-type active region 112N may be in the shape of a strip extending along the first direction X and located on one side of the twelfth P-type active region 112P in the second direction Y. The twelfth N-type active region 112N may serve as the active region of the twelfth N-type transistor N12.

[0230] In exemplary embodiments, the eleventh N-type active region 111N and the twelfth N-type active region 112N may be an integral structure connected to each other.

[0231] In an exemplary embodiment, the thirteenth P-type active region 113P may be located within the region where the N-well region 10 is located, and the orthographic projection of the thirteenth P-type active region 113P on the silicon substrate is located within the range of the orthographic projection of the N-well region 10 on the silicon substrate. The thirteenth P-type active region 113P may be in the shape of a strip extending along the first direction X. The thirteenth P-type active region 113P may serve as the active region of the thirteenth P-type transistor P13.

[0232] In an exemplary embodiment, the thirteenth N-type active region 113N may be located outside the region where the N-well region 10 is located, and the orthographic projection of the thirteenth N-type active region 113N on the silicon substrate does not overlap with the orthographic projection of the N-well region 10 on the silicon substrate. The thirteenth N-type active region 113N may be in the shape of a strip extending along the first direction X and located on one side of the thirteenth P-type active region 113P in the second direction Y. The thirteenth N-type active region 113N may serve as the active region of the thirteenth N-type transistor N13.

[0233] In an exemplary embodiment, the fourteenth P-type active region 114P may be located within the region where the N-well region 10 is located, and the orthographic projection of the fourteenth P-type active region 114P on the silicon substrate is located within the range of the orthographic projection of the N-well region 10 on the silicon substrate. The fourteenth P-type active region 114P may be in the shape of a strip extending along the first direction X, and the fourteenth P-type active region 114P may serve as the active region of the fourteenth P-type transistor P14.

[0234] In an exemplary embodiment, the fourteenth N-type active region 114N may be located outside the region where the N-well region 10 is located, and the orthographic projection of the fourteenth N-type active region 114N on the silicon substrate does not overlap with the orthographic projection of the N-well region 10 on the silicon substrate. The fourteenth N-type active region 114N may be in the shape of a strip extending along the first direction X and located on one side of the fourteenth P-type active region 114P in the second direction Y. The fourteenth N-type active region 114N may serve as the active region of the fourteenth N-type transistor N14.

[0235] In an exemplary embodiment, the fifteenth P-type active region 115P may be located within the region where the N-well region 10 is located, and the orthographic projection of the fifteenth P-type active region 115P on the silicon substrate is located within the range of the orthographic projection of the N-well region 10 on the silicon substrate. The fifteenth P-type active region 115P may be in the shape of a strip extending along the first direction X. The fifteenth P-type active region 115P may serve as the active region of the fifteenth P-type transistor P15.

[0236] In an exemplary embodiment, the fifteenth N-type active region 115N may be located outside the region where the N-well region 10 is located, and the orthographic projection of the fifteenth N-type active region 115N on the silicon substrate does not overlap with the orthographic projection of the N-well region 10 on the silicon substrate. The fifteenth N-type active region 115N may be in the shape of a strip extending along the first direction X and located on one side of the fifteenth P-type active region 115P in the second direction Y. The fifteenth N-type active region 115N may serve as the active region of the fifteenth N-type transistor N15.

[0237] In an exemplary embodiment, in the first region LW, the first P-type active region 101P to the fifteenth P-type active region 115P can be sequentially arranged along the first direction X (along the direction close to the display region), and the first N-type active region 101N to the fifteenth N-type active region 115N can be sequentially arranged along the first direction X (along the direction close to the display region).

[0238] In an exemplary embodiment, the twenty-first to thirty-ninth P-type active regions 121P to 139P may be disposed in the second region LD and serve as P-type active regions for a plurality of P-type transistors in the second operation circuit. The twenty-first to thirty-ninth N-type active regions 121N to 139N may be disposed in the second region LD and serve as N-type active regions for a plurality of N-type transistors in the second operation circuit.

[0239] In an exemplary embodiment, the twenty-first P-type active region 121P may be located within the region where the N-well region 10 is located, and the orthographic projection of the twenty-first P-type active region 121P on the silicon substrate is located within the range of the orthographic projection of the N-well region 10 on the silicon substrate. The twenty-first P-type active region 121P may be in the shape of a strip extending along the first direction X, and the twenty-first P-type active region 121P may serve as the active region of the twenty-first P-type transistor P21.

[0240] In an exemplary embodiment, the twenty-first N-type active region 121N may be located outside the region where the N-well region 10 is located, and the orthographic projection of the twenty-first N-type active region 121N on the silicon substrate does not overlap with the orthographic projection of the N-well region 10 on the silicon substrate. The twenty-first N-type active region 121N may be in the shape of a strip extending along the first direction X and located on one side of the twenty-first P-type active region 121P in the second direction Y. The twenty-first N-type active region 121N may serve as the active region of the twenty-first N-type transistor N21.

[0241] In an exemplary embodiment, the twenty-second P-type active region 122P may be located within the region where the N-well region 10 is located, and the orthographic projection of the twenty-second P-type active region 122P on the silicon substrate is located within the range of the orthographic projection of the N-well region 10 on the silicon substrate. The twenty-second P-type active region 122P may be in the shape of a strip extending along the first direction X, and the twenty-second P-type active region 122P may serve as the active region of the twenty-second P-type transistor P22.

[0242] In an exemplary embodiment, the twenty-second N-type active region 122N may be located outside the region where the N-well region 10 is located, and the orthographic projection of the twenty-second N-type active region 122N on the silicon substrate does not overlap with the orthographic projection of the N-well region 10 on the silicon substrate. The twenty-second N-type active region 122N may be in the shape of a strip extending along the first direction X and located on one side of the twenty-second P-type active region 122P in the second direction Y. The twenty-second N-type active region 122N may serve as the active region of the twenty-second N-type transistor N22.

[0243] In an exemplary embodiment, the twenty-third P-type active region 123P may be located within the region where the N-well region 10 is located, and the orthographic projection of the twenty-third P-type active region 123P on the silicon substrate is located within the range of the orthographic projection of the N-well region 10 on the silicon substrate. The twenty-third P-type active region 123P may be in the shape of a strip extending along the first direction X, and the twenty-third P-type active region 123P may serve as the active region of the twenty-third P-type transistor P23.

[0244] In an exemplary embodiment, the twenty-third N-type active region 123N may be located outside the region where the N-well region 10 is located, and the orthographic projection of the twenty-third N-type active region 123N on the silicon substrate does not overlap with the orthographic projection of the N-well region 10 on the silicon substrate. The twenty-third N-type active region 123N may be in the shape of a strip extending along the first direction X and located on one side of the twenty-third P-type active region 123P in the second direction Y. The twenty-third N-type active region 123N may serve as the active region of the twenty-third N-type transistor N23.

[0245] In an exemplary embodiment, the twenty-fourth P-type active region 124P may be located within the region where the N-well region 10 is located, and the orthographic projection of the twenty-fourth P-type active region 124P on the silicon substrate may be located within the range of the orthographic projection of the N-well region 10 on the silicon substrate. The twenty-fourth P-type active region 124P may be in the shape of a strip extending along the first direction X. The twenty-fourth P-type active region 124P may serve as the active region of the twenty-fourth P-type transistor P24.

[0246] In an exemplary embodiment, the twenty-fourth N-type active region 124N may be located outside the region where the N-well region 10 is located, and the orthographic projection of the twenty-fourth N-type active region 124N on the silicon substrate does not overlap with the orthographic projection of the N-well region 10 on the silicon substrate. The twenty-fourth N-type active region 124N may be in the shape of a strip extending along the first direction X and located on one side of the twenty-fourth P-type active region 124P in the second direction Y. The twenty-fourth N-type active region 124N may serve as the active region of the twenty-fourth N-type transistor N24.

[0247] In an exemplary embodiment, the twenty-fifth P-type active region 125P may be located within the region where the N-well region 10 is located, and the orthographic projection of the twenty-fifth P-type active region 125P on the silicon substrate is located within the range of the orthographic projection of the N-well region 10 on the silicon substrate. The twenty-fifth P-type active region 125P may be in the shape of a strip extending along the first direction X, and the twenty-fifth P-type active region 125P may serve as the active region of the twenty-fifth P-type transistor P25.

[0248] In an exemplary embodiment, the twenty-fifth N-type active region 125N may be located outside the region where the N-well region 10 is located, and the orthographic projection of the twenty-fifth N-type active region 125N on the silicon substrate does not overlap with the orthographic projection of the N-well region 10 on the silicon substrate. The twenty-fifth N-type active region 125N may be in the shape of a strip extending along the first direction X and located on one side of the twenty-fifth P-type active region 125P in the second direction Y. The twenty-fifth N-type active region 125N may serve as the active region of the twenty-fifth N-type transistor N25.

[0249] In an exemplary embodiment, the twenty-sixth P-type active region 126P may be located within the region where the N-well region 10 is located, and the orthographic projection of the twenty-sixth P-type active region 126P on the silicon substrate is located within the range of the orthographic projection of the N-well region 10 on the silicon substrate. The twenty-sixth P-type active region 126P may be in the shape of a strip extending along the first direction X, and the twenty-sixth P-type active region 126P may serve as the active region of the twenty-sixth P-type transistor P26.

[0250] In an exemplary embodiment, the twenty-sixth N-type active region 126N may be located outside the region where the N-well region 10 is located, and the orthographic projection of the twenty-sixth N-type active region 126N on the silicon substrate does not overlap with the orthographic projection of the N-well region 10 on the silicon substrate. The twenty-sixth N-type active region 126N may be in the shape of a strip extending along the first direction X and located on one side of the twenty-sixth P-type active region 126P in the second direction Y. The twenty-sixth N-type active region 126N may serve as the active region of the twenty-sixth N-type transistor N26.

[0251] In an exemplary embodiment, the twenty-seventh P-type active region 127P may be located within the region where the N-well region 10 is located, and the orthographic projection of the twenty-seventh P-type active region 127P on the silicon substrate is located within the range of the orthographic projection of the N-well region 10 on the silicon substrate. The twenty-seventh P-type active region 127P may be in the shape of a strip extending along the first direction X, and the twenty-seventh P-type active region 127P may serve as the active region of the twenty-seventh P-type transistor P27.

[0252] In an exemplary embodiment, the twenty-seventh N-type active region 127N may be located outside the region where the N-well region 10 is located, and the orthographic projection of the twenty-seventh N-type active region 127N on the silicon substrate does not overlap with the orthographic projection of the N-well region 10 on the silicon substrate. The twenty-seventh N-type active region 127N may be in the shape of a strip extending along the first direction X and located on one side of the twenty-seventh P-type active region 127P in the second direction Y. The twenty-seventh N-type active region 127N may serve as the active region of the twenty-seventh N-type transistor N27.

[0253] In an exemplary embodiment, the twenty-eighth P-type active region 128P may be located within the region where the N-well region 10 is located, and the orthographic projection of the twenty-eighth P-type active region 128P on the silicon substrate may be located within the range of the orthographic projection of the N-well region 10 on the silicon substrate. The twenty-eighth P-type active region 128P may be in the shape of a strip extending along the first direction X, and the twenty-eighth P-type active region 128P may serve as the active region of the twenty-eighth P-type transistor P28.

[0254] In an exemplary embodiment, the twenty-eighth N-type active region 128N may be located outside the region where the N-well region 10 is located, and the orthographic projection of the twenty-eighth N-type active region 128N on the silicon substrate does not overlap with the orthographic projection of the N-well region 10 on the silicon substrate. The twenty-eighth N-type active region 128N may be in the shape of a strip extending along the first direction X and located on one side of the twenty-eighth P-type active region 128P in the second direction Y. The twenty-eighth N-type active region 128N may serve as the active region of the twenty-eighth N-type transistor N28.

[0255] In an exemplary embodiment, the twenty-ninth P-type active region 129P may be located within the region where the N-well region 10 is located, and the orthographic projection of the twenty-ninth P-type active region 129P on the silicon substrate is located within the range of the orthographic projection of the N-well region 10 on the silicon substrate. The twenty-ninth P-type active region 129P may be in the shape of a strip extending along the first direction X, and the twenty-ninth P-type active region 129P may serve as the active region of the twenty-ninth P-type transistor P29.

[0256] In exemplary embodiments, the twenty-eighth P-type active region 128P and the twenty-ninth P-type active region 129P may be an integral structure connected to each other.

[0257] In an exemplary embodiment, the twenty-ninth N-type active region 129N may be located outside the region where the N-well region 10 is located, and the orthographic projection of the twenty-ninth N-type active region 129N on the silicon substrate does not overlap with the orthographic projection of the N-well region 10 on the silicon substrate. The twenty-ninth N-type active region 129N may be in the shape of a strip extending along the first direction X and located on one side of the twenty-ninth P-type active region 129P in the second direction Y. The twenty-ninth N-type active region 129N may serve as the active region of the twenty-ninth N-type transistor N29.

[0258] In exemplary embodiments, the twenty-eighth N-type active region 128N and the twenty-ninth N-type active region 129N may be an integral structure connected to each other.

[0259] In an exemplary embodiment, the 30th P-type active region 130P may be located within the region where the N-well region 10 is located, and the orthographic projection of the 30th P-type active region 130P on the silicon substrate is located within the range of the orthographic projection of the N-well region 10 on the silicon substrate. The 30th P-type active region 130P may be in the shape of a strip extending along the first direction X, and the 30th P-type active region 130P may serve as the active region of the 30th P-type transistor P30.

[0260] In an exemplary embodiment, the 30th N-type active region 130N may be located outside the region where the N-well region 10 is located, and the orthographic projection of the 30th N-type active region 130N on the silicon substrate does not overlap with the orthographic projection of the N-well region 10 on the silicon substrate. The 30th N-type active region 130N may be in the shape of a strip extending along the first direction X and located on one side of the 30th P-type active region 130P in the second direction Y. The 30th N-type active region 130N may serve as the active region of the 30th N-type transistor N30.

[0261] In an exemplary embodiment, the thirty-first P-type active region 131P may be located within the region where the N-well region 10 is located, and the orthographic projection of the thirty-first P-type active region 131P on the silicon substrate is located within the range of the orthographic projection of the N-well region 10 on the silicon substrate. The thirty-first P-type active region 131P may be in the shape of a strip extending along the first direction X, and the thirty-first P-type active region 131P may serve as the active region of the thirty-first P-type transistor P31.

[0262] In exemplary embodiments, the 30th P-type active region 130P and the 31st P-type active region 131P may be an integral structure connected to each other.

[0263] In an exemplary embodiment, the thirty-first N-type active region 131N may be located outside the region where the N-well region 10 is located, and the orthographic projection of the thirty-first N-type active region 131N on the silicon substrate does not overlap with the orthographic projection of the N-well region 10 on the silicon substrate. The thirty-first N-type active region 131N may be in the shape of a strip extending along the first direction X and located on one side of the thirty-first P-type active region 131P in the second direction Y. The thirty-first N-type active region 131N may serve as the active region of the thirty-first N-type transistor N31.

[0264] In exemplary embodiments, the 30th N-type active region 130N and the 31st N-type active region 131N may be an integral structure connected to each other.

[0265] In an exemplary embodiment, the thirty-second P-type active region 132P may be located within the region where the N-well region 10 is located, and the orthographic projection of the thirty-second P-type active region 132P on the silicon substrate is located within the range of the orthographic projection of the N-well region 10 on the silicon substrate. The thirty-second P-type active region 132P may be in the shape of a strip extending along the first direction X, and the thirty-second P-type active region 132P may serve as the active region of the thirty-second P-type transistor P32.

[0266] In an exemplary embodiment, the thirty-second N-type active region 132N may be located outside the region where the N-well region 10 is located, and the orthographic projection of the thirty-second N-type active region 132N on the silicon substrate does not overlap with the orthographic projection of the N-well region 10 on the silicon substrate. The thirty-second N-type active region 132N may be in the shape of a strip extending along the first direction X and located on one side of the thirty-second P-type active region 132P in the second direction Y. The thirty-second N-type active region 132N may serve as the active region of the thirty-second N-type transistor N32.

[0267] In an exemplary embodiment, the thirty-third P-type active region 133P may be located within the region where the N-well region 10 is located, and the orthographic projection of the thirty-third P-type active region 133P on the silicon substrate is located within the range of the orthographic projection of the N-well region 10 on the silicon substrate. The thirty-third P-type active region 133P may be in the shape of a strip extending along the first direction X, and the thirty-third P-type active region 133P may serve as the active region of the thirty-third P-type transistor P33.

[0268] In exemplary embodiments, the thirty-second P-type active region 132P and the thirty-third P-type active region 133P may be an integral structure connected to each other.

[0269] In an exemplary embodiment, the thirty-third N-type active region 133N may be located outside the region where the N-well region 10 is located, and the orthographic projection of the thirty-third N-type active region 133N on the silicon substrate does not overlap with the orthographic projection of the N-well region 10 on the silicon substrate. The thirty-third N-type active region 133N may be in the shape of a strip extending along the first direction X and located on one side of the thirty-third P-type active region 133P in the second direction Y. The thirty-third N-type active region 133N may serve as the active region of the thirty-third N-type transistor N33.

[0270] In exemplary embodiments, the thirty-second N-type active region 132N and the thirty-third N-type active region 133N may be an integral structure connected to each other.

[0271] In an exemplary embodiment, the thirty-fourth P-type active region 134P may be located within the region where the N-well region 10 is located, and the orthographic projection of the thirty-fourth P-type active region 134P on the silicon substrate is located within the range of the orthographic projection of the N-well region 10 on the silicon substrate. The thirty-fourth P-type active region 134P may be in the shape of a strip extending along the first direction X, and the thirty-fourth P-type active region 134P may serve as the active region of the thirty-fourth P-type transistor P34.

[0272] In an exemplary embodiment, the thirty-fourth N-type active region 134N may be located outside the region where the N-well region 10 is located, and the orthographic projection of the thirty-fourth N-type active region 134N on the silicon substrate does not overlap with the orthographic projection of the N-well region 10 on the silicon substrate. The thirty-fourth N-type active region 134N may be in the shape of a strip extending along the first direction X and located on one side of the thirty-fourth P-type active region 134P in the second direction Y. The thirty-fourth N-type active region 134N may serve as the active region of the thirty-fourth N-type transistor N34.

[0273] In an exemplary embodiment, the thirty-fifth P-type active region 135P may be located within the region where the N-well region 10 is located, and the orthographic projection of the thirty-fifth P-type active region 135P on the silicon substrate is located within the range of the orthographic projection of the N-well region 10 on the silicon substrate. The thirty-fifth P-type active region 135P may be in the shape of a strip extending along the first direction X, and the thirty-fifth P-type active region 135P may serve as the active region of the thirty-fifth P-type transistor P35.

[0274] In exemplary embodiments, the thirty-fourth P-type active region 134P and the thirty-fifth P-type active region 135P may be an integral structure connected to each other.

[0275] In an exemplary embodiment, the thirty-fifth N-type active region 135N may be located outside the region where the N-well region 10 is located, and the orthographic projection of the thirty-fifth N-type active region 135N on the silicon substrate does not overlap with the orthographic projection of the N-well region 10 on the silicon substrate. The thirty-fifth N-type active region 135N may be in the shape of a strip extending along the first direction X and located on one side of the thirty-fifth P-type active region 135P in the second direction Y. The thirty-fifth N-type active region 135N may serve as the active region of the thirty-fifth N-type transistor N35.

[0276] In exemplary embodiments, the thirty-fourth N-type active region 134N and the thirty-fifth N-type active region 135N may be an integral structure connected to each other.

[0277] In an exemplary embodiment, the thirty-sixth P-type active region 136P may be located within the region where the N-well region 10 is located, and the orthographic projection of the thirty-sixth P-type active region 136P on the silicon substrate is located within the range of the orthographic projection of the N-well region 10 on the silicon substrate. The thirty-sixth P-type active region 136P may be in the shape of a strip extending along the first direction X, and the thirty-sixth P-type active region 136P may serve as the active region of the thirty-sixth P-type transistor P36.

[0278] In an exemplary embodiment, the thirty-sixth N-type active region 136N may be located outside the region where the N-well region 10 is located, and the orthographic projection of the thirty-sixth N-type active region 136N on the silicon substrate does not overlap with the orthographic projection of the N-well region 10 on the silicon substrate. The thirty-sixth N-type active region 136N may be in the shape of a strip extending along the first direction X and located on one side of the thirty-sixth P-type active region 136P in the second direction Y. The thirty-sixth N-type active region 136N may serve as the active region of the thirty-sixth N-type transistor N36.

[0279] In an exemplary embodiment, the thirty-seventh P-type active region 137P may be located within the region where the N-well region 10 is located, and the orthographic projection of the thirty-seventh P-type active region 137P on the silicon substrate may be located within the range of the orthographic projection of the N-well region 10 on the silicon substrate. The thirty-seventh P-type active region 137P may be in the shape of a strip extending along the first direction X, and the thirty-seventh P-type active region 137P may serve as the active region of the thirty-seventh P-type transistor P37.

[0280] In exemplary embodiments, the thirty-sixth P-type active region 136P and the thirty-seventh P-type active region 137P may be an integral structure connected to each other.

[0281] In an exemplary embodiment, the thirty-seventh N-type active region 137N may be located outside the region where the N-well region 10 is located, and the orthographic projection of the thirty-seventh N-type active region 137N on the silicon substrate does not overlap with the orthographic projection of the N-well region 10 on the silicon substrate. The thirty-seventh N-type active region 137N may be in the shape of a strip extending along the first direction X and located on one side of the thirty-seventh P-type active region 137P in the second direction Y. The thirty-seventh N-type active region 137N may serve as the active region of the thirty-seventh N-type transistor N37.

[0282] In exemplary embodiments, the thirty-sixth N-type active region 136N and the thirty-seventh N-type active region 137N may be an integral structure connected to each other.

[0283] In an exemplary embodiment, the thirty-eighth P-type active region 138P may be located within the region where the N-well region 10 is located, and the orthographic projection of the thirty-eighth P-type active region 138P on the silicon substrate is located within the range of the orthographic projection of the N-well region 10 on the silicon substrate. The thirty-eighth P-type active region 138P may be in the shape of a strip extending along the first direction X. The thirty-eighth P-type active region 138P may serve as the active region of the thirty-eighth P-type transistor P38.

[0284] In an exemplary embodiment, the thirty-eighth N-type active region 138N may be located outside the region where the N-well region 10 is located, and the orthographic projection of the thirty-eighth N-type active region 138N on the silicon substrate does not overlap with the orthographic projection of the N-well region 10 on the silicon substrate. The thirty-eighth N-type active region 138N may be in the shape of a strip extending along the first direction X and located on one side of the thirty-eighth P-type active region 138P in the second direction Y. The thirty-eighth N-type active region 138N may serve as the active region of the thirty-eighth N-type transistor N38.

[0285] In an exemplary embodiment, the thirty-ninth P-type active region 139P may be located within the region where the N-well region 10 is located, and the orthographic projection of the thirty-ninth P-type active region 139P on the silicon substrate is located within the range of the orthographic projection of the N-well region 10 on the silicon substrate. The thirty-ninth P-type active region 139P may be in the shape of a strip extending along the first direction X, and the thirty-ninth P-type active region 139P may serve as the active region of the thirty-ninth P-type transistor P39.

[0286] In exemplary embodiments, the thirty-eighth P-type active region 138P and the thirty-ninth P-type active region 139P may be an integral structure connected to each other.

[0287] In an exemplary embodiment, the thirty-ninth N-type active region 139N may be located outside the region where the N-well region 10 is located, and the orthographic projection of the thirty-ninth N-type active region 139N on the silicon substrate does not overlap with the orthographic projection of the N-well region 10 on the silicon substrate. The thirty-ninth N-type active region 139N may be in the shape of a strip extending along the first direction X and located on one side of the thirty-ninth P-type active region 139P in the second direction Y. The thirty-ninth N-type active region 139N may serve as the active region of the thirty-ninth N-type transistor N39.

[0288] In exemplary embodiments, the thirty-eighth N-type active region 138N and the thirty-ninth N-type active region 139N may be an integral structure connected to each other.

[0289] In an exemplary embodiment, in the second region LD, the twenty-first P-type active region 121P to the thirty-ninth P-type active region 139P can be sequentially arranged along the first direction X (along the direction close to the display area), and the twenty-first N-type active region 121N to the thirty-ninth N-type active region 139N can be sequentially arranged along the first direction X (along the direction close to the display area).

[0290] In an exemplary embodiment, the active width of the P-type active region in the fourth NOR gate and the second NAND gate may be greater than the active width of the P-type active region in the fifth to tenth inverters. The active width may be the size of the active region in the second direction Y.

[0291] In an exemplary embodiment, the forty-first to forty-fifth P-type active regions 141P to 145P may be disposed in the third zone LZ and serve as P-type active regions for a plurality of P-type transistors in the third operation circuit. The forty-first to forty-fifth N-type active regions 141N to 145N may be disposed in the third zone LZ and serve as N-type active regions for a plurality of N-type transistors in the third operation circuit.

[0292] In an exemplary embodiment, the forty-first P-type active region 141P may be located within the region where the N-well region 10 is located, and the orthographic projection of the forty-first P-type active region 141P on the silicon substrate is located within the range of the orthographic projection of the N-well region 10 on the silicon substrate. The forty-first P-type active region 141P may be in the shape of a strip extending along the first direction X, and the forty-first P-type active region 141P may serve as the active region of the forty-first P-type transistor P41.

[0293] In an exemplary embodiment, the forty-first N-type active region 141N may be located outside the region where the N-well region 10 is located, and the orthographic projection of the forty-first N-type active region 141N on the silicon substrate does not overlap with the orthographic projection of the N-well region 10 on the silicon substrate. The forty-first N-type active region 141N may be in the shape of a strip extending along the first direction X and located on one side of the forty-first P-type active region 141P in the second direction Y. The forty-first N-type active region 141N may serve as the active region of the forty-first N-type transistor N41.

[0294] In an exemplary embodiment, the forty-second P-type active region 142P may be located within the region where the N-well region 10 is located, and the orthographic projection of the forty-second P-type active region 142P on the silicon substrate is located within the range of the orthographic projection of the N-well region 10 on the silicon substrate. The forty-second P-type active region 142P may be in the shape of a strip extending along the first direction X, and the forty-second P-type active region 142P may serve as the active region of the forty-second P-type transistor P42.

[0295] In an exemplary embodiment, the forty-second N-type active region 142N may be located outside the region where the N-well region 10 is located, and the orthographic projection of the forty-second N-type active region 142N on the silicon substrate does not overlap with the orthographic projection of the N-well region 10 on the silicon substrate. The forty-second N-type active region 142N may be in the shape of a strip extending along the first direction X and located on one side of the forty-second P-type active region 142P in the second direction Y. The forty-second N-type active region 142N may serve as the active region of the forty-second N-type transistor N42.

[0296] In an exemplary embodiment, the forty-third P-type active region 143P may be located within the region where the N-well region 10 is located, and the orthographic projection of the forty-third P-type active region 143P on the silicon substrate may be located within the range of the orthographic projection of the N-well region 10 on the silicon substrate. The forty-third P-type active region 143P may be in the shape of a strip extending along the first direction X, and the forty-third P-type active region 143P may serve as the active region of the forty-third P-type transistor P43.

[0297] In an exemplary embodiment, the forty-third N-type active region 143N may be located outside the region where the N-well region 10 is located, and the orthographic projection of the forty-third N-type active region 143N on the silicon substrate does not overlap with the orthographic projection of the N-well region 10 on the silicon substrate. The forty-third N-type active region 143N may be in the shape of a strip extending along the first direction X and located on one side of the forty-third P-type active region 143P in the second direction Y. The forty-third N-type active region 143N may serve as the active region of the forty-third N-type transistor N43.

[0298] In exemplary embodiments, the forty-first P-type active region 141P, the forty-second P-type active region 142P, and the forty-third P-type active region 143P may be an integral structure connected to each other.

[0299] In exemplary embodiments, the forty-first N-type active region 141N, the forty-second N-type active region 142N, and the forty-third N-type transistor N43 may be an integral structure connected to each other.

[0300] In an exemplary embodiment, the forty-fourth P-type active region 144P may be located within the region where the N-well region 10 is located, and the orthographic projection of the forty-fourth P-type active region 144P on the silicon substrate may be located within the range of the orthographic projection of the N-well region 10 on the silicon substrate. The forty-fourth P-type active region 144P may be in the shape of a strip extending along the first direction X, and the forty-fourth P-type active region 144P may serve as the active region of the forty-fourth P-type transistor P44.

[0301] In an exemplary embodiment, the forty-fourth N-type active region 144N may be located outside the region where the N-well region 10 is located, and the orthographic projection of the forty-fourth N-type active region 144N on the silicon substrate does not overlap with the orthographic projection of the N-well region 10 on the silicon substrate. The forty-fourth N-type active region 144N may be in the shape of a strip extending along the first direction X and located on one side of the forty-fourth P-type active region 144P in the second direction Y. The forty-fourth N-type active region 144N may serve as the active region of the forty-fourth N-type transistor N44.

[0302] In an exemplary embodiment, the forty-fifth P-type active region 145P may be located within the region where the N-well region 10 is located, and the orthographic projection of the forty-fifth P-type active region 145P on the silicon substrate is located within the range of the orthographic projection of the N-well region 10 on the silicon substrate. The forty-fifth P-type active region 145P may be in the shape of a strip extending along the first direction X, and the forty-fifth P-type active region 145P may serve as the active region of the forty-fifth P-type transistor P45.

[0303] In an exemplary embodiment, the forty-fifth N-type active region 145N may be located outside the region where the N-well region 10 is located, and the orthographic projection of the forty-fifth N-type active region 145N on the silicon substrate does not overlap with the orthographic projection of the N-well region 10 on the silicon substrate. The forty-fifth N-type active region 145N may be in the shape of a strip extending along the first direction X and located on one side of the forty-fifth P-type active region 145P in the second direction Y. The forty-fifth N-type active region 145N may serve as the active region of the forty-fifth N-type transistor N45.

[0304] In exemplary embodiments, the forty-fourth P-type active region 144P and the forty-fifth P-type active region 145P may be an integral structure connected to each other.

[0305] In exemplary embodiments, the forty-fourth N-type active region 144N and the forty-fifth N-type active region 145N may be an integral structure connected to each other.

[0306] In an exemplary embodiment, the active width of the forty-first P-type active region 141P (the forty-second P-type active region 142P and the forty-third P-type active region 143P) may be greater than the active width of the forty-fourth P-type active region 144P (the forty-fifth P-type active region 145P), that is, the active width of the P-type transistor in the fifth NOR gate is greater than the active width of the P-type transistor in the third NAND gate, and the active width may be the dimension of the active region in the second direction Y.

[0307] In an exemplary embodiment, in the third region LZ, the forty-first to forty-fifth P-type active regions 141P to 145P may be sequentially disposed along the first direction X, and the forty-first to forty-fifth N-type active regions 141N to 145N may be sequentially disposed along the first direction X.

[0308] In an exemplary embodiment, multiple N-type active regions can be located on one side of the multiple P-type active regions in the second direction Y, forming a compact arrangement layout that is separated in the second direction Y (separated up and down) and arranged sequentially in the first direction X (in a long strip shape).

[0309] In an exemplary embodiment, in the second direction Y, a gap region 50 may be provided between the plurality of P-type active regions and the plurality of N-type active regions. The gap region 50 is configured to serve as an isolation region between the P-type transistor and the N-type transistor on the one hand, and is configured to accommodate a gate via connecting the gate conductive layer and the first conductive layer on the other hand, thereby optimizing the structural layout of the gate drive circuit.

[0310] In an exemplary embodiment, edges of the plurality of P-type active regions close to the gap region 50 may be substantially located on the same straight line extending along the first direction X, and edges of the plurality of N-type active regions close to the gap region 50 may be substantially located on the same straight line extending along the first direction X.

[0311] In an exemplary embodiment, the widths of the gap regions 50 in some transistor groups may be substantially the same, and the widths of the gap regions 50 in other transistor groups may be different. The width of the gap region may be a dimension in the second direction Y.

[0312] In the embodiment of the present disclosure, the widths of the plurality of gap regions 50 may be substantially the same, the edges of the plurality of P-type active regions close to the gap region 50 may be substantially located on the same straight line extending along the first direction X, and the edges of the plurality of N-type active regions close to the gap region 50 may be substantially located on the same straight line extending along the first direction X.

[0313] In an exemplary embodiment, the distance between the P-type active region and the N-type active region in a transistor group may be equivalent to the distance between the P-type transistor and the N-type transistor in the transistor group, that is, the gap region 50 may be the gap region 50 between the P-type transistor and the N-type transistor.

[0314] By setting the positions of the P-type active area and the N-type active area, the present disclosure can effectively ensure the shortest connection lines between devices, optimize the layout design space, ensure that the resistance and capacitance loading (RC loading) of the gate electrodes of the P-type transistor and the N-type transistor are basically consistent, and improve uniformity.

[0315] In an exemplary embodiment, the power active region 100P may be located within the region where the N-well region 10 is located, and the orthographic projection of the power active region 100P on the silicon substrate may be within the range of the orthographic projection of the N-well region 10 on the silicon substrate. The power active region 100P may be in the shape of a straight line or a broken line extending along a first direction X. The power active region 100P may be located on one side of the plurality of P-type active regions opposite to the second direction Y, that is, on a side of the plurality of P-type active regions away from the plurality of N-type active regions. The power active region 100P is configured to be connected to a first power line to be formed subsequently.

[0316] In an exemplary embodiment, the grounding active region 100N may be located outside the region where the N-well region 10 is located, and the orthographic projection of the grounding active region 100N on the silicon substrate does not overlap with the orthographic projection of the N-well region 10 on the silicon substrate. The grounding active region 100N may be in the shape of a straight line or a broken line extending along a first direction X. The grounding active region 100N may be located on one side of the multiple N-type active regions in the second direction Y, that is, on a side of the multiple N-type active regions away from the multiple P-type active regions. The grounding active region 100N is configured to be connected to a ground line to be formed later.

[0317] In an exemplary embodiment, a P-type active region in a transistor group may have a P-type active region width, and an N-type active region may have an N-type active region width. The P-type active region width may be the distance between an edge of the P-type active region on a side close to the power active region and an edge of the P-type active region on a side away from the power active region. The N-type active region width may be the distance between an edge of the N-type active region on a side close to the ground active region and an edge of the second N-type active region on a side away from the ground active region. The P-type active region width and the N-type active region width may be dimensions in the second direction Y.

[0318] In an exemplary embodiment, the widths of the P-type active regions of devices of the same type may be substantially the same, and the widths of the N-type active regions of devices of the same type may be substantially the same. For example, in a plurality of inverters, the widths of the P-type active regions may be substantially the same, and the widths of the N-type active regions may be substantially the same. For another example, in a plurality of NAND gates, the widths of the P-type active regions may be substantially the same, and the widths of the N-type active regions may be substantially the same. For another example, in a plurality of NOR gates, the widths of the P-type active regions may be substantially the same, and the widths of the N-type active regions may be substantially the same.

[0319] In an exemplary embodiment, the widths of the P-type active regions of different types of devices may be different, and the widths of the N-type active regions of different types of devices may be different.

[0320] In an exemplary embodiment, the width of the P-type active region in the NAND gate may be greater than that in the inverter, and the width of the N-type active region in the NAND gate may be greater than that in the inverter.

[0321] In an exemplary embodiment, the width of the P-type active region in the NOR gate may be greater than that in the inverter, and the width of the N-type active region in the NOR gate may be greater than that in the inverter.

[0322] (3) Forming a gate conductive layer pattern. In an exemplary embodiment, forming the gate conductive layer pattern may include: sequentially depositing a first insulating film and a polysilicon film on the silicon substrate on which the aforementioned pattern is formed, first patterning the polysilicon film through a patterning process to form a first insulating layer covering the silicon substrate and a polysilicon layer disposed on the first insulating layer, and then doping the polysilicon layer to form a gate conductive layer pattern, as shown in FIG15A and FIG15B , where FIG15B is a schematic diagram of the gate conductive layer in FIG15A .

[0323] In an exemplary embodiment, the gate conductive layer pattern may include at least: a first P-type gate electrode 201P to a fifteenth P-type gate electrode 215P, a twenty-first P-type gate electrode 221P to a thirty-ninth P-type gate electrode 239P, a forty-first P-type gate electrode 241P to a forty-fifth P-type gate electrode 245P, and a first N-type gate electrode 201N to a fifteenth N-type gate electrode 215N, a twenty-first N-type gate electrode 221N to a thirty-ninth N-type gate electrode 239N, and a forty-first N-type gate electrode 241N to a forty-fifth N-type gate electrode 245N.

[0324] In an exemplary embodiment, the first P-type gate electrode 201P to the fifteenth P-type gate electrode 215P, and the first N-type gate electrode 201N to the fifteenth N-type gate electrode 215N can be set in the first region LW, serving as the P-type gate electrodes of multiple P-type transistors and the N-type gate electrodes of multiple N-type transistors in the first operational circuit.

[0325] In an exemplary embodiment, the shape of the first P-type gate electrode 201P can be a strip shape extending along the second direction Y, the orthographic projection of the first P-type gate electrode 201P on the silicon substrate at least partially overlaps with the orthographic projection of the first P-type active region 101P on the silicon substrate, and the first P-type gate electrode 201P can serve as the gate electrode of the first P-type transistor P1.

[0326] In an exemplary embodiment, the shape of the first N-type gate electrode 201N can be a strip shape extending along the second direction Y, the orthographic projection of the first N-type gate electrode 201N on the silicon substrate at least partially overlaps with the orthographic projection of the first N-type active region 101N on the silicon substrate, and the first N-type gate electrode 201N can serve as the gate electrode of the first N-type transistor N1.

[0327] In an exemplary embodiment, the first P-type gate electrode 201P and the first N-type gate electrode 201N may be an integral structure connected to each other.

[0328] In an exemplary embodiment, the shape of the second P-type gate electrode 202P can be a strip shape extending along the second direction Y, and the orthographic projection of the second P-type gate electrode 202P on the silicon substrate at least partially overlaps with the orthographic projection of the second P-type active region 102P on the silicon substrate. The second P-type gate electrode 202P can serve as the gate electrode of the second P-type transistor P2.

[0329] In an exemplary embodiment, the second N-type gate electrode 202N may be in the shape of a strip extending along the second direction Y, and the orthographic projection of the second N-type gate electrode 202N on the silicon substrate at least partially overlaps with the orthographic projection of the second N-type active region 102N on the silicon substrate. The second N-type gate electrode 202N may serve as the gate electrode of the second N-type transistor N2.

[0330] In an exemplary embodiment, the second P-type gate electrode 202P and the second N-type gate electrode 202N may be an integral structure connected to each other.

[0331] In an exemplary embodiment, the shape of the third P-type gate electrode 203P can be a strip shape extending along the second direction Y, and the orthographic projection of the third P-type gate electrode 203P on the silicon substrate at least partially overlaps with the orthographic projection of the third P-type active area 103P on the silicon substrate, and the third P-type gate electrode 203P can serve as the gate electrode of the third P-type transistor P3.

[0332] In an exemplary embodiment, the shape of the third N-type gate electrode 203N can be a strip shape extending along the second direction Y, the orthographic projection of the third N-type gate electrode 203N on the silicon substrate at least partially overlaps with the orthographic projection of the third N-type active region 103N on the silicon substrate, and the third N-type gate electrode 203N can serve as the gate electrode of the third N-type transistor N3.

[0333] In an exemplary embodiment, the third P-type gate electrode 203P and the third N-type gate electrode 203N may be an integral structure connected to each other.

[0334] In an exemplary embodiment, the shape of the fourth P-type gate electrode 204P can be a strip shape extending along the second direction Y, and the orthographic projection of the fourth P-type gate electrode 204P on the silicon substrate at least partially overlaps with the orthographic projection of the fourth P-type active region 104P on the silicon substrate, and the fourth P-type gate electrode 204P can serve as the gate electrode of the fourth P-type transistor P4.

[0335] In an exemplary embodiment, the fourth N-type gate electrode 204N may be in the shape of a strip extending along the second direction Y, and the orthographic projection of the fourth N-type gate electrode 204N on the silicon substrate at least partially overlaps with the orthographic projection of the fourth N-type active region 104N on the silicon substrate. The fourth N-type gate electrode 204N may serve as the gate electrode of the fourth N-type transistor N4.

[0336] In an exemplary embodiment, the fourth P-type gate electrode 204P and the fourth N-type gate electrode 204N may be an integral structure connected to each other.

[0337] In an exemplary embodiment, the shape of the fifth P-type gate electrode 205P can be a strip shape extending along the second direction Y, and the orthographic projection of the fifth P-type gate electrode 205P on the silicon substrate at least partially overlaps with the orthographic projection of the fifth P-type active region 105P on the silicon substrate, and the fifth P-type gate electrode 205P can serve as the gate electrode of the fifth P-type transistor P5.

[0338] In an exemplary embodiment, the shape of the fifth N-type gate electrode 205N can be a strip shape extending along the second direction Y, the orthographic projection of the fifth N-type gate electrode 205N on the silicon substrate at least partially overlaps with the orthographic projection of the fifth N-type active region 105N on the silicon substrate, and the fifth N-type gate electrode 205N can serve as the gate electrode of the fifth N-type transistor N5.

[0339] In an exemplary embodiment, the fifth P-type gate electrode 205P and the fifth N-type gate electrode 205N may be an integral structure connected to each other.

[0340] In an exemplary embodiment, the shape of the sixth P-type gate electrode 206P can be a strip shape extending along the second direction Y, the orthographic projection of the sixth P-type gate electrode 206P on the silicon substrate at least partially overlaps with the orthographic projection of the sixth P-type active region 106P on the silicon substrate, and the sixth P-type gate electrode 206P can serve as the gate electrode of the sixth P-type transistor P6.

[0341] In an exemplary embodiment, the shape of the sixth N-type gate electrode 206N can be a strip shape extending along the second direction Y, and the orthographic projection of the sixth N-type gate electrode 206N on the silicon substrate at least partially overlaps with the orthographic projection of the sixth N-type active region 106N on the silicon substrate. The sixth N-type gate electrode 206N can serve as the gate electrode of the sixth N-type transistor N6.

[0342] In an exemplary embodiment, the sixth P-type gate electrode 206P and the sixth N-type gate electrode 206N may be an integral structure connected to each other.

[0343] In an exemplary embodiment, the shape of the seventh P-type gate electrode 207P can be a strip shape extending along the second direction Y, and the orthographic projection of the seventh P-type gate electrode 207P on the silicon substrate at least partially overlaps with the orthographic projection of the seventh P-type active region 107P on the silicon substrate, and the seventh P-type gate electrode 207P can serve as the gate electrode of the seventh P-type transistor P7.

[0344] In an exemplary embodiment, the shape of the seventh N-type gate electrode 207N can be a strip shape extending along the second direction Y, the orthographic projection of the seventh N-type gate electrode 207N on the silicon substrate at least partially overlaps with the orthographic projection of the seventh N-type active region 107N on the silicon substrate, and the seventh N-type gate electrode 207N can serve as the gate electrode of the seventh N-type transistor N7.

[0345] In exemplary embodiments, the seventh P-type gate electrode 207P and the seventh N-type gate electrode 207N may be an integral structure connected to each other.

[0346] In an exemplary embodiment, the shape of the eighth P-type gate electrode 208P can be a strip shape extending along the second direction Y, the orthographic projection of the eighth P-type gate electrode 208P on the silicon substrate at least partially overlaps with the orthographic projection of the eighth P-type active region 108P on the silicon substrate, and the eighth P-type gate electrode 208P can serve as the gate electrode of the eighth P-type transistor P8.

[0347] In an exemplary embodiment, the shape of the eighth N-type gate electrode 208N can be a strip shape extending along the second direction Y, the orthographic projection of the eighth N-type gate electrode 208N on the silicon substrate at least partially overlaps with the orthographic projection of the eighth N-type active region 108N on the silicon substrate, and the eighth N-type gate electrode 208N can serve as the gate electrode of the eighth N-type transistor N8.

[0348] In an exemplary embodiment, the eighth P-type gate electrode 208P and the eighth N-type gate electrode 208N may be an integral structure connected to each other.

[0349] In an exemplary embodiment, the shape of the ninth P-type gate electrode 209P can be a strip shape extending along the second direction Y, and the orthographic projection of the ninth P-type gate electrode 209P on the silicon substrate at least partially overlaps with the orthographic projection of the ninth P-type active region 109P on the silicon substrate, and the ninth P-type gate electrode 209P can serve as the gate electrode of the ninth P-type transistor P9.

[0350] In an exemplary embodiment, the shape of the ninth N-type gate electrode 209N can be a strip shape extending along the second direction Y, and the orthographic projection of the ninth N-type gate electrode 209N on the silicon substrate at least partially overlaps with the orthographic projection of the ninth N-type active region 109N on the silicon substrate. The ninth N-type gate electrode 209N can serve as the gate electrode of the ninth N-type transistor N9.

[0351] In an exemplary embodiment, the ninth P-type gate electrode 209P and the ninth N-type gate electrode 209N may be an integral structure connected to each other.

[0352] In an exemplary embodiment, the shape of the tenth P-type gate electrode 210P can be a strip shape extending along the second direction Y, and the orthographic projection of the tenth P-type gate electrode 210P on the silicon substrate at least partially overlaps with the orthographic projection of the tenth P-type active region 110P on the silicon substrate, and the tenth P-type gate electrode 210P can serve as the gate electrode of the tenth P-type transistor P10.

[0353] In an exemplary embodiment, the shape of the tenth N-type gate electrode 210N can be a strip shape extending along the second direction Y, and the orthographic projection of the tenth N-type gate electrode 210N on the silicon substrate at least partially overlaps with the orthographic projection of the tenth N-type active region 110N on the silicon substrate. The tenth N-type gate electrode 210N can serve as the gate electrode of the tenth N-type transistor N10.

[0354] In example embodiments, the tenth P-type gate electrode 210P and the tenth N-type gate electrode 210N may be an integral structure connected to each other.

[0355] In an exemplary embodiment, the shape of the eleventh P-type gate electrode 211P can be a strip shape extending along the second direction Y, the orthographic projection of the eleventh P-type gate electrode 211P on the silicon substrate at least partially overlaps with the orthographic projection of the eleventh P-type active region 111P on the silicon substrate, and the eleventh P-type gate electrode 211P can serve as the gate electrode of the eleventh P-type transistor P11.

[0356] In an exemplary embodiment, the shape of the eleventh N-type gate electrode 211N can be a strip shape extending along the second direction Y, the orthographic projection of the eleventh N-type gate electrode 211N on the silicon substrate at least partially overlaps with the orthographic projection of the eleventh N-type active region 111N on the silicon substrate, and the eleventh N-type gate electrode 211N can serve as the gate electrode of the eleventh N-type transistor N11.

[0357] In exemplary embodiments, the eleventh P-type gate electrode 211P and the eleventh N-type gate electrode 211N may be an integral structure connected to each other.

[0358] In an exemplary embodiment, the shape of the twelfth P-type gate electrode 212P can be a strip shape extending along the second direction Y, the orthographic projection of the twelfth P-type gate electrode 212P on the silicon substrate at least partially overlaps with the orthographic projection of the twelfth P-type active region 112P on the silicon substrate, and the twelfth P-type gate electrode 212P can serve as the gate electrode of the twelfth P-type transistor P12.

[0359] In an exemplary embodiment, the shape of the twelfth N-type gate electrode 212N can be a strip shape extending along the second direction Y, the orthographic projection of the twelfth N-type gate electrode 212N on the silicon substrate at least partially overlaps with the orthographic projection of the twelfth N-type active region 112N on the silicon substrate, and the twelfth N-type gate electrode 212N can serve as the gate electrode of the twelfth N-type transistor N12.

[0360] In exemplary embodiments, the twelfth P-type gate electrode 212P and the twelfth N-type gate electrode 212N may be an integral structure connected to each other.

[0361] In an exemplary embodiment, the shape of the thirteenth P-type gate electrode 213P can be a strip shape extending along the second direction Y, the orthographic projection of the thirteenth P-type gate electrode 213P on the silicon substrate at least partially overlaps with the orthographic projection of the thirteenth P-type active region 113P on the silicon substrate, and the thirteenth P-type gate electrode 213P can serve as the gate electrode of the thirteenth P-type transistor P13.

[0362] In an exemplary embodiment, the shape of the thirteenth N-type gate electrode 213N can be a strip shape extending along the second direction Y, the orthographic projection of the thirteenth N-type gate electrode 213N on the silicon substrate at least partially overlaps with the orthographic projection of the thirteenth N-type active region 113N on the silicon substrate, and the thirteenth N-type gate electrode 213N can serve as the gate electrode of the thirteenth N-type transistor N13.

[0363] In exemplary embodiments, the thirteenth P-type gate electrode 213P and the thirteenth N-type gate electrode 213N may be an integral structure connected to each other.

[0364] In an exemplary embodiment, the shape of the fourteenth P-type gate electrode 214P can be a strip shape extending along the second direction Y, the orthographic projection of the fourteenth P-type gate electrode 214P on the silicon substrate at least partially overlaps with the orthographic projection of the fourteenth P-type active region 114P on the silicon substrate, and the fourteenth P-type gate electrode 214P can serve as the gate electrode of the fourteenth P-type transistor P14.

[0365] In an exemplary embodiment, the shape of the fourteenth N-type gate electrode 214N can be a strip shape extending along the second direction Y, the orthographic projection of the fourteenth N-type gate electrode 214N on the silicon substrate at least partially overlaps with the orthographic projection of the fourteenth N-type active region 114N on the silicon substrate, and the fourteenth N-type gate electrode 214N can serve as the gate electrode of the fourteenth N-type transistor N14.

[0366] In an exemplary embodiment, the shape of the fifteenth P-type gate electrode 215P can be a strip shape extending along the second direction Y, the orthographic projection of the fifteenth P-type gate electrode 215P on the silicon substrate at least partially overlaps with the orthographic projection of the fifteenth P-type active region 115P on the silicon substrate, and the fifteenth P-type gate electrode 215P can serve as the gate electrode of the fifteenth P-type transistor P15.

[0367] In an exemplary embodiment, the shape of the fifteenth N-type gate electrode 215N can be a strip shape extending along the second direction Y, the orthographic projection of the fifteenth N-type gate electrode 215N on the silicon substrate at least partially overlaps with the orthographic projection of the fifteenth N-type active region 115N on the silicon substrate, and the fifteenth N-type gate electrode 215N can serve as the gate electrode of the fifteenth N-type transistor N15.

[0368] In an exemplary embodiment, the two-way selector includes three transistor groups, the P-type gate electrode of the thirteenth P-type transistor P13 and the N-type gate electrode of the thirteenth N-type transistor N13 in the thirteenth transistor group are an integrated structure connected to each other, the P-type gate electrode of the fourteenth P-type transistor P14 and the N-type gate electrode of the fourteenth N-type transistor N14 in the fourteenth transistor group are a non-integrated structure, and the P-type gate electrode of the fifteenth P-type transistor P15 and the N-type gate electrode of the fifteenth N-type transistor N15 in the fifteenth transistor group are a non-integrated structure.

[0369] In an exemplary embodiment, in the first region LW, the first to fifteenth P-type gate electrodes 201P to 215P may be sequentially disposed along the first direction X, and the first to fifteenth N-type gate electrodes 201N to 215N may be sequentially disposed along the first direction X.

[0370] In an exemplary embodiment, the twenty-first P-type gate electrode 221P to the thirty-ninth P-type gate electrode 239P, and the twenty-first N-type gate electrode 221N to the thirty-ninth N-type gate electrode 239N can be set in the second region LD, serving as the P-type gate electrodes of multiple P-type transistors and the N-type gate electrodes of multiple N-type transistors in the second operational circuit.

[0371] In an exemplary embodiment, the shape of the twenty-first P-type gate electrode 221P can be a strip shape extending along the second direction Y, the orthographic projection of the twenty-first P-type gate electrode 221P on the silicon substrate at least partially overlaps with the orthographic projection of the twenty-first P-type active region 121P on the silicon substrate, and the twenty-first P-type gate electrode 221P can serve as the gate electrode of the twenty-first P-type transistor P21.

[0372] In an exemplary embodiment, the shape of the twenty-first N-type gate electrode 221N can be a strip shape extending along the second direction Y, the orthographic projection of the twenty-first N-type gate electrode 221N on the silicon substrate at least partially overlaps with the orthographic projection of the twenty-first N-type active region 121N on the silicon substrate, and the twenty-first N-type gate electrode 221N can serve as the gate electrode of the twenty-first N-type transistor N21.

[0373] In exemplary embodiments, the twenty-first P-type gate electrode 221P and the twenty-first N-type gate electrode 221N may be an integral structure connected to each other.

[0374] In an exemplary embodiment, the shape of the twenty-second P-type gate electrode 222P can be a strip shape extending along the second direction Y, and the orthographic projection of the twenty-second P-type gate electrode 222P on the silicon substrate at least partially overlaps with the orthographic projection of the twenty-second P-type active region 122P on the silicon substrate, and the twenty-second P-type gate electrode 222P can serve as the gate electrode of the twenty-second P-type transistor P22.

[0375] In an exemplary embodiment, the shape of the twenty-second N-type gate electrode 222N can be a strip shape extending along the second direction Y, the orthographic projection of the twenty-second N-type gate electrode 222N on the silicon substrate at least partially overlaps with the orthographic projection of the twenty-second N-type active region 122N on the silicon substrate, and the twenty-second N-type gate electrode 222N can serve as the gate electrode of the twenty-second N-type transistor N22.

[0376] In exemplary embodiments, the twenty-second P-type gate electrode 222P and the twenty-second N-type gate electrode 222N may be an integral structure connected to each other.

[0377] In an exemplary embodiment, the shape of the twenty-third P-type gate electrode 223P can be a strip shape extending along the second direction Y, the orthographic projection of the twenty-third P-type gate electrode 223P on the silicon substrate at least partially overlaps with the orthographic projection of the twenty-third P-type active area 123P on the silicon substrate, and the twenty-third P-type gate electrode 223P can serve as the gate electrode of the twenty-third P-type transistor P23.

[0378] In an exemplary embodiment, the shape of the twenty-third N-type gate electrode 223N can be a strip shape extending along the second direction Y, the orthographic projection of the twenty-third N-type gate electrode 223N on the silicon substrate at least partially overlaps with the orthographic projection of the twenty-third N-type active area 123N on the silicon substrate, and the twenty-third N-type gate electrode 223N can serve as the gate electrode of the twenty-third N-type transistor N23.

[0379] In exemplary embodiments, the twenty-third P-type gate electrode 223P and the twenty-third N-type gate electrode 223N may be an integral structure connected to each other.

[0380] In an exemplary embodiment, the shape of the twenty-fourth P-type gate electrode 224P can be a strip shape extending along the second direction Y, the orthographic projection of the twenty-fourth P-type gate electrode 224P on the silicon substrate at least partially overlaps with the orthographic projection of the twenty-fourth P-type active area 124P on the silicon substrate, and the twenty-fourth P-type gate electrode 224P can serve as the gate electrode of the twenty-fourth P-type transistor P24.

[0381] In an exemplary embodiment, the shape of the twenty-fourth N-type gate electrode 224N can be a strip shape extending along the second direction Y, the orthographic projection of the twenty-fourth N-type gate electrode 224N on the silicon substrate at least partially overlaps with the orthographic projection of the twenty-fourth N-type active region 124N on the silicon substrate, and the twenty-fourth N-type gate electrode 224N can serve as the gate electrode of the twenty-fourth N-type transistor N24.

[0382] In exemplary embodiments, the twenty-fourth P-type gate electrode 224P and the twenty-fourth N-type gate electrode 224N may be an integral structure connected to each other.

[0383] In an exemplary embodiment, the shape of the twenty-fifth P-type gate electrode 225P can be a strip shape extending along the second direction Y, the orthographic projection of the twenty-fifth P-type gate electrode 225P on the silicon substrate at least partially overlaps with the orthographic projection of the twenty-fifth P-type active area 125P on the silicon substrate, and the twenty-fifth P-type gate electrode 225P can serve as the gate electrode of the twenty-fifth P-type transistor P25.

[0384] In an exemplary embodiment, the shape of the twenty-fifth N-type gate electrode 225N can be a strip shape extending along the second direction Y, the orthographic projection of the twenty-fifth N-type gate electrode 225N on the silicon substrate at least partially overlaps with the orthographic projection of the twenty-fifth N-type active area 125N on the silicon substrate, and the twenty-fifth N-type gate electrode 225N can serve as the gate electrode of the twenty-fifth N-type transistor N25.

[0385] In exemplary embodiments, the twenty-fifth P-type gate electrode 225P and the twenty-fifth N-type gate electrode 225N may be an integral structure connected to each other.

[0386] In an exemplary embodiment, the shape of the twenty-sixth P-type gate electrode 226P can be a strip shape extending along the second direction Y, the orthographic projection of the twenty-sixth P-type gate electrode 226P on the silicon substrate at least partially overlaps with the orthographic projection of the twenty-sixth P-type active region 126P on the silicon substrate, and the twenty-sixth P-type gate electrode 226P can serve as the gate electrode of the twenty-sixth P-type transistor P26.

[0387] In an exemplary embodiment, the shape of the twenty-sixth N-type gate electrode 226N can be a strip shape extending along the second direction Y, the orthographic projection of the twenty-sixth N-type gate electrode 226N on the silicon substrate at least partially overlaps with the orthographic projection of the twenty-sixth N-type active region 126N on the silicon substrate, and the twenty-sixth N-type gate electrode 226N can serve as the gate electrode of the twenty-sixth N-type transistor N26.

[0388] In exemplary embodiments, the twenty-sixth P-type gate electrode 226P and the twenty-sixth N-type gate electrode 226N may be an integral structure connected to each other.

[0389] In an exemplary embodiment, the shape of the twenty-seventh P-type gate electrode 227P can be a strip shape extending along the second direction Y, the orthographic projection of the twenty-seventh P-type gate electrode 227P on the silicon substrate at least partially overlaps with the orthographic projection of the twenty-seventh P-type active region 127P on the silicon substrate, and the twenty-seventh P-type gate electrode 227P can serve as the gate electrode of the twenty-seventh P-type transistor P27.

[0390] In an exemplary embodiment, the shape of the twenty-seventh N-type gate electrode 227N can be a strip shape extending along the second direction Y, the orthographic projection of the twenty-seventh N-type gate electrode 227N on the silicon substrate at least partially overlaps with the orthographic projection of the twenty-seventh N-type active region 127N on the silicon substrate, and the twenty-seventh N-type gate electrode 227N can serve as the gate electrode of the twenty-seventh N-type transistor N27.

[0391] In exemplary embodiments, the twenty-seventh P-type gate electrode 227P and the twenty-seventh N-type gate electrode 227N may be an integral structure connected to each other.

[0392] In an exemplary embodiment, the shape of the twenty-eighth P-type gate electrode 228P can be a strip shape extending along the second direction Y, the orthographic projection of the twenty-eighth P-type gate electrode 228P on the silicon substrate at least partially overlaps with the orthographic projection of the twenty-eighth P-type active region 128P on the silicon substrate, and the twenty-eighth P-type gate electrode 228P can serve as the gate electrode of the twenty-eighth P-type transistor P28.

[0393] In an exemplary embodiment, the shape of the twenty-eighth N-type gate electrode 228N can be a strip shape extending along the second direction Y, the orthographic projection of the twenty-eighth N-type gate electrode 228N on the silicon substrate at least partially overlaps with the orthographic projection of the twenty-eighth N-type active region 128N on the silicon substrate, and the twenty-eighth N-type gate electrode 228N can serve as the gate electrode of the twenty-eighth N-type transistor N28.

[0394] In exemplary embodiments, the twenty-eighth P-type gate electrode 228P and the twenty-eighth N-type gate electrode 228N may be an integral structure connected to each other.

[0395] In an exemplary embodiment, the shape of the twenty-ninth P-type gate electrode 229P can be a strip shape extending along the second direction Y, the orthographic projection of the twenty-ninth P-type gate electrode 229P on the silicon substrate at least partially overlaps with the orthographic projection of the twenty-ninth P-type active region 129P on the silicon substrate, and the twenty-ninth P-type gate electrode 229P can serve as the gate electrode of the twenty-ninth P-type transistor P29.

[0396] In an exemplary embodiment, the shape of the twenty-ninth N-type gate electrode 229N can be a strip shape extending along the second direction Y, the orthographic projection of the twenty-ninth N-type gate electrode 229N on the silicon substrate at least partially overlaps with the orthographic projection of the twenty-ninth N-type active region 129N on the silicon substrate, and the twenty-ninth N-type gate electrode 229N can serve as the gate electrode of the twenty-ninth N-type transistor N29.

[0397] In exemplary embodiments, the twenty-ninth P-type gate electrode 229P and the twenty-ninth N-type gate electrode 229N may be an integral structure connected to each other.

[0398] In an exemplary embodiment, the shape of the thirtieth P-type gate electrode 230P can be a strip shape extending along the second direction Y, the orthographic projection of the thirtieth P-type gate electrode 230P on the silicon substrate at least partially overlaps with the orthographic projection of the thirtieth P-type active area 130P on the silicon substrate, and the thirtieth P-type gate electrode 230P can serve as the gate electrode of the thirtieth P-type transistor P30.

[0399] In an exemplary embodiment, the shape of the 30th N-type gate electrode 230N can be a strip shape extending along the second direction Y, the orthographic projection of the 30th N-type gate electrode 230N on the silicon substrate at least partially overlaps with the orthographic projection of the 30th N-type active region 130N on the silicon substrate, and the 30th N-type gate electrode 230N can serve as the gate electrode of the 30th N-type transistor N30.

[0400] In exemplary embodiments, the thirtieth P-type gate electrode 230P and the thirtieth N-type gate electrode 230N may be an integral structure connected to each other.

[0401] In an exemplary embodiment, the shape of the thirty-first P-type gate electrode 231P can be a strip shape extending along the second direction Y, the orthographic projection of the thirty-first P-type gate electrode 231P on the silicon substrate at least partially overlaps with the orthographic projection of the thirty-first P-type active area 131P on the silicon substrate, and the thirty-first P-type gate electrode 231P can serve as the gate electrode of the thirty-first P-type transistor P31.

[0402] In an exemplary embodiment, the shape of the thirty-first N-type gate electrode 231N can be a strip shape extending along the second direction Y, and the orthographic projection of the thirty-first N-type gate electrode 231N on the silicon substrate at least partially overlaps with the orthographic projection of the thirty-first N-type active area 131N on the silicon substrate. The thirty-first N-type gate electrode 231N can serve as the gate electrode of the thirty-first N-type transistor N31.

[0403] In exemplary embodiments, the thirty-first P-type gate electrode 231P and the thirty-first N-type gate electrode 231N may be an integral structure connected to each other.

[0404] In an exemplary embodiment, the shape of the thirty-second P-type gate electrode 232P can be a strip shape extending along the second direction Y, and the orthographic projection of the thirty-second P-type gate electrode 232P on the silicon substrate at least partially overlaps with the orthographic projection of the thirty-second P-type active region 132P on the silicon substrate, and the thirty-second P-type gate electrode 232P can serve as the gate electrode of the thirty-second P-type transistor P32.

[0405] In an exemplary embodiment, the shape of the thirty-second N-type gate electrode 232N can be a strip shape extending along the second direction Y, the orthographic projection of the thirty-second N-type gate electrode 232N on the silicon substrate at least partially overlaps with the orthographic projection of the thirty-second N-type active region 132N on the silicon substrate, and the thirty-second N-type gate electrode 232N can serve as the gate electrode of the thirty-second N-type transistor N32.

[0406] In exemplary embodiments, the thirty-second P-type gate electrode 232P and the thirty-second N-type gate electrode 232N may be an integral structure connected to each other.

[0407] In an exemplary embodiment, the shape of the thirty-third P-type gate electrode 233P can be a strip shape extending along the second direction Y, the orthographic projection of the thirty-third P-type gate electrode 233P on the silicon substrate at least partially overlaps with the orthographic projection of the thirty-third P-type active area 133P on the silicon substrate, and the thirty-third P-type gate electrode 233P can serve as the gate electrode of the thirty-third P-type transistor P33.

[0408] In an exemplary embodiment, the shape of the thirty-third N-type gate electrode 233N can be a strip shape extending along the second direction Y, the orthographic projection of the thirty-third N-type gate electrode 233N on the silicon substrate at least partially overlaps with the orthographic projection of the thirty-third N-type active area 133N on the silicon substrate, and the thirty-third N-type gate electrode 233N can serve as the gate electrode of the thirty-third N-type transistor N33.

[0409] In exemplary embodiments, the thirty-third P-type gate electrode 233P and the thirty-third N-type gate electrode 233N may be an integral structure connected to each other.

[0410] In an exemplary embodiment, the shape of the thirty-fourth P-type gate electrode 234P can be a strip shape extending along the second direction Y, the orthographic projection of the thirty-fourth P-type gate electrode 234P on the silicon substrate at least partially overlaps with the orthographic projection of the thirty-fourth P-type active area 134P on the silicon substrate, and the thirty-fourth P-type gate electrode 234P can serve as the gate electrode of the thirty-fourth P-type transistor P34.

[0411] In an exemplary embodiment, the shape of the thirty-fourth N-type gate electrode 234N can be a strip shape extending along the second direction Y, the orthographic projection of the thirty-fourth N-type gate electrode 234N on the silicon substrate at least partially overlaps with the orthographic projection of the thirty-fourth N-type active area 134N on the silicon substrate, and the thirty-fourth N-type gate electrode 234N can serve as the gate electrode of the thirty-fourth N-type transistor N34.

[0412] In exemplary embodiments, the thirty-fourth P-type gate electrode 234P and the thirty-fourth N-type gate electrode 234N may be an integral structure connected to each other.

[0413] In an exemplary embodiment, the shape of the thirty-fifth P-type gate electrode 235P can be a strip shape extending along the second direction Y, the orthographic projection of the thirty-fifth P-type gate electrode 235P on the silicon substrate at least partially overlaps with the orthographic projection of the thirty-fifth P-type active area 135P on the silicon substrate, and the thirty-fifth P-type gate electrode 235P can serve as the gate electrode of the thirty-fifth P-type transistor P35.

[0414] In an exemplary embodiment, the shape of the thirty-fifth N-type gate electrode 235N can be a strip shape extending along the second direction Y, the orthographic projection of the thirty-fifth N-type gate electrode 235N on the silicon substrate at least partially overlaps with the orthographic projection of the thirty-fifth N-type active area 135N on the silicon substrate, and the thirty-fifth N-type gate electrode 235N can serve as the gate electrode of the thirty-fifth N-type transistor N35.

[0415] In exemplary embodiments, the thirty-fifth P-type gate electrode 235P and the thirty-fifth N-type gate electrode 235N may be an integral structure connected to each other.

[0416] In an exemplary embodiment, the shape of the thirty-sixth P-type gate electrode 236P can be a strip shape extending along the second direction Y, the orthographic projection of the thirty-sixth P-type gate electrode 236P on the silicon substrate at least partially overlaps with the orthographic projection of the thirty-sixth P-type active region 136P on the silicon substrate, and the thirty-sixth P-type gate electrode 236P can serve as the gate electrode of the thirty-sixth P-type transistor P36.

[0417] In an exemplary embodiment, the shape of the thirty-sixth N-type gate electrode 236N can be a strip shape extending along the second direction Y, the orthographic projection of the thirty-sixth N-type gate electrode 236N on the silicon substrate at least partially overlaps with the orthographic projection of the thirty-sixth N-type active region 136N on the silicon substrate, and the thirty-sixth N-type gate electrode 236N can serve as the gate electrode of the thirty-sixth N-type transistor N36.

[0418] In exemplary embodiments, the thirty-sixth P-type gate electrode 236P and the thirty-sixth N-type gate electrode 236N may be an integral structure connected to each other.

[0419] In an exemplary embodiment, the shape of the thirty-seventh P-type gate electrode 237P can be a strip shape extending along the second direction Y, the orthographic projection of the thirty-seventh P-type gate electrode 237P on the silicon substrate at least partially overlaps with the orthographic projection of the thirty-seventh P-type active region 137P on the silicon substrate, and the thirty-seventh P-type gate electrode 237P can serve as the gate electrode of the thirty-seventh P-type transistor P37.

[0420] In an exemplary embodiment, the shape of the thirty-seventh N-type gate electrode 237N can be a strip shape extending along the second direction Y, the orthographic projection of the thirty-seventh N-type gate electrode 237N on the silicon substrate at least partially overlaps with the orthographic projection of the thirty-seventh N-type active region 137N on the silicon substrate, and the thirty-seventh N-type gate electrode 237N can serve as the gate electrode of the thirty-seventh N-type transistor N37.

[0421] In exemplary embodiments, the thirty-seventh P-type gate electrode 237P and the thirty-seventh N-type gate electrode 237N may be an integral structure connected to each other.

[0422] In an exemplary embodiment, the shape of the thirty-eighth P-type gate electrode 238P can be a strip shape extending along the second direction Y, the orthographic projection of the thirty-eighth P-type gate electrode 238P on the silicon substrate at least partially overlaps with the orthographic projection of the thirty-eighth P-type active region 138P on the silicon substrate, and the thirty-eighth P-type gate electrode 238P can serve as the gate electrode of the thirty-eighth P-type transistor P38.

[0423] In an exemplary embodiment, the shape of the thirty-eighth N-type gate electrode 238N can be a strip shape extending along the second direction Y, the orthographic projection of the thirty-eighth N-type gate electrode 238N on the silicon substrate at least partially overlaps with the orthographic projection of the thirty-eighth N-type active region 138N on the silicon substrate, and the thirty-eighth N-type gate electrode 238N can serve as the gate electrode of the thirty-eighth N-type transistor N38.

[0424] In exemplary embodiments, the thirty-eighth P-type gate electrode 238P and the thirty-eighth N-type gate electrode 238N may be an integral structure connected to each other.

[0425] In an exemplary embodiment, the shape of the thirty-ninth P-type gate electrode 239P can be a strip shape extending along the second direction Y, the orthographic projection of the thirty-ninth P-type gate electrode 239P on the silicon substrate at least partially overlaps with the orthographic projection of the thirty-ninth P-type active region 139P on the silicon substrate, and the thirty-ninth P-type gate electrode 239P can serve as the gate electrode of the thirty-ninth P-type transistor P39.

[0426] In an exemplary embodiment, the shape of the thirty-ninth N-type gate electrode 239N can be a strip shape extending along the second direction Y, the orthographic projection of the thirty-ninth N-type gate electrode 239N on the silicon substrate at least partially overlaps with the orthographic projection of the thirty-ninth N-type active region 139N on the silicon substrate, and the thirty-ninth N-type gate electrode 239N can serve as the gate electrode of the thirty-ninth N-type transistor N39.

[0427] In exemplary embodiments, the thirty-ninth P-type gate electrode 239P and the thirty-ninth N-type gate electrode 239N may be an integral structure connected to each other.

[0428] In example embodiments, in the second region LD, the twenty-first to thirty-ninth P-type gate electrodes 221P to 239P may be sequentially disposed along the first direction X, and the twenty-first to thirty-ninth N-type gate electrodes 221N to 239N may be sequentially disposed along the first direction X.

[0429] In an exemplary embodiment, the forty-first P-type gate electrode 241P to the forty-fifth P-type gate electrode 245P, and the forty-first N-type gate electrode 241N to the forty-fifth N-type gate electrode 245N can be set in the third region LZ, serving as the P-type gate electrodes of multiple P-type transistors and the N-type gate electrodes of multiple N-type transistors in the third operational circuit.

[0430] In an exemplary embodiment, the shape of the forty-first P-type gate electrode 241P can be a strip shape extending along the second direction Y, the orthographic projection of the forty-first P-type gate electrode 241P on the silicon substrate at least partially overlaps with the orthographic projection of the forty-first P-type active region 141P on the silicon substrate, and the forty-first P-type gate electrode 241P can serve as the gate electrode of the forty-first P-type transistor P41.

[0431] In an exemplary embodiment, the shape of the forty-first N-type gate electrode 241N can be a strip shape extending along the second direction Y, the orthographic projection of the forty-first N-type gate electrode 241N on the silicon substrate at least partially overlaps with the orthographic projection of the forty-first N-type active region 141N on the silicon substrate, and the forty-first N-type gate electrode 241N can serve as the gate electrode of the forty-first N-type transistor N41.

[0432] In exemplary embodiments, the forty-first P-type gate electrode 241P and the forty-first N-type gate electrode 241N may be an integral structure connected to each other.

[0433] In an exemplary embodiment, the shape of the forty-second P-type gate electrode 242P can be a strip shape extending along the second direction Y, the orthographic projection of the forty-second P-type gate electrode 242P on the silicon substrate at least partially overlaps with the orthographic projection of the forty-second P-type active region 142P on the silicon substrate, and the forty-second P-type gate electrode 242P can serve as the gate electrode of the forty-second P-type transistor P42.

[0434] In an exemplary embodiment, the shape of the forty-second N-type gate electrode 242N can be a strip shape extending along the second direction Y, the orthographic projection of the forty-second N-type gate electrode 242N on the silicon substrate at least partially overlaps with the orthographic projection of the forty-second N-type active region 142N on the silicon substrate, and the forty-second N-type gate electrode 242N can serve as the gate electrode of the forty-second N-type transistor N42.

[0435] In exemplary embodiments, the forty-second P-type gate electrode 242P and the forty-second N-type gate electrode 242N may be an integral structure connected to each other.

[0436] In an exemplary embodiment, the shape of the forty-third P-type gate electrode 243P can be a strip shape extending along the second direction Y, the orthographic projection of the forty-third P-type gate electrode 243P on the silicon substrate at least partially overlaps with the orthographic projection of the forty-third P-type active area 143P on the silicon substrate, and the forty-third P-type gate electrode 243P can serve as the gate electrode of the forty-third P-type transistor P43.

[0437] In an exemplary embodiment, the shape of the forty-third N-type gate electrode 243N can be a strip shape extending along the second direction Y, the orthographic projection of the forty-third N-type gate electrode 243N on the silicon substrate at least partially overlaps with the orthographic projection of the forty-third N-type active area 143N on the silicon substrate, and the forty-third N-type gate electrode 243N can serve as the gate electrode of the forty-third N-type transistor N43.

[0438] In exemplary embodiments, the forty-third P-type gate electrode 243P and the forty-third N-type gate electrode 243N may be an integral structure connected to each other.

[0439] In an exemplary embodiment, the shape of the forty-fourth P-type gate electrode 244P can be a strip shape extending along the second direction Y, the orthographic projection of the forty-fourth P-type gate electrode 244P on the silicon substrate at least partially overlaps with the orthographic projection of the forty-fourth P-type active region 144P on the silicon substrate, and the forty-fourth P-type gate electrode 244P can serve as the gate electrode of the forty-fourth P-type transistor P44.

[0440] In an exemplary embodiment, the shape of the forty-fourth N-type gate electrode 244N can be a strip shape extending along the second direction Y, the orthographic projection of the forty-fourth N-type gate electrode 244N on the silicon substrate at least partially overlaps with the orthographic projection of the forty-fourth N-type active region 144N on the silicon substrate, and the forty-fourth N-type gate electrode 244N can serve as the gate electrode of the forty-fourth N-type transistor N44.

[0441] In exemplary embodiments, the forty-fourth P-type gate electrode 244P and the forty-fourth N-type gate electrode 244N may be an integral structure connected to each other.

[0442] In an exemplary embodiment, the shape of the forty-fifth P-type gate electrode 245P can be a strip shape extending along the second direction Y, the orthographic projection of the forty-fifth P-type gate electrode 245P on the silicon substrate at least partially overlaps with the orthographic projection of the forty-fifth P-type active area 145P on the silicon substrate, and the forty-fifth P-type gate electrode 245P can serve as the gate electrode of the forty-fifth P-type transistor P45.

[0443] In an exemplary embodiment, the shape of the forty-fifth N-type gate electrode 245N can be a strip shape extending along the second direction Y, the orthographic projection of the forty-fifth N-type gate electrode 245N on the silicon substrate at least partially overlaps with the orthographic projection of the forty-fifth N-type active area 145N on the silicon substrate, and the forty-fifth N-type gate electrode 245N can serve as the gate electrode of the forty-fifth N-type transistor N45.

[0444] In exemplary embodiments, the forty-fifth P-type gate electrode 245P and the forty-fifth N-type gate electrode 245N may be an integral structure connected to each other.

[0445] In an exemplary embodiment, the gate electrode widths of the forty-first to forty-fifth P-type gate electrodes 241P to 245P may be substantially the same, that is, the gate electrode widths of the P-type transistors in the fifth NOR gate and the gate electrode widths of the P-type transistors in the third NAND gate may be substantially the same. Since the active width of the P-type transistors in the fifth NOR gate is greater than the active width of the P-type transistors in the third NAND gate, the P-type width-to-length ratio of the P-type transistors in the fifth NOR gate is greater than the P-type width-to-length ratio of the P-type transistors in the third NAND gate. The P-type width-to-length ratio may be the ratio of the active width of the P-type transistor to the gate electrode width of the P-type transistor.

[0446] In an exemplary embodiment, in the third region LZ, the forty-first to forty-fifth P-type gate electrodes 241P to 245P may be sequentially disposed along the first direction X, and the forty-first to forty-fifth N-type gate electrodes 241N to 245N may be sequentially disposed along the first direction X.

[0447] In an exemplary embodiment, the widths of the first P-type gate electrode 201P to the fifteenth P-type gate electrode 215P, the twenty-eighth P-type gate electrode 228P to the thirty-ninth P-type gate electrode 239P, and the forty-first P-type gate electrode 241P to the forty-fifth P-type gate electrode 245P may be substantially the same, and the widths of the first N-type gate electrode 201N to the fifteenth N-type gate electrode 215N, the twenty-eighth N-type gate electrode 228N to the thirty-ninth N-type gate electrode 239N, and the forty-first N-type gate electrode 241N to the forty-fifth N-type gate electrode 245N may be substantially the same.

[0448] (4) Forming a P-type doped (SP) region pattern. In an exemplary embodiment, forming the P-type doped region pattern may include: coating a photoresist on the silicon substrate on which the aforementioned pattern is formed, forming a plurality of opening regions through exposure and development, removing the photoresist within the plurality of opening regions, and forming a plurality of P-type doped regions within the opening regions through a doping process, as shown in FIG16A and FIG16B , where FIG16B is a schematic diagram of the P-type doped region in FIG16A .

[0449] In example embodiments, the plurality of P-type doping regions may include at least a first P-type doping region 31 and a second P-type doping region 32 .

[0450] In an exemplary embodiment, the first P-type doping region 31 can be located within the area where the N-well region 10 is located, and the orthographic projection of the first P-type doping region 31 on the silicon substrate includes the orthographic projections of the first P-type active region 101P to the fifteenth P-type active region 115P, the twenty-first P-type active region 121P to the thirty-ninth P-type active region 139P, and the forty-first P-type active region 141P to the forty-fifth P-type active region 145P on the silicon substrate, so that a P-type source region and a P-type drain region are respectively formed on both sides of the first direction X of the P-type gate electrode.

[0451] In an exemplary embodiment, the P-type source region and the P-type drain region of each P-type transistor are both P-type heavily doped regions P+.

[0452] In an exemplary embodiment, the active region between some adjacent P-type gate electrodes can serve as the P-type source region of a P-type transistor and the P-type source region of another P-type transistor at the same time, or can serve as the P-type drain region of a P-type transistor and the P-type drain region of another P-type transistor at the same time, or can serve as the P-type source region of a P-type transistor and the P-type drain region of another P-type transistor at the same time.

[0453] In an exemplary embodiment, the second P-type doping region 32 may be located outside the N-well region 10 , and the orthographic projection of the second P-type doping region 32 on the silicon substrate includes the orthographic projection of the grounded active region 100N on the silicon substrate.

[0454] (5) Forming an N-type doping (SN) region pattern. In an exemplary embodiment, forming the N-type doping region pattern may include: coating a photoresist on the silicon substrate on which the aforementioned pattern is formed, forming a plurality of opening regions by exposure and development, removing the photoresist within the plurality of opening regions, and forming a plurality of N-type doping regions within the opening regions by a doping process, as shown in FIG17A and FIG17B , where FIG17B is a schematic diagram of the N-type doping region in FIG17A .

[0455] In example embodiments, the plurality of N-type doping regions may include at least a first N-type doping region 41 and a second N-type doping region 42 .

[0456] In an exemplary embodiment, the first N-type doping region 41 may be located outside the region where the N-well region 10 is located. The orthographic projection of the first N-type doping region 41 on the silicon substrate includes the orthographic projections of the first N-type active region 101N to the fifteenth N-type active region 115N, the twenty-first N-type active region 121N to the thirty-ninth N-type active region 139N, and the forty-first N-type active region 141N to the forty-fifth N-type active region 145N on the silicon substrate, so that an N-type source region and an N-type drain region are respectively formed on both sides of the N-type gate electrode in the first direction X.

[0457] In an exemplary embodiment, the N-type source region and the N-type drain region of each N-type transistor are both N-type heavily doped regions N+.

[0458] In an exemplary embodiment, the active region between some adjacent N-type gate electrodes can serve as both the N-type source region of an N-type transistor and the N-type source region of another N-type transistor, or can serve as both the N-type drain region of an N-type transistor and the N-type drain region of another N-type transistor, or can serve as both the N-type source region of an N-type transistor and the N-type drain region of another N-type transistor.

[0459] In an exemplary embodiment, the second N-type doping region 42 may be located within the N-well region 10 , and the orthographic projection of the second N-type doping region 42 on the silicon substrate includes the orthographic projection of the power active region 100P on the silicon substrate.

[0460] (6) Forming a second insulating layer pattern. In an exemplary embodiment, forming the second insulating layer pattern may include: depositing a second insulating film on the silicon substrate having the aforementioned pattern formed thereon, patterning the second insulating film through a patterning process to form a second insulating layer covering the gate conductive layer pattern, wherein a plurality of vias are provided on the second insulating layer, as shown in FIG. 18 .

[0461] In an exemplary embodiment, the plurality of via holes may include at least first to sixty-ninth via holes V1 to V69 , one hundred and first to eighty-third via holes V101 to V183 , two hundred and first to two hundred and nineteenth via holes V201 to V219 , a thirty-first to thirty-first via hole V301 , and a thirty-second to thirty-second via hole V302 .

[0462] In an exemplary embodiment, the orthographic projection of the first via V1 on the silicon substrate can be located within the range of the orthographic projection of the first P-type source region of the first P-type transistor P1 on the silicon substrate. The first insulating layer and the second insulating layer in the first via V1 are etched away to expose the surface of the first P-type source region. The first via V1 is configured to connect the subsequently formed eighteenth connecting electrode to the first P-type source region through the via.

[0463] In an exemplary embodiment, the orthographic projection of the second via V2 on the silicon substrate can be located within the range of the orthographic projection of the first P-type drain region of the first P-type transistor P1 (also the second P-type drain region of the second P-type transistor P2) on the silicon substrate, the first insulating layer and the second insulating layer in the second via V2 are etched away to expose the surface of the first P-type drain region (also the second P-type drain region), and the second via V2 is configured to connect the subsequently formed nineteenth connecting electrode to the first P-type drain region (also the second P-type drain region) through the via.

[0464] In an exemplary embodiment, the orthographic projection of the third via V3 on the silicon substrate can be located within the range of the orthographic projection of the second P-type source region of the second P-type transistor P2 on the silicon substrate, the first insulating layer and the second insulating layer in the third via V3 are etched away to expose the surface of the second P-type source region, and the third via V3 is configured to connect the subsequently formed twentieth connecting electrode to the second P-type source region through the via.

[0465] In an exemplary embodiment, the orthographic projection of the fourth via V4 on the silicon substrate can be located within the range of the orthographic projection of the first N-type source region of the first N-type transistor N1 on the silicon substrate, the first insulating layer and the second insulating layer in the fourth via V4 are etched away to expose the surface of the first N-type source region, and the fourth via V4 is configured to connect the subsequently formed twenty-first connecting electrode to the first N-type source region through the via.

[0466] In an exemplary embodiment, the orthographic projection of the fifth via V5 on the silicon substrate can be located within the range of the orthographic projection of the first N-type drain region of the first N-type transistor N1 (also the second N-type source region of the second N-type transistor N2) on the silicon substrate, and the first insulating layer and the second insulating layer within the fifth via V5 are etched away to expose the surface of the first N-type drain region (also the second N-type source region), and the fifth via V5 is configured to connect the subsequently formed twenty-second connecting electrode to the first N-type drain region (also the second N-type source region) through the via.

[0467] In an exemplary embodiment, the orthographic projection of the sixth via V6 on the silicon substrate can be located within the range of the orthographic projection of the second N-type drain region of the second N-type transistor N2 on the silicon substrate, the first insulating layer and the second insulating layer within the sixth via V6 are etched away to expose the surface of the second N-type drain region, and the sixth via V6 is configured to connect the subsequently formed twenty-third connecting electrode to the second N-type drain region through the via.

[0468] In an exemplary embodiment, the orthographic projection of the seventh via V7 on the silicon substrate can be located within the range of the orthographic projection of the third P-type source region of the third P-type transistor P3 on the silicon substrate, the first insulating layer and the second insulating layer in the seventh via V7 are etched away to expose the surface of the third P-type source region, and the seventh via V7 is configured to connect the subsequently formed twenty-fourth connecting electrode to the third P-type source region through the via.

[0469] In an exemplary embodiment, the orthographic projection of the eighth via V8 on the silicon substrate can be located within the range of the orthographic projection of the third P-type drain region of the third P-type transistor P3 on the silicon substrate, the first insulating layer and the second insulating layer within the eighth via V8 are etched away to expose the surface of the third P-type drain region, and the eighth via V8 is configured to connect the subsequently formed twenty-fifth connecting electrode to the third P-type drain region through the via.

[0470] In an exemplary embodiment, the orthographic projection of the ninth via V9 on the silicon substrate can be located within the range of the orthographic projection of the third N-type source region of the third N-type transistor N3 on the silicon substrate, the first insulating layer and the second insulating layer in the ninth via V9 are etched away to expose the surface of the third N-type source region, and the ninth via V9 is configured to connect the subsequently formed twenty-seventh connecting electrode to the third N-type source region through the via.

[0471] In an exemplary embodiment, the orthographic projection of the tenth via V10 on the silicon substrate can be located within the range of the orthographic projection of the third N-type drain region of the third N-type transistor N3 on the silicon substrate. The first insulating layer and the second insulating layer in the tenth via V10 are etched away to expose the surface of the third N-type drain region. The tenth via V10 is configured to connect the subsequently formed twenty-fifth connecting electrode to the third N-type drain region through the via.

[0472] In an exemplary embodiment, the orthographic projection of the eleventh via V11 on the silicon substrate can be located within the range of the orthographic projection of the fourth P-type source region of the fourth P-type transistor P4 on the silicon substrate, the first insulating layer and the second insulating layer within the eleventh via V11 are etched away to expose the surface of the fourth P-type source region, and the eleventh via V11 is configured to connect the subsequently formed twenty-seventh connecting electrode to the fourth P-type source region through the via.

[0473] In an exemplary embodiment, the orthographic projection of the twelfth via V12 on the silicon substrate can be located within the range of the orthographic projection of the fourth P-type drain region of the fourth P-type transistor P4 (also the fifth P-type source region of the fifth P-type transistor P5) on the silicon substrate, and the first insulating layer and the second insulating layer in the twelfth via V12 are etched away to expose the surface of the fourth P-type drain region (also the fifth P-type source region), and the twelfth via V12 is configured to connect the subsequently formed twenty-eighth connecting electrode to the fourth P-type drain region (also the fifth P-type source region) through the via.

[0474] In an exemplary embodiment, the orthographic projection of the thirteenth via V13 on the silicon substrate can be located within the range of the orthographic projection of the fifth P-type drain region of the fifth P-type transistor P5 on the silicon substrate, the first insulating layer and the second insulating layer within the thirteenth via V13 are etched away to expose the surface of the fifth P-type drain region, and the thirteenth via V13 is configured to connect the subsequently formed twenty-ninth connecting electrode to the fifth P-type drain region through the via.

[0475] In an exemplary embodiment, the orthographic projection of the fourteenth via V14 on the silicon substrate can be located within the range of the orthographic projection of the fourth N-type source region of the fourth N-type transistor N4 on the silicon substrate, the first insulating layer and the second insulating layer in the fourteenth via V14 are etched away to expose the surface of the fourth N-type source region, and the fourteenth via V14 is configured to connect the subsequently formed thirtieth connecting electrode to the fourth N-type source region through the via.

[0476] In an exemplary embodiment, the orthographic projection of the fifteenth via V15 on the silicon substrate can be located within the range of the orthographic projection of the fourth N-type drain region of the fourth N-type transistor N4 (also the fifth N-type drain region of the fifth N-type transistor N5) on the silicon substrate, the first insulating layer and the second insulating layer within the fifteenth via V15 are etched away to expose the surface of the fourth N-type drain region (also the fifth N-type drain region), and the fifteenth via V15 is configured to connect the subsequently formed thirty-first connecting electrode to the fourth N-type drain region (also the fifth N-type drain region) through the via.

[0477] In an exemplary embodiment, the orthographic projection of the sixteenth via V16 on the silicon substrate can be located within the range of the orthographic projection of the fifth N-type source region of the fifth N-type transistor N5 on the silicon substrate, the first insulating layer and the second insulating layer in the sixteenth via V16 are etched away to expose the surface of the fifth N-type source region, and the sixteenth via V16 is configured to connect the subsequently formed thirty-second connecting electrode to the fifth N-type source region through the via.

[0478] In an exemplary embodiment, the orthographic projection of the seventeenth via V17 on the silicon substrate can be located within the range of the orthographic projection of the sixth P-type source region of the sixth P-type transistor P6 on the silicon substrate, the first insulating layer and the second insulating layer in the seventeenth via V17 are etched away to expose the surface of the sixth P-type source region, and the seventeenth via V17 is configured to connect the subsequently formed thirty-third connecting electrode to the sixth P-type source region through the via.

[0479] In an exemplary embodiment, the orthographic projection of the eighteenth via V18 on the silicon substrate can be located within the range of the orthographic projection of the sixth P-type drain region of the sixth P-type transistor P6 on the silicon substrate, the first insulating layer and the second insulating layer in the eighteenth via V18 are etched away to expose the surface of the sixth P-type drain region, and the eighteenth via V18 is configured to connect the subsequently formed thirty-fifth connecting electrode to the sixth P-type drain region through the via.

[0480] In an exemplary embodiment, the orthographic projection of the nineteenth via V19 on the silicon substrate can be located within the range of the orthographic projection of the sixth N-type source region of the sixth N-type transistor N6 on the silicon substrate, the first insulating layer and the second insulating layer in the nineteenth via V19 are etched away to expose the surface of the sixth N-type source region, and the nineteenth via V19 is configured to connect the subsequently formed thirty-fourth connecting electrode to the sixth N-type source region through the via.

[0481] In an exemplary embodiment, the orthographic projection of the twentieth via V20 on the silicon substrate may be located within the range of the orthographic projection of the sixth N-type drain region of the sixth N-type transistor N6 on the silicon substrate, the first insulating layer and the second insulating layer within the twentieth via V20 are etched away to expose the surface of the sixth N-type drain region, and the twentieth via V20 is configured to connect the subsequently formed thirty-fifth connecting electrode to the sixth N-type drain region through the via.

[0482] In an exemplary embodiment, the orthographic projection of the twenty-first via V21 on the silicon substrate can be located within the range of the orthographic projection of the seventh P-type source region of the seventh P-type transistor P7 on the silicon substrate, the first insulating layer and the second insulating layer within the twenty-first via V21 are etched away to expose the surface of the seventh P-type source region, and the twenty-first via V21 is configured to connect the subsequently formed thirty-sixth connecting electrode to the seventh P-type source region through the via.

[0483] In an exemplary embodiment, the orthographic projection of the twenty-second via V22 on the silicon substrate can be located within the range of the orthographic projection of the seventh P-type drain region of the seventh P-type transistor P7 (also the eighth P-type source region of the eighth P-type transistor P8) on the silicon substrate, and the first insulating layer and the second insulating layer within the twenty-second via V22 are etched away to expose the surface of the seventh P-type drain region (also the eighth P-type source region), and the twenty-second via V22 is configured to connect the subsequently formed thirty-seventh connecting electrode to the seventh P-type drain region (also the eighth P-type source region) through the via.

[0484] In an exemplary embodiment, the orthographic projection of the twenty-third via V23 on the silicon substrate can be located within the range of the orthographic projection of the eighth P-type drain region of the eighth P-type transistor P8 on the silicon substrate, the first insulating layer and the second insulating layer within the twenty-third via V23 are etched away to expose the surface of the eighth P-type drain region, and the twenty-third via V23 is configured to connect the subsequently formed thirty-eighth connecting electrode to the eighth P-type drain region through the via.

[0485] In an exemplary embodiment, the orthographic projection of the twenty-fourth via V24 on the silicon substrate can be located within the range of the orthographic projection of the seventh N-type source region of the seventh N-type transistor N7 on the silicon substrate, the first insulating layer and the second insulating layer within the twenty-fourth via V24 are etched away to expose the surface of the seventh N-type source region, and the twenty-fourth via V24 is configured to connect the subsequently formed thirty-ninth connecting electrode to the seventh N-type source region through the via.

[0486] In an exemplary embodiment, the orthographic projection of the twenty-fifth via V25 on the silicon substrate can be located within the range of the orthographic projection of the seventh N-type drain region of the seventh N-type transistor N7 (also the eighth N-type drain region of the eighth N-type transistor N8) on the silicon substrate, the first insulating layer and the second insulating layer within the twenty-fifth via V25 are etched away to expose the surface of the seventh N-type drain region (also the eighth N-type drain region), and the twenty-fifth via V25 is configured to connect the subsequently formed fortieth connecting electrode to the seventh N-type drain region (also the eighth N-type drain region) through the via.

[0487] In an exemplary embodiment, the orthographic projection of the twenty-sixth via V26 on the silicon substrate can be located within the range of the orthographic projection of the eighth N-type source region of the eighth N-type transistor N8 on the silicon substrate, the first insulating layer and the second insulating layer within the twenty-sixth via V26 are etched away to expose the surface of the eighth N-type source region, and the twenty-sixth via V26 is configured to connect the subsequently formed forty-first connecting electrode to the eighth N-type source region through the via.

[0488] In an exemplary embodiment, the orthographic projection of the twenty-seventh via V27 on the silicon substrate can be located within the range of the orthographic projection of the ninth P-type source region of the ninth P-type transistor P9 on the silicon substrate, the first insulating layer and the second insulating layer within the twenty-seventh via V27 are etched away to expose the surface of the ninth P-type source region, and the twenty-seventh via V27 is configured to connect the subsequently formed forty-second connecting electrode to the ninth P-type source region through the via.

[0489] In an exemplary embodiment, the orthographic projection of the twenty-eighth via V28 on the silicon substrate can be located within the range of the orthographic projection of the ninth P-type drain region of the ninth P-type transistor P9 on the silicon substrate, the first insulating layer and the second insulating layer within the twenty-eighth via V28 are etched away to expose the surface of the ninth P-type drain region, and the twenty-eighth via V28 is configured to connect the subsequently formed forty-fourth connecting electrode to the ninth P-type drain region through the via.

[0490] In an exemplary embodiment, the orthographic projection of the twenty-ninth via V29 on the silicon substrate can be located within the range of the orthographic projection of the ninth N-type source region of the ninth N-type transistor N9 on the silicon substrate, the first insulating layer and the second insulating layer within the twenty-ninth via V29 are etched away to expose the surface of the ninth N-type source region, and the twenty-ninth via V29 is configured to connect the subsequently formed forty-third connecting electrode to the ninth N-type source region through the via.

[0491] In an exemplary embodiment, the orthographic projection of the 30th via V30 on the silicon substrate can be located within the range of the orthographic projection of the ninth N-type drain region of the ninth N-type transistor N9 on the silicon substrate, the first insulating layer and the second insulating layer within the 30th via V30 are etched away to expose the surface of the ninth N-type drain region, and the 30th via V30 is configured to connect the subsequently formed forty-fourth connecting electrode to the ninth N-type drain region through the via.

[0492] In an exemplary embodiment, the orthographic projection of the thirty-first via V31 on the silicon substrate can be located within the range of the orthographic projection of the tenth P-type source region of the tenth P-type transistor P10 on the silicon substrate, the first insulating layer and the second insulating layer within the thirty-first via V31 are etched away to expose the surface of the tenth P-type source region, and the thirty-first via V31 is configured to connect the subsequently formed forty-fifth connecting electrode to the tenth P-type source region through the via.

[0493] In an exemplary embodiment, the orthographic projection of the thirty-second via V32 on the silicon substrate can be located within the range of the orthographic projection of the tenth P-type drain region of the tenth P-type transistor P10 on the silicon substrate, the first insulating layer and the second insulating layer within the thirty-second via V32 are etched away to expose the surface of the tenth P-type drain region, and the thirty-second via V32 is configured to connect the subsequently formed forty-seventh connecting electrode to the tenth P-type drain region through the via.

[0494] In an exemplary embodiment, the orthographic projection of the thirty-third via V33 on the silicon substrate can be located within the range of the orthographic projection of the tenth N-type source region of the tenth N-type transistor N10 on the silicon substrate, the first insulating layer and the second insulating layer in the thirty-third via V33 are etched away to expose the surface of the tenth N-type source region, and the thirty-third via V33 is configured to connect the subsequently formed forty-sixth connecting electrode to the tenth N-type source region through the via.

[0495] In an exemplary embodiment, the orthographic projection of the thirty-fourth via V34 on the silicon substrate can be located within the range of the orthographic projection of the tenth N-type drain region of the tenth N-type transistor N10 on the silicon substrate, the first insulating layer and the second insulating layer within the thirty-fourth via V34 are etched away to expose the surface of the tenth N-type drain region, and the thirty-fourth via V34 is configured to connect the subsequently formed forty-seventh connecting electrode to the tenth N-type drain region through the via.

[0496] In an exemplary embodiment, the orthographic projection of the thirty-fifth via V35 on the silicon substrate can be located within the range of the orthographic projection of the eleventh P-type source region of the eleventh P-type transistor P11 on the silicon substrate, the first insulating layer and the second insulating layer in the thirty-fifth via V35 are etched away to expose the surface of the eleventh P-type source region, and the thirty-fifth via V35 is configured to connect the subsequently formed forty-eighth connecting electrode to the eleventh P-type source region through the via.

[0497] In an exemplary embodiment, the orthographic projection of the thirty-sixth via V36 on the silicon substrate can be located within the range of the orthographic projection of the eleventh P-type drain region of the eleventh P-type transistor P11 (also the twelfth P-type source region of the twelfth P-type transistor P12) on the silicon substrate, the first insulating layer and the second insulating layer in the thirty-sixth via V36 are etched away to expose the surface of the eleventh P-type drain region (also the twelfth P-type source region), and the thirty-sixth via V36 is configured to connect the subsequently formed forty-ninth connecting electrode to the eleventh P-type drain region (also the twelfth P-type source region) through the via.

[0498] In an exemplary embodiment, the orthographic projection of the thirty-seventh via V37 on the silicon substrate can be located within the range of the orthographic projection of the twelfth P-type drain region of the twelfth P-type transistor P12 on the silicon substrate, the first insulating layer and the second insulating layer within the thirty-seventh via V37 are etched away to expose the surface of the twelfth P-type drain region, and the thirty-seventh via V37 is configured to connect the subsequently formed fiftieth connecting electrode to the twelfth P-type drain region through the via.

[0499] In an exemplary embodiment, the orthographic projection of the thirty-eighth via V38 on the silicon substrate can be located within the range of the orthographic projection of the eleventh N-type source region of the eleventh N-type transistor N11 on the silicon substrate, the first insulating layer and the second insulating layer in the thirty-eighth via V38 are etched away to expose the surface of the eleventh N-type source region, and the thirty-eighth via V38 is configured to connect the subsequently formed fifty-first connecting electrode to the eleventh N-type source region through the via.

[0500] In an exemplary embodiment, the orthographic projection of the thirty-ninth via V39 on the silicon substrate can be located within the range of the orthographic projection of the eleventh N-type drain region of the eleventh N-type transistor N11 (also the twelfth N-type drain region of the twelfth N-type transistor N12) on the silicon substrate, and the first insulating layer and the second insulating layer within the thirty-ninth via V39 are etched away to expose the surface of the eleventh N-type drain region (also the twelfth N-type drain region), and the thirty-ninth via V39 is configured to connect the subsequently formed fifty-second connecting electrode to the eleventh N-type drain region (also the twelfth N-type drain region) through the via.

[0501] In an exemplary embodiment, the orthographic projection of the fortieth via V40 on the silicon substrate can be located within the range of the orthographic projection of the twelfth N-type source region of the twelfth N-type transistor N12 on the silicon substrate, the first insulating layer and the second insulating layer in the fortieth via V40 are etched away to expose the surface of the twelfth N-type source region, and the fortieth via V40 is configured to connect the subsequently formed fifty-third connecting electrode to the twelfth N-type source region through the via.

[0502] In an exemplary embodiment, the orthographic projection of the forty-first via V41 on the silicon substrate can be located within the range of the orthographic projection of the thirteenth P-type source region of the thirteenth P-type transistor P13 on the silicon substrate, the first insulating layer and the second insulating layer within the forty-first via V41 are etched away to expose the surface of the thirteenth P-type source region, and the forty-first via V41 is configured to connect the subsequently formed fifty-fourth connecting electrode to the thirteenth P-type source region through the via.

[0503] In an exemplary embodiment, the orthographic projection of the forty-second via V42 on the silicon substrate can be located within the range of the orthographic projection of the thirteenth P-type drain region of the thirteenth P-type transistor P13 on the silicon substrate, the first insulating layer and the second insulating layer within the forty-second via V42 are etched away to expose the surface of the thirteenth P-type drain region, and the forty-second via V42 is configured to connect the subsequently formed fifty-sixth connecting electrode to the thirteenth P-type drain region through the via.

[0504] In an exemplary embodiment, the orthographic projection of the forty-third via V43 on the silicon substrate can be located within the range of the orthographic projection of the thirteenth N-type source region of the thirteenth N-type transistor N13 on the silicon substrate, the first insulating layer and the second insulating layer in the forty-third via V43 are etched away to expose the surface of the thirteenth N-type source region, and the forty-third via V43 is configured to connect the subsequently formed fifty-fifth connecting electrode to the thirteenth N-type source region through the via.

[0505] In an exemplary embodiment, the orthographic projection of the forty-fourth via V44 on the silicon substrate can be located within the range of the orthographic projection of the thirteenth N-type drain region of the thirteenth N-type transistor N13 on the silicon substrate, the first insulating layer and the second insulating layer in the forty-fourth via V44 are etched away to expose the surface of the thirteenth N-type drain region, and the forty-fourth via V44 is configured to connect the subsequently formed fifty-sixth connecting electrode to the thirteenth N-type drain region through the via.

[0506] In an exemplary embodiment, the orthographic projection of the forty-fifth via V45 on the silicon substrate can be located within the range of the orthographic projection of the fourteenth P-type source region of the fourteenth P-type transistor P14 on the silicon substrate, the first insulating layer and the second insulating layer within the forty-fifth via V45 are etched away to expose the surface of the fourteenth P-type source region, and the forty-fifth via V45 is configured to connect the subsequently formed fifty-seventh connecting electrode to the fourteenth P-type source region through the via.

[0507] In an exemplary embodiment, the orthographic projection of the forty-sixth via V46 on the silicon substrate can be located within the range of the orthographic projection of the fourteenth P-type drain region of the fourteenth P-type transistor P14 on the silicon substrate, the first insulating layer and the second insulating layer within the forty-sixth via V46 are etched away to expose the surface of the fourteenth P-type drain region, and the forty-sixth via V46 is configured to connect the subsequently formed fifty-eighth connecting electrode to the fourteenth P-type drain region through the via.

[0508] In an exemplary embodiment, the orthographic projection of the forty-seventh via V47 on the silicon substrate can be located within the range of the orthographic projection of the fourteenth N-type source region of the fourteenth N-type transistor N14 on the silicon substrate, the first insulating layer and the second insulating layer within the forty-seventh via V47 are etched away to expose the surface of the fourteenth N-type source region, and the forty-seventh via V47 is configured to connect the subsequently formed fifty-seventh connecting electrode to the fourteenth N-type source region through the via.

[0509] In an exemplary embodiment, the orthographic projection of the forty-eighth via V48 on the silicon substrate can be located within the range of the orthographic projection of the fourteenth N-type drain region of the fourteenth N-type transistor N14 on the silicon substrate, the first insulating layer and the second insulating layer within the forty-eighth via V48 are etched away to expose the surface of the fourteenth N-type drain region, and the forty-eighth via V48 is configured to connect the subsequently formed fifty-eighth connecting electrode to the fourteenth N-type drain region through the via.

[0510] In an exemplary embodiment, the orthographic projection of the forty-ninth via V49 on the silicon substrate can be located within the range of the orthographic projection of the fifteenth P-type drain region of the fifteenth P-type transistor P15 on the silicon substrate, the first insulating layer and the second insulating layer within the forty-ninth via V49 are etched away to expose the surface of the fifteenth P-type drain region, and the forty-ninth via V49 is configured to connect the subsequently formed fifty-ninth connecting electrode to the fifteenth P-type drain region through the via.

[0511] In an exemplary embodiment, the orthographic projection of the fiftieth via V50 on the silicon substrate can be located within the range of the orthographic projection of the fifteenth P-type source region of the fifteenth P-type transistor P15 on the silicon substrate, the first insulating layer and the second insulating layer within the fiftieth via V50 are etched away to expose the surface of the fifteenth P-type source region, and the fiftieth via V50 is configured to connect the subsequently formed sixtieth connecting electrode to the fifteenth P-type source region through the via.

[0512] In an exemplary embodiment, the orthographic projection of the fifty-first via V51 on the silicon substrate can be located within the range of the orthographic projection of the fifteenth N-type drain region of the fifteenth N-type transistor N15 on the silicon substrate, the first insulating layer and the second insulating layer within the fifty-first via V51 are etched away to expose the surface of the fifteenth N-type drain region, and the fifty-first via V51 is configured to connect the subsequently formed fifty-ninth connecting electrode to the fifteenth N-type drain region through the via.

[0513] In an exemplary embodiment, the orthographic projection of the fifty-second via V52 on the silicon substrate can be located within the range of the orthographic projection of the fifteenth N-type source region of the fifteenth N-type transistor N15 on the silicon substrate, the first insulating layer and the second insulating layer within the fifty-second via V52 are etched away to expose the surface of the fifteenth N-type source region, and the fifty-second via V52 is configured to connect the subsequently formed sixtieth connecting electrode to the fifteenth N-type source region through the via.

[0514] In an exemplary embodiment, the orthographic projection of the fifty-third via V53 on the silicon substrate can be located within the range of the orthographic projection of the first P-type gate electrode 201P (also the first N-type gate electrode 201N) on the silicon substrate, and the second insulating layer in the fifty-third via V53 is etched away to expose the surface of the first P-type gate electrode 201P (also the first N-type gate electrode 201N), and the fifty-third via V53 is configured to connect the subsequently formed first connecting electrode to the first P-type gate electrode 201P (also the first N-type gate electrode 201N) through the via.

[0515] In an exemplary embodiment, the orthographic projection of the fifty-fourth via V54 on the silicon substrate can be located within the range of the orthographic projection of the second P-type gate electrode 202P (also the second N-type gate electrode 202N) on the silicon substrate, and the second insulating layer in the fifty-fourth via V54 is etched away to expose the surface of the second P-type gate electrode 202P (also the second N-type gate electrode 202N). The fifty-fourth via V54 is configured to connect the subsequently formed second connecting electrode to the second P-type gate electrode 202P (also the second N-type gate electrode 202N) through the via.

[0516] In an exemplary embodiment, in the second direction Y, the fifty-third via V53 can be disposed in the middle of the first P-type gate electrode 201P (also the first N-type gate electrode 201N), and the fifty-fourth via V54 can be disposed in the middle of the second P-type gate electrode 202P (also the second N-type gate electrode 202N). The fifty-third via V53 and the fifty-fourth via V54 can be located on the same straight line extending along the first direction X. That is, the gate vias of the two transistor groups in the first NAND gate are located on the same straight line extending along the first direction X. This can effectively improve the uniformity of signal writing into the transistors in the first NAND gate. For example, in the second direction Y, the fifty-third via V53 and the fifty-fourth via V54 can be located between 1 / 3 and 2 / 3 of the gate electrode.

[0517] In an exemplary embodiment, the orthographic projection of the fifty-fifth via V55 on the silicon substrate can be located within the range of the orthographic projection of the third P-type gate electrode 203P (also the third N-type gate electrode 203N) on the silicon substrate, and the second insulating layer in the fifty-fifth via V55 is etched away to expose the surface of the third P-type gate electrode 203P (also the third N-type gate electrode 203N). The fifty-fifth via V55 is configured to connect a subsequently formed third connecting electrode to the third P-type gate electrode 203P (also the third N-type gate electrode 203N) through the via.

[0518] In an exemplary embodiment, the orthographic projection of the fifty-sixth via V56 on the silicon substrate can be located within the range of the orthographic projection of the fourth P-type gate electrode 204P (also the fourth N-type gate electrode 204N) on the silicon substrate, and the second insulating layer in the fifty-sixth via V56 is etched away to expose the surface of the fourth P-type gate electrode 204P (also the fourth N-type gate electrode 204N). The fifty-sixth via V56 is configured to connect the subsequently formed fourth connecting electrode to the fourth P-type gate electrode 204P (also the fourth N-type gate electrode 204N) through the via.

[0519] In an exemplary embodiment, the orthographic projection of the fifty-seventh via V57 on the silicon substrate can be located within the range of the orthographic projection of the fifth P-type gate electrode 205P (also the fifth N-type gate electrode 205N) on the silicon substrate, and the second insulating layer in the fifty-seventh via V57 is etched away to expose the surface of the fifth P-type gate electrode 205P (also the fifth N-type gate electrode 205N). The fifty-seventh via V57 is configured to connect the subsequently formed fifth connecting electrode to the fifth P-type gate electrode 205P (also the fifth N-type gate electrode 205N) through the via.

[0520] In an exemplary embodiment, the orthographic projection of the fifty-eighth via V58 on the silicon substrate can be located within the range of the orthographic projection of the sixth P-type gate electrode 206P (also the sixth N-type gate electrode 206N) on the silicon substrate, and the second insulating layer in the fifty-eighth via V58 is etched away to expose the surface of the sixth P-type gate electrode 206P (also the sixth N-type gate electrode 206N). The fifty-eighth via V58 is configured to connect the subsequently formed sixth connecting electrode to the sixth P-type gate electrode 206P (also the sixth N-type gate electrode 206N) through the via.

[0521] In an exemplary embodiment, the orthographic projection of the fifty-ninth via V59 on the silicon substrate can be located within the range of the orthographic projection of the seventh P-type gate electrode 207P (also the seventh N-type gate electrode 207N) on the silicon substrate, and the second insulating layer in the fifty-ninth via V59 is etched away to expose the surface of the seventh P-type gate electrode 207P (also the seventh N-type gate electrode 207N). The fifty-ninth via V59 is configured to connect the subsequently formed seventh connecting electrode to the seventh P-type gate electrode 207P (also the seventh N-type gate electrode 207N) through the via.

[0522] In an exemplary embodiment, the orthographic projection of the sixtieth via V60 on the silicon substrate may be located within the range of the orthographic projection of the eighth P-type gate electrode 208P (also the eighth N-type gate electrode 208N) on the silicon substrate, the second insulating layer within the sixtieth via V60 is etched away to expose the surface of the eighth P-type gate electrode 208P (also the eighth N-type gate electrode 208N), and the sixtieth via V60 is configured to connect the subsequently formed eighth connecting electrode to the eighth P-type gate electrode 208P (also the eighth N-type gate electrode 208N) through the via.

[0523] In an exemplary embodiment, the orthographic projection of the sixty-first via V61 on the silicon substrate can be located within the range of the orthographic projection of the ninth P-type gate electrode 209P (also the ninth N-type gate electrode 209N) on the silicon substrate, and the second insulating layer in the sixty-first via V61 is etched away to expose the surface of the ninth P-type gate electrode 209P (also the ninth N-type gate electrode 209N). The sixty-first via V61 is configured to connect the subsequently formed ninth connecting electrode to the ninth P-type gate electrode 209P (also the ninth N-type gate electrode 209N) through the via.

[0524] In an exemplary embodiment, the orthographic projection of the sixty-second via V62 on the silicon substrate can be located within the range of the orthographic projection of the tenth P-type gate electrode 210P (also the tenth N-type gate electrode 210N) on the silicon substrate, and the second insulating layer in the sixty-second via V62 is etched away to expose the surface of the tenth P-type gate electrode 210P (also the tenth N-type gate electrode 210N), and the sixty-second via V62 is configured to connect the subsequently formed tenth connecting electrode to the tenth P-type gate electrode 210P (also the tenth N-type gate electrode 210N) through the via.

[0525] In an exemplary embodiment, the orthographic projection of the sixty-third via V63 on the silicon substrate can be located within the range of the orthographic projection of the eleventh P-type gate electrode 211P (also the eleventh N-type gate electrode 211N) on the silicon substrate, and the second insulating layer in the sixty-third via V63 is etched away to expose the surface of the eleventh P-type gate electrode 211P (also the eleventh N-type gate electrode 211N). The sixty-third via V63 is configured to connect the subsequently formed eleventh connecting electrode to the eleventh P-type gate electrode 211P (also the eleventh N-type gate electrode 211N) through the via.

[0526] In an exemplary embodiment, the orthographic projection of the sixty-fourth via V64 on the silicon substrate can be located within the range of the orthographic projection of the twelfth P-type gate electrode 212P (also the twelfth N-type gate electrode 212N) on the silicon substrate, and the second insulating layer in the sixty-fourth via V64 is etched away to expose the surface of the twelfth P-type gate electrode 212P (also the twelfth N-type gate electrode 212N), and the sixty-fourth via V64 is configured to connect the subsequently formed twelfth connecting electrode to the twelfth P-type gate electrode 212P (also the twelfth N-type gate electrode 212N) through the via.

[0527] In an exemplary embodiment, the orthographic projection of the sixty-fifth via V65 on the silicon substrate can be located within the range of the orthographic projection of the thirteenth P-type gate electrode 213P (also the thirteenth N-type gate electrode 213N) on the silicon substrate, and the second insulating layer in the sixty-fifth via V65 is etched away to expose the surface of the thirteenth P-type gate electrode 213P (also the thirteenth N-type gate electrode 213N). The sixty-fifth via V65 is configured to connect the subsequently formed thirteenth connecting electrode to the thirteenth P-type gate electrode 213P (also the thirteenth N-type gate electrode 213N) through the via.

[0528] In an exemplary embodiment, the orthographic projection of the sixty-sixth via V66 on the silicon substrate can be located within the range of the orthographic projection of the fourteenth P-type gate electrode 214P on the silicon substrate, the second insulating layer in the sixty-sixth via V66 is etched away to expose the surface of the fourteenth P-type gate electrode 214P, and the sixty-sixth via V66 is configured to connect the subsequently formed fourteenth connecting electrode to the fourteenth P-type gate electrode 214P through the via.

[0529] In an exemplary embodiment, the orthographic projection of the sixty-seventh via V67 on the silicon substrate can be located within the range of the orthographic projection of the fourteenth N-type gate electrode 214N on the silicon substrate, the second insulating layer in the sixty-seventh via V67 is etched away to expose the surface of the fourteenth N-type gate electrode 214N, and the sixty-seventh via V67 is configured to connect the subsequently formed fifteenth connecting electrode to the fourteenth N-type gate electrode 214N through the via.

[0530] In an exemplary embodiment, the orthographic projection of the sixty-eighth via V68 on the silicon substrate can be located within the range of the orthographic projection of the fifteenth P-type gate electrode 215P on the silicon substrate, the second insulating layer in the sixty-eighth via V68 is etched away to expose the surface of the fifteenth P-type gate electrode 215P, and the sixty-eighth via V68 is configured to connect the first end of the subsequently formed sixteenth connecting electrode to the fifteenth P-type gate electrode 215P through the via.

[0531] In an exemplary embodiment, the orthographic projection of the sixty-ninth via V69 on the silicon substrate can be located within the range of the orthographic projection of the fifteenth N-type gate electrode 215N on the silicon substrate, the second insulating layer in the sixty-ninth via V69 is etched away to expose the surface of the fifteenth N-type gate electrode 215N, and the sixty-ninth via V69 is configured to connect the first end of the subsequently formed seventeenth connecting electrode to the fifteenth N-type gate electrode 215N through the via.

[0532] In an exemplary embodiment, the first to sixty-ninth vias V1 to V69 may be disposed in the first region LW, and one or more of the first to sixty-ninth vias V1 to V69 may be plural to reduce contact resistance and increase connection reliability.

[0533] In an exemplary embodiment, the fifty-third via V53 to the sixty-ninth via V69 can be referred to as gate vias, and one or more of the above-mentioned gate vias can be located in the gap region 50 between the P-type active area and the N-type active area, so as to facilitate the arrangement of multiple connecting electrodes formed subsequently, optimize the connection structure between the first conductive layer and the gate conductive layer, and reduce the occupied area of ​​the gate drive circuit.

[0534] In an exemplary embodiment, the gate vias in the first inverter, the second inverter, the third inverter, and the fourth inverter may be referred to as first gate vias. The first gate vias are configured to connect a subsequently formed first gate connection electrode to the P-type gate electrode of the P-type transistor and the N-type gate electrode of the N-type transistor through the first gate vias. The first gate vias may include a fifty-fifth via V55, a fifty-eighth via V58, a sixty-first via V61, and a sixty-second via V62.

[0535] In an exemplary embodiment, the gate vias in the first NAND gate, the first NOR gate, the second NOR gate, and the third NOR gate may be referred to as second gate vias. The second gate vias are configured to connect a subsequently formed second gate connection electrode to the P-type gate electrode of the P-type transistor and the N-type gate electrode of the N-type transistor through the second gate vias. The second gate vias may include a fifty-third via V53, a fifty-fourth via V54, a fifty-sixth via V56, a fifty-seventh via V57, a fifty-ninth via V59, a sixtieth via V60, a sixty-third via V63, and a sixty-fourth via V64.

[0536] In an exemplary embodiment, the first gate via in at least one inverter is closer to the N-type active region of the N-type transistor than the second gate via in the second direction Y. For example, the fifty-fifth via V55 (the first gate via in the first inverter) is closer to the N-type active region of the N-type transistor than the fifty-fourth via V54 (the second gate via in the first NAND gate).

[0537] In an exemplary embodiment, the second gate via in the first NAND gate is closer to the P-type active region of the P-type transistor than the first gate via in the second direction Y. For example, the fifty-fourth via V54 (the second gate via in the first NAND gate) is closer to the P-type active region of the P-type transistor than the fifty-fifth via V55 (the first gate via in the first inverter).

[0538] In an exemplary embodiment, the second gate via in the first NOR gate is closer to the P-type active region of the P-type transistor than the first gate via in the second direction Y. For example, the fifty-sixth via V56 (the second gate via in the first NOR gate) is closer to the P-type active region of the P-type transistor than the fifty-fifth via V55 (the first gate via in the first inverter).

[0539] In an exemplary embodiment, the first gate vias of the plurality of inverters in the first operational circuit may be located on the same straight line extending along the first direction X, and the second gate vias of the plurality of NAND gates and the plurality of NOR gates in the first operational circuit may be located on the same straight line extending along the first direction X. This is not only beneficial to process uniformity and uniformity of signal transmission, but also beneficial to the arrangement of the plurality of connecting electrodes subsequently formed, and optimizes the connection structure between the first conductive layer and the gate conductive layer.

[0540] In an exemplary embodiment, the orthographic projection of the 101st via V101 on the silicon substrate can be located within the range of the orthographic projection of the 21st P-type source region of the 21st P-type transistor P21 on the silicon substrate, the first insulating layer and the second insulating layer within the 101st via V101 are etched away to expose the surface of the 21st P-type transistor P21, and the 101st via V101 is configured to connect the subsequently formed 120th connecting electrode to the 21st P-type source region through the via.

[0541] In an exemplary embodiment, the orthographic projection of the 102nd via hole V102 on the silicon substrate may be located within the range of the orthographic projection of the 21st P-type drain region of the 21st P-type transistor P21 on the silicon substrate, the first insulating layer and the second insulating layer within the 102nd via hole V102 are etched away to expose the surface of the 21st P-type transistor P21, and the 102nd via hole V102 is configured to connect the subsequently formed 122nd connecting electrode to the 21st P-type drain region through the via hole.

[0542] In an exemplary embodiment, the orthographic projection of the 103rd via hole V103 on the silicon substrate may be located within the range of the orthographic projection of the 21st N-type source region of the 21st N-type transistor N21 on the silicon substrate. The first insulating layer and the second insulating layer within the 103rd via hole V103 are etched away to expose the surface of the 21st N-type source region. The 103rd via hole V103 is configured to connect the subsequently formed 121st connecting electrode to the 21st N-type source region through the via hole.

[0543] In an exemplary embodiment, the orthographic projection of the 104th via hole V104 on the silicon substrate may be located within the range of the orthographic projection of the 21st N-type drain region of the 21st N-type transistor N21 on the silicon substrate. The first insulating layer and the second insulating layer within the 104th via hole V104 are etched away to expose the surface of the 21st N-type drain region. The 104th via hole V104 is configured to connect the subsequently formed 122nd connecting electrode to the 21st N-type drain region through the via hole.

[0544] In an exemplary embodiment, the orthographic projection of the 105th via V105 on the silicon substrate can be located within the range of the orthographic projection of the 22nd P-type source region of the 22nd P-type transistor P22 on the silicon substrate, the first insulating layer and the second insulating layer within the 105th via V105 are etched away to expose the surface of the 22nd P-type source region, and the 105th via V105 is configured to connect the subsequently formed 123rd connecting electrode to the 22nd P-type source region through the via.

[0545] In an exemplary embodiment, the orthographic projection of the 106th via hole V106 on the silicon substrate can be located within the range of the orthographic projection of the 22nd P-type drain region of the 22nd P-type transistor P22 on the silicon substrate, the first insulating layer and the second insulating layer within the 106th via hole V106 are etched away to expose the surface of the 22nd P-type drain region, and the 106th via hole V106 is configured to connect the subsequently formed 125th connecting electrode to the 22nd P-type drain region through the via hole.

[0546] In an exemplary embodiment, the orthographic projection of the 107th via V107 on the silicon substrate can be located within the range of the orthographic projection of the 22nd N-type source region of the 22nd N-type transistor N2 on the silicon substrate, the first insulating layer and the second insulating layer within the 107th via V107 are etched away to expose the surface of the 22nd N-type source region, and the 107th via V107 is configured to connect the subsequently formed 124th connecting electrode to the 22nd N-type source region through the via.

[0547] In an exemplary embodiment, the orthographic projection of the 108th via V108 on the silicon substrate can be located within the range of the orthographic projection of the 22nd N-type drain region of the 22nd N-type transistor N2 on the silicon substrate. The first insulating layer and the second insulating layer within the 108th via V108 are etched away to expose the surface of the 22nd N-type drain region. The 108th via V108 is configured to connect the subsequently formed 125th connecting electrode to the 22nd N-type drain region through the via.

[0548] In an exemplary embodiment, the orthographic projection of the 109th via hole V109 on the silicon substrate can be located within the range of the orthographic projection of the 23rd P-type source region of the 23rd P-type transistor P23 on the silicon substrate, the first insulating layer and the second insulating layer within the 109th via hole V109 are etched away to expose the surface of the 23rd P-type source region, and the 109th via hole V109 is configured to connect the subsequently formed 126th connecting electrode to the 23rd P-type source region through the via hole.

[0549] In an exemplary embodiment, the orthographic projection of the 110th via hole V110 on the silicon substrate can be located within the range of the orthographic projection of the 23rd P-type drain region of the 23rd P-type transistor P23 on the silicon substrate, the first insulating layer and the second insulating layer within the 110th via hole V110 are etched away to expose the surface of the 23rd P-type drain region, and the 110th via hole V110 is configured to connect the subsequently formed 128th connecting electrode to the 23rd P-type drain region through the via hole.

[0550] In an exemplary embodiment, the orthographic projection of the 111th via V111 on the silicon substrate can be located within the range of the orthographic projection of the 23rd N-type source region of the 23rd N-type transistor N23 on the silicon substrate, the first insulating layer and the second insulating layer within the 111th via V111 are etched away to expose the surface of the 23rd N-type source region, and the 111th via V111 is configured to connect the subsequently formed 127th connecting electrode to the 23rd N-type source region through the via.

[0551] In an exemplary embodiment, the orthographic projection of the 112th via V112 on the silicon substrate can be located within the range of the orthographic projection of the 23rd N-type drain region of the 23rd N-type transistor N23 on the silicon substrate, the first insulating layer and the second insulating layer within the 112th via V112 are etched away to expose the surface of the 23rd N-type drain region, and the 112th via V112 is configured to connect the subsequently formed 128th connecting electrode to the 23rd N-type drain region through the via.

[0552] In an exemplary embodiment, the orthographic projection of the 113th via hole V113 on the silicon substrate may be located within the range of the orthographic projection of the 24th P-type source region of the 24th P-type transistor P24 on the silicon substrate, the first insulating layer and the second insulating layer within the 113th via hole V113 are etched away to expose the surface of the 24th P-type source region, and the 113th via hole V113 is configured to connect the subsequently formed 129th connecting electrode to the 24th P-type source region through the via hole.

[0553] In an exemplary embodiment, the orthographic projection of the 114th via V114 on the silicon substrate can be located within the range of the orthographic projection of the 24th P-type drain region of the 24th P-type transistor P24 on the silicon substrate, the first insulating layer and the second insulating layer within the 114th via V114 are etched away to expose the surface of the 24th P-type drain region, and the 114th via V114 is configured to connect the subsequently formed 131st connecting electrode to the 24th P-type drain region through the via.

[0554] In an exemplary embodiment, the orthographic projection of the 115th via V115 on the silicon substrate can be located within the range of the orthographic projection of the 24th N-type source region of the 24th N-type transistor N24 on the silicon substrate, the first insulating layer and the second insulating layer within the 115th via V115 are etched away to expose the surface of the 24th N-type source region, and the 115th via V115 is configured to connect the subsequently formed 130th connecting electrode to the 24th N-type source region through the via.

[0555] In an exemplary embodiment, the orthographic projection of the 116th via V116 on the silicon substrate can be located within the range of the orthographic projection of the 24th N-type drain region of the 24th N-type transistor N24 on the silicon substrate. The first insulating layer and the second insulating layer within the 116th via V116 are etched away to expose the surface of the 24th N-type drain region. The 116th via V116 is configured to connect the subsequently formed 131st connecting electrode to the 24th N-type drain region through the via.

[0556] In an exemplary embodiment, the orthographic projection of the 117th via V117 on the silicon substrate can be located within the range of the orthographic projection of the 25th P-type source region of the 25th P-type transistor P25 on the silicon substrate, the first insulating layer and the second insulating layer within the 117th via V117 are etched away to expose the surface of the 25th P-type source region, and the 117th via V117 is configured to connect the subsequently formed 132nd connecting electrode to the 25th P-type source region through the via.

[0557] In an exemplary embodiment, the orthographic projection of the 118th via V118 on the silicon substrate can be located within the range of the orthographic projection of the 25th P-type drain region of the 25th P-type transistor P25 on the silicon substrate, the first insulating layer and the second insulating layer within the 118th via V118 are etched away to expose the surface of the 25th P-type drain region, and the 118th via V118 is configured to connect the subsequently formed 134th connecting electrode to the 25th P-type drain region through the via.

[0558] In an exemplary embodiment, the orthographic projection of the 119th via V119 on the silicon substrate can be located within the range of the orthographic projection of the 25th N-type source region of the 25th N-type transistor N25 on the silicon substrate, the first insulating layer and the second insulating layer within the 119th via V119 are etched away to expose the surface of the 25th N-type source region, and the 119th via V119 is configured to connect the subsequently formed 133rd connecting electrode to the 25th N-type source region through the via.

[0559] In an exemplary embodiment, the orthographic projection of the 120th via hole V120 on the silicon substrate may be located within the range of the orthographic projection of the 25th N-type drain region of the 25th N-type transistor N25 on the silicon substrate. The first insulating layer and the second insulating layer within the 120th via hole V120 are etched away to expose the surface of the 25th N-type drain region. The 120th via hole V120 is configured to connect the subsequently formed 134th connecting electrode to the 25th N-type drain region through the via hole.

[0560] In an exemplary embodiment, the orthographic projection of the 121st via hole V121 on the silicon substrate may be located within the range of the orthographic projection of the 26th P-type source region of the 26th P-type transistor P26 on the silicon substrate, the first insulating layer and the second insulating layer within the 121st via hole V121 are etched away to expose the surface of the 26th P-type source region, and the 121st via hole V121 is configured to connect the subsequently formed 135th connecting electrode to the 26th P-type source region through the via hole.

[0561] In an exemplary embodiment, the orthographic projection of the 122nd via hole V122 on the silicon substrate may be located within the range of the orthographic projection of the 26th P-type drain region of the 26th P-type transistor P26 on the silicon substrate, the first insulating layer and the second insulating layer within the 122nd via hole V122 are etched away to expose the surface of the 26th P-type drain region, and the 122nd via hole V122 is configured to connect the subsequently formed 137th connecting electrode to the 26th P-type drain region through the via hole.

[0562] In an exemplary embodiment, the orthographic projection of the 123rd via hole V123 on the silicon substrate may be located within the range of the orthographic projection of the 26th N-type source region of the 26th N-type transistor N26 on the silicon substrate, the first insulating layer and the second insulating layer within the 123rd via hole V123 are etched away to expose the surface of the 26th N-type source region, and the 123rd via hole V123 is configured to connect the subsequently formed 136th connecting electrode to the 26th N-type source region through the via hole.

[0563] In an exemplary embodiment, the orthographic projection of the 124th via hole V124 on the silicon substrate may be located within the range of the orthographic projection of the 26th N-type drain region of the 26th N-type transistor N26 on the silicon substrate, the first insulating layer and the second insulating layer within the 124th via hole V124 are etched away to expose the surface of the 26th N-type drain region, and the 124th via hole V124 is configured to connect the subsequently formed 137th connecting electrode to the 26th N-type drain region through the via hole.

[0564] In an exemplary embodiment, the orthographic projection of the 125th via hole V125 on the silicon substrate may be located within the range of the orthographic projection of the 27th P-type source region of the 27th P-type transistor P27 on the silicon substrate, the first insulating layer and the second insulating layer within the 125th via hole V125 are etched away to expose the surface of the 27th P-type source region, and the 125th via hole V125 is configured to connect the subsequ...

Claims

1. A gate driving circuit, comprising a logic operation circuit disposed on a silicon substrate. The logic operation circuit at least includes a first operation circuit for generating a write switch signal, a second operation circuit for generating a display switch signal, and a third operation circuit for generating a display reset signal. The write switch signal, the display switch signal, and the display reset signal are configured to be output to a display area. At least two of the first operation circuit, the second operation circuit, and the third operation circuit have at least one same input signal. At least one input signal of the second operation circuit is provided by the first operation circuit. The second operation circuit or the third operation circuit is disposed on a side of the first operation circuit closer to the display area.

2. The gate driving circuit according to claim 1, wherein, The second operation circuit is disposed on a side of the first operation circuit closer to the display area, and the third operation circuit is disposed on a side of the second operation circuit closer to the display area. An output terminal of the first operation circuit is connected to an input terminal of the second operation circuit. The input terminal of the second operation circuit is disposed on a side of the output terminal of the first operation circuit closer to the display area.

3. The gate driving circuit according to claim 1, wherein, The first operation circuit, the second operation circuit, and the third operation circuit each include a plurality of transistor groups sequentially disposed along a first direction. At least one transistor group includes a P-type transistor and an N-type transistor disposed on a side of the P-type transistor in a second direction. The first direction and the second direction intersect. The number of transistor groups in the third operation circuit is less than the number of transistor groups in the first operation circuit, and the number of transistor groups in the third operation circuit is less than the number of transistor groups in the second operation circuit.

4. The gate driving circuit according to claim 3, wherein, The plurality of transistor groups in the first operation circuit form a first NAND gate, a first inverter, a first NOR gate, a second inverter, a second NOR gate, a fourth inverter, a third inverter, a third NOR gate, and a two-way selector sequentially disposed along a direction closer to the display area. The first NAND gate, the first NOR gate, the second NOR gate, and the third NOR gate each include two transistor groups. The first inverter, the second inverter, the third inverter, and the fourth inverter each include one transistor group. The two-way selector includes three transistor groups.

5. The gate driving circuit according to claim 4, wherein, In at least one transistor group, the P-type transistor at least includes a P-type active region, a P-type source electrode, and a P-type drain electrode. A first end of the P-type source electrode is connected to a first power supply line. A second end of the P-type source electrode is connected to a first region of the P-type active region through a via. The P-type source electrode in at least one transistor group has a first P-type length, and the P-type source electrode in at least another transistor group has a second P-type length. The ratio of the first P-type length to the second P-type length is 0.95 to 1.

05. The first P-type length and the second P-type length are dimensions in the second direction.

6. The gate driving circuit according to claim 4, wherein, In at least one transistor group, the N-type transistor includes at least an N-type active region, an N-type source electrode, and an N-type drain electrode. A first end of the N-type source electrode is connected to a ground wire, and a second end of the N-type source electrode is connected to a first region of the N-type active region through a via hole. The N-type source electrodes in at least one transistor group have a first N-type length, and the N-type source electrodes in at least another transistor group have a second N-type length. The ratio of the first N-type length to the second N-type length is from 0.95 to 1.05, and the first N-type length and the second N-type length are dimensions in the second direction.

7. The gate driving circuit according to claim 4, wherein, At least one transistor group in the first inverter, the second inverter, the third inverter, and the fourth inverter includes a first gate connection electrode, and the first gate connection electrode is connected to a P-type gate electrode of a P-type transistor and an N-type gate electrode of an N-type transistor through a first gate via hole. The first gate via hole is disposed in a gap region between the P-type active region of the P-type transistor and the N-type active region of the N-type transistor.

8. The gate driving circuit according to claim 7, wherein, At least one transistor group in the first NAND gate, the first NOR gate, the second NOR gate, and the third NOR gate includes a second gate connection electrode, and the second gate connection electrode is connected to a P-type gate electrode of a P-type transistor and an N-type gate electrode of an N-type transistor through a second gate via hole. The second gate via hole is disposed in the gap region; In the second direction, the second gate via hole is closer to the P-type active region of the P-type transistor than the first gate via hole, and the first gate via hole is closer to the N-type active region of the N-type transistor than the second gate via hole.

9. The gate driving circuit according to claim 8, wherein A plurality of first gate via holes are located on the same straight line extending along the first direction, and a plurality of second gate via holes are located on the same straight line extending along the first direction.

10. The gate driving circuit according to claim 4, wherein The plurality of transistor groups in the first arithmetic circuit includes at least a first transistor group, a second transistor group, and a third transistor group. The first transistor group includes a first P-type transistor and a first N-type transistor. The second transistor group includes a second P-type transistor and a second N-type transistor. The third transistor group includes a third P-type transistor and a third N-type transistor. The first arithmetic circuit further includes a first connection line. A first end of the first connection line is connected to a P-type drain electrode of the first P-type transistor and a P-type drain electrode of the second P-type transistor. A second end of the first connection line is connected to a P-type gate electrode of the third P-type transistor and an N-type gate electrode of the third N-type transistor. A region between the first end and the second end of the first connection line is connected to an N-type drain electrode of the second N-type transistor. A positive projection of the first connection line on the silicon substrate overlaps at least partially with positive projections of the P-type gate electrode of the second P-type transistor and the N-type gate electrode of the second N-type transistor on the silicon substrate.

11. The gate driving circuit according to claim 10, wherein, The multiple transistor groups in the first arithmetic circuit further include a fourth transistor group and a fifth transistor group. The fourth transistor group includes a fourth P-type transistor and a fourth N-type transistor, and the fifth transistor group includes a fifth P-type transistor and a fifth N-type transistor; The first arithmetic circuit further includes a first signal connection line. The first end of the first signal connection line is connected to the P-type drain electrode of the third P-type transistor and the N-type drain electrode of the third N-type transistor, and the second end of the second signal connection line is connected to the P-type gate electrode of the fifth P-type transistor and the N-type gate electrode of the fifth N-type transistor; The orthographic projection of the first signal connection line on the silicon substrate at least partially overlaps with the orthographic projections of the P-type gate electrode of the fourth P-type transistor and the N-type gate electrode of the fourth N-type transistor on the silicon substrate.

12. The gate driving circuit according to claim 11, wherein, In the second direction, the first signal connection line is disposed on a side of the first connection line close to the P-type active region of the P-type transistor.

13. The gate driving circuit according to claim 11, wherein, In a direction perpendicular to the silicon substrate, the logic arithmetic circuit may include a first conductive layer and a second conductive layer disposed on a side of the first conductive layer away from the silicon substrate. The first connection line is disposed in the first conductive layer, and the first signal connection line is disposed in the second conductive layer.

14. The gate driving circuit according to claim 4, wherein The multiple transistor groups in the first arithmetic circuit at least include a fourth transistor group, a fifth transistor group, and a sixth transistor group. The fourth transistor group includes a fourth P-type transistor and a fourth N-type transistor, the fifth transistor group includes a fifth P-type transistor and a fifth N-type transistor, and the sixth transistor group includes a sixth P-type transistor and a sixth N-type transistor; The first arithmetic circuit further includes a second connection line. The first end of the second connection line is connected to the N-type drain electrode of the fourth N-type transistor and the N-type drain electrode of the fifth N-type transistor, and the second end of the second connection line is connected to the P-type gate electrode of the sixth P-type transistor and the N-type gate electrode of the sixth N-type transistor. The region between the first end and the second end of the second connection line is connected to the P-type drain electrode of the fifth P-type transistor; The orthographic projection of the second connection line on the silicon substrate at least partially overlaps with the orthographic projections of the P-type gate electrode of the fifth P-type transistor and the N-type gate electrode of the fifth N-type transistor on the silicon substrate.

15. The gate driving circuit according to claim 14, wherein, The multiple transistor groups in the first arithmetic circuit further include a seventh transistor group and an eighth transistor group. The seventh transistor group includes a seventh P-type transistor and a seventh N-type transistor. The eighth transistor group includes an eighth P-type transistor and an eighth N-type transistor. The first arithmetic circuit further includes a second signal transfer line. The first end of the second signal transfer line is connected to the P-type drain electrode of the sixth P-type transistor and the N-type drain electrode of the sixth N-type transistor. The second end of the second signal transfer line is connected to the P-type gate electrode of the eighth P-type transistor and the N-type gate electrode of the eighth N-type transistor. The orthographic projection of the second signal transfer line on the silicon substrate overlaps at least partially with the orthographic projections of the P-type gate electrode of the seventh P-type transistor and the N-type gate electrode of the seventh N-type transistor on the silicon substrate.

16. The gate driving circuit according to claim 15, wherein, In the second direction, the second signal transfer line is disposed on a side of the second connection line closer to the P-type active region of the P-type transistor.

17. The gate driving circuit according to claim 15, wherein, In a direction perpendicular to the silicon substrate, the logic arithmetic circuit may include a first conductive layer and a second conductive layer disposed on a side of the first conductive layer away from the silicon substrate. The second connection line is disposed in the first conductive layer, and the second signal transfer line is disposed in the second conductive layer.

18. The gate driving circuit according to claim 4, wherein, The two-way selector includes a thirteenth transistor group, a fourteenth transistor group, and a fifteenth transistor group. The P-type gate electrode of the P-type transistor and the N-type gate electrode of the N-type transistor in the thirteenth transistor group are an integrally connected structure. The P-type gate electrode of the P-type transistor and the N-type gate electrode of the N-type transistor in the fourteenth transistor group are not an integrally connected structure. The P-type gate electrode of the P-type transistor and the N-type gate electrode of the N-type transistor in the fifteenth transistor group are not an integrally connected structure.

19. The gate driving circuit according to claim 18, wherein, The first arithmetic circuit further includes at least two sixth connection lines. The first end of the sixth connection line is connected to the fifty-eighth connection electrode that serves as the P-type drain electrode of the fourteenth P-type transistor and the N-type drain electrode of the fourteenth N-type transistor. The second end of the sixth connection line is connected to the fifty-ninth connection electrode that serves as the P-type drain electrode of the fifteenth P-type transistor and the N-type drain electrode of the fifteenth N-type transistor. The fifty-eighth connection electrode, the fifty-ninth connection electrode, and the two sixth connection lines form a mesh-like communication structure.

20. The gate driving circuit according to claim 18, wherein, The fourth inverter includes a ninth transistor group, and the ninth transistor group includes a ninth P-type transistor and a ninth N-type transistor; the first operation circuit further includes a third signal connection line, a first end of the third signal connection line is connected to a P-type drain electrode of the ninth P-type transistor and an N-type drain electrode of the ninth N-type transistor, and a second end of the third signal connection line is connected to a P-type source electrode of the fifteenth P-type transistor and an N-type source electrode of the fifteenth N-type transistor; a positive projection of the third signal connection line on the silicon substrate at least partially overlaps with positive projections of an N-type gate electrode of a tenth N-type transistor, an N-type gate electrode of an eleventh N-type transistor, an N-type gate electrode of a twelfth N-type transistor, an N-type gate electrode of a thirteenth N-type transistor, an N-type gate electrode of a fourteenth N-type transistor, and an N-type gate electrode of the fifteenth N-type transistor on the silicon substrate.

21. The gate driving circuit according to claim 20, wherein, The logic operation circuit further includes a seventh signal line for transmitting a reset signal, and the third signal connection line is disposed on a side of the seventh signal line close to the P-type transistor.

22. The gate driving circuit according to claim 4, wherein, The first NOR gate includes a fourth P-type transistor, a fourth N-type transistor, a fifth P-type transistor, and a fifth N-type transistor, and the logic operation circuit further includes a fourth signal line for transmitting a first input signal, and the fourth signal line is connected to a P-type gate electrode of the fourth P-type transistor and an N-type gate electrode of the fourth N-type transistor; the fourth signal line has a first signal length and a first signal width, a ratio of the first signal length to the first signal width is greater than or equal to 35, the first signal length is a dimension in the first direction, and the first signal width is a dimension in the second direction.

23. The gate driving circuit according to claim 3, wherein, Multiple transistor groups in the second operation circuit form a fifth inverter, a sixth inverter, a seventh inverter, an eighth inverter, a ninth inverter, a tenth inverter, a latch, a fourth NOR gate, and a second NAND gate that are sequentially arranged along a direction close to the display area, the fifth inverter to the tenth inverter each include one transistor group, the latch includes nine transistor groups, and the fourth NOR gate and the second NAND gate each include two transistor groups.

24. The gate driving circuit according to claim 23, wherein, At least one transistor group among the fifth inverter to the tenth inverter includes a gate connection electrode and a common drain electrode, the gate connection electrode is connected to a P-type gate electrode of a P-type transistor and an N-type gate electrode of an N-type transistor, and the common drain electrode simultaneously serves as a P-type drain electrode of the P-type transistor and an N-type drain electrode of the N-type transistor; The common drain electrode in the fifth inverter is connected to the gate connection electrode in the sixth inverter, the common drain electrode in the sixth inverter is connected to the gate connection electrode in the seventh inverter, the common drain electrode in the seventh inverter is connected to the gate connection electrode in the eighth inverter, the common drain electrode in the eighth inverter is connected to the gate connection electrode in the ninth inverter, and the common drain electrode in the ninth inverter is connected to the gate connection electrode in the tenth inverter; the common drain electrode in at least one inverter has a first drain length, and the common drain electrode in at least another inverter has a second drain length, the ratio of the first drain length to the second drain length is from 0.95 to 1.05, and the first drain length and the second drain length are dimensions in the second direction.

25. The gate driving circuit according to claim 24, wherein, The gate connection electrode in at least one inverter has a first gate length, and the gate connection electrode in at least another inverter has a second gate length, the ratio of the first gate length to the second gate length is from 0.95 to 1.05, and the first gate length and the second gate length are dimensions in the first direction.

26. The gate driving circuit according to claim 23, wherein, At least one transistor group in the fifth to tenth inverters includes a third gate connection electrode, and the third gate connection electrode is connected to the P-type gate electrode of the P-type transistor and the N-type gate electrode of the N-type transistor through a third gate via; at least one transistor group in the latch, the fourth NOR gate, and the second NAND gate includes a fourth gate connection electrode, and the fourth gate connection electrode is connected to the P-type gate electrode of the P-type transistor and the N-type gate electrode of the N-type transistor through a fourth gate via; the third gate via and the fourth gate via are located in a gap region between the P-type active region of the P-type transistor and the N-type active region of the N-type transistor; In the second direction, the fourth gate via is closer to the P-type active region of the P-type transistor than the third gate via.

27. The gate driving circuit according to claim 26, wherein, A plurality of third gate vias in the fifth to tenth inverters are located on the same third gate via line, and the third gate via line is a straight line extending along the first direction; a plurality of fourth gate vias in the latch are located on the same fourth gate via line, and the fourth gate via line is a straight line extending along the first direction.

28. The gate driving circuit according to claim 27, wherein, The latch includes at least a twenty-eighth transistor group, a twenty-ninth transistor group, and a thirtieth transistor group, and the latch further includes an eleventh connection line. The first end of the eleventh connection line is connected to the twenty-eighth transistor group, and the second end of the eleventh connection line is connected to the thirtieth transistor group. At least a part of the eleventh connection line is located on one side of the fourth gate via line in the second direction, and at least another part of the eleventh connection line is bent toward the direction of the fourth gate via line.

29. The gate driving circuit according to claim 23, wherein, The logic operation circuit further includes a third signal line for transmitting a second input signal. One end of the third signal line is connected to a transistor group in the latch. The other end of the third signal line is connected to another transistor group in the latch after crossing at least 5 transistor groups. The orthographic projection of the third signal line on the silicon substrate does not overlap with the orthographic projection of the gate electrodes of the transistors in the fifth to tenth inverters on the silicon substrate. The orthographic projection of the third signal line on the silicon substrate at least partially overlaps with the orthographic projection of the P-type gate electrodes of the P-type transistors in the latch, the fourth NOR gate, and the second NAND gate on the silicon substrate.

30. The gate driving circuit according to claim 23, wherein, The second operation circuit further includes a fourth signal trace, a fifth signal trace, a sixth signal trace, and a seventh signal trace arranged in sequence along the direction close to the display area. The fifth signal trace and the seventh signal trace are configured to transmit power supply signals. The fourth signal trace and the sixth signal trace are configured to transmit ground signals. The orthographic projection of the fourth signal trace on the silicon substrate at least partially overlaps with the orthographic projection of the fifth inverter and the sixth inverter on the silicon substrate. The orthographic projection of the fifth signal trace on the silicon substrate at least partially overlaps with the orthographic projection of the seventh inverter, the eighth inverter, and the ninth inverter on the silicon substrate. The orthographic projection of the sixth signal trace on the silicon substrate at least partially overlaps with the orthographic projection of the latch on the silicon substrate. The orthographic projection of the seventh signal trace on the silicon substrate at least partially overlaps with the orthographic projection of the fourth NOR gate and the second NAND gate on the silicon substrate.

31. The gate driving circuit according to claim 30, wherein, The fourth signal trace and the fifth signal trace have the same first trace width. The sixth signal trace and the seventh signal trace have the same second trace width. The second trace width is greater than the first trace width. The first trace width and the second trace width are dimensions in the first direction.

32. The gate driving circuit according to claim 30, wherein, Among the multiple transistor groups overlapping with the fourth signal trace or the fifth signal trace, at least one P-type transistor in one transistor group has a first P-type width-to-length ratio. Among the multiple transistor groups overlapping with the sixth signal trace or the seventh signal trace, at least one P-type transistor in one transistor group has a second P-type width-to-length ratio. The second P-type width-to-length ratio is greater than the first P-type width-to-length ratio.

33. The gate driving circuit according to claim 30, wherein, Among the multiple transistor groups overlapping with the fourth signal trace or the fifth signal trace, at least one N-type transistor in one transistor group has a first N-type width-to-length ratio. Among the multiple transistor groups overlapping with the sixth signal trace or the seventh signal trace, at least one N-type transistor in one transistor group has a second N-type width-to-length ratio. The second N-type width-to-length ratio is greater than the first N-type width-to-length ratio.

34. The gate driving circuit according to claim 3, wherein, A plurality of transistor groups in the third arithmetic circuit form a fifth NOR gate and a third NAND gate that are sequentially arranged along the direction close to the display area. The fifth NOR gate includes a forty-first P-type transistor, a forty-first N-type transistor, a forty-second P-type transistor, a forty-second N-type transistor, a forty-third P-type transistor, and a forty-third N-type transistor. The third NAND gate includes a forty-fourth P-type transistor, a forty-fourth N-type transistor, a forty-fifth P-type transistor, and a forty-fifth N-type transistor. The P-type width-to-length ratio of the P-type transistors in the fifth NOR gate is greater than the P-type width-to-length ratio of the P-type transistors in the third NAND gate.

35. The gate driving circuit according to claim 34, wherein, The third arithmetic circuit further includes an eleventh signal transfer line. The first end of the eleventh signal transfer line is connected to the forty-third P-type transistor, and the second end of the eleventh signal transfer line is connected to the gate electrode of the forty-fifth P-type transistor. The positive projection of the eleventh signal transfer line on the silicon substrate does not overlap with the positive projection of the P-type active region of the forty-fourth P-type transistor on the silicon substrate.

36. The gate driving circuit according to claim 35, wherein, The forty-fifth P-type transistor at least includes a P-type active region, a P-type source electrode, and a P-type drain electrode. The first end of the P-type source electrode is connected to the first power supply line. The second end of the P-type source electrode is connected to the first region of the P-type active region through a via. The first end of the P-type drain electrode is connected to the output signal line of the third arithmetic circuit. The second end of the P-type drain electrode is connected to the second region of the P-type active region through a via. The positive projection of the eleventh signal transfer line on the silicon substrate at least partially overlaps with the positive projection of the P-type drain electrode of the forty-fifth P-type transistor on the silicon substrate.

37. The gate driving circuit according to claim 36, wherein, The positive projection of the output signal line of the third arithmetic circuit on the silicon substrate at least partially overlaps with the positive projection of the P-type gate electrode of the forty-fifth P-type transistor on the silicon substrate.

38. The gate driving circuit according to claim 36, wherein, The eleventh signal transfer line is arranged between the output signal line of the third arithmetic circuit and the P-type active region of the forty-fourth P-type transistor.

39. The gate driving circuit according to any one of claims 1 to 38, wherein, The logic arithmetic circuit at least includes a first signal line for transmitting a transmission ratio control signal, a second signal line for transmitting a third input signal, a third signal line for transmitting a second input signal, a fourth signal line for transmitting a first input signal, a fifth signal line, a sixth signal line for transmitting a first reset signal, a seventh signal line for transmitting a second reset signal, and an eighth signal line for transmitting a clock signal. The first signal line, the second signal line, the third signal line, the sixth signal line, the eighth signal line, the seventh signal line, and the fifth signal line are sequentially arranged along the second direction. The fourth signal line is arranged on one side of the fifth signal line in the opposite direction of the second direction Y.

40. The gate driving circuit according to claim 39, wherein, The positive projection of the first signal line on the silicon substrate does not overlap with the positive projection of the P-type gate electrodes of the plurality of transistor groups in the first arithmetic circuit and the second arithmetic circuit on the silicon substrate.

41. The gate driving circuit according to claim 39, wherein, The positive projection of the second signal line on the silicon substrate does not overlap with the positive projections of the P-type gate electrodes of multiple inverters in the first arithmetic circuit and the second arithmetic circuit on the silicon substrate.

42. The gate driving circuit according to claim 39, wherein The positive projection of the third signal line on the silicon substrate does not overlap with the positive projections of the P-type gate electrodes of multiple inverters in the first arithmetic circuit and the second arithmetic circuit on the silicon substrate.

43. The gate driving circuit according to any one of claims 1 to 42, wherein, The gate driving circuit further includes a shift register circuit, a level converter, and a line driving enhancer disposed on the silicon substrate. The shift register circuit is configured to generate a sequential shift timing according to a timing signal. The logic arithmetic circuit is configured to generate a target timing through logic arithmetic. The level converter is configured to perform a voltage domain conversion on the target timing. The line driving enhancer is configured to enhance the converted signal and output it to the scan signal line in the display area.

44. A display substrate, comprising a display area and a non-display area; the display area includes a plurality of sub-pixels, and at least one sub-pixel includes a pixel driving circuit and at least one scan signal line, and the scan signal line is configured to provide a scan signal to the connected pixel driving circuit; the non-display area includes a plurality of cascaded gate driving circuits, at least one gate driving circuit is connected to the scan signal line in the display area, and at least one gate driving circuit includes the gate driving circuit according to any one of claims 1 to 43.

45. A display device, comprising the display substrate according to claim 44.

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