Co-packaged optics structure and manufacturing method therefor

Abstract

The present application provides a co-packaged optics structure and a manufacturing method therefor. The co-packaged optics structure comprises: an electronic chip packaging unit, wherein electronic chips are packaged in the electronic chip packaging unit; and an optical chip unit, wherein the optical chip unit comprises an optical chip and an optical window located on the front surface of the optical chip, the front surfaces of the electronic chips in the electronic chip packaging unit are opposite to and electrically connected to the front surface of the optical chip in the optical chip unit, and there is no overlapping area between the projection of the electronic chip packaging unit on the optical chip unit and the optical window. The co-packaged optics structure provided by the present application can achieve high-efficiency signal transmission and improve the product yield of the co-packaged optics structure.

Description

A photoelectric sealing structure and its preparation method

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to the Chinese patent application filed with the China Patent Office on January 11, 2024, with application number 202410044146.X and invention name “A photoelectric sealing structure and its preparation method”, the entire contents of which are incorporated by reference into this application. Technical Field

[0003] The present application relates to the field of semiconductor packaging technology, and in particular to a photoelectric sealing structure and a preparation method thereof. Background Art

[0004] Currently, most optoelectronic packaging projects in the industry use wire bonding to output signals after the optical chip and electrical chip are bonded. On the one hand, the transmission efficiency is low, and on the other hand, wire arc protection in the overall structure also becomes a key issue in product transportation and structure.

[0005] To solve the above technical problems, technicians in this field have cited through-silicon via technology to achieve high-speed electrical signal transmission between the substrate and the electrical integrated chip. Through-silicon via (TSV) technology has the highest stacking density in the three-dimensional direction, improving power consumption and other advantageous performance, but the welding yield is not high, resulting in a low yield of the optoelectronic sealing structure; in addition, there is still the problem of low signal transmission efficiency.

[0006] Summary of the Invention

[0007] Therefore, the technical problem to be solved by the present application is to overcome the defects of low signal transmission and low yield of the optoelectronic sealing structure in the prior art, thereby providing an optoelectronic sealing structure and a preparation method thereof.

[0008] The present application provides a photoelectric sealing structure, comprising: an electrical chip packaging unit; the electrical chip packaging unit encapsulates an electrical chip; an optical chip unit; the optical chip unit comprises an optical chip and an optical window located on the front surface of the optical chip; the front surface of the electrical chip in the electrical chip packaging unit is opposite to and electrically connected to the front surface of the optical chip in the optical chip unit; the projection of the electrical chip packaging unit on the optical chip unit has no overlapping area with the optical window.

[0009] Optionally, it also includes: a substrate having a receiving groove; the optical chip is located in the receiving groove; the front of the optical chip is exposed by the receiving groove; the electrical chip packaging unit is located on the side of the substrate having the receiving groove; the electrical chip packaging unit includes: a plurality of electrical chips arranged at intervals; a redistribution structure connecting the front of each of the electrical chips; the front of the electrical chip in the electrical chip packaging unit is electrically connected to the front of the optical chip through the redistribution structure.

[0010] Optionally, the electrical chip packaging unit further includes a plurality of resistors and capacitors arranged around the electrical chip, and the resistors and capacitors are connected to the substrate through the rewiring structure; the resistors and capacitors include a resistor-capacitor body and a resistor-capacitor pad surrounding the resistor-capacitor body; the electrical chip has a chip pad on the side facing the rewiring structure; the rewiring structure includes a first wiring path and a second wiring path spaced apart, the first wiring path being electrically connected to the resistor-capacitor pad and the substrate respectively, and the second wiring path being electrically connected to the chip pad and the optical chip respectively.

[0011] Optionally, it also includes: a plurality of first solder balls located between the rewiring structure and the optical chip; a plurality of second solder balls located between the rewiring structure and the substrate; the first wiring paths are electrically connected to the resistor-capacitor pads and the second solder balls, respectively, and the second solder balls are also electrically connected to the substrate; the second wiring paths are electrically connected to the chip pads and the first solder balls, respectively, and the first solder balls are also electrically connected to the optical chip.

[0012] Optionally, the electrical chip packaging unit further includes: a plastic encapsulation layer located on a side of the redistribution structure away from the substrate and the optical chip, wherein the plastic encapsulation layer covers the electrical chip and the resistor and capacitor components.

[0013] Optionally, there is a gap between the optical chip and the side walls and bottom walls of the receiving groove, and the size of the gap is 700 μm-900 μm.

[0014] The present application also provides a method for preparing a photoelectric sealing structure, comprising: forming an electrical chip packaging unit; the electrical chip packaging unit encapsulating an electrical chip; forming an optical chip unit; the optical chip unit comprising an optical chip and an optical window located on the front surface of the optical chip; arranging the front surface of the electrical chip in the electrical chip packaging unit relative to the front surface of the optical chip in the optical chip unit for electrical connection; the projection of the electrical chip packaging unit on the optical chip unit having no overlapping area with the optical window.

[0015] Optionally, it also includes: providing a substrate having a receiving groove; after the front side of the electrical chip in the electrical chip packaging unit and the front side of the optical chip in the optical chip unit are arranged relative to each other and electrically connected, the optical chip is placed in the receiving groove, and the front side of the optical chip is exposed by the receiving groove; the electrical chip packaging unit is located on the side of the substrate having the receiving groove.

[0016] Optionally, the steps of forming an electrical chip packaging unit include: providing a carrier; forming a thermal peeling film on one surface of the carrier; forming a redistribution structure on a side of the thermal peeling film away from the carrier; forming a plurality of electrical chips on a side of the redistribution structure away from the carrier, the redistribution structure connecting the front sides of the electrical chips; in the step of arranging the front sides of the electrical chip in the electrical chip packaging unit and the front sides of the optical chip in the optical chip unit relative to each other for electrical connection, the front sides of the electrical chip in the electrical chip packaging unit are electrically connected to the front sides of the optical chip in the optical chip unit through the redistribution structure.

[0017] Optionally, after a redistribution structure is formed on a side of the thermal peeling film away from the carrier, and before a plurality of electrical chips are formed on a side of the redistribution structure away from the carrier, a plurality of resistors and capacitors are formed on a side of the partial redistribution structure away from the carrier; after the plurality of electrical chips are formed, the plurality of resistors and capacitors surround the electrical chips; the steps of forming the plurality of resistors and capacitors include: installing resistors and capacitors on a side of the redistribution structure away from the carrier by electronic circuit assembly technology; the redistribution structure includes a first wiring path and a second wiring path spaced apart; the resistors and capacitors include a resistor-capacitor body and a resistor-capacitor pad surrounding the resistor-capacitor body; the resistor-capacitor pad is electrically connected to the first wiring path; the electrical chip has a chip pad; and the chip pad is electrically connected to the second wiring path.

[0018] Optionally, after forming a plurality of resistors and capacitors, a plastic encapsulation layer is formed on one side of the redistribution structure having the plurality of electrical chips and resistors and capacitors, wherein the plastic encapsulation layer covers the electrical chips and resistors and capacitors.

[0019] Optionally, the step of forming the electrical chip packaging unit further includes: after forming a plurality of electrical chips and resistors and capacitors on one side of the redistribution structure, removing the carrier board and the thermal peeling film.

[0020] Optionally, before the front side of the electrical chip in the electrical chip packaging unit is arranged relative to the front side of the optical chip in the optical chip unit for electrical connection, a plurality of first sub-solder balls are formed on the other side of the rewiring structure away from the plurality of electrical chips and resistors and capacitors; a plurality of second sub-solder balls are formed on the front surface of the optical chip; in the process of setting the front side of the electrical chip in the electrical chip packaging unit relative to the front side of the optical chip in the optical chip unit for electrical connection, the first sub-solder balls and the second sub-solder balls merge with each other to form first solder balls after the front side of the electrical chip in the electrical chip packaging unit is arranged relative to the front side of the optical chip in the optical chip unit for electrical connection, and the plurality of first solder balls are located between the rewiring structure and the optical chip.

[0021] Optionally, before the front side of the electrical chip in the electrical chip packaging unit and the front side of the optical chip in the optical chip unit are arranged opposite to each other for electrical connection, the method further includes: performing a dicing process on the electrical chip packaging unit.

[0022] The technical solution of this application has the following advantages:

[0023] In the optoelectronic package structure provided herein, the front surface of the electrical chip in the electrical chip packaging unit faces and is electrically connected to the front surface of the optical chip in the optical chip unit. The projection of the electrical chip packaging unit on the optical chip unit does not overlap with the optical window. When the electrical chip is powered on, it can directly and quickly drive the optical chip, outputting an optical signal from the optical window without the need for expensive through-silicon via (TSV) structures. This not only enables highly efficient signal transmission, but also improves the soldering yield of the optoelectronic package structure, thereby increasing the product yield of the optoelectronic package structure.

[0024] Optionally, the electrical chip packaging unit further includes a plurality of resistors and capacitors disposed around the electrical chip, wherein the resistors and capacitors are connected to the substrate via the redistribution structure. The provision of the resistors and capacitors can improve coupling efficiency.

[0025] Optionally, the electrical chip packaging unit includes a rewiring structure connecting the front surfaces of the electrical chips; the front surfaces of the electrical chips in the electrical chip packaging unit are electrically connected to the front surfaces of the optical chips in the optical chip unit via the rewiring structure. This wafer-level rewiring process enables the output of optical-electrical combined signals, thereby improving overall transmission efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the following is a brief introduction to the drawings required for use in the specific implementation methods or the description of the prior art. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0027] FIG1 is a cross-sectional view of the optoelectronic sealing structure in Example 1 of the present application;

[0028] FIG2 is a top view of the optoelectronic sealing structure in Example 1 of the present application;

[0029] FIG3 is a schematic flow chart of a method for preparing a photoelectric package structure in Example 2 of the present application;

[0030] 4 to 13 are schematic structural diagrams of the process of preparing the optoelectronic sealing structure in Example 2 of the present application. DETAILED DESCRIPTION

[0031] The following will clearly and completely describe the technical solution of this application in conjunction with the accompanying drawings. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of this application.

[0032] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings and are intended solely to facilitate the description of this application and simplify the description. They do not indicate or imply that the devices or components referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0033] In the description of this application, it should be noted that, unless otherwise expressly specified or limited, the terms "mounted," "connected," and "connected" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integral connections; mechanical connections or electrical connections; direct connections or indirect connections through an intermediate medium; and internal connections between two components. Those skilled in the art will understand the specific meanings of the above terms in this application based on the specific circumstances.

[0034] In addition, the technical features involved in the different embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.

[0035] Example 1

[0036] In combination with Figures 1 and 2, this embodiment provides a photoelectric sealing structure, including: an electrical chip packaging unit A; the electrical chip packaging unit A encapsulates an electrical chip 2; an optical chip unit; the optical chip unit includes an optical chip 6 and an optical window 9 located on the front surface of the optical chip 6; the front surface of the electrical chip 2 in the electrical chip packaging unit A is opposite to and electrically connected to the front surface of the optical chip 6 in the optical chip unit; the projection of the electrical chip packaging unit A on the optical chip unit has no overlapping area with the optical window 9.

[0037] In this embodiment, the front surface of the electrical chip 2 in the electrical chip package unit A faces and is electrically connected to the front surface of the optical chip 6 in the optical chip unit. The projection of the electrical chip package unit A on the optical chip unit does not overlap with the optical window 9. When powered on, the electrical chip 2 can directly and quickly drive the optical chip, outputting an optical signal from the optical window without the need for expensive through-silicon via (TSV) structures. This not only enables highly efficient signal transmission, but also improves the soldering yield of the optoelectronic package structure, thereby enhancing the product yield of the optoelectronic package structure.

[0038] The optoelectronic sealing structure also includes: a substrate 8, which has a receiving groove 4; the optical chip 6 is located in the receiving groove 4; the front of the optical chip 6 is exposed by the receiving groove 4; the electrical chip packaging unit A is located on the side of the substrate 8 having the receiving groove 4. The electrical chip packaging unit A includes: a plurality of electrical chips 2 arranged at intervals; a rewiring structure 1, which connects the front of each of the electrical chips 2; the front of the electrical chip 2 in the electrical chip packaging unit A is electrically connected to the front of the optical chip 6 in the optical chip unit through the rewiring structure 1. The rewiring structure 1 is formed by a wafer-level process to realize the output of the optoelectronic sealing signal and improve the overall transmission efficiency of the optoelectronic sealing structure; in addition, the electrical chip packaging unit A includes a plurality of electrical chips 2 arranged at intervals, and the electrical chip packaging unit A contains a plurality of electrical chips 2, which is conducive to the efficient output of electrical signals.

[0039] In one embodiment, there is a gap between the optical chip 6 and the side walls and bottom walls of the receiving groove 4, and the size of the gap is 700μm-900μm, for example, 700μm, 800μm or 900μm. The purpose of leaving a certain gap between the optical chip 6 and the side walls and bottom walls of the receiving groove 4 is to provide a safety distance and avoid tolerance. If the size of the gap is too large, the size of the substrate 8 is too large, which can easily aggravate the warping problem during reflow, affect the welding effect, and reduce the effect of improving the product yield of the optoelectronic sealing structure; if the size of the gap is too small, the safety distance is small when placing the optical chip 6 in the receiving groove 4 of the substrate 8, and the effect of avoiding tolerance is reduced.

[0040] In one embodiment, the electrical chip packaging unit A further includes a plurality of resistors and capacitors 3 disposed around the electrical chip 2, and the resistors and capacitors 3 are connected to the substrate 8 via the redistribution structure 1. The resistors and capacitors 3 are used to improve coupling efficiency, thereby improving photoelectric conversion efficiency.

[0041] In one embodiment, the resistor-capacitor element 3 includes a resistor-capacitor body 31 and a resistor-capacitor pad 32 surrounding the resistor-capacitor body 31. The material of the resistor-capacitor body 31 includes ceramic, so it is necessary to set the resistor-capacitor pad 32 around the resistor-capacitor body 31 for electrical connection to the redistribution structure 1 to achieve a path. The side of the electronic chip 2 facing the redistribution structure 1 has a chip pad (not shown in the figure). The chip pad can be an embedded chip pad or an exposed chip pad, and there is no specific limitation on the position of the chip pad.

[0042] In one embodiment, the rewiring structure 1 includes a first wiring path and a second wiring path spaced apart. The first wiring path is electrically connected to the RC pads 32 and the substrate 8, respectively, while the second wiring path is electrically connected to the chip pads and the optical chip 6. Thus, the electrical path for achieving optoelectronic sealing signal output through the rewiring structure 1 is as follows: the substrate 8 is electrically connected to the RC pads 32, which are connected in series with the spaced apart electrical chip 2. This allows signals exiting the RC pads 32 directly into the electrical chip 2, then out through the chip pads of the electrical chip 2, and finally into the optical chip 6.

[0043] The optoelectronic sealing structure also includes: a plurality of first solder balls 5 located between the rewiring structure 1 and the optical chip 6; a plurality of second solder balls 7 located between the rewiring structure 1 and the substrate 8; the first wiring path is electrically connected to the resistor-capacitor pad 32 and the second solder ball 7 respectively, the second solder ball 7 is also electrically connected to the substrate 8, the second wiring path is electrically connected to the chip pad and the first solder ball 5 respectively, and the first solder ball 5 is also electrically connected to the optical chip 6.

[0044] The electrical chip packaging unit A further includes: a plastic encapsulation layer 10 located on a side of the redistribution structure 1 away from the substrate 8 and the optical chip 6 , wherein the plastic encapsulation layer 10 covers the electrical chip 2 and the resistor and capacitor 3 .

[0045] Example 2

[0046] This embodiment provides a method for preparing a photoelectric sealing structure, referring to FIG3 , including:

[0047] S1: forming an electric chip packaging unit; the electric chip packaging unit encapsulates an electric chip;

[0048] S1: forming an optical chip unit; the optical chip unit includes an optical chip and an optical window located on the front surface of the optical chip;

[0049] S1: The front surface of the electrical chip in the electrical chip packaging unit and the front surface of the optical chip in the optical chip unit are arranged opposite to each other and electrically connected; the projection of the electrical chip packaging unit on the optical chip unit does not have an overlapping area with the optical window.

[0050] The preparation method of the optoelectronic package structure also includes: providing a substrate having a receiving groove; after the front surface of the electrical chip in the electrical chip packaging unit and the front surface of the optical chip in the optical chip unit are arranged opposite to each other and electrically connected, the optical chip is placed in the receiving groove, and the front surface of the optical chip is exposed by the receiving groove; the electrical chip packaging unit is located on the side of the substrate having the receiving groove.

[0051] The following describes in detail the method for preparing the optoelectronic sealing structure with reference to FIG. 4 to FIG. 13 .

[0052] 4 , a carrier plate C is provided; a thermal peeling film 11 is formed on one side surface of the carrier plate C.

[0053] 5 , a redistribution structure 1 is formed on a side of the thermal release film 11 away from the carrier C.

[0054] It can be known that the rewiring structure 1 includes a dielectric layer and rewiring in the dielectric layer, wherein the rewiring material is a metal material, such as copper, which has a conductive function and is used for subsequent electrical connection between the resistor and capacitor pads and the substrate, as well as the chip pads and the optical chip; the dielectric layer is used to protect the rewiring.

[0055] In one embodiment, the number of dielectric layers can be one or more layers, and accordingly, the number of redistribution layers can be one or more layers. FIG5 illustrates the case where the number of dielectric layers and the number of redistribution layers are three.

[0056] The rewiring structure 1 includes a first wiring path and a second wiring path that are spaced apart.

[0057] 6 , a plurality of resistors and capacitors 3 are formed on a side of the partial redistribution structure 1 away from the carrier C.

[0058] The step of forming the plurality of resistors and capacitors 3 includes mounting the resistors and capacitors 3 on a side of the redistribution structure 1 away from the carrier C using surface mount technology. Mounting the resistors and capacitors 3 on one side of the redistribution structure 1 using surface mount technology (SMT) has two advantages: improved coupling efficiency and optimized manufacturing processes for subsequent products on substrate 8.

[0059] In one embodiment, the resistor-capacitor element 3 includes a resistor-capacitor body 31 and a resistor-capacitor pad 32 surrounding the resistor-capacitor body, wherein the resistor-capacitor pad 32 is electrically connected to the first wiring path. The resistor-capacitor body 31 is made of a ceramic material. The resistor-capacitor pad 32 is provided around the resistor-capacitor body 31 to achieve electrical connection with the substrate by being electrically connected to the first wiring path.

[0060] 7 , a plurality of electrical chips 2 are formed on a side of the redistribution structure 1 away from the carrier C, and the redistribution structure 1 connects the front surfaces of the electrical chips 2 .

[0061] After forming a plurality of electrical chips 2, a plurality of resistors and capacitors 3 surround the electrical chips. This arrangement is intended to improve coupling efficiency, further realize the output of optoelectronic sealing signals, and improve overall transmission efficiency.

[0062] The electric chip 2 has a chip pad; the chip pad is electrically connected to the second wiring path.

[0063] 8 , a plastic encapsulation layer 10 is formed on one side of the redistribution structure 1 having a plurality of electrical chips 2 and resistors and capacitors 3 , and the plastic encapsulation layer 10 covers the electrical chips 2 and resistors and capacitors 3 .

[0064] 9 , the carrier plate C and the thermal peeling film 11 are removed.

[0065] The process of removing the carrier plate C and the thermal peeling film 11 is a conventional process in the art and will not be described in detail in this embodiment.

[0066] 10 , a plurality of first sub-solder balls 5a and a plurality of second solder balls 7 are formed on the other side of the redistribution structure 1 away from the plurality of electrical chips 2 and the resistors and capacitors 3. The plurality of second solder balls 7 are used to achieve electrical connection between the redistribution structure 1 and the substrate in the optoelectronic package structure.

[0067] In this embodiment, after forming a plurality of first sub-solder balls 5a and a plurality of second solder balls 7, the redistribution structure 1, the resistor and capacitor 3, the electric chip 2, the plastic encapsulation layer 10, and the plurality of first sub-solder balls 5a and the plurality of second solder balls 7 form an electric chip packaging unit A; the electric chip packaging unit A is subjected to a dicing process so that it can be used as an independent unit for subsequent packaging processes.

[0068] It should be noted that the structure of the first sub-solder ball 5a is a UBM structure, and the structure of the second solder ball 7 is a bump structure. The first sub-solder ball 5a and the second solder ball 7 have different structures due to their different positions and connection relationships, but they are both conventional structures in this field and will not be introduced in detail in this application.

[0069] 11 , an optical chip unit is formed; the optical chip unit includes an optical chip 6 and an optical window located on the front surface of the optical chip 6 .

[0070] In one embodiment, a plurality of second sub-solder balls 5 b are formed on the front surface of the optical chip 6 .

[0071] It should be noted that the second sub-solder ball 5 b and the light window (see FIG. 2 ) are spaced apart.

[0072] 12 , the front surface of the electrical chip 2 in the electrical chip packaging unit A and the front surface of the optical chip 6 in the optical chip unit are arranged opposite to each other and electrically connected.

[0073] Optionally, in the step of electrically connecting the front surface of the electrical chip 2 in the electrical chip packaging unit A to the front surface of the optical chip 6 in the optical chip unit, the front surface of the electrical chip 2 in the electrical chip packaging unit A is electrically connected to the front surface of the optical chip 6 in the optical chip unit through the redistribution structure 1.

[0074] Optionally, during the process of electrically connecting the front surface of the electrical chip 2 in the electrical chip package unit A to the front surface of the optical chip 6 in the optical chip unit, the first sub-solder balls 5a and the second sub-solder balls 5b are fused together to form first solder balls 5 after the front surface of the electrical chip 2 in the electrical chip package unit A and the front surface of the optical chip 6 in the optical chip unit are electrically connected. Several first solder balls 5 are located between the redistribution structure 1 and the optical chip 6. Therefore, the front surface of the optical chip 6 is electrically connected to the redistribution structure 1 via the several first solder balls, and is further electrically connected to the front surface of the electrical chip 2 in the electrical chip package unit A.

[0075] From the above description, it can be known that one end of the second wiring path of the rewiring structure 1 is connected to the chip pad and the other end is connected to one end of the first solder ball 5 , and the other end of the first solder ball 5 is connected to the optical chip 6 .

[0076] Referring to Figure 13, a substrate 8 is provided, which has a receiving groove 4; after the front surface of the electrical chip 2 in the electrical chip packaging unit A is arranged opposite to the front surface of the optical chip 6 in the optical chip unit and electrically connected, the optical chip 6 is placed in the receiving groove 4, and the front surface of the optical chip 6 is exposed by the receiving groove 4; the electrical chip packaging unit A is located on the side of the substrate 8 having the receiving groove 4.

[0077] It should be noted that, when placing the optical chip 6 in the receiving groove 4 , a certain gap should be kept between the optical chip 6 and the side walls and bottom wall of the receiving groove 4 as a safety distance to avoid the tolerance generated during operation from affecting signal transmission.

[0078] After the optical chip 6 is placed in the receiving groove 4, a plurality of second solder balls 7 are located between the rewiring structure 1 and the substrate 8. One end of a first wiring path included in the rewiring structure 1 is connected to the resistor-capacitor pad, and the other end is connected to one end of a second solder ball 7. The other end of the second solder ball 7 is connected to the substrate 8. Specifically, the substrate 8 has a plurality of pads (not shown) on the side facing the electrical chip packaging unit A. The other ends of the second solder balls 7 are electrically connected to the pads of the substrate 8.

[0079] Obviously, the above embodiments are merely examples for clarity of explanation and are not intended to limit the implementation methods. Those skilled in the art will readily appreciate that other variations or modifications based on the above descriptions are possible. It is not necessary and impossible to enumerate all implementation methods here. Obvious variations or modifications arising therefrom remain within the scope of protection of this application.

Claims

1. An optoelectronic co-packaging structure, characterized in that, Comprising: An electrical chip packaging unit; the electrical chip packaging unit packages an electrical chip; An optical chip unit; The optical chip unit includes an optical chip and an optical window located on the front surface of the optical chip; The front surface of the electrical chip in the electrical chip packaging unit faces and is electrically connected to the front surface of the optical chip in the optical chip unit; the projection of the electrical chip packaging unit on the optical chip unit does not have an overlapping area with the optical window.

2. The optoelectronic co-packaging structure according to claim 1, wherein, Further comprising: A substrate, the substrate having a receiving groove; The optical chip is located in the receiving groove; The front surface of the optical chip is exposed by the receiving groove; The electrical chip packaging unit is located on one side of the substrate having the receiving groove; The electrical chip packaging unit includes: a plurality of electrical chips arranged at intervals; a redistribution structure connecting the front surfaces of the electrical chips; the front surfaces of the electrical chips in the electrical chip packaging unit are electrically connected to the front surface of the optical chip through the redistribution structure.

3. The optoelectronic co-packaging structure according to claim 2, wherein The electrical chip packaging unit further includes a plurality of resistor-capacitor components arranged around the electrical chips, and the resistor-capacitor components are connected to the substrate through the redistribution structure; The resistor-capacitor component includes a resistor-capacitor body and a resistor-capacitor pad surrounding the resistor-capacitor body; one side of the electrical chip facing the redistribution structure has a chip pad; The redistribution structure includes a first wiring path and a second wiring path arranged at intervals, the first wiring path is electrically connected to the resistor-capacitor pad and the substrate respectively, and the second wiring path is electrically connected to the chip pad and the optical chip respectively.

4. The optoelectronic co-packaging structure according to claim 3, wherein, Further comprising: A plurality of first solder balls located between the redistribution structure and the optical chip; A plurality of second solder balls located between the redistribution structure and the substrate; The first wiring path is electrically connected to the resistor-capacitor pad and the second solder ball respectively, the second solder ball is also electrically connected to the substrate, the second wiring path is electrically connected to the chip pad and the first solder ball respectively, and the first solder ball is also electrically connected to the optical chip.

5. The optoelectronic co-packaging structure according to claim 3, wherein, The electrical chip packaging unit further includes: a molding layer located on a side of the redistribution structure away from the substrate and the optical chip, and the molding layer covers the electrical chips and the resistor-capacitor components.

6. The optoelectronic co-packaging structure according to claim 2, wherein, There is a gap between the optical chip and the side wall and the bottom wall of the receiving groove, and the size of the gap is 700μm - 900μm.

7. A preparation method of an optoelectronic co-packaging structure, characterized in that, Comprising: Forming an electrical chip packaging unit; the electrical chip packaging unit packages an electrical chip; Forming an optical chip unit; the optical chip unit includes an optical chip and an optical window located on the front surface of the optical chip; Oppositely arranging and electrically connecting the front surface of the electrical chip in the electrical chip packaging unit with the front surface of the optical chip in the optical chip unit; the projection of the electrical chip packaging unit on the optical chip unit does not have an overlapping area with the optical window.

8. The manufacturing method of the optoelectronic co-packaging structure according to claim 7, characterized in that, Further comprising: Providing a substrate, the substrate having a receiving groove; after oppositely arranging and electrically connecting the front surface of the electrical chip in the electrical chip packaging unit with the front surface of the optical chip in the optical chip unit, placing the optical chip in the receiving groove, the front surface of the optical chip is exposed by the receiving groove; the electrical chip packaging unit is located on one side of the substrate having the receiving groove.

9. The manufacturing method of the optoelectronic co-packaging structure according to claim 7, characterized in that, The steps of forming an electrical chip packaging unit include: Providing a carrier board; forming a thermal release film on one surface of the carrier board; forming a redistribution structure on a side of the thermal release film away from the carrier board; forming a plurality of electrical chips on a side of the redistribution structure away from the carrier board, and the redistribution structure is connected to the front sides of the respective electrical chips; In the step of electrically connecting the front sides of the electrical chips in the electrical chip packaging unit to face the front sides of the optical chips in the optical chip unit, the front sides of the electrical chips in the electrical chip packaging unit are electrically connected to the front sides of the optical chips in the optical chip unit through the redistribution structure.

10. The manufacturing method of the optoelectronic co-packaging structure according to claim 9, characterized in that, After forming the redistribution structure on a side of the thermal release film away from the carrier board and before forming a plurality of electrical chips on a side of the redistribution structure away from the carrier board, forming a plurality of resistors and capacitors on a side of a part of the redistribution structure away from the carrier board; After forming a plurality of electrical chips, the plurality of resistors and capacitors surround the electrical chips; The steps of forming a plurality of resistors and capacitors include: installing the resistors and capacitors on a side of the redistribution structure away from the carrier board through an electronic circuit assembly technology; The redistribution structure includes a first wiring path and a second wiring path arranged at intervals; the resistor and capacitor component includes a resistor and capacitor body and a resistor and capacitor pad surrounding the resistor and capacitor body; the resistor and capacitor pad is electrically connected to the first wiring path; the electrical chip has a chip pad; the chip pad is electrically connected to the second wiring path.

11. The manufacturing method of the optoelectronic co-packaging structure according to claim 10, characterized in that, After forming a plurality of resistors and capacitors, forming a molding compound layer on a side of the redistribution structure having a plurality of electrical chips and resistors and capacitors, and the molding compound layer covers the electrical chips and the resistors and capacitors.

12. The method for manufacturing the optoelectronic co-packaged structure according to claim 10, wherein, The steps of forming the electrical chip packaging unit further include: after forming a plurality of electrical chips and resistors and capacitors on one side of the redistribution structure, removing the carrier board and the thermal release film.

13. The manufacturing method of the optoelectronic co-packaging structure according to claim 12, characterized in that, Before electrically connecting the front sides of the electrical chips in the electrical chip packaging unit to face the front sides of the optical chips in the optical chip unit, forming a plurality of first sub solder balls on the other side of the redistribution structure away from the plurality of electrical chips and resistors and capacitors; Forming a plurality of second sub solder balls on the front surface of the optical chip; In the process of electrically connecting the front sides of the electrical chips in the electrical chip packaging unit to face the front sides of the optical chips in the optical chip unit, the first sub solder balls and the second sub solder balls are fused with each other to form first solder balls after electrically connecting the front sides of the electrical chips in the electrical chip packaging unit to face the front sides of the optical chips in the optical chip unit, and a plurality of first solder balls are located between the redistribution structure and the optical chip.

14. The manufacturing method of the optoelectronic co-packaging structure according to claim 12, wherein Before electrically connecting the front sides of the electrical chips in the electrical chip packaging unit to face the front sides of the optical chips in the optical chip unit, it further includes: performing a dicing process on the electrical chip packaging unit.

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