Method and circuit for reducing residual error generated during hall current rotation

Abstract

A method and circuit for reducing a residual error generated during Hall current rotation, which method and circuit solve the problem of a residual error in a Hall induction voltage caused by the parasitic resistance or capacitance of a Hall element during Hall current rotation. The method specifically comprises: when a Hall current starts phase rotation, applying a first preset voltage to induction output terminals (B, D) within a preset time period, and at the same time, applying a second preset voltage to bias input terminals (A, C), so that the voltages of the induction output terminals (B, D) and the bias input terminals (A, C) all quickly change from a present steady state to a new steady state within a short period of time. Subsequently, the time for an initial error value of a Hall induction voltage to exponentially converge to zero is significantly shortened, so that a residual error in the Hall induction voltage is obviously reduced when Hall current rotation is finished. Compared with the prior art, the method can effectively and quickly reduce a residual error in a Hall induction voltage, thereby improving the output accuracy of a Hall sensor. The method is particularly applicable to the situation of high-frequency Hall current rotation.

Description

A method and circuit for reducing residual error generated when Hall current rotates Technical Field

[0001] The present invention relates to the field of Hall sensors, and in particular to a method and a circuit for reducing residual errors generated when Hall current rotates. Background Art

[0002] Hall sensors often employ Hall current rotation to eliminate the effects of Hall element mismatch and low-frequency noise on the sensor output. This technique involves sequentially applying a Hall bias voltage or current between two diagonal terminals of the Hall element and simultaneously detecting the Hall-induced voltage generated between two other, orthogonal terminals to characterize the magnetic flux density of the magnetic field perpendicular to the Hall element. Hall current rotation is essentially a chopper stabilization technique, with the Hall current rotation frequency / chopping frequency proportional to the bandwidth of the Hall sensor. However, as Hall sensors become faster, the Hall current rotation frequency continues to increase, increasing the delay caused by the parasitic resistance and capacitance of the Hall element itself.

[0003] Hall current rotation technology can employ different phase rotations (e.g., 2 / 4 / 8 / 16 phases). Two-phase rotation is used as an example for illustration. Figure 1 shows a schematic diagram of Hall current rotation with two-phase rotation. Figure 2 shows the waveforms of the voltages at terminals A and D on the Hall element shown in Figure 1, as well as the voltage sensed by the Hall element. V SENSE is the voltage sensed by the Hall element, known as the Hall-induced voltage. This Hall-induced voltage is proportional to the magnetic flux density of the magnetic field perpendicular to the Hall element. However, in practice, Hall elements have parasitic resistance R and parasitic capacitance C, as shown in Figure 3. These form a time constant τ = RC. After each current rotation (switching), the V SENSE error exponentially converges to zero from (VHI - VLO - VH), where VH is the ideal Hall-induced voltage. In practice, the parasitic resistance and capacitance of the Hall element form a first-order low-pass network. Each time the current rotates, the voltages at each terminal of the Hall element exhibit a first-order step response. After each current rotation, it takes a certain amount of time for the four terminals of the Hall element to reach a new steady state. As shown in Figure 2, the gray waveform represents the ideal voltage waveform, while the black waveform represents the voltage waveform with parasitic resistance and capacitance. The percentage error between the two decreases at the rate of exp(-t / RC). Therefore, the larger the RC product, the longer it takes to converge to the ideal value. For example, after 3τ, the error decreases to below approximately 5%; after 7τ, the error decreases to below approximately 0.1%.

[0004] When the Hall current rotation frequency is low, there's enough time for the error to decay to a negligible level. However, as the Hall current rotation frequency increases, the residual error at the end of a switching cycle becomes larger and more significant. This makes it impossible to distinguish this residual error from the Hall-effect voltage sensed by the Hall element, ultimately becoming an error in the Hall sensor's output, affecting the accuracy of the sensor's output signal. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to provide a method and circuit for reducing the residual error generated when the Hall current rotates, by introducing a first preset voltage and a second preset voltage within a preset time period to reduce the residual error of the Hall element at the end of the current rotation switching cycle.

[0006] The present invention solves the above-mentioned technical problem with the following technical solution: a method for reducing residual error generated when Hall current rotates, applied to a Hall element, wherein the Hall element includes a bias input terminal and a sensing output terminal, the method comprising:

[0007] When the Hall current begins to rotate phase, a first preset voltage is applied to the sensing output terminal within a preset time period, so that the voltage of the sensing output terminal is quickly converted from the first current steady-state voltage to a first new steady-state voltage; wherein the first new steady-state voltage matches the first preset voltage; and

[0008] Determining a bias type of the bias input terminal, wherein when the bias type is current bias, applying a second preset voltage to the bias input terminal within the preset time period so that the voltage of the bias input terminal is rapidly converted from the second current steady-state voltage to a second new steady-state voltage; wherein the second new steady-state voltage matches the second preset voltage.

[0009] On the basis of the above technical solution, the present invention can also be improved as follows.

[0010] Furthermore, the sensing output terminal includes a first sensing output terminal and a second sensing output terminal. When the Hall current begins to rotate in phase, a first preset voltage is applied to the sensing output terminal within a preset time period, so that the voltage of the sensing output terminal is rapidly converted from a first current steady-state voltage to a first new steady-state voltage. The matching of the first new steady-state voltage with the first preset voltage specifically includes:

[0011] If the first current steady-state voltage of the first sensing output terminal is a high steady-state voltage and the corresponding first current steady-state voltage of the second sensing output terminal is a low steady-state voltage, then when the Hall current begins to rotate its phase, an intermediate steady-state voltage is simultaneously applied to the first sensing output terminal and the second sensing output terminal within the preset time period, so that the voltage of the first sensing output terminal is quickly converted from the high steady-state voltage to the first new steady-state voltage, and the voltage of the second sensing output terminal is quickly converted from the low steady-state voltage to the first new steady-state voltage; wherein the first new steady-state voltage matches the intermediate steady-state voltage.

[0012] Furthermore, simultaneously applying an intermediate steady-state voltage to the first sensing output terminal and the second sensing output terminal specifically includes:

[0013] A first switch is used to short-circuit the first sensing output terminal and the second sensing output terminal within the preset time period.

[0014] Furthermore, the sensing output terminal includes a first sensing output terminal and a second sensing output terminal. When the Hall current begins to rotate in phase, a first preset voltage is applied to the sensing output terminal within a preset time period, so that the voltage of the sensing output terminal is rapidly converted from a first current steady-state voltage to a first new steady-state voltage. The matching of the first new steady-state voltage with the first preset voltage specifically includes:

[0015] If the first current steady-state voltage of the first sensing output terminal is an intermediate steady-state voltage, and the corresponding first current steady-state voltage of the second sensing output terminal is an intermediate steady-state voltage, then when the Hall current starts to rotate its phase, a high steady-state voltage is applied to the first sensing output terminal and a low steady-state voltage is applied to the second sensing output terminal within the preset time period, so that the voltage of the first sensing output terminal is quickly converted from the intermediate steady-state voltage to the first new steady-state voltage, and the voltage of the second sensing output terminal is quickly converted from the intermediate steady-state voltage to the first new steady-state voltage; wherein the first new steady-state voltage of the first sensing output terminal matches the high steady-state voltage, and the first new steady-state voltage of the second sensing output terminal matches the low steady-state voltage.

[0016] Furthermore, applying a high steady-state voltage to the first sensing output terminal and applying a low steady-state voltage to the second sensing output terminal during the preset time period specifically includes:

[0017] During the preset time period, using a second switch to connect the first sensing output terminal and the second sensing output terminal to a preset common mode voltage;

[0018] The preset common mode voltage is an average value of steady-state values ​​of the Hall-induced voltage of the first sensing output terminal and the Hall-induced voltage of the second sensing output terminal within the rotation phase of the Hall current.

[0019] Furthermore, the bias input terminal includes a first bias input terminal and a second bias input terminal; determining a bias type of the bias input terminal, wherein when the bias type is current bias, applying a second preset voltage to the bias input terminal within the preset time period so that the voltage of the bias input terminal is quickly converted from a second current steady-state voltage to a second new steady-state voltage; wherein matching the second new steady-state voltage with the second preset voltage specifically includes:

[0020] If the second current steady-state voltage of the first bias input terminal is a high steady-state voltage and the corresponding second current steady-state voltage of the second bias input terminal is a low steady-state voltage, an intermediate steady-state voltage is simultaneously applied to the first bias input terminal and the second bias input terminal within the preset time period, so that the voltage of the first bias input terminal is quickly converted from the high steady-state voltage to the second new steady-state voltage, and the voltage of the second bias input terminal is quickly converted from the low steady-state voltage to the second new steady-state voltage; wherein the second new steady-state voltage matches the intermediate steady-state voltage.

[0021] Furthermore, the method further includes: applying an intermediate steady-state voltage to the first bias input terminal and the second bias input terminal simultaneously within the preset time period;

[0022] During a preset time period, the first bias input terminal is connected to an intermediate steady-state voltage using a third switch and a first voltage source; and

[0023] The second bias input terminal is connected to an intermediate steady-state voltage using a fourth switch and a second voltage source.

[0024] Furthermore, the bias input terminal includes a first bias input terminal and a second bias input terminal; determining a bias type of the bias input terminal, wherein when the bias type is current bias, applying a second preset voltage to the bias input terminal within the preset time period so that the voltage of the bias input terminal is quickly converted from a second current steady-state voltage to a second new steady-state voltage; wherein matching the second new steady-state voltage with the second preset voltage specifically includes:

[0025] If the second current steady-state voltage of the first bias input terminal is an intermediate steady-state voltage, and the corresponding second current steady-state voltage of the second bias input terminal is an intermediate steady-state voltage, a high steady-state voltage is applied to the first bias input terminal and a low steady-state voltage is applied to the second bias input terminal within the preset time period, so that the voltage of the first bias input terminal is quickly converted from the intermediate steady-state voltage to the second new steady-state voltage, and the voltage of the second bias input terminal is quickly converted from the intermediate steady-state voltage to the second new steady-state voltage; wherein the second new steady-state voltage of the first bias input terminal matches the high steady-state voltage, and the second new steady-state voltage of the second bias input terminal matches the low steady-state voltage.

[0026] Furthermore, applying a high steady-state voltage to the first bias input terminal and applying a low steady-state voltage to the second bias input terminal during the preset time period specifically includes:

[0027] During a preset time period, the first bias input terminal is connected to a high steady-state voltage using a fifth switch and a third voltage source; and

[0028] The second bias input terminal is connected to a low steady-state voltage using a sixth switch and a fourth voltage source.

[0029] Based on the above method for reducing the residual error generated when the Hall current rotates, the present invention also provides a circuit for reducing the residual error generated when the Hall current rotates.

[0030] A circuit for reducing residual error generated when Hall current rotates is applied to a Hall element, wherein the Hall element includes a bias input terminal and a sensing output terminal. The circuit includes:

[0031] a first preset voltage circuit connected to the sensing output terminal and configured to apply a first preset voltage to the sensing output terminal within a preset time period when the Hall current begins to rotate phase, so as to quickly convert the voltage of the sensing output terminal from a first current steady-state voltage to a first new steady-state voltage; wherein the first new steady-state voltage matches the first preset voltage;

[0032] a second preset voltage circuit connected to the bias input terminal and configured to apply a second preset voltage to the bias input terminal when the bias type of the bias input terminal is current bias and within the preset time period, so that the voltage of the bias input terminal is quickly converted from the second current steady-state voltage to a second new steady-state voltage; wherein the second new steady-state voltage matches the second preset voltage.

[0033] The beneficial effects of the present invention are as follows: in a method and circuit for reducing residual errors generated when a Hall current rotates, although the parasitic resistance / capacitance of a Hall element cannot be changed, when the Hall current begins to rotate in phase, a first preset voltage is applied to a sensing output terminal of the Hall element within a preset time period, so that the voltage of the sensing output terminal is rapidly converted from a first current steady-state voltage to a first new steady-state voltage, and the first new steady-state voltage matches the first preset voltage; at the same time, a second preset voltage is applied to a bias input terminal of the Hall element, so that the voltage of the bias input terminal is rapidly converted from a second current steady-state voltage to a second new steady-state voltage, and the second new steady-state voltage matches the second preset voltage. In addition, because the preset time period is relatively short within the Hall current rotation cycle, the voltage states of the sensing output terminal and the bias input terminal can be converted from the current steady state to the new steady state in a very short time. Consequently, at the end of the preset time period, the initial value of the residual error of the Hall sensing voltage is significantly reduced. Furthermore, within a period of time after the end of the preset time period, the time it takes for the initial value of the residual error of the Hall sensing voltage to converge to zero in an exponential manner is correspondingly significantly reduced. Consequently, at the end of the Hall current rotation cycle, the residual error of the Hall sensing voltage is also significantly reduced, thereby preventing the residual error of the Hall sensing voltage from becoming an error in the final output of the Hall sensor. Compared to the prior art, the present invention can effectively and quickly reduce the residual error of the Hall sensing voltage, thereby improving the output accuracy of the Hall sensor, and is particularly suitable for high-frequency Hall current rotation situations. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] FIG1 is a schematic diagram of Hall current rotation in the prior art;

[0035] FIG2 is a waveform diagram of the voltage at terminals AD on the Hall element shown in FIG1 and the voltage induced by the Hall element;

[0036] FIG3 is a schematic diagram showing the existence of parasitic resistance and parasitic capacitance in a Hall element in the prior art;

[0037] FIG4 is a step diagram of a method for reducing residual error generated when Hall current rotates according to the present invention;

[0038] 5 is a waveform diagram of a Hall current rotation clock, a preset time period, a voltage of an AD terminal, and a Hall induced voltage in a method for reducing a Hall current rotation residual error according to the present invention;

[0039] FIG6 is a diagram of step S11a of a method for reducing residual error generated when Hall current rotates as shown in FIG4 ;

[0040] FIG7 is a diagram of step S11a1 of the method for reducing residual error generated when the Hall current rotates as shown in FIG6 ;

[0041] FIG8 is a diagram of step S11a' of a method for reducing residual error generated when Hall current rotates as shown in FIG4 ;

[0042] FIG9 is a diagram of step S11a'1 of a method for reducing residual error generated when Hall current rotates as shown in FIG8 ;

[0043] FIG10 is a diagram of step S11b of a method for reducing residual error generated when Hall current rotates as shown in FIG4 ;

[0044] FIG11 is a diagram of step S11b1 of the method for reducing residual error generated when the Hall current rotates as shown in FIG10 ;

[0045] FIG12 is a diagram of step S11b′ of a method for reducing residual error generated when Hall current rotates as shown in FIG4 ;

[0046] FIG13 is a diagram of step S11b'1 of a method for reducing residual error generated when Hall current rotates as shown in FIG12;

[0047] FIG14 is a block diagram of a circuit for reducing residual error generated when Hall current rotates according to the present invention;

[0048] FIG15 is a circuit diagram of a circuit for reducing residual error generated when Hall current rotates according to an embodiment of FIG14 ;

[0049] FIG16 is a circuit diagram of a preset time period setting circuit of a circuit for reducing residual errors generated when Hall current rotates according to an embodiment of FIG14 . DETAILED DESCRIPTION

[0050] The principles and features of the present invention are described below with reference to the accompanying drawings. The examples given are only used to explain the present invention and are not used to limit the scope of the present invention.

[0051] As shown in Figures 1 and 2, during the Hall current rotation process, the terminal voltages of the Hall element have three stable states: a high steady state, an intermediate steady state, and a low steady state. When a terminal of the Hall element is in the high steady state, the voltage at that terminal is the high steady-state voltage VHI. When a terminal of the Hall element is in the intermediate steady state, the voltage at that terminal is the intermediate steady-state voltage VMED. When a terminal of the Hall element is in the low steady state, the voltage at that terminal is the low steady-state voltage VLO. For each terminal of the Hall element, its voltage switches between two stable states: the high steady-state voltage VHI and the intermediate steady-state voltage VMED, or the low steady-state voltage VLO and the intermediate steady-state voltage VMED. In other words, in Hall current rotation technology, the voltage at each terminal of the Hall element flips once every half clock cycle of the clock signal CLK. That is, each terminal voltage gradually changes from its current steady-state voltage to its corresponding new steady-state voltage during each half clock cycle.

[0052] However, as shown in Figure 3, due to the parasitic resistance R and parasitic capacitance C of the Hall element, a corresponding residual error is generated each time the voltage at each terminal is converted from the current steady-state voltage to the corresponding new steady-state voltage. When the Hall current rotation frequency is low, there is enough time for the residual error to decay to a negligible range. However, as the frequency increases, the residual error will become non-negligible at the end of a Hall current rotation cycle. This residual error is indistinguishable from the Hall induced voltage sensed by the Hall element and will eventually become an error in the sensor output.

[0053] Therefore, the present invention provides a method for reducing residual error generated when Hall current rotates, which is applied to a Hall element, wherein the Hall element includes a bias input terminal and a sensing output terminal. The sensing output terminal includes a first sensing output terminal B and a second sensing output terminal D. The bias input terminal includes a first bias input terminal A and a second bias input terminal C.

[0054] As shown in Figures 4 and 5, CLK in Figure 5 represents the waveform of the Hall current rotation clock; SET represents the waveform of the change in the preset time period, wherein the time when the high level in SET lasts for a period of time is the preset time period; VB represents the waveform of the voltage of the first sensing output terminal B, wherein the gray square wave is the ideal waveform of the voltage of the first sensing output terminal B when the Hall element does not have parasitic resistance and parasitic capacitance, and the black line is the actual waveform of the voltage of the first sensing output terminal B after the method of the present invention is adopted; VD represents the waveform of the voltage of the second sensing output terminal D, wherein the gray square wave is the ideal waveform of the voltage of the second sensing output terminal D when the Hall element does not have parasitic resistance and parasitic capacitance, and the black line is the actual waveform of the voltage of the second sensing output terminal D after the method of the present invention is adopted; VA represents the first bias input terminal The figure shows the waveform of the voltage of the first bias input terminal A, wherein the gray square wave is the ideal waveform of the voltage of the first bias input terminal A when the Hall element does not have parasitic resistance and parasitic capacitance, and the black line is the actual waveform of the voltage of the first bias input terminal A after the method of the present invention is adopted; VC represents the waveform of the voltage of the second bias input terminal C, wherein the gray square wave is the ideal waveform of the voltage of the second bias input terminal C when the Hall element does not have parasitic resistance and parasitic capacitance, and the black line is the actual waveform of the voltage of the second bias input terminal C after the method of the present invention is adopted; VSENSE represents the waveform of the Hall induced voltage of the Hall element, wherein the gray square wave is the ideal waveform of the Hall induced voltage when the Hall element does not have parasitic resistance and parasitic capacitance, and the black line is the actual waveform of the Hall induced voltage after the method of the present invention is adopted.

[0055] The method comprises:

[0056] Step S1: When the Hall current starts to rotate phase, a first preset voltage is applied to the sensing output terminal within a preset time period, so that the voltage of the sensing output terminal is quickly converted from a first current steady-state voltage to a first new steady-state voltage; wherein the first new steady-state voltage matches the first preset voltage; and

[0057] Determine a bias type for the bias input terminal, where bias types include current bias and voltage bias. When the bias type is current bias, apply a second preset voltage to the bias input terminal within the preset time period, so that the voltage at the bias input terminal rapidly transitions from the second current steady-state voltage to a second new steady-state voltage; wherein the second new steady-state voltage matches the second preset voltage. Furthermore, when the bias type is voltage bias, since the bias voltage source itself has low resistance, application of a preset voltage to the corresponding bias input terminal is not required.

[0058] In this embodiment, although the parasitic resistance R and parasitic capacitance C of the Hall element cannot be changed, when the Hall current begins to rotate its phase, a first preset voltage is applied to the sensing output terminal of the Hall element within a preset time period, so that the voltage of the sensing output terminal is rapidly converted from the first current steady-state voltage to a first new steady-state voltage, and the first new steady-state voltage matches the first preset voltage; at the same time, a second preset voltage is applied to the bias input terminal of the Hall element, so that the voltage of the bias input terminal is rapidly converted from the second current steady-state voltage to a second new steady-state voltage, and the second new steady-state voltage matches the second preset voltage. In addition, since the preset time period is relatively short within the Hall current rotation cycle, the voltage states of the sensing output terminal and the bias input terminal can be converted from the current steady state to the new steady state in a very short time. Consequently, at the end of the preset time period, the initial value of the residual error of the Hall sensing voltage is significantly reduced. Furthermore, within a period of time after the end of the preset time period, the time for the initial value of the residual error of the Hall sensing voltage to gradually converge to zero in an exponential manner is correspondingly significantly reduced. As a result, at the end of the Hall current rotation cycle, the residual error of the Hall sensing voltage is also significantly reduced. The ratio of the residual error reduction is the ratio of the Hall sensing voltage VSENSE error at the start and end time points of the preset time period, thereby preventing the residual error of the Hall sensing voltage from becoming an error in the final output of the Hall sensor. Compared to the prior art, the present invention can effectively and quickly reduce the residual error of the Hall sensing voltage, thereby improving the output accuracy of the Hall sensor, and is particularly suitable for high-frequency Hall current rotation.

[0059] In addition, it should be noted that the Hall current rotation can adopt 2 / 4 / 8 / 16 phase rotation. For ease of understanding, the present invention only takes 2-phase rotation as an example to illustrate the method of the present invention, but the method of the present invention can be extended to more phase Hall current rotation.

[0060] In some embodiments, when the Hall current begins to rotate phase, a first preset voltage is applied to the sensing output terminal within a preset time period, so that the voltage of the sensing output terminal is rapidly converted from a first current steady-state voltage to a first new steady-state voltage; wherein the first new steady-state voltage matches the first preset voltage, specifically comprising:

[0061] 5 and 6 , in step S11a, if the first current steady-state voltage of the first sensing output terminal B is the high steady-state voltage VHI and the corresponding first current steady-state voltage of the second sensing output terminal D is the low steady-state voltage VLO, then when the Hall current begins to rotate in phase, the intermediate steady-state voltage VMED is simultaneously applied to the first sensing output terminal B and the second sensing output terminal D within the preset time period, so that the voltage VB of the first sensing output terminal B is rapidly converted from the high steady-state voltage VHI to the first new steady-state voltage, and the voltage VD of the second sensing output terminal D is rapidly converted from the low steady-state voltage VLO to the first new steady-state voltage; wherein the first new steady-state voltage matches the intermediate steady-state voltage VMED.

[0062] Specifically, when the clock signal CLK is at a high level, the voltage VB of the first sensing output terminal B changes from the high steady-state voltage VHI to the intermediate steady-state voltage VMED, and simultaneously, the voltage VD of the second sensing output terminal D changes from the low steady-state voltage VLO to the intermediate steady-state voltage VMED. It can be understood that the moment the rising edge of the clock signal CLK arrives is the current steady-state, and thereafter, the clock signal CLK changes to a new steady-state after being at a high level for half a cycle. Therefore, the first current steady-state voltage of the first sensing output terminal B is the high steady-state voltage VHI, the first new steady-state voltage of the first sensing output terminal B is the intermediate steady-state voltage VMED, the first current steady-state voltage of the second sensing output terminal D is the low steady-state voltage VLO, and the first new steady-state voltage of the second sensing output terminal D is the intermediate steady-state voltage VMED.

[0063] Therefore, at this time, the first preset voltage simultaneously applied to the first sensing output terminal B and the second sensing output terminal D within the preset time period is the intermediate steady-state voltage VMED or close to the intermediate steady-state voltage VMED, so that the voltage of the first sensing output terminal B is quickly converted from the high steady-state voltage VHI to the intermediate steady-state voltage VMED, and the voltage of the second sensing output terminal D is quickly converted from the low steady-state voltage VLO to the intermediate steady-state voltage VMED.

[0064] In this embodiment, further comparison of Figure 2 and Figure 5 shows that when the Hall current starts to rotate in phase and the clock signal CLK is at a high level, the curve of the voltage VB in Figure 5 transforming from the high steady-state voltage VHI to the intermediate steady-state voltage VMED is much steeper than the curve of the voltage VB in Figure 2 transforming from the high steady-state voltage VHI to the intermediate steady-state voltage VMED. Therefore, the time for the voltage VB in Figure 5 to transform from the high steady-state voltage VHI to the intermediate steady-state voltage VMED is shorter; at the same time, the curve of the voltage VD in Figure 5 transforming from the low steady-state voltage VLO to the intermediate steady-state voltage VMED is much steeper than the curve of the voltage VD in Figure 2 transforming from the low steady-state voltage VLO to the intermediate steady-state voltage VMED. Therefore, the time for the voltage VD in Figure 5 to transform from the low steady-state voltage VLO to the intermediate steady-state voltage VMED is shorter.

[0065] In some embodiments, as shown in FIG7 , simultaneously applying the intermediate steady-state voltage VMED to the first sensing output terminal B and the second sensing output terminal D specifically includes:

[0066] Step S11a1: Using the first switch K1, short-circuit the first sensing output terminal B and the second sensing output terminal D within the preset time period.

[0067] In this embodiment, a first switch K1 is used to short-circuit the first sensing output terminal B and the second sensing output terminal D during a preset time period. This means that the first sensing output terminal B and the second sensing output terminal D are connected during the preset time period, but disconnected outside of the preset time period. In the case of simultaneously applying the intermediate steady-state voltage VMED to the first and second sensing output terminals B and D, the first and second sensing output terminals B and D can be replaced by short-circuiting them. This allows the first and second sensing output terminals B and D to be connected during the preset time period, forming a low-resistance path. This reduces the impedance of the first and second sensing output terminals B and D during the preset time period, thereby reducing the corresponding time constant. Consequently, compared to prior art techniques that do not form a low-resistance path, the present invention enables the voltages of the first and second sensing output terminals B and D to converge to a new steady-state voltage in a shorter time.

[0068] In addition, for the preset time period, its starting point is the time point when the clock signal CLK flips; the time length between the starting point and the end point of the preset time period is preferably greater than three times the first preset time constant; wherein, the first preset time constant is the product of the parasitic capacitance of the Hall element itself and the impedance of the first switch K1.

[0069] In some embodiments, when the Hall current begins to rotate phase, a first preset voltage is applied to the sensing output terminal within a preset time period, so that the voltage of the sensing output terminal is rapidly converted from a first current steady-state voltage to a first new steady-state voltage; wherein the first new steady-state voltage matches the first preset voltage, specifically comprising:

[0070] As shown in FIG8 , in step S11a′, if the first current steady-state voltage of the first sensing output terminal B is the intermediate steady-state voltage VMED, and the corresponding first current steady-state voltage of the second sensing output terminal D is the intermediate steady-state voltage VMED, then when the Hall current begins to rotate in phase, a high steady-state voltage VHI is applied to the first sensing output terminal B and a low steady-state voltage VLO is applied to the second sensing output terminal D within the preset time period, so that the voltage VB of the first sensing output terminal B is rapidly converted from the intermediate steady-state voltage VMED to the first new steady-state voltage, and the voltage VD of the second sensing output terminal D is rapidly converted from the intermediate steady-state voltage VMED to the first new steady-state voltage. The first new steady-state voltage of the first sensing output terminal B matches the high steady-state voltage VHI, and the first new steady-state voltage of the second sensing output terminal D matches the low steady-state voltage VLO.

[0071] Specifically, when the clock signal CLK is at a low level, the voltage VB of the first sensing output terminal B changes from the intermediate steady-state voltage VMED to the high steady-state voltage VHI, and simultaneously, the voltage VD of the second sensing output terminal D changes from the intermediate steady-state voltage VMED to the low steady-state voltage VLO. It can be understood that the moment the falling edge of the clock signal CLK arrives is the current steady-state, and thereafter, the clock signal CLK changes to a new steady-state after being at a low level for half a cycle. Therefore, the first current steady-state voltage of the first sensing output terminal B is the intermediate steady-state voltage VMED, and the first new steady-state voltage of the first sensing output terminal B is the high steady-state voltage VHI. The first current steady-state voltage of the second sensing output terminal D is the intermediate steady-state voltage VMED, and the first new steady-state voltage of the second sensing output terminal D is the low steady-state voltage VLO.

[0072] Therefore, in the present invention, within a preset time period, the first preset voltage applied to the first sensing output terminal B is the high steady-state voltage VHI or is close to the high steady-state voltage VHI, so that the voltage of the first sensing output terminal B is quickly converted from the intermediate steady-state voltage VMED to the high steady-state voltage VHI; at the same time, the first preset voltage applied to the second sensing output terminal D is the low steady-state voltage VLO or is close to the low steady-state voltage VLO, so that the voltage of the second sensing output terminal D is quickly converted from the intermediate steady-state voltage VMED to the low steady-state voltage VLO.

[0073] In this embodiment, by comparing Figure 2 and Figure 5, it can be found that when the Hall current starts to rotate in phase and the clock signal CLK is at a low level, the curve of the voltage VB in Figure 5 transforming from the intermediate steady-state voltage VMED to the high steady-state voltage VHI is much steeper than the curve of the voltage VB in Figure 2 transforming from the intermediate steady-state voltage VMED to the high steady-state voltage VHI. Therefore, the time for the voltage VB in Figure 5 to transform from the intermediate steady-state voltage VMED to the high steady-state voltage VHI is shorter; at the same time, the curve of the voltage VD in Figure 5 transforming from the intermediate steady-state voltage VMED to the low steady-state voltage VLO is much steeper than the curve of the voltage VD in Figure 2 transforming from the intermediate steady-state voltage VMED to the low steady-state voltage VLO. Therefore, the time for the voltage VD in Figure 5 to transform from the low steady-state voltage VLO to the intermediate steady-state voltage VMED is shorter.

[0074] In some embodiments, as shown in FIG9 , applying a high steady-state voltage VHI to the first sensing output terminal B and applying a low steady-state voltage VLO to the second sensing output terminal D during the preset time period specifically includes:

[0075] Step S11a'1: Within the preset time period, use the second switch K2 to connect the first sensing output terminal B and the second sensing output terminal D to a preset common mode voltage VCM;

[0076] The preset common mode voltage VCM is an average value of steady-state values ​​of the Hall sensing voltage Vsens+ of the first sensing output terminal B and the Hall sensing voltage Vsens− of the second sensing output terminal D within the Hall current rotation phase.

[0077] In this embodiment, a second switch K2 is used to control the connection of the first sensing output terminal B and the second sensing output terminal D to a preset common-mode voltage VCM. Specifically, during a preset time period, the preset common-mode voltage VCM is connected between the first sensing output terminal B and the second sensing output terminal D, while the second switch K2 is turned off outside of the preset time period. Connecting the two sensing output terminals to the preset common-mode voltage VCM during the preset time period is because the preset common-mode voltage VCM determines the steady-state values ​​of the Hall-sensed voltages Vsens+ and Vsens- at the two sensing output terminals. In steady-state conditions (sufficiently long after a single current cycle), the Hall-sensed voltage Vsens+ at the first Hall sensing terminal B and the Hall-sensed voltage Vsens- at the second Hall sensing terminal D are nearly equal, with only a slight voltage difference caused by the Hall effect. Their average value is equal to the average of the high steady-state voltage VHI at the first Hall sensing terminal B and the low steady-state voltage VLO at the second Hall sensing terminal D. Therefore, connecting the two sensing output terminals to the preset common-mode voltage during the preset time period allows the two sensing output terminals to converge to near their steady-state values ​​in a shorter time.

[0078] In addition, for the preset time period, its starting point is the time point when the clock signal CLK flips; the time length between the starting point and the end point of the preset time period is preferably greater than three times the second preset time constant; wherein, the second preset time constant is the product of the parasitic capacitance of the Hall element itself and the impedance of the second switch K2.

[0079] In some embodiments, determining a bias type of the bias input terminal, wherein when the bias type is current bias, applying a second preset voltage to the bias input terminal within the preset time period so that the voltage of the bias input terminal is rapidly converted from the second current steady-state voltage to a second new steady-state voltage; wherein the second new steady-state voltage matches the second preset voltage, as shown in FIG10 , specifically includes:

[0080] Step S11b: If the second current steady-state voltage of the first bias input terminal A is a high steady-state voltage VHI, and the corresponding second current steady-state voltage of the second bias input terminal C is a low steady-state voltage VLO, by simultaneously applying an intermediate steady-state voltage VMED to the first bias input terminal A and the second bias input terminal C within the preset time period, the voltage VA of the first bias input terminal A is quickly converted from the high steady-state voltage VHI to the second new steady-state voltage, and the voltage of the second bias input terminal C is quickly converted from the low steady-state voltage VLO to the second new steady-state voltage; wherein the second new steady-state voltage matches the intermediate steady-state voltage VMED.

[0081] Specifically, when the clock signal CLK is at a low level, the voltage VA of the first bias input terminal A is converted from the high steady-state voltage VHI to the intermediate steady-state voltage VMED, and at the same time, the voltage VC of the second bias input terminal C is converted from the low steady-state voltage VLO to the intermediate steady-state voltage VMED; it can be understood that the moment when the falling edge of the clock signal CLK arrives is the current steady-state, and thereafter the clock signal CLK changes to a new steady-state after passing through a low level for half a cycle; therefore, the second current steady-state voltage of the first bias input terminal A is the high steady-state voltage VHI, the second new steady-state voltage of the first bias input terminal A is the intermediate steady-state voltage VMED, the second current steady-state voltage of the second bias input terminal C is the low steady-state voltage VLO, and the second new steady-state voltage of the second bias input terminal C is the intermediate steady-state voltage VMED.

[0082] Therefore, the present invention applies the intermediate steady-state voltage VMED to the first bias input terminal A and the second bias input terminal C simultaneously within a preset time period, so that the voltage VA of the first bias input terminal A is quickly converted from the high steady-state voltage VHI to the intermediate steady-state voltage VMED, and the voltage VC of the second bias input terminal C is quickly converted from the low steady-state voltage VLO to the intermediate steady-state voltage VMED.

[0083] In this embodiment, by comparing Figure 2 and Figure 5, it can be found that when the Hall current starts to rotate in phase and the clock signal CLK is at a low level, the curve of the voltage VA in Figure 5 that is converted from the high steady-state voltage VHI to the intermediate steady-state voltage VMED is much steeper than the curve of the voltage VA in Figure 2 that is converted from the high steady-state voltage VHI to the intermediate steady-state voltage VMED. Therefore, the time for the voltage VA in Figure 5 to be converted from the high steady-state voltage VHI to the intermediate steady-state voltage VMED is shorter; at the same time, the curve of the voltage VC in Figure 5 that is converted from the low steady-state voltage VLO to the intermediate steady-state voltage VMED is much steeper than the curve of the voltage VC in Figure 2 that is converted from the low steady-state voltage VLO to the intermediate steady-state voltage VMED. Therefore, the time for the voltage VC in Figure 5 to be converted from the low steady-state voltage VLO to the intermediate steady-state voltage VMED is shorter.

[0084] In some embodiments, by simultaneously applying the intermediate steady-state voltage VMED to the first bias input terminal A and the second bias input terminal C within the preset time period, as shown in FIG11 , the method specifically includes:

[0085] Step S11b1: within a preset time period, using the third switch K3 and the first voltage source V1, connect the first bias input terminal A to the intermediate steady-state voltage VMED; and

[0086] The fourth switch K4 and the second voltage source V2 are used to connect the second bias input terminal C to the intermediate steady-state voltage VMED.

[0087] In this embodiment, the output voltages of the first voltage source V1 and the second voltage source V2 are both an intermediate steady-state voltage VMED. The first voltage source V1 is connected to the first bias input terminal A via a third switch K3, and the second voltage source V2 is connected to the second bias input terminal C via a fourth switch K4. During a preset time period, the third switch K3 and the fourth switch K4 are controlled to be conductive, so that the intermediate steady-state voltage VMED is applied to both the first bias input terminal A and the second bias input terminal C simultaneously.

[0088] In other embodiments, the bias type of the first bias input terminal A and / or the second bias input terminal C may include voltage bias. If the bias type of the first bias input terminal A is current bias and the bias type of the second bias input terminal C is voltage bias, the fourth switch K4 can be kept in the off state. If the bias type of the first bias input terminal A is voltage bias and the bias type of the second bias input terminal C is current bias, the third switch K3 can be kept in the off state. If the bias type of the first bias input terminal A is voltage bias and the bias type of the second bias input terminal C is voltage bias, the third switch K3 and the fourth switch K4 can be kept in the off state. For bias input terminals with voltage bias, when the Hall current begins to rotate phase, an external second preset voltage is not required. This is because the delay is caused by the RC product, and the voltage source of the voltage bias itself has a low resistance. Low resistance means that R is very small, resulting in a very small delay, so an external second preset voltage is not required.

[0089] In addition, for the preset time period, its starting point is the time point when the clock signal CLK flips; the time length between the starting point and the end point of the preset time period is preferably greater than three times the third preset time constant; wherein, the third preset time constant is the product of the parasitic capacitance of the Hall element itself and the impedance of the third switch K3 or the fourth switch K4.

[0090] In some embodiments, determining the bias type of the bias input terminal, where the bias type is current bias, applying a second preset voltage to the bias input terminal within the preset time period so that the voltage of the bias input terminal is rapidly converted from the second current steady-state voltage to a second new steady-state voltage; wherein the second new steady-state voltage matches the second preset voltage, as shown in FIG12 , specifically includes:

[0091] Step S11b`: If the second current steady-state voltage of the first bias input terminal A is the intermediate steady-state voltage VMED, and the corresponding second current steady-state voltage of the second bias input terminal C is the intermediate steady-state voltage VMED, by applying a high steady-state voltage VHI to the first bias input terminal A and a low steady-state voltage VLO to the second bias input terminal C within the preset time period, the voltage VA of the first bias input terminal A is quickly converted from the intermediate steady-state voltage VMED to the second new steady-state voltage, and the voltage VC of the second bias input terminal C is quickly converted from the intermediate steady-state voltage VMED to the second new steady-state voltage; wherein the second new steady-state voltage of the first bias input terminal A matches the high steady-state voltage VHI, and the second new steady-state voltage of the second bias input terminal C matches the low steady-state voltage VLO.

[0092] Specifically, when the clock signal CLK is at a high level, the voltage VA of the first bias input terminal A is converted from the intermediate steady-state voltage VMED to the high steady-state voltage VHI, and at the same time, the voltage VC of the second bias input terminal C is converted from the intermediate steady-state voltage VMED to the low steady-state voltage VLO; it can be understood that the moment the rising edge of the clock signal CLK arrives is the current steady-state, and thereafter the clock signal CLK changes to a new steady-state after passing through a high level for half a cycle; therefore, the second current steady-state voltage of the first bias input terminal A is the intermediate steady-state voltage VMED, the second new steady-state voltage of the first bias input terminal A is the high steady-state voltage VHI, the second current steady-state voltage of the second bias input terminal C is the intermediate steady-state voltage VMED, and the second new steady-state voltage of the second bias input terminal C is the low steady-state voltage VLO.

[0093] Therefore, in the present invention, the second preset voltage applied to the first bias input terminal A within a preset time period is a high steady-state voltage VHI or close to the high steady-state voltage VHI, so that the voltage VA of the first bias input terminal A is quickly converted from the intermediate steady-state voltage VMED to the high steady-state voltage VHI; at the same time, the second preset voltage applied to the second bias input terminal C is a low steady-state voltage VLO or close to the low steady-state voltage VLO, so that the voltage VC of the second bias input terminal C is quickly converted from the intermediate steady-state voltage VMED to the low steady-state voltage VLO.

[0094] In this embodiment, by continuing to compare Figure 2 and Figure 5, it can be found that when the Hall current starts to rotate in phase and the clock signal CLK is at a high level, the curve of the voltage VA in Figure 5 changing from the intermediate steady-state voltage VMED to the high steady-state voltage VHI is much steeper than the curve of the voltage VA in Figure 2 changing from the intermediate steady-state voltage VMED to the high steady-state voltage VHI. Therefore, the time for the voltage VA in Figure 5 to change from the intermediate steady-state voltage VMED to the high steady-state voltage VHI is shorter; at the same time, the curve of the voltage VC in Figure 5 changing from the intermediate steady-state voltage VMED to the low steady-state voltage VLO is much steeper than the curve of the voltage VC in Figure 2 changing from the intermediate steady-state voltage VMED to the low steady-state voltage VLO. Therefore, the time for the voltage VC in Figure 5 to change from the low steady-state voltage VLO to the intermediate steady-state voltage VMED is shorter.

[0095] In some embodiments, during the preset time period, a high steady-state voltage VHI is applied to the first bias input terminal A, and a low steady-state voltage VLO is applied to the second bias input terminal C, as shown in FIG13 , specifically including:

[0096] Step S11b'1: within a preset time period, using the fifth switch K5 and the third voltage source V3, connect the first bias input terminal A to the high steady-state voltage VHI; and

[0097] The sixth switch K6 and the fourth voltage source V4 are used to connect the second bias input terminal C to the low steady-state voltage VLO.

[0098] In this embodiment, the voltage output by the third voltage source V3 is a high steady-state voltage VHI, and the voltage output by the fourth voltage source V4 is a low steady-state voltage VLO. The third voltage source V3 is connected to the first bias input terminal A via a fifth switch K5, and the fourth voltage source V4 is connected to the second bias input terminal C via a sixth switch K6. During a preset time period, the fifth switch K5 and the sixth switch K6 are controlled to be conductive, thereby connecting the first bias input terminal A to the high steady-state voltage VHI and connecting the second bias input terminal C to the low steady-state voltage VLO.

[0099] In other embodiments, if the bias type of the first bias input terminal A is current bias and the bias type of the second bias input terminal C is voltage bias, the sixth switch K6 may be kept in an off state. If the bias type of the first bias input terminal A is voltage bias and the bias type of the second bias input terminal C is current bias, the fifth switch K5 may be kept in an off state. If the bias type of the first bias input terminal A is voltage bias and the bias type of the second bias input terminal C is voltage bias, the fifth switch K5 and the sixth switch K6 may be kept in an off state. For bias input terminals with voltage bias, when the Hall current begins to rotate phase, it is not necessary to connect an external second preset voltage. This is because the delay is caused by the RC product, and the voltage source of the voltage bias itself has a low resistance. Low resistance means that R is very small, and thus the delay is very small, so an external second preset voltage is not required.

[0100] In addition, for the preset time period, its starting point is the time point when the clock signal CLK flips; the time length between the starting point and the end point of the preset time period is preferably greater than three times the fourth preset time constant; wherein, the fourth preset time constant is the product of the parasitic capacitance of the Hall element itself and the impedance of the fifth switch K5 or the sixth switch K4.

[0101] It should be noted that, in order to maintain consistency of the preset time periods, all switches used in the present invention are switches with equal impedance.

[0102] A comprehensive comparison of Figures 2 and 5 shows that each flip of the clock signal CLK causes VA, VB, VC, and VD to change exponentially. When the preset time period SET is high, VA, VB, VC, and VD change even faster than in Figure 2. Therefore, when the Hall current rotation frequency is high, the voltage states of the sensing output terminal and the bias input terminal can transition from the current steady state to the new steady state in a very short time. Consequently, at the end of the preset time period, the initial error value of the Hall induced voltage is significantly reduced. Furthermore, for a period of time after the end of the preset time period, the time it takes for the initial error value of the Hall induced voltage to gradually converge to zero exponentially is correspondingly significantly reduced. Consequently, the residual error of the Hall induced voltage is also significantly reduced at the end of the Hall current rotation cycle, thereby preventing the residual error of the Hall induced voltage from becoming an error in the final output of the Hall sensor. Compared to the prior art, the present invention can effectively and rapidly reduce the residual error of the Hall induced voltage, thereby improving the output accuracy of the Hall sensor and is particularly suitable for high-frequency Hall current rotation.

[0103] Based on the above method for reducing the residual error generated when the Hall current rotates, the present invention also provides a circuit for reducing the residual error generated when the Hall current rotates.

[0104] As shown in FIG14 , a circuit 1 for reducing residual error generated when Hall current rotates is applied to a Hall element 2, wherein the Hall element 2 includes a bias input terminal 3 and a sensing output terminal 4. The circuit 1 includes:

[0105] a first preset voltage circuit 5 connected to the sensing output terminal 4 and configured to apply a first preset voltage to the sensing output terminal 4 within a preset time period when the Hall current begins to rotate phase, so as to quickly convert the voltage of the sensing output terminal 4 from a first current steady-state voltage to a first new steady-state voltage; wherein the first new steady-state voltage matches the first preset voltage;

[0106] The second preset voltage circuit 6 is connected to the bias input terminal 3 and is used to apply a second preset voltage to the bias input terminal 3 when the bias type of the bias input terminal 3 is current bias and within the preset time period, so that the voltage of the bias input terminal 3 is quickly converted from the second current steady-state voltage to a second new steady-state voltage; wherein the second new steady-state voltage matches the second preset voltage.

[0107] In this embodiment, a first preset voltage circuit 5 is provided, and is used to apply a first preset voltage to the sensing output terminal 4 of the Hall element 2 within a preset time period, so that the voltage of the sensing output terminal 4 is quickly converted from the first current steady-state voltage to a first new steady-state voltage, and the first new steady-state voltage matches the first preset voltage; at the same time, a second preset voltage circuit 6 is provided, and is used to apply a second preset voltage to the bias input terminal 3 of the Hall element 2, so that the voltage of the bias input terminal 3 is quickly converted from the second current steady-state voltage to a second new steady-state voltage, and the second new steady-state voltage matches the second preset voltage. In addition, since the preset time period is relatively short within the Hall current rotation cycle, the voltage states of the sensing output terminal 4 and the bias input terminal 3 can be converted from the current steady state to the new steady state in a very short time. Consequently, at the end of the preset time period, the initial value of the error of the Hall sensing voltage is significantly reduced. Furthermore, within a period of time after the end of the preset time period, the time for the initial value of the error of the Hall sensing voltage to gradually converge to zero in an exponential manner is correspondingly significantly reduced. As a result, at the end of the Hall current rotation cycle, the residual error of the Hall sensing voltage is also significantly reduced. The ratio of the residual error reduction is the ratio of the Hall sensing voltage VSENSE error at the start and end time points of the preset time period, thereby preventing the residual error of the Hall sensing voltage from becoming the error in the final output of the Hall sensor. Compared with the prior art, the present invention can effectively and quickly reduce the residual error of the Hall sensing voltage, thereby improving the output accuracy of the Hall sensor, and is particularly suitable for high-frequency Hall current rotation.

[0108] As shown in FIG15 , in some embodiments, the bias input terminal 3 includes a first bias input terminal A and a second bias input terminal C. The sensing output terminal 4 includes a first sensing output terminal B and a second sensing output terminal D.

[0109] The first preset voltage circuit 5 includes a first switch K1 connected between the first sensing output terminal B and the second sensing output terminal D, and configured to control the first sensing output terminal B and the second sensing output terminal D to be short-circuited within a preset time period.

[0110] In some embodiments, the first preset voltage circuit 5 includes a second switch K2, one end of which is connected to the first sensing output terminal B and the second sensing output terminal D, and the other end of which is connected to a preset common-mode voltage VCM, for controlling the first sensing output terminal B and the second sensing output terminal D to be connected to the preset common-mode voltage VCM during the preset time period.

[0111] In some embodiments, the second preset voltage circuit 6 includes a third switch K3 and a first voltage source V1. The first voltage source V1 is connected to the first bias input terminal A through the third switch K3, and is used to control the first bias input terminal A to access the intermediate steady-state voltage VMED.

[0112] In some embodiments, the second preset voltage circuit 6 includes a fourth switch K4 and a second voltage source V2. The second voltage source V2 is connected to the second bias input terminal C through the fourth switch K4, and is used to control the second bias input terminal C to access the intermediate steady-state voltage VMED.

[0113] In some embodiments, the second preset voltage circuit 6 includes a fifth switch K5 and a third voltage source V3. The third voltage source V3 is connected to the first bias input terminal A through the fifth switch K5, and is used to control the first bias input terminal A to access the high steady-state voltage VHI.

[0114] In some embodiments, the second preset voltage circuit 6 includes a sixth switch K6 and a fourth voltage source V4. The fourth voltage source V4 is connected to the second bias input terminal C through the sixth switch K6, and is used to control the second bias input terminal C to access the low steady-state voltage VLO.

[0115] In some embodiments, the circuit 1 further includes a preset time period setting circuit 7 connected to the first preset voltage circuit 5 and the second preset voltage circuit 6. Specifically, the preset time period setting circuit 7 is connected to the first switch K1, the second switch K2, the third switch K3, the fourth switch K4, the fifth switch K5, and the sixth switch K6, and is configured to control the first switch K1, the second switch K2, the third switch K3, the fourth switch K4, the fifth switch K5, and the sixth switch K6 to be turned on during the preset time period and turned off outside the preset time period.

[0116] The output voltages of the first voltage source V1 and the second voltage source V2 are both the intermediate steady-state voltage VMED, the voltage output by the third voltage source V3 is the high steady-state voltage VHI, and the voltage output by the fourth voltage source V4 is both the low steady-state voltage VLO.

[0117] Specifically, a circuit diagram of the preset time period setting circuit 7 is shown in FIG16 , where M1-M4 are transistors, C1 and C2 are capacitors, NOT1-NOT3 are inverters, AND1 and AND2 are AND gates, inv1 and inv2 are inverters, and OR is an OR gate. The time during which SET is continuously high is the preset time period. The SET signal generated by the preset time period setting circuit is applied to the corresponding switch. When the SET signal is high, the switch is turned on, and when the SET signal is low, the switch is turned on.

[0118] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A method for reducing the residual error generated when the Hall current rotates, which is applied to a Hall element, wherein the Hall element includes a bias input terminal and an induction output terminal, and is characterized in that, The method includes: When the Hall current starts to rotate in phase, by applying a first preset voltage to the induction output terminal within a preset time period, the voltage of the induction output terminal is rapidly converted from a first current steady-state voltage to a first new steady-state voltage; wherein, the first new steady-state voltage matches the first preset voltage; and Determine the bias type of the bias input terminal. When the bias type is current bias, by applying a second preset voltage to the bias input terminal within the preset time period, the voltage of the bias input terminal is rapidly converted from a second current steady-state voltage to a second new steady-state voltage; wherein, the second new steady-state voltage matches the second preset voltage.

2. The method for reducing the residual error generated when the Hall current rotates according to claim 1, wherein the induction output terminal comprises a first induction output terminal and a second induction output terminal; characterized in that, When the Hall current starts to rotate in phase, by applying a first preset voltage to the induction output terminal within a preset time period, the voltage of the induction output terminal is rapidly converted from a first current steady-state voltage to a first new steady-state voltage; specifically included in that the first new steady-state voltage matches the first preset voltage: If the first current steady-state voltage of the first induction output terminal is a high steady-state voltage and the first current steady-state voltage of the second induction output terminal is a low steady-state voltage, then when the Hall current starts to rotate in phase, by applying an intermediate steady-state voltage to the first induction output terminal and the second induction output terminal simultaneously within the preset time period, the voltage of the first induction output terminal is rapidly converted from the high steady-state voltage to the first new steady-state voltage, and the voltage of the second induction output terminal is rapidly converted from the low steady-state voltage to the first new steady-state voltage; wherein, the first new steady-state voltage matches the intermediate steady-state voltage.

3. The method for reducing the residual error generated when the Hall current rotates according to claim 2, wherein Specifically included in simultaneously applying the intermediate steady-state voltage to the first induction output terminal and the second induction output terminal: Using a first switch to short-circuit the first induction output terminal and the second induction output terminal within the preset time period.

4. The method for reducing the residual error generated when the Hall current rotates according to claim 1, wherein the induction output terminal includes a first induction output terminal and a second induction output terminal; characterized in that, When the Hall current starts to rotate in phase, by applying a first preset voltage to the induction output terminal within a preset time period, the voltage of the induction output terminal is rapidly converted from a first current steady-state voltage to a first new steady-state voltage; specifically included in that the first new steady-state voltage matches the first preset voltage: If the first current steady-state voltage of the first induction output terminal is the intermediate steady-state voltage, and correspondingly the first current steady-state voltage of the second induction output terminal is the intermediate steady-state voltage, when the Hall current starts to rotate the phase, by applying a high steady-state voltage to the first induction output terminal and simultaneously applying a low steady-state voltage to the second induction output terminal within the preset time period, the voltage of the first induction output terminal is rapidly converted from the intermediate steady-state voltage to the first new steady-state voltage, and the voltage of the second induction output terminal is rapidly converted from the intermediate steady-state voltage to the first new steady-state voltage; wherein, the first new steady-state voltage of the first induction output terminal matches the high steady-state voltage; the first new steady-state voltage of the second induction output terminal matches the low steady-state voltage.

5. The method for reducing residual error generated when the Hall current rotates according to claim 4, characterized in that, In applying a high steady-state voltage to the first induction output terminal and simultaneously applying a low steady-state voltage to the second induction output terminal within the preset time period, it specifically includes: Within the preset time period, use a second switch to commonly connect the first induction output terminal and the second induction output terminal to a preset common-mode voltage; Wherein, the preset common-mode voltage is the average value of the steady-state values of the Hall induction voltages of the first induction output terminal and the second induction output terminal during the rotation phase of the Hall current.

6. The method for reducing the residual error generated when the Hall current rotates according to claim 1, wherein the bias input terminal includes a first bias input terminal and a second bias input terminal; characterized in that, Determine the bias type of the bias input terminal. When the bias type is current bias, within the preset time period, apply a second preset voltage to the bias input terminal to rapidly convert the voltage of the bias input terminal from the second current steady-state voltage to the second new steady-state voltage; wherein, in that the second new steady-state voltage matches the second preset voltage, it specifically includes: If the second current steady-state voltage of the first bias input terminal is the high steady-state voltage, and correspondingly the second current steady-state voltage of the second bias input terminal is the low steady-state voltage, by applying an intermediate steady-state voltage to the first bias input terminal and the second bias input terminal simultaneously within the preset time period, the voltage of the first bias input terminal is rapidly converted from the high steady-state voltage to the second new steady-state voltage, and the voltage of the second bias input terminal is rapidly converted from the low steady-state voltage to the second new steady-state voltage; wherein, the second new steady-state voltage matches the intermediate steady-state voltage.

7. The method for reducing the residual error generated during the rotation of the Hall current according to claim 6, characterized in that, In applying an intermediate steady-state voltage to the first bias input terminal and the second bias input terminal simultaneously within the preset time period, it specifically includes: Within the preset time period, use a third switch and a first voltage source to connect the first bias input terminal to the intermediate steady-state voltage; and Use a fourth switch and a second voltage source to connect the second bias input terminal to the intermediate steady-state voltage.

8. The method for reducing the residual error generated when the Hall current rotates according to claim 1, wherein the bias input terminal includes a first bias input terminal and a second bias input terminal; characterized in that, Determine the bias type of the bias input terminal. When the bias type is current bias, apply a second preset voltage to the bias input terminal within the preset time period to rapidly convert the voltage of the bias input terminal from the second current steady-state voltage to the second new steady-state voltage. Wherein, the matching between the second new steady-state voltage and the second preset voltage specifically includes: When the second current steady-state voltage of the first bias input terminal is the intermediate steady-state voltage and the second current steady-state voltage of the second bias input terminal is the intermediate steady-state voltage, within the preset time period, apply a high steady-state voltage to the first bias input terminal and apply a low steady-state voltage to the second bias input terminal simultaneously, so that the voltage of the first bias input terminal is rapidly converted from the intermediate steady-state voltage to the second new steady-state voltage, and the voltage of the second bias input terminal is rapidly converted from the intermediate steady-state voltage to the second new steady-state voltage. Wherein, the second new steady-state voltage of the first bias input terminal matches the high steady-state voltage, and the second new steady-state voltage of the second bias input terminal matches the low steady-state voltage.

9. The method for reducing residual error generated during rotation of Hall current according to claim 8, wherein The specific implementation of applying a high steady-state voltage to the first bias input terminal and applying a low steady-state voltage to the second bias input terminal simultaneously within the preset time period includes: Within the preset time period, use the fifth switch and the third voltage source to connect the first bias input terminal to the high steady-state voltage; and Use the sixth switch and the fourth voltage source to connect the second bias input terminal to the low steady-state voltage.

10. A circuit for reducing residual errors generated when a Hall current rotates, which is applied to a Hall element, wherein the Hall element includes a bias input terminal and an induction output terminal, and is characterized in that, The circuit includes: A first preset voltage circuit, connected to the induction output terminal, is used to apply a first preset voltage to the induction output terminal when the Hall current starts to rotate the phase and within the preset time period, so that the voltage of the induction output terminal is rapidly converted from the first current steady-state voltage to the first new steady-state voltage. Wherein, the first new steady-state voltage matches the first preset voltage; A second preset voltage circuit, connected to the bias input terminal, is used to apply a second preset voltage to the bias input terminal when the bias type of the bias input terminal is current bias and within the preset time period, so that the voltage of the bias input terminal is rapidly converted from the second current steady-state voltage to the second new steady-state voltage. Wherein, the second new steady-state voltage matches the second preset voltage.

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