Digital filtering method applied to low-speed Δ-ΣADC, digital filter, and Δ-Σadc

Abstract

The present invention relates to a digital filtering method applied to a low-speed Δ-ΣADC, a digital filter and a Δ-ΣADC. The digital filtering method comprises: on the basis of a code stream signal and a clock signal, acquiring a high code stream period count value in each preset clock period; on the basis of the clock signal, acquiring a clock count value; and every time the clock count value reaches a preset clock period, latching the high code stream period count value to acquire a high code stream period count latch value and outputting same. The digital filter comprises a clock circuit, a first counter, a second counter and a latch. The Δ-ΣADC comprises a modulator and a digital filter. Compared with the existing solutions using a CIC digital extraction filter and a high-order FIR comb filter, the present invention uses two simplified counting and latching solutions in low-speed applications to achieve efficient filtering and downsampling, thereby simplifying the overall design and effectively reducing hardware costs.

Description

A digital filtering method, digital filter and Δ-Σ ADC applied to low-speed Δ-Σ ADC Technical Field

[0001] The present invention relates to the field of digital filtering, and in particular to a digital filtering method, a digital filter and a delta-sigma ADC applied to a low-speed delta-sigma ADC. Background Art

[0002] Delta-sigma (ΔΣ) ADCs are a common architecture for high-precision analog-to-digital converters (ADCs). These ADCs primarily consist of a ΔΣ modulator and a digital filter. The ΔΣ modulator converts the input analog signal into a 1-bit bit stream with a sampling frequency of fS. Its output duty cycle represents the magnitude of the input analog signal. The digital filter then filters and downsamples the 1-bit bit stream to produce an N-bit binary output. As shown in Figure 1, the ΔΣ modulator uses oversampling and noise shaping techniques to modulate the quantization noise to a higher frequency, reducing the quantization noise within the analog input signal's passband. The digital filter then removes high-frequency quantization noise outside the passband and downsamples the signal to the Nyquist frequency for output.

[0003] A commonly used digital filter structure uses a CIC (Cascaded Integrator-Comb) digital decimation filter coupled with a high-order FIR (Finite Impulse Response) comb filter. The CIC digital decimation filter primarily converts a 1-bit, high-speed, low-resolution sampled signal into an N-bit, high-resolution binary signal at the Nyquist frequency. Because the CIC digital decimation filter has large spectral sidelobes and limited attenuation of high-frequency phase noise, a high-order FIR comb filter is required to remove this high-frequency phase noise. While a high-order FIR comb filter can achieve a higher signal-to-noise ratio, the hardware is expensive and occupies a large area, increasing the overall area and cost of the delta-sigma ADC.

[0004] However, for some low-speed Δ-Σ ADC applications, such as temperature sensors, the input analog signal changes very slowly and the ADC bandwidth requirement is very low. If the above-mentioned existing digital filtering solution is used, its structure is relatively complex and the cost is too high. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to address the deficiencies of the existing technology and provide a digital filtering method, a digital filter and a Δ-Σ ADC for low-speed Δ-Σ ADC. Through two simplified counting and latching schemes, filtering and downsampling in low-speed applications are realized, which simplifies the overall design and effectively reduces hardware costs.

[0006] The present invention solves the above-mentioned technical problem with the following technical solution: providing a digital filter for low-speed delta-sigma ADC, comprising:

[0007] a clock circuit for generating a clock signal;

[0008] a first counter connected to the modulator for generating a code stream signal and the clock circuit, and configured to obtain a high code stream period count value in each preset clock period according to the code stream signal and the clock signal;

[0009] a second counter, connected to the clock circuit, and configured to obtain a clock count value according to the clock signal;

[0010] a latch connected to the first counter and the second counter, respectively, the latch being configured to latch the high code stream period count value each time the clock count value reaches the preset clock period, so as to obtain and output a high code stream period count latch value;

[0011] A bitwise AND operator is connected between the second counter and the latch, and is connected to the first counter, and is used to generate a latch signal and output it to the latch every time the clock count value reaches the preset clock cycle, and is used to generate a clear signal and output it to the first counter after the latch completes latching.

[0012] On the basis of the above technical solution, the present invention can also be improved as follows.

[0013] Furthermore, the first counter includes:

[0014] a first NOT gate and a second NOT gate, wherein the input end of the first NOT gate is connected to the clock circuit, and the output end of the first NOT gate is connected to the input end of the second NOT gate;

[0015] a first D flip-flop, wherein a data input terminal of the first D flip-flop is connected to the modulator for generating a code stream signal, and a clock input terminal of the first D flip-flop is connected to the output terminal of the first NOT gate;

[0016] an AND gate, wherein one input terminal of the AND gate is connected to the main output terminal of the first D flip-flop, and the other input terminal of the AND gate is connected to the output terminal of the second NOT gate;

[0017] N-bit cascaded second D flip-flops, wherein the clock input of the first-stage second D flip-flop is connected to the output of the AND gate, the data inputs of each stage of the second D flip-flop are correspondingly connected to the complement outputs of the second D flip-flops of each stage, and the main output of the upper-stage second D flip-flop is connected to the clock input of the lower-stage second D flip-flop; each stage of the second D flip-flop further includes a clear input;

[0018] a third NOT gate, wherein an input end of the third NOT gate is connected to the bitwise AND operator to receive the clear signal, and an output end of the third NOT gate is respectively connected to the clear input end of each stage of the second D flip-flop;

[0019] Where N is equal to the number of bits of the delta-sigma ADC.

[0020] Based on the above-mentioned digital filter applied to a low-speed delta-sigma ADC, the present invention further provides a delta-sigma ADC, comprising:

[0021] A modulator, configured to output a code stream signal according to an input analog signal; and

[0022] The digital filter as described above is connected to the modulator.

[0023] Based on the above-mentioned digital filter applied to low-speed Δ-Σ ADC, the present invention also provides a digital filtering method applied to low-speed Δ-Σ ADC, which includes:

[0024] According to the code stream signal and the clock signal, a high code stream cycle count value is obtained in each preset clock cycle;

[0025] Obtaining a clock count value according to the clock signal;

[0026] Every time the clock count value reaches the preset clock cycle, the high code stream cycle count value is latched to obtain and output a high code stream cycle count latch value.

[0027] On the basis of the above technical solution, the present invention can also be improved as follows.

[0028] Furthermore, according to the bit stream signal and the clock signal, obtaining a high bit stream period count value in each preset clock cycle specifically includes:

[0029] Obtaining the preset clock period according to the clock signal;

[0030] In each of the preset clock cycles, the high code stream period count value is obtained according to the code stream signal at a high level.

[0031] Further, obtaining a clock count value according to the clock signal specifically includes:

[0032] Obtaining a clock cycle according to the clock signal;

[0033] After each clock cycle, the clock count value obtained is the previous clock count value plus 1.

[0034] Furthermore, when the clock count value reaches the preset clock cycle, the high code stream cycle count value is latched to obtain the high code stream cycle count latch value and output it, the method further includes:

[0035] The latched high code stream period count value is cleared.

[0036] Furthermore, when the clock count value reaches the preset clock cycle, the high code stream cycle count value is latched to obtain and output a high code stream cycle count latch value, which specifically includes:

[0037] By performing a bitwise AND operation, it is determined that the clock count value has fully counted the preset clock cycle.

[0038] generating a latch signal according to the clock count value having counted up to the preset clock period;

[0039] According to the latch signal, the high code stream period count value is latched to obtain and output a high code stream period count latch value.

[0040] Further, when the number of bits of the Δ-Σ ADC is N, the preset clock period is 2 to the Nth power, and the high code stream period count latch value is used as the final output; or

[0041] When the number of bits of the Δ-Σ ADC is N, the preset clock period is 2 to the Mth power, and M>N, then the upper N bits of the high code stream cycle count latch value are intercepted as the final output.

[0042] The present invention has the following beneficial effects: by obtaining a high-bitrate cycle count value and a clock count value within each preset clock cycle, and further latching the high-bitrate cycle count value each time the clock count reaches the preset clock cycle, the present invention obtains and outputs a latched high-bitrate cycle count value. Compared to existing solutions that use a CIC digital decimation filter plus a high-order FIR comb filter, the present invention achieves filtering and downsampling in low-speed applications through two simplified counting and latching schemes, simplifying the overall design and effectively reducing hardware costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] FIG1 is a schematic structural diagram of a Δ-Σ ADC in the prior art;

[0044] FIG2 is a step diagram of a digital filtering method applied to a low-speed Δ-Σ ADC according to an embodiment of the present invention;

[0045] FIG3 is a specific diagram of step S1 in the digital filtering method applied to a low-speed Δ-Σ ADC according to an embodiment of FIG2 ;

[0046] FIG4 is a specific diagram of step S2 in the digital filtering method applied to a low-speed Δ-Σ ADC according to an embodiment of FIG2 ;

[0047] FIG5 is a specific diagram of step S3 in the digital filtering method applied to a low-speed Δ-Σ ADC according to an embodiment of FIG2 ;

[0048] FIG6 is a block diagram of a delta-sigma ADC according to an embodiment of the present invention;

[0049] FIG7 is a structural diagram of a digital filter and a modulator connected to a low-speed delta-sigma ADC according to an embodiment of the present invention;

[0050] FIG8 is another structural diagram of a digital filter and a modulator connected to a low-speed delta-sigma ADC according to an embodiment of the present invention;

[0051] FIG9 is a schematic structural diagram of a first counter in a digital filter applied to a low-speed Δ-Σ ADC according to an embodiment of FIG7 ;

[0052] FIG10 is a timing diagram of each node in the first counter shown in FIG9 . DETAILED DESCRIPTION

[0053] The principles and features of the present invention are described below with reference to the accompanying drawings. The examples given are only used to explain the present invention and are not used to limit the scope of the present invention.

[0054] As shown in Figure 2, a digital filtering method applied to a low-speed delta-sigma ADC includes:

[0055] Step S1: obtaining a high code stream period count value CNTD in each preset clock cycle according to the code stream signal DIN and the clock signal CLK;

[0056] Step S2: Obtain a clock count value CNTT according to the clock signal CLK;

[0057] Step S3: Whenever the clock count value CNTT reaches the preset clock cycle, the high code rate cycle count value CNTD is latched to obtain and output a high code rate cycle count latch value DOUT.

[0058] The digital filtering method of the present invention counts the high bit rate signal in the bit rate signal DIN and the clock signal CLK within each preset clock cycle, and latches the current high bit rate cycle count value CNTD every time the clock count value CNTT reaches a preset clock cycle. This allows calculation of the average duty cycle of the bit rate signal DIN within each preset clock cycle. This average duty cycle is equal to the high bit rate cycle count value divided by the preset clock cycle, and this average duty cycle represents the magnitude of the input analog signal. The bit rate signal DIN is converted from the input analog signal through techniques such as oversampling and noise shaping, while the high bit rate cycle count latch value DOUT is a value representing the high bit rate signal count in the bit rate signal DIN. Therefore, the high bit rate cycle count latch value DOUT is the output value after digital filtering of the input analog signal. Compared to existing solutions that use a CIC digital decimation filter plus a high-order FIR comb filter, the present invention achieves filtering and downsampling of low-speed sampled signals in low-speed applications through two simplified counting and latching schemes, simplifying the overall design and effectively reducing hardware costs. In some embodiments, the above-mentioned step S1 and step S2 can be interchanged or performed simultaneously, which is not limited in the present invention.

[0059] In some embodiments, according to the bit stream signal DIN and the clock signal CLK, obtaining the high bit stream period count value CNTD in each preset clock cycle, as shown in FIG3 , specifically includes:

[0060] Step S11, obtaining the preset clock period according to the clock signal CLK;

[0061] Step S12: In each of the preset clock cycles, according to the code stream signal CNTD at a high level, obtaining the high code stream period count value CNTD.

[0062] Specifically, the bit stream signal DIN is a 1-bit signal, each bit of which contains only one binary digit, meaning that each bit of the bit stream is either "0" or "1." When the bit stream in the bit stream signal DIN is "0," representing a low bit stream, the bit stream signal DIN is at a low level. When the bit stream in the bit stream signal DIN is "1," representing a high bit stream, the bit stream signal DIN is at a high level. Therefore, within the preset clock cycle 2N, each time a high bit stream arrives in the bit stream signal DIN, the high bit stream cycle count value CNTD is incremented by 1; otherwise, it remains unchanged, thereby obtaining the high bit stream cycle count value CNTD. Furthermore, the high bit stream cycle count can employ a binary cyclic counting method, which is simple, easy to implement, and inexpensive.

[0063] In some embodiments, obtaining a clock count value CNTT according to the clock signal CLK, as shown in FIG4 , specifically includes:

[0064] Step S21: Obtain a clock period according to the clock signal CLK;

[0065] Step S22: After each clock cycle, the clock count value CNTT obtained is the previous clock count value plus 1.

[0066] In this embodiment, the clock signal CLK is counted continuously, and each time a clock cycle comes, the clock count value CNTT is increased by 1. In addition, the clock count can also adopt a binary cycle counting method, which is simple and easy to implement, and has low implementation cost.

[0067] As shown in FIG2 , in some embodiments, after latching the high bit rate cycle count value CNTD to obtain and output the high bit rate cycle count latch value DOUT each time the clock count value CNTT reaches the preset clock cycle, the method further includes:

[0068] Step S4: clear the latched high code rate period count value CNTD.

[0069] Among them, when the clock count value CNTT counts to a full preset clock cycle, the latched high code stream cycle count value CNTD will be cleared, so that at the beginning of the next preset clock cycle, the high code stream cycle count value CNTD will start counting from zero, and the high code stream cycle count value CNTD within the preset clock cycle can be intuitively obtained.

[0070] In some embodiments, when the clock count value CNTT reaches the preset clock cycle, the high bit rate cycle count value CNTD is latched to obtain the high bit rate cycle count latch value and output it, as shown in FIG5 , specifically including:

[0071] Step S31: Determine, through a bitwise AND operation, whether the clock count value CNTT has counted to the full preset clock period;

[0072] Step S32: generating a latch signal according to the clock count value having counted up to the preset clock period;

[0073] Step S33: latch the high code rate cycle count value CNTT according to the latch signal to obtain a high code rate cycle count latch value DOUT and output it.

[0074] In this embodiment, the bitwise AND operation is a process of counting the clock count value CNTT based on a preset clock cycle. Assuming that the clock count value CNTT starts from zero, the operation outputs a level signal. If the output level signal is a high level signal, it means that the preset clock cycle has been counted. The high level signal at this time is the latch signal, which triggers the latching of the current high code rate cycle count value CNTT to obtain the high code rate cycle count latch value DOUT and output it.

[0075] In some embodiments, when the number of bits of the Δ-Σ ADC is N, the preset clock period is 2 to the Nth power, and the high code stream period count latch value DOUT is used as the final output.

[0076] Specifically, when the number of bits of the Δ-Σ ADC is N and the preset clock period is 2 to the power of N, the number of bits of the high code rate cycle count latch value DOUT is N, which is exactly equal to the number of bits of the Δ-Σ ADC. At this time, all bits [N-1:0] of the high code rate cycle count latch value DOUT can be used as the final output.

[0077] In some embodiments, when the number of bits of the Δ-Σ ADC is N, the preset clock period is 2 to the Mth power, and M>N, the upper N bits of the high code stream period count latch value DOUT are intercepted as the final output.

[0078] Specifically, when the number of bits of the Δ-Σ ADC is N and the preset clock period is 2 to the Mth power, M>N can be set. That is, the duty cycle of the code stream signal DIN within 2M periods is calculated, and the number of bits of the high code stream cycle count latch value DOUT is M bits. At this time, if the Δ-Σ ADC wants to output N bits, the high N bits [M-1:MN] can be intercepted from all bits [M-1:0] of the high code stream cycle count latch value DOUT as the final output.

[0079] As shown in FIG6 , the present invention further provides a delta-sigma ADC comprising a modulator 200 and a digital filter 100 . The modulator 200 is configured to output a bit stream signal DIN based on an input analog signal. The digital filter 100 is connected to the modulator 200 and configured to filter and downsample the bit stream signal DIN.

[0080] Specifically, modulator 200 is a delta-sigma modulator, which converts an input analog signal into a 1-bit bit stream signal DIN with a sampling frequency of fS. Its output duty cycle represents the magnitude of the input analog signal. Through techniques such as oversampling and noise shaping, the delta-sigma modulator modulates the quantization noise to a higher frequency, reducing the quantization noise within the passband of the input analog signal. Digital filter 100 uses a clock signal CLK, which is the same frequency as the sampling frequency of modulator 200, and filters and downsamples the 1-bit bit stream signal DIN using two simple N-bit binary cyclic counters, producing an N-bit binary output that filters out high-frequency quantization noise outside the signal passband and downsamples it to the Nyquist frequency. Because digital filter 100 is implemented using two simple N-bit binary cyclic counters, compared to existing CIC digital decimation filters plus high-order FIR comb filters, the digital filter 100 of the present invention has a simpler structure, lower hardware cost, and a smaller footprint, which in turn reduces the cost and area of ​​the delta-sigma ADC.

[0081] The present invention also provides a digital filter 100 for a low-speed delta-sigma ADC. Specifically, as shown in FIG7 , the digital filter 100 includes a clock circuit 1 for generating a clock signal CLK, a first counter 2, a second counter 3, and a latch 4. The first counter 2 is connected to a modulator 200 for generating a bit stream signal DIN and the clock circuit 1, and is configured to obtain a high bit stream period count value CNTD within each preset clock cycle based on the bit stream signal DIN and the clock signal CLK. The second counter 3 is connected to the clock circuit 1, and is configured to obtain a clock count value CNTT based on the clock signal CLK. The latch 4 is connected to the first counter 2 and the second counter 3, respectively, and is configured to latch the high bit stream period count value CNTD each time the clock count value CNTT reaches the preset clock cycle, thereby obtaining and outputting a high bit stream period count latch value DOUT.

[0082] In the present invention, two counters are used to count the high bit stream in the bit stream signal DIN and the clock signal CLK, respectively. When the clock count value CNTT reaches a preset clock cycle, the current high bit stream cycle count value CNTD is latched. In this way, the average duty cycle of the bit stream signal DIN within each preset clock cycle can be calculated. This average duty cycle represents the size of the input analog signal. The bit stream signal DIN is processed by the modulator 200 from the input analog signal, and the high bit stream cycle count latch value DOUT is a value for counting the high bit stream signal in the bit stream signal DIN. Therefore, the high bit stream cycle count latch value DOUT is the output value after digital filtering of the input analog signal. Compared with the existing solution of using a CIC digital extraction filter plus a high-order FIR comb filter, the present invention achieves filtering and downsampling of low-speed sampling signals through two simplified counting and latching schemes in low-speed applications, simplifying the design of the overall hardware structure and effectively reducing hardware costs.

[0083] In some embodiments, the first counter 2 and the second counter 3 are both N-bit binary cyclic counters.

[0084] As shown in Figure 8, in some embodiments, the digital filter 100 also includes a bitwise AND operator 5, which is connected between the second counter 3 and the latch 4, and is connected to the first counter 2, and is used to generate a latch signal and output it to the latch 4 every time the clock count value CNTT reaches the preset clock cycle, and is used to generate a clear signal and output it to the first counter 2 after the latch 4 completes latching.

[0085] Specifically, the bitwise AND operator 5 is an N-input AND gate. If the second counter 3 starts counting from zero, the bitwise AND operator 5 outputs a high-level signal, indicating that the preset clock cycle has been counted. The high-level signal in this case is a latch signal, which triggers the latch 4 to latch the current high code stream cycle count value CNTT to obtain and output the high code stream cycle count latch value DOUT. After the latch 4 latches the current high code stream cycle count value CNTT, the bitwise AND operator 5 also generates a clear signal and outputs it to the first counter 2 to clear the high code stream cycle count value CNTD in the first counter 2. In this way, at the beginning of the next preset clock cycle, the high code stream cycle count value CNTD restarts from zero, thereby intuitively obtaining the high code stream cycle count value CNTD within the preset clock cycle.

[0086] In some embodiments, as shown in FIG9 , the first counter 2 includes a first NOT gate N1, a second NOT gate N2, a first D flip-flop DFF1, an AND gate &, an N-bit cascaded second D flip-flop DFF2, and a third NOT gate N3. The input of the first NOT gate N1 is connected to the clock circuit 1 to receive the clock signal CLK, and the output of the first NOT gate N1 is connected to the input of the second NOT gate N2.

[0087] A data input terminal D of a first D flip-flop DFF1 is connected to the modulator to receive the bit stream signal DIN. A clock input terminal of the first D flip-flop DFF1 is connected to the output terminal of the first NOT gate N1. One input terminal of an AND gate & is connected to the main output terminal Q of the first D flip-flop DFF1, and the other input terminal of the AND gate & is connected to the output terminal of the second NOT gate N2.

[0088] N-bit cascaded second D flip-flops DFF2, wherein the clock input of the first-stage second D flip-flop DFF2 is connected to the output of the AND gate &, the data input D of each stage of the second D flip-flop DFF2 is correspondingly connected to the complement output of the second D flip-flop DFF2 of each stage, and the main output Q of the upper-stage second D flip-flop DFF2 is connected to the clock input of the lower-stage second D flip-flop DFF2. Each stage of the second D flip-flop also includes a clear input. N is equal to the number of bits of the delta-sigma ADC.

[0089] The input end of the third NOT gate N3 is connected to the bitwise AND operator 5 to receive the clear signal, and the output end of the third NOT gate N3 is respectively connected to the clear input end of each stage of the second D flip-flop DFF2.

[0090] Specifically, in the first counter 2, the clock signal CLK passes through the first NOT gate N1 and inputs the first D flip-flop DFF1. Under the action of the inverted clock signal CLK, the first D flip-flop DFF1 processes the input code stream signal DIN to output a first main output signal. After passing through the first NOT gate N1 and the second NOT gate N2, the clock signal CLK returns to its original state. The AND gate & performs an AND operation on the first main output signal and the clock signal CLK after passing through the first NOT gate N1 and the second NOT gate N2 to generate a first clock signal, which in turn provides a clock signal to the first-stage second D flip-flop DFF2. In the N-bit cascaded second D flip-flops DFF2, the output of the main output terminal of the upper-stage second D flip-flop DFF2 serves as the clock signal for the lower-stage second D flip-flops DFF2. The output of the main output terminal of each stage of the second D flip-flop DFF2 corresponds to each bit of the high code stream cycle count value CNTD. When the clear signal generated by the bitwise AND operator 5 is output to the clear input terminal of the N-bit cascaded second D flip-flops DFF2, the output of the main output terminal of each stage of the second D flip-flops DFF2 is cleared.

[0091] Figure 10 is a timing diagram of the nodes in first counter 2. As can be seen from Figure 10, the first main output signal is delayed by half a clock cycle relative to the bit stream signal DIN. The first clock signal is high only when both the clock signal CLK and the first main output signal are high. The high bit stream cycle count value CNTD can be considered to be counting the first clock signal. When the first clock signal reaches a high level, the high bit stream cycle count value CNTD is incremented by 1.

[0092] The first counter 2 in the present invention is mainly composed of a NOT gate, an AND gate and a plurality of D flip-flops, and has a simple structure, reliable counting results and low cost.

[0093] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A digital filter applied to a low-speed Δ-Σ ADC, characterized in that, Comprising: A clock circuit for generating a clock signal; A first counter connected to a modulator for generating a bitstream signal and the clock circuit, and configured to obtain a high bitstream period count value within each preset clock period according to the bitstream signal and the clock signal; A second counter connected to the clock circuit, and configured to obtain a clock count value according to the clock signal; A latch respectively connected to the first counter and the second counter, and the latch is configured to latch the high bitstream period count value when the clock count value counts up to the preset clock period, so as to obtain a high bitstream period count latch value and output it; A bitwise AND operator, which is connected between the second counter and the latch, and is also connected to the first counter, and is configured to generate a latch signal and output it to the latch when the clock count value counts up to the preset clock period, and is configured to generate a clear signal and output it to the first counter after the latch completes latching.

2. The digital filter applied to a low-speed Δ-Σ ADC according to claim 1, wherein The first counter includes: A first NOT gate and a second NOT gate, the input terminal of the first NOT gate is connected to the clock circuit, and the output terminal of the first NOT gate is connected to the input terminal of the second NOT gate; A first D flip-flop, the data input terminal of the first D flip-flop is connected to a modulator for generating a bitstream signal, and the clock input terminal of the first D flip-flop is connected to the output terminal of the first NOT gate; An AND gate, one input terminal of the AND gate is connected to the master output terminal of the first D flip-flop, and the other input terminal of the AND gate is connected to the output terminal of the second NOT gate; An N-bit cascaded second D flip-flop, wherein the clock input terminal of the first-level second D flip-flop is connected to the output terminal of the AND gate, the data input terminals of each level of the second D flip-flop are correspondingly connected to the complement output terminals of each level of the second D flip-flop, and the master output terminal of the upper-level second D flip-flop is connected to the clock input terminal of the lower-level second D flip-flop; each level of the second D flip-flop also includes a clear input terminal; A third NOT gate, the input terminal of the third NOT gate is connected to the bitwise AND operator, and the output terminal of the third NOT gate is respectively connected to the clear input terminals of each level of the second D flip-flop; Wherein, N is equal to the number of bits of the Δ-Σ ADC.

3. A Δ-Σ ADC, characterized in that, Comprising: A modulator for outputting a bitstream signal according to an input analog signal; And The digital filter according to claim 1 or 2, the digital filter being connected to the modulator.

4. A digital filtering method applied to a low-speed Δ-Σ ADC, characterized in that, Applied to the digital filter according to claim 1 or 2, including: Obtaining a high bitstream period count value within each preset clock period according to the bitstream signal and the clock signal; Obtaining a clock count value according to the clock signal; When the clock count value counts up to the preset clock period, obtaining a high bitstream period count latch value and outputting it by latching the high bitstream period count value.

5. The digital filtering method applied to a low-speed Δ-Σ ADC according to claim 4, characterized in that In obtaining a high bitstream period count value within each preset clock period according to the bitstream signal and the clock signal, specifically including: Obtaining the preset clock period according to the clock signal; Within each preset clock period, obtaining the high bitstream period count value according to the bitstream signal that is at a high level.

6. The digital filtering method applied to a low-speed Δ-Σ ADC according to claim 4, wherein In obtaining a clock count value according to the clock signal, specifically including: Obtain a clock period according to the clock signal; After each of the clock periods, the obtained clock count value is the previous clock count value plus 1.

7. The digital filtering method applied to a low-speed Δ-Σ ADC according to claim 4, wherein When the clock count value is full of the preset clock period each time, after latching the high bitstream period count value to obtain a high bitstream period count latch value and outputting it, it further includes: Clearing the latched high bitstream period count value.

8. The digital filtering method applied to a low-speed Δ-Σ ADC according to claim 4, wherein, When the clock count value is full of the preset clock period each time, and latching the high bitstream period count value to obtain a high bitstream period count latch value and outputting it, specifically includes: Determine that the clock count value is full of the preset clock period through bitwise AND operation, Generate a latch signal according to the fact that the clock count value is full of the preset clock period, Latch the high bitstream period count value according to the latch signal to obtain a high bitstream period count latch value and output it.

9. The digital filtering method applied to a low-speed Δ-Σ ADC according to claim 4, characterized in that, When the number of bits of the Δ-Σ ADC is N, and the preset clock period is 2 to the Nth power, then use the high bitstream period count latch value as the final output; Or When the number of bits of the Δ-Σ ADC is N, the preset clock period is 2 to the Mth power, and M > N, then intercept the high N bits of the high bitstream period count latch value as the final output.

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