Storage chip, memory apparatus, and electronic device

Abstract

An embodiment of the present application discloses a storage chip, comprising a storage array and a detection circuit. When the detection circuit applies a second voltage to signal lines other than a first signal line among a plurality of signal lines in the storage array, the detection circuit can detect whether a first electrical signal on the first signal line meets expectations, so as to determine whether the resistance of the first signal line or charging and discharging of a capacitor on the first signal line meets expectations, thereby achieving efficient and fast determination of the electric leakage condition of the first signal line.

Description

Storage chip, storage device and electronic device

[0001] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office on January 11, 2024, with Chinese application number 202410046801.5 and application name “A memory chip, a storage device and an electronic device”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of storage technology, and in particular to a storage chip, a storage device, and an electronic device. Background Art

[0003] The memory array in a storage device typically includes multiple memory cells. Currently, memory cells, such as a one switch one resistor (1S1R) design, typically include a gate transistor and a memory element. Read and write operations on the memory cell are performed via bit lines and word lines connected to the memory cell.

[0004] Because memory arrays typically have large capacities, the number of memory cells connected to each wordline or bitline is often on the order of k (1024). Therefore, once leakage occurs in the memory array, the reliability of the memory device is significantly impacted. Therefore, a method for quickly and effectively identifying wordline or bitline leakage in a memory device is urgently needed.

[0005] Summary of the Invention

[0006] The present invention provides a memory chip that can quickly and effectively identify word line or bit line leakage in a memory device. The present invention also provides a corresponding memory device and electronic device.

[0007] In a first aspect, the present application provides a memory chip, which includes: a memory array, the memory array including multiple memory cells, the multiple memory cells are connected by multiple signal lines, and the multiple signal lines include word lines and bit lines; a detection circuit, used to: apply a first voltage to a first signal line among the multiple signal lines, apply a second voltage to signal lines other than the first signal line among the multiple signal lines, the first voltage and the second voltage are different; detect a first electrical signal on the first signal line; and determine whether the first signal line has leakage based on the value of the first electrical signal.

[0008] In the first aspect, when the detection circuit applies a second voltage to a signal line other than the first signal line among multiple signal lines of the storage array, it can detect whether the first electrical signal of the first signal line meets expectations, thereby judging whether the resistance condition on the first signal line or the charging and discharging condition of the capacitance on the first signal line meets expectations, so as to efficiently and quickly determine the leakage condition of the first signal line.

[0009] In some examples, the first voltage may be a very small voltage, that is, a voltage with an absolute value close to 0, so that a short circuit or leakage condition of the first signal line itself can be quickly detected. For example, the first voltage may be 0.3V.

[0010] In a possible implementation manner of the first aspect, the second voltage causes all signal lines except the first signal line among the plurality of signal lines to be at a zero level.

[0011] In this possible implementation, when performing leakage detection on the first signal line, it is only necessary to apply a non-zero voltage to the first signal line, and there is no need to apply a non-zero voltage to other signal lines among the multiple signal lines except the first signal line. Compared with the traditional leakage detection scheme that requires applying a non-zero voltage to at least two signal lines such as the word line and the bit line at the same time for leakage detection, the control method of this possible implementation is simpler.

[0012] In a possible implementation manner of the first aspect, the detection circuit is configured to: during a process of continuously applying the first voltage to the first signal line, detect a current of the first signal line as the first electrical signal.

[0013] In this possible implementation, the detection circuit can apply a voltage to the first signal line through a power supply or other means, so that the voltage of the first signal line can be continuously maintained at a relatively stable voltage value (i.e., the first voltage). In this case, while the first voltage is continuously applied to the first signal line, the current of the first signal line can be obtained by detecting the current of the first signal line to determine whether the resistance of the first signal line meets expectations, thereby determining whether a fault condition of the first signal line is present.

[0014] In a possible implementation of the first aspect, when the detection circuit determines whether the first signal line is leaking based on the value of the first electrical signal, it is specifically used to: compare the first electrical signal with a preset current; when the first electrical signal is greater than the preset current, it is determined that the first signal line is leaking.

[0015] In this possible implementation, at the first voltage, if the first electrical signal is greater than a preset current, it indicates that there may be a short circuit or leakage between the first signal line and other signal lines, that is, it is determined that the first signal line is leaking.

[0016] In a possible implementation manner of the first aspect, the detection circuit is configured to: after stopping applying the first voltage to the first signal line, detect the voltage of the first signal line as the first electrical signal.

[0017] In this possible implementation, by charging the capacitor on the first signal line and controlling the voltage of the first signal line to reach the first voltage, the charging of the capacitor on the first signal line can be stopped. Since the capacitor will start to discharge according to the discharge curve of the capacitor after charging, after controlling the voltage of the first signal line to reach the first voltage, the voltage of the first signal line will continue to decrease as the capacitor discharges. At this time, after stopping charging the capacitor on the first signal line and stopping applying the first voltage to the first signal line for a specified period of time, it can be determined whether the voltage of the first signal line (specifically, the first capacitor voltage of the capacitor on the first signal line) meets expectations, thereby judging whether the discharge of the capacitor meets expectations and judging the leakage of the first signal line.

[0018] In a possible implementation of the first aspect, when the detection circuit determines whether the first signal line is leaking based on the value of the first electrical signal, it is specifically used to: compare the first electrical signal with a preset voltage; when the first electrical signal is less than the preset voltage, it is determined that the first signal line is leaking.

[0019] In this possible implementation, at the first voltage, if the first electrical signal is less than the preset voltage, it indicates that the capacitor on the first signal line is discharging too quickly, indicating that there may be a short circuit or leakage between the first signal line and other signal lines, that is, it is determined that the first signal line is leaking.

[0020] In a possible implementation manner of the first aspect, a first voltage applied when the first signal line is a bit line and a first voltage applied when the first signal line is a word line are opposite voltages.

[0021] In a possible implementation of the first aspect, each storage unit includes a gate transistor; the detection circuit is further used to: apply a third voltage to the first signal line, the absolute value of the third voltage is greater than the absolute value of the first voltage; detect the current of the first signal line, and when the current of the first signal line is greater than a second preset current, it is determined that there is a gate transistor leakage in the storage unit connected to the first signal line.

[0022] In this possible implementation, the detection circuit may be configured to execute the step of applying a third voltage to the first signal line and subsequent steps after detecting multiple signal lines of the memory chip and finding that the multiple signal lines do not have leakage current. Alternatively, the step of applying a third voltage to the first signal line and subsequent steps may be executed after leakage detection is performed on a first signal line and it is determined that the first signal line does not have leakage current. In some examples, the third voltage may be applied to the first signal line after determining that the first signal line does not have leakage current based on the value of the first electrical signal, thereby successively performing leakage detection on the signal line itself and leakage detection on the selection transistor of the memory cell, thereby achieving accurate judgment of the leakage type.

[0023] In a possible implementation manner of the first aspect, a leakage detection instruction is built into the detection circuit of the memory chip, and the leakage detection instruction includes an identifier of the first signal line and a value of the first voltage.

[0024] In this possible implementation, since only a non-zero voltage needs to be applied to the first signal line, while the other signal lines remain at zero level, there is no need to carry information about other signal lines except the first signal line (such as address information and information about control parameters such as voltage). Instead, only the field for recording the address of the first signal line and the field for recording the control parameters of the voltage corresponding to the first signal line need to be recorded.

[0025] It can be seen that in this possible implementation method, the field length required for the leakage detection instruction is significantly shorter than that of the traditional leakage detection instruction, thereby reducing the transmission time and processing time of the leakage detection instruction and improving the transmission efficiency and processing efficiency of the instruction.

[0026] A second aspect of the present application provides a storage device, which includes a storage controller and a storage chip as described in the first aspect or any possible implementation of the first aspect, wherein the storage controller is used to read data from the storage chip or write data to the storage chip.

[0027] A third aspect of the present application provides an electronic device, comprising a processor and a storage device as described in the second aspect or any possible implementation of the second aspect, wherein the processor is used to read data from the storage device or write data to the storage device.

[0028] Among them, the technical effects brought about by the second to third aspects or any possible implementation methods thereof can refer to the technical effects brought about by the first aspect or the relevant possible implementation methods of the first aspect, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] FIG1a is an exemplary schematic diagram of the turn-on voltage of 1S1R when the PCM is in the high-resistance “0” state provided by an embodiment of the present application;

[0030] FIG1 b is an exemplary schematic diagram of the turn-on voltage of 1S1R when the PCM is in the low-resistance “1” state provided by an embodiment of the present application;

[0031] FIG2 is an exemplary schematic diagram of the threshold transition voltage and read voltage of 1S1R provided in an embodiment of the present application;

[0032] FIG3 is an exemplary schematic diagram of a memory chip provided in an embodiment of the present application;

[0033] FIG4 is an exemplary schematic diagram of an operation on a memory cell in a 1S1R array provided in an embodiment of the present application;

[0034] FIG5a is an exemplary schematic diagram of a memory chip provided in an embodiment of the present application;

[0035] FIG5 b is an exemplary schematic diagram of a storage device provided in an embodiment of the present application;

[0036] FIG5c is an exemplary schematic diagram of an electronic device provided in an embodiment of the present application;

[0037] FIG6 is an exemplary schematic diagram of a leakage detection method provided in an embodiment of the present application;

[0038] FIG7 a is an exemplary schematic diagram of leakage of the first signal line when the first signal line is a bit line provided by an embodiment of the present application;

[0039] FIG7 b is an exemplary schematic diagram of leakage of the first signal line when the first signal line is a word line provided by an embodiment of the present application;

[0040] FIG7 c is an exemplary schematic diagram of implementing gate transistor leakage detection for storage cells on the first signal line when there is no short circuit leakage on the first signal line according to an embodiment of the present application;

[0041] FIG8 is an exemplary schematic diagram of the first voltage and the third voltage provided in an embodiment of the present application. DETAILED DESCRIPTION

[0042] The following describes the embodiments of the present application in conjunction with the accompanying drawings. The terms used in the implementation methods of the present application are only used to explain the specific embodiments of the present application and are not intended to limit the present application.

[0043] Those skilled in the art will appreciate that, with the development of technology and the emergence of new scenarios, the technical solutions provided in the embodiments of this application are also applicable to similar technical problems.

[0044] In this application, "at least one" means one or more, and "more" means two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone, where A and B can be singular or plural. The character " / " generally indicates that the objects associated before and after are in an "or" relationship. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single or plural items. The terms "first", "second", etc. in the specification and claims of this application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the terms used in this way can be interchangeable where appropriate. This is merely a way of distinguishing objects with the same properties when describing them in the embodiments of this application. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, so that a process, method, system, product, or apparatus that comprises a list of elements is not necessarily limited to those elements but may include other elements not expressly listed or inherent to such process, method, product, or apparatus.

[0045] Before describing a memory chip, a memory device, an electronic device, etc. provided in the embodiments of the present application, some concepts involved in the embodiments of the present application are first described.

[0046] 1. Phase change memory (PCM):

[0047] PCM is a new type of non-volatile semiconductor memory based on chalcogenides. It uses phase-change materials to form storage cells. The difference in electrical properties between the crystalline and amorphous states of the phase-change material can be used to store "0" / "1" bits of information. Specifically, the high-resistance amorphous state (referred to as the high-resistance state in subsequent embodiments) is defined as the RESET ("0") state, and the low-resistance crystalline state (referred to as the low-resistance state in subsequent embodiments) is defined as the SET ("1") state.

[0048] 2. Ovonic threshold switch (OTS):

[0049] OTS is a new type of bidirectional switching transistor also based on sulfur compounds. When a read pulse in any direction (forward or reverse) and below a specific threshold voltage (Vth) is applied to the switching transistor, the response current is small, generally below the nA level, resulting in a high-resistance non-conducting state. When a pulse in any direction and above a specific threshold voltage (Vth) is applied to the switch, the response current is large, generally above 10uA, resulting in a low-resistance conducting state. The switching characteristics of OTS (the ratio of on-state current to off-state current) are similar to those of diodes. In some scenarios, the structure and manufacturing process of the two-terminal OTS are simpler than those of diodes. Therefore, OTS can be integrated with PCM memory to achieve high-density three-dimensional storage.

[0050] 3. Single gate transistor and single resistor (1S1R):

[0051] The invention includes a storage unit integrating an OTS (selector / switch) and a PCM (resistor), namely a 1S1R. In the 1S1R, the OTS and PCM are connected in series and stacked in 3D, thereby obtaining a two-dimensional or even three-dimensional storage array, thereby obtaining a storage device.

[0052] For 1S1R, when PCM is in the high-resistance "0" state, a voltage of Vth-reset (greater than the Vth required for OTS to turn on itself) needs to be applied across 1S1R to turn on 1S1R. As shown in Figure 1a, Vth-reset is equal to the threshold voltage Vth of OTS plus the threshold voltage Vth-pcm0 of the high-resistance PCM (generally higher than 1V). According to the voltage division principle of the series circuit: when Vth-reset is applied to the 1S1R device, the high-resistance PCM also withstands a certain voltage division. After deducting this voltage division, the voltage division of OTS is greater than the Vth of OTS, and the device can be turned on. When PCM is in the low-resistance "1" state, a voltage of Vth-set needs to be applied across 1S1R to turn on OTS. As shown in Figure 1b, Vth-set is equal to the threshold voltage Vth of OTS plus the threshold voltage Vth-pcm1 of the low-resistance PCM (generally close to 0V). The reason is similar: when Vth-set is applied to the 1S1R device, the low-resistance PCM also withstands a certain voltage division (this voltage division is much lower than the voltage division of the high-resistance PCM). After deducting this voltage division, the voltage division of OTS is greater than its own Vth, and the device can be turned on.

[0053] Based on these characteristics, a three-dimensional (3D) memory array integrating an OTS and PCM can store "0" / "1" bits of information, rather than distinguishing between the high-resistance and low-resistance states of the PCM. Instead, it can identify the threshold transition voltages of the memory cells containing the OTS and PCM. When the PCM is in the high-resistance state, the high threshold transition voltage is defined as "0"; when the PCM is in the low-resistance state, the low threshold transition voltage is defined as "1." The difference between the high and low threshold transition voltages is typically greater than 1V, and a read pulse can be applied within this voltage range. For a memory cell storing a "0" bit, since its threshold voltage is higher than the read voltage Vread of the read pulse, the OTS in the memory cell does not turn on, resulting in a relatively small current being detected. For a memory cell storing a "1" bit, since its threshold voltage is lower than the read voltage Vread, the OTS in the memory cell turns on, resulting in a relatively large current being detected. This method of distinguishing the read current magnitude achieves the purpose of distinguishing the storage state of a memory cell.

[0054] Figure 2 shows an exemplary diagram of the threshold transition voltage and read voltage of the 1S1R. When the PCM is in the high-resistance RESET "0" state, the 1S1R responds to a low current under the read voltage Vread (greater than Vth-set and less than Vth-reset). When the PCM is in the low-resistance SET "1" state, the 1S1R responds to a high current under the read voltage Vread. This read voltage can be used to determine the storage state of the 1S1R and, therefore, the information stored therein.

[0055] Since the Vth of OTS and the Vth-reset voltage of 1S1R are greater than 3.3V, in actual storage devices, it is generally considered to obtain the high voltage required for operation by applying positive and negative voltages simultaneously, such as applying a positive voltage through the word line and a negative voltage through the bit line.

[0056] In actual use, while the 1S1R structure brings high density, it also introduces the less reliable OTS as a selection tube. OTS leakage may cause the entire row or column of units in the storage array to fail, thus causing reliability problems.

[0057] 4. Word line (WL):

[0058] The signal line required to select a physical row in a memory array, working together with the bit line to select a memory cell. In addition to serving as an address selection, in memory arrays such as 3D PCM, the word line often serves as one end of the read / write driver. In subsequent embodiments of this application, the word line is used as the positive terminal, but this is not a limitation in actual application scenarios.

[0059] 5. Bit line (BL):

[0060] The signal line required to select a physical column in a memory array works together with the word line to select a memory cell. Like the word line, in addition to serving as an address selection, the bit line can also serve as a read / write driver in memory arrays such as 3D PCM. In subsequent embodiments of this application, the bit line is used as the negative terminal, but this is not a limitation in actual application scenarios.

[0061] 6. Bit width:

[0062] The number of storage units a storage device can read or write at a time. In computer systems, common storage devices have bit widths of 8, 16, 32, and 64 bits.

[0063] 7. Row address and column address:

[0064] Generally, a memory array consists of multiple memory cells arranged in two or even three dimensions. Each time a memory array is read or written, it typically accesses multiple memory cells, not just one, based on the bit width. These multiple memory cells share a unique address. Due to the two-dimensional nature of planar space, the row address and column address are the two components used to determine this unique address. Due to the aforementioned concept of bit width, selecting a row address may actually select multiple word lines; similarly, selecting a column address may actually select multiple bit lines.

[0065] With the advancement of semiconductor technology, memory arrays have broken through the limitations of the classic two-dimensional arrangement. For three-dimensional memory arrays, for easier processing, it is also possible to merge the addresses of the third dimension into row addresses or column addresses.

[0066] With the continuous development of technology, high-density storage devices such as 3D structures have been proposed to achieve large-capacity storage. For example, a high-density three-dimensional phase-change memory device can be constructed using a 1S1R memory cell with a crossbar structure.

[0067] In high-density storage devices, the spacing between the word lines and bit lines connecting the memory cells is typically very small, for example, at a scale of 20nm. The high density and the difficulty of etching can lead to leakage or even short circuits between adjacent word lines and bit lines due to uneven spacing control or structural collapse. Furthermore, there is a certain probability that gate transistors such as OTS will experience irreversible performance degradation during use. For example, leakage current in the subthreshold region may increase, or the device may completely become low-resistance, lose switching characteristics, and thus cause the entire word line or bit line to fail.

[0068] Because memory arrays typically have large capacities, each wordline or bitline connects to a number of memory cells on the order of k (1024). Therefore, any leakage in the memory array can significantly impact the reliability of the storage device. To reduce the raw bit error rate (RBER), quickly and effectively identifying wordline or bitline leakage, or even identifying it in advance, is crucial for improving the reliability of the entire storage device.

[0069] Currently, when performing leakage detection on a word line in a memory array, it is usually necessary to apply a voltage to the word line and to apply voltages to multiple bit lines in sequence to detect leakage on the word line; the traditional method of performing leakage detection on the bit line is similar to the traditional method of performing leakage detection on the word line mentioned above.

[0070] As can be seen, the traditional signal line leakage detection process requires multiple read and write operations, which is time-consuming and has low detection efficiency. Furthermore, this traditional leakage detection process cannot determine the type of leakage. For example, if leakage is determined on a certain bit line, it may be due to a short circuit leakage on the bit line itself, or it may be due to deterioration in the performance of the gate transistors in one or more memory cells connected to the bit line, causing leakage. However, the specific cause of the bit line leakage cannot be identified.

[0071] It can be seen that the current word line and bit line leakage detection method for a memory array cannot quickly and effectively identify the leakage of signal lines such as word lines or bit lines in a memory device.

[0072] Based on this, an embodiment of the present application provides a memory chip that can quickly and effectively identify the leakage of word lines or bit lines in a memory array. In some examples, leakage types such as gate leakage, word line leakage, and bit line leakage can be distinguished, and the degree of leakage of the gate can also be identified.

[0073] In the example shown in FIG. 3 , the memory chip 30 according to the embodiment of the present application includes a memory array 301 and a detection circuit 302 .

[0074] The memory array 301 includes a plurality of memory cells connected by a plurality of signal lines including word lines and bit lines.

[0075] The specific type of the storage array 301 is not limited herein. For example, the storage array 301 may be a 3D PCM, a dynamic random access memory (DRAM), a flash memory, a static random access memory (SRAM), or the like.

[0076] The storage array 301 may be a two-dimensional storage array, a three-dimensional storage array, or a storage array with other structures.

[0077] The plurality of memory cells in the memory array 301 are connected to a plurality of signal lines, which include word lines and bit lines.

[0078] The specific structure of the storage unit and the signal line is not limited here. For example, each storage unit may include a memory. In addition, in some examples, each storage unit may also include a gate transistor.

[0079] For example, as shown in the example of FIG4 , each storage unit may include a strobe transistor and a memory connected in series.

[0080] The specific types of the gate transistor and the memory are not limited here. Specifically, the gate transistor can be an OTS or other types of gate transistors, and the memory can be a PCM memory.

[0081] Any memory cell in the memory array 301 may be connected to a word line and a bit line to be selected through the word line and the bit line and to perform a read operation and / or a write operation.

[0082] For example, as shown in the example of FIG4 , the operation on the storage unit is described by taking the 1S1R array as an example.

[0083] In the example shown in Figure 4, a positive voltage V1 (which can be 3.5V) is generally applied to the selected wordline. Only one wordline is selected during a read or write command, while the remaining unselected wordlines are applied with a zero voltage V2. A negative voltage V3 (which can be -3V) is generally applied to the selected bitline. Only one bitline is selected during a read or write command, while the remaining unselected bitlines are applied with a zero voltage V4. Only the combined voltage difference between the positive voltage V1 and the negative voltage V3 can select and potentially activate the memory cell to be operated. For example, when the combined voltage difference between the positive voltage V1 and the negative voltage V3 is greater than Vth-reset, the OTS of the memory cell in a high-impedance state can be activated. However, other memory cells on the same bitline or wordline as the memory cell to be operated are not activated because they only receive a half-select voltage (i.e., only positive or negative voltages are applied during a read or write command). Memory cells not on the same bitline or wordline as the memory cell to be operated have no voltage applied at all and are similarly not activated.

[0084] Of course, in some other examples, the memory cell may not include a gate transistor. Alternatively, the connection relationship between the memory cell and the signal line may be different from the example shown in Figure 4. Figure 4 is only for illustrative purposes and is not limiting.

[0085] The detection circuit 302 shown in FIG. 3 may be connected to signal lines in the memory array 301 , thereby applying voltage to one or more signal lines and detecting electrical signals on the one or more signal lines, thereby performing leakage detection.

[0086] The specific structure of the detection circuit 302 can be various. For example, the detection circuit 302 can include multiple circuits, such as a word line leakage detection circuit and a bit line leakage detection circuit. Alternatively, the detection circuit 302 can be obtained by improving the read / write circuit of the memory array. The improved read / write circuit can not only apply read voltages and write voltages to the memory array, but also apply the first voltage, second voltage, and third voltage used in the leakage detection process of the embodiment of the present application, and can detect electrical signals such as current and voltage on the word lines and bit lines.

[0087] An exemplary specific structure of the memory chip 30 is described below with reference to FIG. 5 a .

[0088] FIG. 5 a is a schematic diagram showing an exemplary structure of a memory chip 30 in an embodiment of the present application.

[0089] In the example shown in FIG5 a , the memory chip 30 may include an IO circuit module, an instruction decoder, a control circuit, a word line leakage detection circuit, a row decoder, a bit line leakage detection circuit, a column decoder, a read / write circuit, and a memory array.

[0090] In the example shown in FIG5a, leakage detection of the signal lines in the memory array can be implemented through the word line leakage detection circuit and the bit line leakage detection circuit, and the memory array can be read and written through the read / write circuit. The word line leakage detection circuit and the read / write circuit can control the memory array through the row decoder, and the bit line leakage detection circuit and the read / write circuit can control the memory array through the column decoder. The control circuit can control the word line leakage detection circuit, the bit line leakage detection circuit, and the read / write circuit, etc. In addition, the memory chip 30 can exchange information with other devices through the IO circuit module, and decode the instructions (such as leakage detection instructions, etc.) received through the IO circuit module through the instruction decoder, and then control it through the control circuit.

[0091] It can be seen that in the example shown in FIG. 5 a , leakage detection of the signal line can be implemented by the word line leakage detection circuit and the bit line leakage detection circuit.

[0092] It should be noted that the example shown in FIG5a is only an exemplary structural diagram of the memory chip 30 and is not limiting. In other examples, the structure of the memory chip 30 may have other situations.

[0093] For example, in some other examples, the word line leakage detection circuit and the bit line leakage detection circuit can be integrated together. Alternatively, the word line leakage detection circuit or the bit line leakage detection circuit can be integrated or combined with other circuits, for example, they can be combined with read / write circuits to implement functions such as controlling the word lines and bit lines of the memory array and reading electrical signals.

[0094] 5b , the memory chip 30 may be connected to a memory controller 401 , both of which are included in a memory device 40 . The memory controller 401 is used to read data from the memory chip 30 or write data to the memory chip 30 .

[0095] The storage controller 401 is a device that performs necessary control on access to the storage chip 30 according to certain timing rules, including control of address signals, data signals, and various command signals, so that devices accessing the storage chip 30 (such as processors, etc.) can use the storage resources on the storage chip 30 according to their own requirements.

[0096] 5c , the storage device 40 may be connected to a processor 501, and both the storage device 40 and the processor 501 are included in the electronic device 50. The processor 501 is configured to read data from the storage device 40 or write data to the storage device 40.

[0097] The processor 501 may be a central processing unit (CPU), a microprocessor, an application specific integrated circuit (ASIC), a graphics processing unit (GPU), a digital signal processor (DSP), a field programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, or any combination thereof. The processor 501 may write data to the storage device 40 (e.g., write leakage detection instructions, etc.), and may also read data from the storage device 40 (e.g., read leakage detection results, etc.).

[0098] In this example, the processor 501 can send the leakage detection instruction to the memory chip 30 through the memory controller 401. After the memory chip 30 receives the leakage detection instruction through the IO circuit module, it can parse the leakage detection instruction through the instruction decoder, so that the word line leakage detection circuit or the bit line leakage detection circuit can be used to perform leakage detection on signal lines such as word lines or bit lines in the memory array. Then, the word line leakage detection circuit or the bit line leakage detection circuit can detect the electrical signal to determine the leakage detection status of the memory chip and return it to the processor.

[0099] In the embodiment of the present application, leakage detection of a first signal line among a plurality of signal lines can be implemented by using the detection circuit in the memory chip of any of the above embodiments.

[0100] The first signal line may be a bit line or a word line.

[0101] Specifically, as shown in FIG6 , the detection circuit is used to execute steps 601 - 603 .

[0102] In step 601 , a first voltage is applied to a first signal line among a plurality of signal lines, and a second voltage is applied to signal lines other than the first signal line among the plurality of signal lines.

[0103] The first voltage is different from the second voltage.

[0104] In the embodiment of the present application, the first voltage applied when the first signal line is a bit line and the first voltage applied when the first signal line is a word line are opposite voltages.

[0105] For example, when the first signal line is a bit line, the first voltage is a negative voltage, and when the first signal line is a word line, the first voltage is a positive voltage.

[0106] In the embodiment of the present application, there may be multiple ways to apply the first voltage to the first signal line.

[0107] For example, in some examples, the first voltage may be continuously applied to the first signal line through a power supply, etc. In this way, the voltage of the first signal line may be stably maintained at the first voltage.

[0108] In other examples, the first voltage may be applied to a first signal line among the plurality of signal lines by charging a capacitor on the first signal line.

[0109] The capacitance on the first signal line may be a parasitic capacitance of the first signal line, which is a capacitance generated due to the structure of the first signal line itself. Alternatively, in some examples, the first signal line may also be connected to a capacitor.

[0110] In this example, charging the capacitor on the first signal line may include applying a first voltage to one end of the capacitor so that the capacitor voltage reaches the first voltage, and stopping charging the capacitor after the capacitor voltage reaches the first voltage. The end of the capacitor to which the first voltage is applied may be connected to the storage unit via the first signal line.

[0111] The first voltage may be a voltage that will not cause the memory cell connected to the first signal line to be turned on when there is no fault.

[0112] The specific value of the first voltage can be determined based on a specific fault detection scenario. For example, the first voltage can be a voltage close to 0 to detect whether there is a short circuit or leakage on the first signal line.

[0113] In an embodiment of the present application, the second voltage applied to the signal lines other than the first signal line is a voltage that does not affect leakage detection of the first signal line. In some embodiments, the second voltage causes all signal lines other than the first signal line to be at zero level.

[0114] Here, making the signal lines other than the first signal line among the plurality of signal lines zero level may be grounding the signal lines other than the first signal line among the plurality of signal lines, thereby making the voltage on the signal lines other than the first signal line among the plurality of signal lines zero.

[0115] In this way, when performing leakage detection on the first signal line, it is only necessary to apply a non-zero voltage to the first signal line, and there is no need to apply a non-zero voltage to other signal lines except the first signal line among the multiple signal lines. Compared with the traditional leakage detection scheme that requires applying a non-zero voltage to at least two signal lines such as the word line and the bit line at the same time for leakage detection, the control method of the embodiment of the present application is simpler.

[0116] Step 602: Detect a first electrical signal on a first signal line.

[0117] In different scenarios, the specific form of the first electrical signal may be different.

[0118] In some examples, while the detection circuit continuously applies the first voltage to the first signal line, the detection circuit detects the current of the first signal line as the first electrical signal.

[0119] In this example, the detection circuit can apply a voltage to the first signal line through a power supply or other means, so that the voltage of the first signal line can be continuously maintained at a relatively stable voltage value (i.e., the first voltage). In this case, while the first voltage is continuously applied to the first signal line, the current of the first signal line can be obtained by detecting the current of the first signal line to determine whether the resistance of the first signal line meets expectations, thereby determining whether a fault condition of the first signal line is present.

[0120] In other examples, after stopping applying the first voltage to the first signal line, the detection circuit detects the voltage of the first signal line as the first electrical signal.

[0121] In this example, by charging the capacitor on the first signal line and controlling the voltage of the first signal line to reach the first voltage, the charging of the capacitor on the first signal line can be stopped. Since the capacitor will start to discharge according to the discharge curve of the capacitor after charging, after controlling the voltage of the first signal line to reach the first voltage, the voltage of the first signal line will continue to decrease as the capacitor discharges. At this time, after stopping charging the capacitor on the first signal line and stopping applying the first voltage to the first signal line for a specified period of time, it can be determined whether the voltage of the first signal line (specifically, the first capacitor voltage of the capacitor on the first signal line) meets expectations, thereby judging whether the discharge of the capacitor meets expectations and judging the leakage of the first signal line.

[0122] The specified time duration can be determined based on a normal discharge curve of the capacitor. For example, in the normal discharge curve of the capacitor, the capacitor voltage of the capacitor drops by 20% 5 ms after the voltage of the first signal line reaches the first voltage and charging of the capacitor stops. Then, 5 ms after the first voltage is stopped from being applied to the first signal line, the first capacitor voltage of the capacitor can be detected to determine whether it meets expectations (for example, a drop of about 20% relative to the first voltage, or a drop much greater than 20%), thereby determining the leakage condition of the first signal line.

[0123] Step 603: Determine whether the first signal line has leakage according to the value of the first electrical signal.

[0124] In an embodiment of the present application, it is possible to detect whether the first electrical signal of the first signal line meets expectations, thereby judging whether the resistance condition on the first signal line or the charging and discharging condition of the capacitor on the first signal line meets expectations, so as to efficiently and quickly determine the leakage condition of the first signal line.

[0125] In some embodiments, the leakage type on the first signal line can be identified by setting the value of the first voltage.

[0126] In this embodiment, the first voltage may be a very small voltage, that is, a voltage with an absolute value close to 0, so that the short circuit leakage of the first signal line itself can be detected quickly. For example, the first voltage may be 0.3V.

[0127] In addition, since the type of the first electrical signal may be different in different situations, the specific conditions for determining whether the first signal line has leakage according to the value of the first electrical signal may also be determined according to specific situations.

[0128] In one example, while the detection circuit continuously applies the first voltage to the first signal line, the current of the first signal line is detected as the first electrical signal.

[0129] At this time, when the detection circuit determines whether the first signal line has leakage according to the value of the first electrical signal, it is specifically used to:

[0130] The first electrical signal is compared with a preset current, and when the first electrical signal is greater than the preset current, it is determined that the first signal line is leaking.

[0131] In this example, under low voltage, if the first electrical signal is greater than the preset current, it means that there may be a short circuit or leakage between the first signal line and other signal lines, that is, it is determined that the first signal line is leaking.

[0132] In another example, after stopping applying the first voltage to the first signal line, the detection circuit detects the voltage of the first signal line as the first electrical signal.

[0133] At this time, when the detection circuit determines whether the first signal line has leakage according to the value of the first electrical signal, it is specifically used to:

[0134] The first electrical signal is compared with a preset voltage. When the first electrical signal is less than the preset voltage, it is determined that the first signal line is leaking.

[0135] In this example, the voltage of the first signal line can be a first capacitor voltage of a capacitor on the first signal line. Under low voltage conditions, if the first capacitor voltage is less than a preset voltage, it indicates that the capacitor is discharging too quickly, indicating that there may be a short circuit or leakage between the first signal line and other signal lines, which means that leakage is confirmed on the first signal line.

[0136] FIG. 7 a is a schematic diagram showing an exemplary leakage of the first signal line when the first signal line is a bit line.

[0137] Wherein, a certain bit line of the memory array is used as the first signal line. At this time, the word line in the memory array and other bit lines except the bit line are all applied with a zero level.

[0138] If, after the voltage of the bit line reaches the first voltage, it is detected that the current of the bit line is greater than the preset current or the voltage of the bit line is less than the preset voltage, it can be determined that the bit line has a short circuit leakage.

[0139] FIG. 7 b is a schematic diagram showing an exemplary leakage of the first signal line when the first signal line is a word line.

[0140] Wherein, a certain word line of the memory array is used as the first signal line. At this time, the bit lines in the memory array and other bit lines except the word line are all applied with a zero level.

[0141] If, after the voltage of the word line reaches the first voltage, it is detected that the current of the word line is greater than the preset current or the voltage of the bit line is less than the preset voltage, it can be determined that the word line has a short circuit leakage.

[0142] In some embodiments, after applying a first voltage to a first signal line among a plurality of signal lines and setting all signal lines except the first signal line to a zero level, a first electrical signal from the first signal line is detected. Based on the first electrical signal, it is determined that the first signal line itself is not leaking electricity, thereby detecting leakage in the memory cell. In many cases, the performance of the gate transistor in the memory cell is prone to deterioration, resulting in a loss of switching characteristics. Therefore, leakage in the gate transistor in the memory cell can often be detected to determine the performance of the gate transistor.

[0143] The following is an introduction to the leakage detection process of the detection unit.

[0144] Specifically, in some embodiments, each storage unit includes a gate transistor;

[0145] The detection circuit is also used to:

[0146] applying a third voltage to the first signal line, wherein an absolute value of the third voltage is greater than an absolute value of the first voltage;

[0147] The current of the first signal line is detected. When the current of the first signal line is greater than a second preset current, it is determined that a gate transistor in the storage unit connected to the first signal line has leakage.

[0148] In the embodiment of the present application, the detection circuit may execute the step of applying the third voltage to the first signal line and subsequent steps after detecting that multiple signal lines of the memory chip have no leakage current. Alternatively, the detection circuit may execute the step of applying the third voltage to the first signal line and subsequent steps after performing leakage detection on a first signal line and determining that the first signal line has no leakage current.

[0149] Furthermore, in some examples, after stopping applying the first voltage to the first signal line, the voltage of the first signal line may be detected. When the voltage of the first signal line is less than a second preset voltage, it is determined that a gate transistor in a memory cell connected to the first signal line has leakage.

[0150] FIG. 7 c is a schematic diagram illustrating an exemplary implementation of gate leakage detection for storage cells on the first signal line when there is no short circuit leakage on the first signal line.

[0151] In the example shown in FIG. 7 c , if the third voltage is applied to the first signal line and it is detected that the current of the first signal line is greater than the second preset current, it is determined that the gate transistor of the memory cell is leaking.

[0152] It can be seen that in the embodiment of the present application, after determining that the first signal line has no leakage based on the value of the first electrical signal, a third voltage can be applied to the first signal line, so that leakage detection of the signal line itself and leakage detection of the selection tube of the storage unit can be performed successively, thereby achieving accurate judgment of the leakage type.

[0153] In addition, in the embodiment of the present application, the number of the third voltage can be one or more, which is not limited here.

[0154] In some embodiments, the third voltage is multiple in number;

[0155] After determining that the first signal line has no leakage, the detection circuit is further configured to:

[0156] According to a preset order, multiple third voltages are applied to the first signal line in sequence, and each time a third voltage is applied to the first signal line, the current of the first signal line is detected until it is detected that the current of the first signal line corresponding to any third voltage is greater than the corresponding second preset current, then it is determined that there is a gate tube leakage in the storage unit connected to the first signal line, or until multiple third voltages are traversed.

[0157] In the embodiment of the present application, the second preset currents corresponding to different third voltages can be different or the same. For example, the second preset current corresponding to the smaller third voltage is smaller than the second preset current corresponding to the larger third voltage. If the voltage of the first signal line is detected to determine whether the gate transistor is leaking, the second preset voltage corresponding to the smaller third voltage is smaller than the second preset voltage corresponding to the larger third voltage.

[0158] In some examples of the embodiments of the present application, the preset order can be from small to large. This allows the voltage of the first signal line to be controlled to gradually increase, which is less difficult and generally less time-consuming. Furthermore, within the voltage range, multiple third voltages can be used to flexibly and comprehensively detect leakage in the memory cell, improving the accuracy of leakage detection and facilitating timely detection of leakage.

[0159] In some embodiments, the detection circuit is configured to:

[0160] If it is detected that the current of the first signal line corresponding to any third voltage is greater than the corresponding second preset current, the leakage degree of the gate transistor of the memory unit is determined according to the third voltage.

[0161] In the embodiment of the present application, the leakage condition of the selection tube of the storage unit can be segmentedly detected through multiple third voltages, so as to identify the performance deterioration degree of the storage unit and other devices on the first signal line, and provide important information for the life status detection of the storage unit.

[0162] For example, if leakage of the gate tube is detected when a smaller third voltage is applied to the first signal line among the multiple third voltages, the leakage of the gate tube and other devices in the storage unit is relatively serious, indicating that the performance of the storage unit has deteriorated seriously and the degree of wear is high.

[0163] In the embodiment of the present application, the specific value of the third voltage may be within a specified range.

[0164] The absolute value of the third voltage is greater than the absolute value of the first voltage. In addition, in some embodiments, the absolute value of the third voltage is not greater than the second preset voltage.

[0165] The second preset voltage may be no higher than a maximum value of an absolute value of a voltage of a word line connected to the memory cell and an absolute value of a voltage of a bit line connected to the memory cell in a write operation or a read operation on the memory cell.

[0166] In the absence of a fault in the memory array, during a write or read operation on a memory cell, the voltage of the word line connected to the memory cell and the voltage of the bit line connected to the memory cell can be considered to be a half-select voltage. Therefore, the second preset voltage may not be higher than the half-select voltage. When the voltage applied to the memory cell is only the half-select voltage, the memory cell will generally not turn on. In this case, the current of the first signal line should be less than the second preset current. If the current of the first signal line is greater than the second preset current, it is determined that there is leakage in the gate transistor of the memory cell connected to the first signal line.

[0167] 8 , the values ​​of the first voltage and one or more third voltages are exemplarily introduced below.

[0168] In the example shown in FIG8 , the storage unit is 1S1R.

[0169] At this time, a very small voltage (ie, a first voltage with an absolute value close to 0) can be applied to quickly detect the short circuit and leakage of the first signal line itself.

[0170] Exemplarily, the first voltage may be 0.3V.

[0171] Furthermore, it is understood that during normal read and write operations on a memory cell, the voltage difference between the word line and the bit line connected to the memory cell can activate the memory cell. However, if a voltage is applied only to the memory cell via the word line and a zero level is applied to the memory cell via the bit line, or if a voltage is applied only to the bit line and a zero level is applied to the memory cell via the word line, it can be considered that only a half-select voltage is applied to the memory cell.

[0172] In a normal circuit, a memory cell to which only a half-select voltage is applied will not be turned on.

[0173] During leakage detection, the second preset voltage corresponding to the memory cell can be greater than the first voltage and, if it is not faulty, will not cause the memory cell to turn on. In this case, the second preset voltage can be considered the half-select voltage. When the half-select voltage has multiple values ​​(for example, when the absolute value of the voltage applied to the word line of the memory cell is different from the absolute value of the voltage applied to the bit line of the memory cell), the second preset voltage can be considered the maximum of the absolute values ​​of the half-select voltages.

[0174] Specifically, the second preset voltage may be no higher than the maximum of the absolute value of the voltage of the word line connected to the memory cell and the absolute value of the voltage of the bit line connected to the memory cell during a write operation or a read operation on the memory cell. Furthermore, the second preset voltage is lower than the threshold voltage Vth-reset of the memory cell 1S1R when the PCM is in a high-resistance "0" state, the threshold voltage Vth-set of the memory cell 1S1R when the PCM is in a low-resistance "1" state, and the read voltage Vread of the memory cell.

[0175] At this time, the third voltage in the embodiment of the present application can be located in a voltage range that is greater than the first voltage but not greater than the second preset voltage, and one or more third voltages can be selected within the voltage range to perform leakage detection.

[0176] For example, in the example shown in Figure 8, the third voltage 1 and the third voltage 2 can be determined, so that the leakage condition of the storage unit can be segmented detected through the third voltage 1 and the third voltage 2, thereby identifying the degree of wear of devices such as the storage unit on the first signal line, providing important information for the life status detection of the storage unit.

[0177] In an embodiment of the present application, there may be multiple ways to trigger the memory chip to execute the above step 601 and subsequent steps. For example, a user may input a leakage detection instruction through a processor of an electronic device, and the leakage detection instruction may be transmitted to the memory chip through a storage controller to trigger the memory chip to execute the above step 601 and subsequent steps. Alternatively, the leakage detection instruction may be pre-configured in the memory chip, and the processor may send an instruction to the memory chip to instruct the memory chip to perform leakage detection according to the information in the pre-configured leakage detection instruction; or, the memory chip may periodically perform leakage detection according to the information in the pre-configured leakage detection instruction.

[0178] It can be seen that in some examples, before the memory chip executes the above step 601, a leakage detection instruction may be built into the detection circuit of the memory chip.

[0179] The leakage detection instruction includes an identifier of the first signal line and a value of the first voltage.

[0180] In this way, the memory chip can execute the above step 601 and subsequent steps according to the leakage detection instruction.

[0181] In the embodiment of the present application, the leakage detection instruction is used to instruct to perform leakage detection on the first signal line.

[0182] The leakage detection instruction may include multiple fields, one of which may record the identifier of the first signal line, and another field may record the value of the first voltage.

[0183] The identifier of the first signal line may be the number of the first signal line or the address of the first signal line.

[0184] The first signal line can be determined according to the field recording the identifier of the first signal line in the leakage detection instruction, and the magnitude of the voltage applied to the first signal line can be determined according to the field recording the value of the first voltage in the leakage detection instruction.

[0185] In addition, in some other examples, the leakage detection instruction may further include other fields to record one or more information such as an identifier of the leakage detection instruction and other control parameters.

[0186] One or more fields in the leakage detection instruction may be sent through one cycle or through multiple cycles.

[0187] Compared with traditional leakage detection instructions, the leakage detection instructions in the embodiments of the present application may have fewer fields, thereby enabling more efficient information transmission and processing.

[0188] Specifically, a traditional leakage detection instruction may include the following fields: leakage detection instruction identifier, column address (bit line address), row address (bit line address), bit line control parameters, word line control parameters and other information.

[0189] For example, Table 1 shows the information of the fields in a traditional leakage detection instruction.

[0190] Table 1: Information in traditional leakage detection instructions

[0191] In Table 1, the leakage detection instruction identifier is used to indicate the execution of leakage detection. Furthermore, in conventional leakage detection instructions, the voltages applied to the word lines and bit lines are not zero. Therefore, the control parameters need to include information about the voltages to be applied to the word lines and the voltages to be applied to the bit lines.

[0192] In some examples of the present application, the information of the fields of the leakage detection instruction is shown in Table 2.

[0193] Table 2: Information in an exemplary leakage detection instruction of this application

[0194] In the example shown in Table 2, the identifier of the leakage detection instruction is used to instruct to perform leakage detection. The address of the first signal line is the identifier of the first signal line.

[0195] In this example, since only a non-zero voltage needs to be applied to the first signal line, while the other signal lines remain at a zero level, compared to the example shown in Table 1, the example shown in Table 2 does not need to carry information about other signal lines except for the first signal line (such as address information and information about control parameters such as voltage). Instead, it is only necessary to record the field for recording the address of the first signal line and the field for recording the control parameters of the voltage corresponding to the first signal line. In some examples, it may also include an identifier for a leakage detection instruction.

[0196] It can be seen that in the example shown in Table 2, the field length required by the leakage detection instruction is significantly shorter than that of the traditional leakage detection instruction, thereby reducing the transmission time and processing time of the leakage detection instruction and improving the transmission efficiency and processing efficiency of the instruction.

[0197] In the embodiment of the present application, after executing step 601 according to the leakage detection instruction, the detection circuit of the memory chip needs to wait for a certain delay before obtaining the first electrical signal of the first signal line and determining the leakage condition of the first signal line.

[0198] In one example, after executing the leakage detection instruction and determining the leakage condition of the first signal line after a certain delay, feedback information is returned to the processor of the electronic device regardless of whether the leakage condition of the first signal line indicates that the first signal line is leaking or not.

[0199] In other examples, since the probability of leakage is very low, an early warning method can also be used. That is, only when the leakage detection instruction is executed and it is determined that leakage occurs in the first signal line after a certain delay, feedback information is returned to the processor to indicate that leakage occurs in the first signal line.

[0200] Those skilled in the art will clearly understand that, for the convenience and brevity of description, the specific working processes of the above-described equipment, devices, chips and units can refer to the corresponding processes in the aforementioned embodiments and will not be repeated here.

[0201] In the several embodiments provided in this application, it should be understood that the disclosed devices, apparatuses, chips, units and methods can be implemented in other ways. For example, the embodiments described above are merely illustrative. For example, the division of units is merely a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interface, device or unit, which can be electrical, mechanical or other forms.

[0202] Units described as separate components may or may not be physically separate, and components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple units. Some or all of the units may be selected to achieve the purpose of the present embodiment according to actual needs.

[0203] In addition, the functional units in the various embodiments of the present application may be integrated into a single processing unit, or each unit may exist physically separately, or two or more units may be integrated into a single unit. The aforementioned integrated units may be implemented in the form of hardware or software functional units.

[0204] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for enabling a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of each embodiment of the present application. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

Claims

1. A storage chip, the storage chip comprising: A storage array, the storage array including a plurality of storage units, the plurality of storage units being connected by a plurality of signal lines, the plurality of signal lines including word lines and bit lines; A detection circuit, configured to: Apply a first voltage to a first signal line among the plurality of signal lines, and apply a second voltage to signal lines other than the first signal line among the plurality of signal lines, the first voltage being different from the second voltage; Detect a first electrical signal on the first signal line; Judge whether the first signal line is leaking electricity according to the value of the first electrical signal.

2. The storage chip according to claim 1, characterized in that, The second voltage causes the signal lines other than the first signal line among the plurality of signal lines to all be at zero level.

3. The storage chip according to claim 1, wherein The detection circuit is configured to: During the process of continuously applying the first voltage to the first signal line, detect the current of the first signal line as the first electrical signal.

4. The storage chip according to claim 3, characterized in that, When the detection circuit judges whether the first signal line is leaking electricity according to the value of the first electrical signal, specifically: Compare the first electrical signal with a preset current, and when the first electrical signal is greater than the preset current, determine that the first signal line is leaking electricity.

5. The storage chip according to claim 1, wherein The detection circuit is configured to: After stopping applying the first voltage to the first signal line, detect the voltage of the first signal line as the first electrical signal.

6. The storage chip according to claim 5, characterized in that, When the detection circuit judges whether the first signal line is leaking electricity according to the value of the first electrical signal, specifically: Compare the first electrical signal with a preset voltage, and when the first electrical signal is less than the preset voltage, determine that the first signal line is leaking electricity.

7. The memory chip according to any one of claims 1-6, characterized in that, The first voltage applied when the first signal line is a bit line and the first voltage applied when the first signal line is a word line are opposite voltages.

8. The storage chip according to any one of claims 1 to 7, characterized in that, Each of the storage units includes a select tube; the detection circuit is further configured to: Apply a third voltage to the first signal line, the absolute value of the third voltage being greater than the absolute value of the first voltage; Detect the current of the first signal line, and when the current of the first signal line is greater than a second preset current, determine that there is a leak in the select tube of the storage unit connected to the first signal line.

9. The storage chip according to any one of claims 1 to 8, characterized in that, A leakage detection instruction is built into the detection circuit of the storage chip, and the leakage detection instruction includes an identifier of the first signal line and a value of the first voltage.

10. A storage device, characterized in that, The storage device includes a storage controller and the storage chip according to any one of claims 1 to 9, and the storage controller is configured to read data from the storage chip or write data to the storage chip.

11. An electronic device, characterized in that, The electronic device includes a processor and the storage device according to claim 10, and the processor is configured to read data from the storage device or write data to the storage device.

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