Method for accessing memory, and device

Abstract

The present application relates to the technical field of terminals, discloses a method for accessing a memory, and a device, and can solve the problem that a terminal device having a multi-processor architecture cannot realize scientific and ordered memory access. In the present application, a plurality of processors of the terminal device share a same memory, so that any processor can normally store data, modify or read the stored data, etc. in any usage scenario. Moreover, any processor among the plurality of processors can realize mutual exclusion access to the memory by the plurality of processors on the basis of the obtained situation of whether other processors are accessing the memory, thereby realizing more scientific and ordered memory sharing. The solution in which the plurality of processors of the terminal device share the same memory can also reduce the production costs of the terminal device and provide support for the miniaturization of the terminal device.

Description

Method and device for accessing memory

[0001] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office on January 10, 2024, with application number 202410042162.5 and application name “Method and Device for Accessing Memory”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of terminal technology, and in particular to a method and device for accessing a memory. Background Art

[0003] Currently, some terminal devices use multi-processor architectures for business functionality and battery life considerations. For example, some terminal devices include dual processors, such as a main processor and a coprocessor. For terminal devices with multi-processor architectures, how to manage memory access between multiple processors is a problem that needs to be solved. Summary of the Invention

[0004] The present application provides a method and device for accessing memory, which can solve the problem that terminal devices with multi-processor architecture cannot achieve scientific and orderly memory access.

[0005] To achieve the above objectives, this application adopts the following technical solutions:

[0006] In a first aspect, a method for accessing a memory is provided, which is applied to a first processor in a terminal device. In addition to the first processor, the terminal device also includes a second processor and a memory, and the first processor and the second processor share the memory. The method includes: the first processor receives a service request from an application for requesting access to the memory; the first processor obtains first information from the second processor for indicating whether the second processor is accessing the memory; and the first processor accesses the memory in response to the service request when the first information indicates that the second processor is not accessing the memory.

[0007] The solution provided by the first aspect above is that multiple processors of the terminal device (such as the first processor and the second processor) share the same memory, which can ensure that in any usage scenario, any processor can normally perform data storage, modification or reading of stored data, etc. In addition, any processor among the multiple processors (such as the first processor) can realize mutually exclusive access to the memory by multiple processors based on the acquired access conditions of other processors (such as the second processor), such as whether other processors are accessing the memory, thereby realizing more scientific and orderly sharing of the memory. Moreover, the solution of multiple processors of the terminal device (such as the first processor and the second processor) sharing the same memory can also reduce the production cost of the terminal device and provide support for the miniaturization of the terminal device.

[0008] As an example, the first information can represent whether the second processor is accessing the memory in plain text, such as direct indication or other plain text forms; or the first information can represent whether the second processor is accessing the memory in an implicit form, such as parameter representation, preset action (such as no reply) representation or other implicit forms, which are not limited in this application.

[0009] As an example, the first processor may directly obtain information from the second processor that indicates whether the second processor is accessing the memory. However, this application does not limit the first processor and the specific method and process for obtaining the information that indicates whether the second processor is accessing the memory. For example, in some examples, the first processor may also obtain the information that indicates whether the second processor is accessing the memory from a third party, such as a state storage unit.

[0010] As an example, the first processor is an application processor (AP), and the second processor is a microprogrammed control unit (MCU); alternatively, the first processor is an MCU, the second processor is an AP, and the memory is an embedded multi-media card (eMMC). Of course, the first processor or the second processor may also be a device, module, or chip with other structures or functions, which is not limited in this application.

[0011] As a possible implementation, the first processor includes a first pin, the second processor includes a second pin, the first pin is connected to the second pin, and the first processor obtains first information from the second processor, including: the first processor obtains the status of the first pin, and the status of the first pin is used to indicate whether the second processor is accessing the memory. It can be understood that since the first pin of the first processor is connected to the second pin of the second processor, the first pin can sense the status of the second pin. Based on this, the first pin can identify whether the second processor is accessing the memory through the sensed status of the second pin. This solution provides a more convenient, low-cost, low-power, and accurate implementation method for obtaining information about other processors accessing the memory.

[0012] As a possible implementation, the state of the first pin includes a first level and a second level, and the method further includes: if the state of the first pin is the first level, determining that the second processor is accessing the memory; if the state of the first pin is the second level, determining that the second processor is not accessing the memory. Based on this, a more convenient, low-cost, low-power, and accurate implementation method for obtaining information about other processors accessing the memory can be provided.

[0013] As an example, the first level is a high level, and the second level is a low level; or, the first level is a low level, and the second level is a high level, which is not specifically limited in this application.

[0014] As a possible implementation, when the state of the second pin is at the third level, the state of the first pin is at the first level; and when the state of the second pin is at the fourth level, the state of the first pin is at the second level. Based on this, the first processor can sense the state of the second pin based on the state of the first pin, and then accurately determine whether the second processor is accessing the memory, thereby conveniently and accurately obtaining the second processor's memory access status.

[0015] As an example, the third level is a high level, and the fourth level is a low level; or, the third level is a low level, and the fourth level is a high level, which is not specifically limited in this application.

[0016] As a possible implementation, the first processor further includes a third pin, the state of which indicates whether the first processor is accessing memory. This allows other processors to easily determine whether the first processor is accessing memory, thereby preventing conflicts caused by multiple processors accessing memory simultaneously and achieving more efficient and orderly memory sharing.

[0017] As a possible implementation, when the first processor is accessing the memory, the state of the third pin is at the fifth level; when the first processor is not accessing the memory, the state of the third pin is at the sixth level. Based on this, other processors can be quickly and accurately informed of whether the first processor is accessing the memory.

[0018] As an example, the fifth level is a high level, and the sixth level is a low level; or, the fifth level is a low level, and the sixth level is a high level, which is not specifically limited in this application.

[0019] As a possible implementation, the method further includes: before the first processor accesses the memory, adjusting the state of the third pin from the sixth level to the fifth level. Based on this, other processors can easily know whether the first processor is accessing the memory, thereby preventing conflicts caused by multiple processors accessing the memory simultaneously and achieving more scientific and orderly memory sharing.

[0020] As a possible implementation, the first processor adjusts the state of the third pin from the sixth level to the fifth level, including: after receiving the service request, the first processor obtains second information from the second processor that indicates whether the second processor accesses the memory; when the second information indicates that the second processor does not access the memory, the first processor adjusts the state of the third pin from the sixth level to the fifth level. Based on this, the first processor adjusts the state of the third pin when it is about to start accessing the memory to promptly notify other processors whether the first processor is accessing the memory. In addition, in order to avoid conflicts caused by the first processor and the second processor accessing the memory at the same time after the first processor determines that the state of the first pin is the second level based on the second information and then determines that the second processor does not access the memory, the first processor can again determine whether the second processor accesses the memory based on the obtained first information to ensure that the first processor does not access the memory at the same time as the second processor.

[0021] As one possible implementation, the first processor obtaining the first information from the second processor includes: when the second information indicates that the second processor is accessing a memory, waiting for a preset period of time before obtaining the first information from the second processor. This can avoid wasting power consumption and processing resources on the terminal device caused by the first processor continuously obtaining the first information from the second processor.

[0022] As one possible implementation, the memory includes: a partition corresponding to the first processor and not corresponding to the second processor, and partitions corresponding to the first processor and the second processor. The service request is used to request access to one or more of the following partitions in the memory: a partition corresponding to the first processor and not corresponding to the second processor, and a partition corresponding to the first processor and the second processor. Based on this, regardless of which memory partition the first processor accesses, data can be stored, modified, or read normally, and multiple processors can share the memory in a more scientific and orderly manner.

[0023] As an example, the memory also includes a partition corresponding to the second processor and not corresponding to the first processor. Of course, this application does not limit the specific partitions of the memory, for example, the memory may not include an exclusive partition corresponding to the first processor or the second processor.

[0024] As one possible implementation, the first processor accesses the memory to perform one or more of the following: reading data from the memory, writing data to the memory, or modifying data in the memory. Based on this, regardless of the purpose of the first processor accessing the memory, data access can be performed normally, and multiple processors can share the memory in a more scientific and orderly manner.

[0025] In a second aspect, a chip is provided, comprising a processing module and one or more pins, wherein the processing module and the one or more pins are used to support the chip to implement the method in any possible implementation manner of the first aspect.

[0026] As an example, the chip is such as an AP or an MCU.

[0027] In a third aspect, a terminal device is provided, comprising: a first processor, a second processor and a memory, wherein the first processor and the second processor share the memory, and the first processor or the second processor is used to implement the method in any possible implementation manner of the first aspect.

[0028] In a fourth aspect, a computer-readable storage medium is provided, on which computer program instructions are stored. When the computer program instructions are executed by a processor, the method in any possible implementation of the first aspect is implemented.

[0029] In a fifth aspect, a computer program product comprising instructions is provided, which, when executed on a computer, enables the computer to implement the method in any possible implementation of the first aspect.

[0030] In a sixth aspect, a chip system is provided, comprising a processing circuit and a storage medium storing computer program instructions; when the computer program instructions are executed by the processor, the method according to any possible implementation of the first aspect is implemented. The chip system may be composed of a chip alone or may include a chip and other discrete components. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] FIG1 is a schematic diagram of the structure of a terminal device including a dual-processor and dual-memory architecture;

[0032] FIG2 is a schematic diagram of the hardware structure of a terminal device provided in an embodiment of the present application;

[0033] FIG3 is a schematic diagram of the structure of a terminal device in which a main processor and a coprocessor share the same memory according to an embodiment of the present application;

[0034] FIG4 is a schematic diagram of a storage area division method of a memory provided in an embodiment of the present application;

[0035] FIG5 is a schematic diagram of a software structure of a terminal device provided in an embodiment of the present application;

[0036] FIG6 is a diagram illustrating an architecture of a memory access process provided by an embodiment of the present application;

[0037] FIG7 is a diagram illustrating another memory access process architecture provided by an embodiment of the present application;

[0038] FIG8 is an architecture diagram of an interactive process for accessing a memory provided by an embodiment of the present application;

[0039] FIG9 is a flow chart of a method for accessing a memory provided in an embodiment of the present application;

[0040] FIG10 is a flow chart of another method for accessing a memory provided in an embodiment of the present application;

[0041] FIG11 is a flow chart of a process for accessing a memory provided in an embodiment of the present application. DETAILED DESCRIPTION

[0042] The technical solutions in the embodiments of the present application will be described below in conjunction with the accompanying drawings in the embodiments of the present application. In the description of the embodiments of the present application, unless otherwise specified, " / " means or, for example, A / B can mean A or B; "and / or" in this article is merely a description of the association relationship of associated objects, indicating that three relationships can exist, for example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. In addition, in the description of the embodiments of the present application, "multiple" means two or more than two.

[0043] In the following, the terms "first," "second," and so on are used solely to distinguish different descriptive objects and do not limit the position, order, priority, quantity, or content of the described objects. For example, if the described object is a "field," the ordinal number preceding the "field" in "first field" and "second field" does not define the position or order of the "fields." "First" and "second" do not define whether the modified "fields" are in the same message, nor do they restrict the order of the "first field" and "second field." For another example, if the described object is a "level," the ordinal number preceding the "level" in "first level" and "second level" does not define the priority of the "levels." For another example, the number of described objects is not limited by the ordinal number and can be one or more. For example, in the case of "first device," the number of "devices" can be one or more. Furthermore, the objects modified by different prefixes can be the same or different. For example, if the described object is a "device," the "first device" and "second device" can be the same type or different types. For another example, if the described object is a "level," the "first level" and "second level" can be the same level or different levels. In short, the use of prefixes such as ordinal numbers to distinguish the described objects in the embodiments of the present application does not constitute a restriction on the described objects. For the statement of the described objects, please refer to the description in the context of the claims or embodiments, and no unnecessary restrictions should be constituted due to the use of such prefixes.

[0044] Furthermore, in the embodiments of the present application, "connection" may be a direct connection or an indirect connection; in addition, it may refer to an electrical connection or a communication connection; for example, the connection between two electrical components A and B may refer to a direct connection between A and B, or it may refer to an indirect connection between A and B through other electrical components or connection media, or it may refer to an indirect connection between A and B through other communication devices or communication media, as long as communication between A and B can be achieved.

[0045] As described in the background technology, for reasons of business functionality, battery life, etc., some terminal devices adopt a multi-processor architecture such as a dual-processor architecture, for example, a dual-processor architecture using a main processor and a coprocessor. As an example, a terminal device may include an application processor (AP) and a microprogrammed control unit (MCU). Among them, the AP is mainly responsible for running the operating system and multimedia applications, such as the system on chip (SOC); the MCU is sometimes also called a single-chip microcomputer, which is mainly used for signal control. Due to the low cost and low power consumption of the MCU, it can also be used for some simple calculations.

[0046] As a possible structure, the terminal device also includes a memory that provides data storage services for the AP, such as an embedded multi-media card (eMMC). Based on this, the MCU can interact with the AP to achieve the purpose of storing MCU-related data with the help of the memory configured for the AP.

[0047] With the diversification of terminal devices and the demand for low power consumption, more and more terminal devices support low-power modes (such as super power saving mode, the specific mode name is not limited). In low-power mode, some idle hardware modules can be powered off to save power. For example, in low-power mode, the terminal device's access point and its configured memory (such as eMMC) may be powered off, while the MCU operates normally. In this case, the power-off of the AP and memory will make it impossible for the MCU to store data normally or read, modify, or delete data stored in the memory normally.

[0048] In order to solve the above-mentioned problems existing in terminal devices in low-power mode, as a possible structure, the terminal device may include multiple memories configured for multiple processors respectively, such as the terminal device may adopt a dual-processor and dual-memory architecture. As shown in Figure 1, the terminal device may include eMMC1 and eMMC2 configured for AP and MCU respectively, wherein the AP and MCU can be connected to eMMC1 and eMMC2 respectively through the secure digital input and output (SDIO) interface (SDIO1 and SDIO2 as shown in Figure 1), and the AP and MCU can be connected through the serial peripheral interface (SPI) described in Figure 1 for relevant interaction. Based on this, whether in normal mode or low-power mode, the MCU can normally store data and read, modify, delete, etc. the stored data.

[0049] However, the dual-processor and dual-memory architecture in Figure 1 splits the storage space between the AP and MCU. This causes data from applications related to both the AP and MCU (such as music) to be written to both eMMC1 and eMMC2. Furthermore, dual memory is expensive and affects the hardware layout of terminal devices. Especially with the current diversification of terminal devices, these cost and layout challenges may pose a significant obstacle to the demand for lower-cost and smaller devices.

[0050] In order to solve the above-mentioned problems existing in terminal devices with dual-processor and dual-memory architectures, and to solve the problem that the MCU of terminal devices with dual-processor and single-memory structures cannot perform normal data storage and normal reading, modification, and deletion of data stored in the memory in low-power mode, an embodiment of the present application provides a solution in which multiple processors share the same memory. In this solution, the terminal device includes multiple processors, such as a main processor and a coprocessor, and the multiple processors share the same memory. Based on this, compared with the architecture in which the MCU uses the memory configured for the AP to store MCU-related data, even if the AP and the memory configured for the AP are powered off in low-power mode, the storage of MCU-related data and the normal reading, modification, and deletion of stored data can still be carried out normally.

[0051] In addition, compared with the dual processor and dual memory architecture shown in Figure 1, the solution provided by the embodiment of the present application can avoid the problem of repeated writing of data of some applications related to both AP and MCU, and can also reduce the production cost of terminal equipment and provide support for the miniaturization of terminal equipment.

[0052] In addition, in the solution provided in the embodiment of the present application, multiple processors of the terminal device can share the same memory, and any one of the multiple processors can realize mutually exclusive access to the memory by multiple processors based on the information obtained about the memory access of other processors, such as whether other processors are accessing the memory, thereby realizing more scientific and orderly memory sharing.

[0053] The terminal devices described in the embodiments of the present application may include, but are not limited to, smartphones, netbooks, tablet computers, smart drawing boards, handwriting boards, smart watches, smart bracelets, phone watches, smart glasses, smart cameras, PDAs, car computers, personal computers (PCs), personal digital assistants (PDAs), portable multimedia players (PMPs), augmented reality (AR) / virtual reality (VR) devices, smart TVs, projection devices, or somatosensory game consoles in human-computer interaction scenarios. Alternatively, the terminal devices may be terminal devices of other types or structures, which are not limited in the present application.

[0054] As an example, please refer to Figure 2, which shows a hardware structure diagram of a terminal device provided in an embodiment of the present application, including a main processor and a coprocessor, and the main processor and the coprocessor share the same memory as an example.

[0055] As shown in Figure 2, the terminal device may include a main processor, a coprocessor, a memory, an audio module, a speaker, a microphone, a display, a camera, and a sensor module. The sensor module may include an acceleration sensor, a gyroscope sensor, a magnetic sensor, a gravity sensor, a bone conduction sensor, and the like, as shown in Figure 2. In some possible configurations, the sensor module may also include a touch sensor, a pressure sensor, an air pressure sensor, a distance sensor, a proximity light sensor, a fingerprint sensor, an ambient light sensor, and other types of sensors, which are not specifically limited in the embodiments of this application.

[0056] The main processor is primarily responsible for running the operating system and multimedia applications, such as managing and maintaining application information and application-related user information, and implementing system functions (such as music playback and watch face functions). The main processor may include but is not limited to the AP. The coprocessor is mainly used for signal control and some simple calculations, such as music player-related control, watch face-related control, sensor module measurement control, and calculations related to sensor data. The coprocessor may include but is not limited to low-power processors such as MCU.

[0057] Terminal devices can implement audio functions such as music playback and recording through audio modules, speakers, microphones, and APs.

[0058] The audio module is used to convert digital audio information into analog audio signal output, and is also used to convert analog audio input into digital audio signals. The audio module can also be used to encode and decode audio signals. In some embodiments, the audio module can be provided in the main processor, or some functional modules of the audio module can be provided in the main processor.

[0059] A speaker, also known as a horn, is used to convert electrical audio signals into sound signals. The terminal device can listen to music or make hands-free calls through the speaker.

[0060] A microphone, also known as a "microphone" or "microphone," is used to convert sound signals into electrical signals. When making a call or sending a voice message, the user can put their mouth close to the microphone and speak, inputting the sound signal into the microphone. The terminal device can be equipped with at least one microphone C. In other embodiments, the terminal device can be equipped with two microphones, which can not only collect sound signals but also implement noise reduction functions. In other embodiments, the terminal device can also be equipped with three, four, or more microphones to collect sound signals, reduce noise, identify the source of sound, implement directional recording functions, etc.

[0061] An acceleration sensor (or accelerometer) can detect the magnitude of a terminal device's acceleration in all directions (generally three axes). When the terminal device is stationary, it can detect the magnitude and direction of gravity. It can also be used to identify the terminal device's posture, for applications such as pedometers. In some embodiments, the terminal device can derive the user's direction and speed of movement based on the data detected by the acceleration sensor.

[0062] The gyroscope sensor can be used to determine the motion posture of the terminal device during the motion process. In some embodiments, the rotation direction and rotation angular velocity of the terminal device around three axes (i.e., x, y and z axes) can be determined by the gyroscope sensor.

[0063] Magnetic sensors, such as Hall effect sensors, convert changes in the magnetic properties of a sensitive element caused by external factors such as magnetic fields, currents, stress and strain, temperature, and light into electrical signals, thereby detecting the corresponding physical quantity. In some embodiments, magnetic sensors can measure the angle between a terminal device and the four directions of east, south, west, and north.

[0064] The gravity sensor can be used to detect the magnitude and direction of gravity on the terminal device. In some embodiments, the terminal device can obtain information such as the user's location and altitude based on the data detected by the gravity sensor.

[0065] Bone conduction sensors can acquire vibration signals. In some embodiments, they can capture vibration signals from vibrating bones in the human body. Bone conduction sensors can also contact the human pulse to receive blood pressure signals. In some embodiments, the blood pressure signals acquired by the bone conduction sensor can be used to parse heart rate information, enabling functions such as heart rate monitoring and sleep detection.

[0066] Display screens are used to display images, videos, and more. They include display panels. Display panels can be liquid crystal displays (LCDs), organic light-emitting diodes (OLEDs), active-matrix organic light-emitting diodes (AMOLEDs), flexible light-emitting diodes (FLEDs), MiniLEDs, MicroLEDs, Micro-OLEDs, and quantum dot light-emitting diodes (QLEDs).

[0067] The memory can be used to store computer-executable program code. For example, computer programs may include operating systems and application programs. The executable program code includes instructions. The main processor or coprocessor executes the instructions stored in the memory to perform various functional applications and data processing in the terminal device.

[0068] Taking the main processor as AP and the coprocessor as MCU as an example, the memory can be used to store AP-related data and MCU-related data, AP-related data such as AP system data, AP application data for implementing different functions, etc., MCU-related data such as sensor hub system data, sensor hub application data, sensor module-related data (such as sports, health data, etc.), etc., which are not specifically limited in the embodiments of this application.

[0069] As an example, the memory may be an eMMC, or the memory may include an eMMC.

[0070] In an embodiment of the present application, the memory may include a program storage area and a data storage area. The program storage area may store an operating system, at least one application required for a function, etc. The data storage area may store data created during the use of the terminal device, etc. In addition, the memory may include a high-speed random access memory, and may also include a non-volatile memory, such as at least one disk storage device, a flash memory device, a universal flash storage (UFS), etc. The main processor or the coprocessor executes various functional applications and data processing of the terminal device by running the instructions stored in the memory.

[0071] It is understood that the structure illustrated in FIG2 of the present application does not constitute a specific limitation on the terminal device. In other embodiments of the present application, the terminal device may include more or fewer components than shown. For example, the terminal device may also include a modem processor, a graphics processing unit (GPU), an image signal processor (ISP), a flight controller, a video codec, a digital signal processor (DSP), a baseband processor, a neural network processing unit (NPU), and other one or more processing units, wherein different processing units may be independent devices or integrated into one or more processors. For another example, the terminal device may also include a charging management module, a power management module, a battery, an antenna, a mobile communication module, a wireless communication module, buttons, indicators, and other one or more devices.

[0072] Alternatively, the terminal device may combine certain components, or separate certain components, or arrange the components in different ways. The components shown in FIG2 may be implemented in hardware, software, or a combination of software and hardware.

[0073] As an example, please refer to Figure 3, which shows a schematic diagram of the structure of a terminal device provided by an embodiment of the present application, including a main processor and a coprocessor, and the main processor and the coprocessor share the same memory as an example. In Figure 3, the main processor is such as an AP, the coprocessor is such as an MCU, and the memory shared by the main processor and the coprocessor is such as an eMMC.

[0074] In some embodiments, the memory may include multiple partitions, and the multiple partitions may include partitions exclusively occupied by the main processor and the coprocessor, such as the first partition (i.e., the main processor exclusive partition) and the second partition (i.e., the coprocessor exclusive partition) as shown in FIG3 . In the embodiment of the present application, an exclusive partition refers to providing data access services for a specific processor, including providing data storage services, data reading services, etc., but cannot provide data access services for other processors. That is to say, the first partition of the memory shown in FIG3 is used to store data from the main processor and can support the main processor to read the data stored in the first partition. The first partition cannot store data from the coprocessor and cannot support the coprocessor to read the data stored in the first partition. Similarly, the second partition of the memory shown in FIG3 is used to store data from the coprocessor and can support the coprocessor to read the data stored in the second partition. The second partition cannot store data from the main processor and cannot support the main processor to read the data stored in the second partition.

[0075] In some embodiments, to avoid the problem of duplicate writing of data for applications related to both the AP and the MCU, as a possible structure, as shown in FIG3 , the memory may include, in addition to the first partition and the second partition exclusively used by the main processor and the coprocessor, a third partition (i.e., a shared partition) that can be shared by the main processor and the coprocessor. The third partition shown in FIG3 can not only store data from the main processor and support the main processor to read data stored in the third partition, but also store data from the coprocessor and support the coprocessor to read data stored in the third partition.

[0076] In some embodiments, the first partition shown in Figure 3 can be used to store data related to functions or applications related to the main processor (such as AP), the second partition shown in Figure 3 can be used to store data related to functions or applications related to the coprocessor (such as MCU), and the third partition shown in Figure 3 can be used to store data related to functions or applications related to both the main processor (such as AP) and the coprocessor (such as MCU).

[0077] As an example, please refer to Figure 4, which shows a schematic diagram of a storage area partitioning method for a memory provided in an embodiment of the present application, taking a smartwatch as an example, where the terminal device includes an AP and an MCU. As shown in Figure 4, a memory, such as an eMMC, can include a first partition exclusively for the AP, a second partition exclusively for the MCU, and a third partition shared by the AP and MCU.

[0078] The first partition shown in FIG. 4 (e.g., an AP-exclusive partition) can be used to store AP system data, application data of AP applications corresponding to one or more functions provided by the AP (hereinafter referred to as "AP application data"), and other data related to AP-related functions or applications. For example, the AP system data includes AP system-related instructions, such as AP system-related instructions stored in the first partition, allowing the AP to execute various AP system functions of the terminal device; and the AP application data includes AP application-related instructions, such as AP application-related instructions stored in the first partition, allowing the AP to execute AP application functions and related data processing of the terminal device.

[0079] As an example, as shown in FIG4 , the first partition may also include multiple sub-partitions, and different sub-partitions may be used to store different types of data, such as AP system data, AP application data, etc., respectively.

[0080] The second partition shown in FIG4 (such as the MCU exclusive partition) can be used to store sensor hub system data, application data, sensor module measurement data (such as motion, health data, etc.) and other data related to MCU functions or applications. For example, the sensor hub system data such as sensor hub system related instructions are stored, and the MCU can execute various sensor hub system functions of the terminal device by running the sensor hub system related instructions stored in the second partition; the sensor hub application data such as sensor hub application related instructions, the MCU can execute the MCU application functions of the terminal device and related data processing by running the sensor hub application related instructions stored in the second partition, and the related data processing such as calculating and processing the sensor module measurement data to obtain the user's heart rate, sleep status, pedometer status, sports health status, etc.; the sensor module measurement data such as the user's heart rate data, sleep data, pedometer data, sports health data, etc. measured by the sensor module.

[0081] As an example, as shown in FIG4 , the second partition may also include multiple sub-partitions, and different sub-partitions may be used to store different types of data, such as sensor hub system data and application data, sensor module measurement data, etc.

[0082] The third partition (eg, shared partition) shown in FIG4 can be used to store data related to functions or applications such as music and dials that are related to both the main processor (eg, AP) and the coprocessor (eg, MCU).

[0083] As an example, please refer to Figure 5, which shows a software structure diagram provided by an embodiment of the present application, taking the main processor as an AP and the coprocessor as an MCU as an example. As shown in Figure 5, the terminal device may include an AP system, an MCU system, and a memory (such as an eMMC). Among them, the AP system and the MCU system include an application layer, a framework layer (framework, FWK), and a kernel layer from top to bottom.

[0084] The application layer can include a range of applications. As shown in Figure 5, the application layer of the AP system can include applications such as music and watch faces, while the application layer of the MCU system can include applications such as heart rate, pedometer, sports health, music, sleep, and watch faces.

[0085] The framework layer provides application programming interfaces (APIs) and programming frameworks for applications in the application layer. As shown in Figure 5, the framework layer of the AP system provides frameworks such as the music framework and the watch face framework for upper-layer AP applications. The framework layer of the MCU system provides frameworks such as the heart rate framework, the step counting framework, the sports and health framework, the music framework, the sleep framework, and the watch face framework for upper-layer MCU applications.

[0086] The kernel layer is the layer between hardware and software. The kernel layer can include drivers for the hardware, such as the storage driver and one or more sensor drivers shown in Figure 5. The hardware shown in Figure 5 includes a memory device (such as eMMC) and one or more sensors.

[0087] The memory (e.g., eMMC) shown in FIG5 can be used to store AP-related data and MCU-related data. AP-related data includes AP system data, AP application data for implementing different functions, and MCU-related data includes sensor hub system data, sensor hub application data, sensor module-related data (e.g., sports and health data), and the embodiments of this application do not specifically limit this. The sensors shown in FIG5 may include, but are not limited to, one or more of the following: a speed sensor, a gyroscope sensor, a magnetic sensor, a gravity sensor, a bone conduction sensor, and the like. The sensors can be used to measure one or more of the following data: heart rate data, sleep data, pedometer data, sports and health data, and the like.

[0088] Of course, the embodiments of the present application do not limit the specific hardware included in the terminal device. For example, the terminal device may also include one or more hardware such as a camera, a display screen (touch screen), a camera, a microphone, etc. Correspondingly, the kernel layer of the AP system and the MCU system of the terminal device may also include one or more drivers such as a camera driver, a display driver, and a microphone driver.

[0089] In some embodiments, as shown in FIG5 , the kernel layer may also include a file system related to file storage. The file system is primarily responsible for managing and storing file information, such as organizing and managing files stored on the memory. For example, the file system can be used to store metadata about one or more data items in the memory, such as the inode number, file size, access permissions, creation time, modification time, and the data's location in the memory. Another example is that the file system can be used to store directory entries for one or more data items in the memory, such as the data's name, inode pointer, and hierarchical relationships with other directory entries.

[0090] In some embodiments, as shown in FIG5 , the kernel layer may further include a virtual file system (VFS), which serves as an interface between the file system and the upper-layer service framework. This VFS abstracts the details of the file system so that different file systems appear identical to the upper-layer system core and other processes running in the system. For example, the VFS may define a set of data structures and standard interfaces supported by all file systems.

[0091] It should be noted that Figure 5 is merely an example of a software structure diagram for a terminal device, which simply lists the layers and software modules relevant to the present application solution. In actual applications, the software system of a terminal device, such as an AP system or an MCU system, may also include other layers, and each layer may also include other software modules for implementing one or more functions or services. This embodiment of the present application does not specifically limit this.

[0092] In some embodiments, when a processor has a need to access the memory, such as when application A in the first processor has a need to access the memory as shown in FIG6 or FIG7 , application A can initiate a service request to the file system 1 of the first processor to access the memory. After receiving the service request from application A, the file system 1 can call the storage driver 1 to obtain the specific situation of other processors (such as the second processor) accessing the memory, such as whether other processors (such as the second processor) are accessing the memory. If no processor is accessing the memory, the first processor responds to the service request of application A and starts to access the memory; if other processors (such as the second processor) are accessing the memory, the first processor temporarily does not respond to the service request of application A and temporarily does not access the memory until no processor accesses the memory.

[0093] Similarly, when application B in the second processor shown in Figure 6 or Figure 7 has a need to access the memory, application B can initiate a service request to the file system 2 of the second processor to access the memory. After receiving the service request from application B, file system 2 can call storage driver 2 to obtain the specific situation of other processors (such as the first processor) accessing the memory, such as whether other processors (such as the first processor) are accessing the memory. If no processor is accessing the memory, the second processor responds to the service request of application B and starts accessing the memory; if other processors (such as the first processor) are accessing the memory, the second processor temporarily does not respond to the service request of application B and temporarily does not access the memory until no processor accesses the memory.

[0094] As a possible implementation manner, the storage driver of a processor may directly obtain from the storage drivers of other processors whether other processors are accessing the memory.

[0095] Exemplarily, as shown in FIG6 , the storage driver 1 of the first processor can directly obtain from the storage driver 2 of the second processor whether the second processor is accessing the memory. For example, the storage driver 1 of the first processor and the storage driver 2 of the second processor are respectively provided with pins, such as the storage driver 1 of the first processor is provided with a first pin, and the storage driver 2 of the second processor is provided with a second pin, and the first pin is connected to the second pin. Based on this, the first processor can obtain the state of the second pin by obtaining the state of the first pin, and then determine whether the second processor is accessing the memory. For example, assuming that the second processor is accessing the memory, the state of the second pin is usually the third level. When the state of the second pin is the third level, the state of the first pin of the first processor connected to the second pin is the first level; based on this, if the state of the first pin is the first level, the first processor can determine that the state of the second pin is the third level and thus determine that the second processor is accessing the memory. For another example, assuming that the second processor does not access the memory, the state of the second pin is usually the fourth level. When the state of the second pin is the fourth level, the state of the first pin of the first processor connected to the second pin is the second level. Based on this, if the state of the first pin is the second level, the first processor can determine that the state of the second pin is the fourth level and thus determine that the second processor does not access the memory.

[0096] Similarly, as shown in Figure 6, the storage driver 2 of the second processor can directly obtain from the storage driver 1 of the first processor whether the first processor is accessing the memory. For example, the storage driver 1 of the first processor is provided with a third pin, and the storage driver 2 of the second processor is provided with a fourth pin, and the third pin is connected to the fourth pin. Based on this, the second processor can obtain the state of the third pin by obtaining the state of the fourth pin, and then determine whether the first processor is accessing the memory. For example, assuming that the first processor is accessing the memory, the state of the third pin is usually the third level. When the state of the third pin is the third level, the state of the fourth pin of the second processor connected to the third pin is the first level; based on this, if the state of the fourth pin is the first level, the second processor can determine that the state of the third pin is the third level and thus determine that the first processor is accessing the memory. For another example, assuming that the first processor does not access the memory, the state of the third pin is usually the fourth level. When the state of the third pin is the fourth level, the state of the fourth pin of the second processor connected to the third pin is the second level. Based on this, if the state of the fourth pin is the second level, the second processor can determine that the state of the third pin is the fourth level and thus determine that the first processor does not access the memory.

[0097] As an example, the first level is a high level, and the second level is a low level; or, the first level is a low level, and the second level is a high level.

[0098] As an example, the third level is a high level, and the fourth level is a low level; or, the fourth level is a low level, and the third level is a high level.

[0099] As an example, the first pin, the second pin, the third pin or the fourth pin is a general purpose input / output (GPIO) pin; of course, the first pin, the second pin, the third pin and the fourth pin can also be other pins, and the embodiments of the present application do not make specific limitations.

[0100] As a possible implementation, as shown in FIG7 , the terminal device may include a status storage unit for storing status flags of each processor accessing the memory, such as storing status flags for identifying whether each processor is accessing the memory.

[0101] For example, when the first processor writes data to or reads data from the memory via the storage driver 1 in response to a service request from application A, a first flag may be stored in the state storage unit, and the first flag is used to identify that the first processor is accessing the memory. For example, the storage driver 1 of the first processor may write the first flag to the state storage unit when it starts accessing the memory and delete the first flag when it ends accessing the memory. Based on this, when the first processor accesses the memory and application B in the second processor has a need to access the memory, the second processor can determine that the first processor is accessing the memory based on the first flag obtained from the state storage unit.

[0102] Similarly, when the second processor writes data to or reads data from the memory through the storage driver 2 in response to the service request of application B, a second mark can be stored in the state storage unit, and the second mark is used to identify that the second processor is accessing the memory. For example, the storage driver 2 of the second processor can write the second mark to the state storage unit when it starts accessing the memory and delete the second mark when it ends accessing the memory. Based on this, when the second processor accesses the memory, when application A in the first processor has a need to access the memory, the first processor can determine that the second processor is accessing the memory based on the second mark obtained from the state storage unit.

[0103] The following embodiments use the method of a storage driver of a first processor directly obtaining information from another processor, such as a storage driver of a second processor, as an example to specifically introduce the method for accessing memory provided in the embodiments of the present application.

[0104] As an example, please refer to Figure 8. Figure 8 illustrates an architecture diagram of an interaction process for accessing memory provided by an embodiment of the present application, using a terminal device including an AP and an MCU, with eMMC as the memory. As shown in Figure 8, the AP can obtain the status of the MCU's pin B based on the status of pin A, thereby determining whether the MCU is accessing the eMMC. Furthermore, the MCU can obtain the status of the AP's pin A based on the status of pin B, thereby determining whether the AP is accessing the eMMC. For example, pin A or pin B can be a GPIO pin, etc., without specific limitation. When deciding to access the eMMC based on whether the MCU processor is accessing the eMMC, the AP can write data to, read data from, or modify data in the eMMC via input / output interface A. Furthermore, when deciding to access the eMMC based on whether the AP processor is accessing the eMMC, the MCU can write data to, read data from, or modify data in the eMMC via input / output interface B. For example, input / output interface A or input / output interface B can be an SDIO interface, etc., without specific limitation.

[0105] It should be noted that Figure 8 only uses pin A as an example, where it can be used by the AP to obtain information about whether the MCU is accessing the eMMC, and can also be used to indicate to other processors (such as the MCU) whether the AP is accessing the eMMC. However, this application does not limit whether the two are represented by the state of the same pin. For example, in some embodiments, the AP may include a first pin and a third pin, where the first pin is used by the AP to obtain information about whether the MCU is accessing the eMMC, and the third pin is used to indicate to other processors (such as the MCU) whether the AP is accessing the eMMC.

[0106] Similarly, the MCU can obtain information about whether the AP is accessing the eMMC through pin B, and indicate to other processors (such as the AP) whether the MCU is accessing the eMMC through pin B. Alternatively, in some embodiments, the MCU may include a second pin and a fourth pin, wherein the fourth pin is used for the MCU to obtain information about whether the AP is accessing the eMMC, and the second pin is used to indicate to other processors (such as the AP) whether the MCU is accessing the eMMC.

[0107] As an example, please refer to Figure 9, which shows a flow chart of a method for accessing a memory provided by an embodiment of the present application, using a first processor and a second processor in a terminal device sharing the same memory as an example. As shown in Figure 9, the method can be implemented based on S901-S903:

[0108] S901: A first processor receives a service request from an application, where the service request is used to request access to a memory.

[0109] The first processor may be any one of multiple processors of the terminal device, for example, the first processor may be a main processor or a coprocessor. Taking a terminal device including an AP and an MCU as an example, the first processor may be the AP or the MCU.

[0110] In some embodiments, the service request may be a request initiated by an application in the first processor. As an example, the application may include, but is not limited to, any one or more of the following applications: music, heart rate, pedometer, sports and health, music, sleep, watch face, etc. This embodiment of the application does not specifically limit this, and the specific application installed in the first processor, the specific functions of each application, and the specific usage scenario may be determined.

[0111] Taking the first processor as an AP as an example, applications that initiate service requests include music, watch faces, etc.; taking the first processor as an MCU as an example, applications that initiate service requests include heart rate, pedometer, sports health, music, sleep, watch faces, etc.

[0112] In some embodiments, the purpose of an application accessing a memory through a business request may include, but is not limited to, one or more of the following: reading data in the memory, writing data to the memory, and modifying data in the memory. This embodiment of the present application does not make specific limitations and may depend on the specific functions and specific usage scenarios of the application.

[0113] In some embodiments, the purpose of an application accessing memory through a business request may include but is not limited to accessing a partition corresponding to the first processor and not corresponding to the second processor (i.e., an exclusive partition of the first processor), and / or a partition corresponding to the first processor and the second processor (i.e., a shared partition of the first processor and the second processor).

[0114] The exclusive partition of the first processor is used to store data from the first processor and can support the first processor to read data stored in the exclusive partition of the first processor. The exclusive partition of the first processor cannot store data from other processors (such as the second processor) and cannot support other processors to read data stored in the exclusive partition of the first processor. The shared partition can not only store data from the first processor and support the first processor to read data stored in the shared partition, but also store data from other processors (such as the second processor) and support other processors to read data stored in the shared partition.

[0115] In some embodiments, the memory may further include an exclusive partition for the second processor, wherein the exclusive partition for the second processor is used to store data from the second processor and can support the second processor to read data stored in the exclusive partition for the second processor, but the exclusive partition for the second processor cannot store data from other processors (such as the first processor) and cannot support other processors to read data stored in the exclusive partition for the second processor.

[0116] S902: The first processor obtains information about memory access by the second processor.

[0117] In some embodiments, the first processor may obtain second information, where the second information is used to characterize a situation in which the second processor accesses the memory, such as whether the second processor is accessing the memory.

[0118] As a possible implementation, as shown in FIG9 , the first processor may obtain from the second processor the situation of the second processor accessing the memory, such as obtaining from the second processor second information indicating whether the second processor accesses the memory.

[0119] As an example, a first processor includes a first pin, and a second processor includes a second pin, and the first pin is connected to the second pin. The first processor can obtain second information by obtaining the state of the first pin, namely, whether the second processor is accessing a memory. The state of the first pin is used to indicate whether the second processor is accessing the memory. For example, the state of the first pin can be represented by a level, such as the state of the first pin includes a first level and a second level.

[0120] For example, if the state of the first pin is a first level, it is determined that the second processor is accessing the memory; if the state of the first pin is a second level, it is determined that the second processor is not accessing the memory. The first level may be a high level and the second level may be a low level; or the first level may be a low level and the second level may be a high level, without specific limitation.

[0121] It can be understood that, assuming the second processor is not accessing the memory, the second processor can set the state of the second pin to the fourth level. When the state of the second pin is the fourth level, the state of the first pin of the first processor connected to the second pin is the second level. Based on this, if the state of the first pin is the second level, the first processor can determine that the state of the second pin is the fourth level and thus determine that the second processor is not accessing the memory. Also, assuming the second processor is accessing the memory, the second processor can set the state of the second pin to the third level. When the state of the second pin is the third level, the state of the first pin of the first processor connected to the second pin is the first level. Based on this, if the state of the first pin is the first level, the first processor can determine that the state of the second pin is the third level and thus determine that the second processor is accessing the memory. The third level can be a high level, and the fourth level can be a low level; or the third level can be a low level and the fourth level can be a high level, without specific limitation.

[0122] As another possible implementation method, the first processor can directly obtain whether other processors are accessing the memory from the storage driver of other processors of the terminal device such as the second processor. The first processor can also obtain whether other processors are accessing the memory from other modules independent of the first processor and the second processor, such as a status storage unit.

[0123] As an example, as shown in Figure 9, the terminal device may include a status storage unit, which is used to store the status flag bits of each processor accessing the memory, such as storing the status flag bits used to identify whether each processor is accessing the memory. The first processor can obtain the situation of the second processor accessing the memory from the status storage unit, such as obtaining the second information representing whether the second processor is accessing the memory from the status storage unit.

[0124] For example, when the second processor writes data to or reads data from the memory in response to a service request of an application, a second flag may be stored in the status storage unit, wherein the second flag is used to identify that the second processor is accessing the memory; based on this, when the second processor accesses the memory, the first processor can obtain the status flag bit from the status storage unit and determine that the second processor is accessing the memory based on the status flag bit (such as the second flag). Alternatively, when the second processor accesses the memory, the second flag is not stored in the status storage unit to indicate that the second processor is not accessing the memory; based on this, the first processor can obtain the status flag bit from the status storage unit and determine that the second processor is not accessing the memory based on the status flag bit (such as not including the second flag).

[0125] The embodiment of the present application does not specifically limit the specific manner and specific process of the first processor obtaining the information of the second processor accessing the memory in S902.

[0126] Furthermore, the embodiments of the present application do not limit the specific form of the information used to characterize the second processor's access to the memory. For example, in some examples, the information used to characterize the second processor's access to the memory (such as the second information) may be in plain text, such as a direct indication; in other examples, the information used to characterize the second processor's access to the memory (such as the second information) may be in an implicit form, such as a parameter representation, such as a level indication, or a representation of a preset action (such as no reply), and the embodiments of the present application do not impose any specific limitations thereon.

[0127] In some embodiments, the execution result of S902 is that the second processor does not access the memory (eg, the second information indicates that the second processor does not access the memory). In this case, the first processor executes S903 shown in FIG. 9 .

[0128] S903: The first processor accesses the memory in response to the service request.

[0129] The specific operation of the first processor in response to the service request to access the memory is related to the purpose of the application accessing the memory through the service request. For example, assuming that the purpose of the application accessing the memory through the service request is to read the first data in the memory, the first processor reads the first data that the application wants to read from the memory in response to the service request. For another example, assuming that the purpose of the application accessing the memory through the service request is to write the second data to the memory, the first processor writes the second data that the application wants to write to the memory in response to the service request. For another example, assuming that the purpose of the application accessing the memory through the service request is to modify the third data in the memory, the first processor modifies the third data in the memory in response to the service request.

[0130] In some embodiments, the first processor can set the state of the third pin so that when the first processor accesses the memory, the state of the third pin is at the fifth level, wherein the state of the third pin at the fifth level is used to indicate that the first processor is accessing the memory. As a possible implementation method, the first processor can adjust the state of the third pin from the sixth level to the fifth level after determining that the second processor is not accessing the memory based on the execution result of S902 and before the first processor accesses the memory, wherein the state of the third pin at the sixth level is used to indicate that the first processor is not accessing the memory. Based on this, it is easy for other processors to know that the first processor is accessing the memory, thereby preventing conflicts caused by multiple processors accessing the memory at the same time and achieving more scientific and orderly memory sharing.

[0131] In some embodiments, after executing S903, i.e., after the first processor ends accessing the memory, the first processor may reset the state of the third pin so that the state of the third pin is at the sixth level when the first processor is not accessing the memory. This allows other processors to know that the first processor is not accessing the memory, thereby achieving more scientific and orderly memory sharing.

[0132] In some embodiments, the result of executing S902 is that the second processor is accessing the memory (e.g., the second information indicates that the second processor is accessing the memory). In this case, the first processor temporarily stops accessing the memory and obtains information about the second processor accessing the memory again after a period of time. When the second processor does not access the memory, S903 shown in FIG10 is executed. The first processor can obtain information about the second processor accessing the memory again through S1001 shown in FIG10:

[0133] S1001: The first processor obtains information about memory access by the second processor.

[0134] In some embodiments, the first processor may obtain first information, where the first information is used to characterize a situation in which the second processor accesses the memory, such as whether the second processor is accessing the memory.

[0135] As a possible implementation, as shown in FIG10 , the first processor may obtain from the second processor the situation of the second processor accessing the memory, such as obtaining from the second processor first information indicating whether the second processor accesses the memory.

[0136] As an example, the first processor can obtain the second information by obtaining the state of the first pin, namely, whether the second processor is accessing the memory. For example, if the state of the first pin is at the second level, the first processor can determine that the second processor is not accessing the memory; if the state of the first pin is at the first level, the first processor can determine that the second processor is accessing the memory. The first level can be a high level, and the second level can be a low level; or the first level can be a low level, and the second level can be a high level, without specific limitation.

[0137] As another possible implementation, as shown in FIG10 , the terminal device may include a status storage unit, which is used to store status flags of each processor accessing the memory, such as storing status flags for identifying whether each processor is accessing the memory. The first processor may obtain the situation of the second processor accessing the memory from the status storage unit, such as obtaining first information representing whether the second processor is accessing the memory from the status storage unit.

[0138] For example, if the status flag includes the second identifier, the first processor may determine that the second processor is accessing the memory; if the status flag does not include the second identifier, the first processor may determine that the second processor is not accessing the memory.

[0139] It should be noted that the embodiments of the present application do not limit the specific form of the information used to characterize the second processor's access to the memory. For example, in some examples, the information used to characterize the second processor's access to the memory (such as the first information) may be in plain text, such as a direct indication; in other examples, the information used to characterize the second processor's access to the memory (such as the first information) may be in an implicit form, such as a parameter representation such as a level indication, or a representation of a preset action (such as no reply), and the embodiments of the present application do not impose any specific limitations thereon.

[0140] As a possible implementation, if the result of executing S902 is that the second processor is accessing the memory (e.g., the second information indicates that the second processor is accessing the memory), the first processor may temporarily stop accessing the memory and periodically obtain the first information according to a certain period T (e.g., every 100 milliseconds), such as obtaining the first information from the second processor or the state storage unit. Based on this, when the second processor ends accessing the memory, the first processor can determine based on the obtained first information that the second processor is not accessing the memory and then execute S903; alternatively, when the second processor has not ended accessing the memory, the first processor determines based on the obtained first information that the second processor is accessing the memory and then continues to periodically obtain the first information from the second processor according to the period T.

[0141] As another possible implementation, if the execution result of S902 is that the second processor is accessing the memory (such as the second information indicates that the second processor is accessing the memory), the first processor can instruct the second processor to notify the first processor after completing the access to the memory. For example, the first processor can enable an interrupt monitoring function, wherein after the interrupt monitoring function is enabled, the second processor actively notifies the first processor after completing the access to the memory. It can be understood that compared to the implementation method in which the first processor periodically obtains the first information, this implementation method can avoid the waste of power consumption and processing resources caused by the first processor continuously obtaining the first information on the terminal device.

[0142] As another possible implementation, if the execution result of S902 is that the second processor is accessing the memory (such as the second information indicates that the second processor is accessing the memory), the first processor can wait for a period of time, such as waiting for a preset time (such as 5 milliseconds) before obtaining the first information, such as obtaining the first information from the second processor or the state storage unit. Based on this, when the second processor ends accessing the memory, the first processor can determine based on the obtained first information that the second processor has not accessed the memory, and then execute S903; or, when the second processor has not ended accessing the memory, the first processor determines based on the obtained first information that the second processor is accessing the memory and then continues to obtain the first information from the second processor periodically according to period T. It can be understood that compared to the implementation method in which the first processor periodically obtains the first information, this implementation method can avoid the waste of power consumption and processing resources caused to the terminal device by the first processor constantly obtaining the first information.

[0143] The embodiment of the present application does not specifically limit the specific manner and specific process of the first processor obtaining the information of the second processor accessing the memory in S1001.

[0144] It should be noted that Figures 9 and 10 only take the terminal device including the first processor and the second processor as an example, and the embodiments of the present application do not limit the number of processors sharing the same memory in the terminal device. For example, in some embodiments, the terminal device includes a third processor that is different from the first processor and the second processor. In this case, in addition to obtaining the information about the second processor accessing the memory, the first processor also obtains the information about the third processor accessing the memory. Furthermore, when the second processor, the third processor and other processors do not access the memory, the first processor executes S903 shown in Figure 9. When a processor among other processors is accessing the memory, the first processor temporarily does not access the memory until it is determined based on the execution result of S1001 shown in Figure 10 that the second processor, the third processor and other processors do not access the memory, and then executes S903 shown in Figure 10.

[0145] As an example, please refer to Figure 11, which takes the first processor accessing the memory as an example to illustrate a process flow chart of accessing the memory provided by an embodiment of the present application. As shown in Figure 11, the process of accessing the memory may include S1101-S1108:

[0146] S1101: A first processor receives a service request for accessing a memory.

[0147] The first processor may be any one of multiple processors of the terminal device, for example, the first processor may be a main processor or a coprocessor. Taking a terminal device including an AP and an MCU as an example, the first processor may be the AP or the MCU.

[0148] In some embodiments, the service request may be a request initiated by an application in the first processor, such as including but not limited to any one or more of the following applications: music, heart rate, pedometer, sports health, music, sleep, watch face, etc.

[0149] In some embodiments, the purpose of the service requester may include, but is not limited to, one or more of the following: reading data from a memory, writing data to a memory, and modifying data from a memory. This embodiment of the present application does not specifically limit this. For example, the purpose of the service requester may include, but is not limited to, one or more of the following: reading data from an exclusive partition of a first processor in memory, reading data from a shared partition of memory, writing data to an exclusive partition of a first processor in memory, writing data to a shared partition of memory, modifying data from an exclusive partition of a first processor in memory, and modifying data from a shared partition of memory.

[0150] S1102: The first processor triggers a file operation.

[0151] As an example, the first processor triggers a file operation to trigger a specific access operation, such as writing, reading, etc.

[0152] As an example, if the purpose of the business request is to read, the first processor can trigger a read operation, such as the first processor can call a read instruction; if the purpose of the business request is to write, the first processor can trigger a read and write operation, such as the first processor can call a write instruction.

[0153] S1103: The first processor calls a storage driver.

[0154] As an example, the first processor calls a storage driver to obtain information about memory access by another processor (such as the second processor).

[0155] In some embodiments, a storage driver of a first processor includes a first pin, and the state of the first pin is used to indicate whether a memory (e.g., a second processor) to which a second pin connected to the first pin belongs is accessing the memory. Based on this, the first processor can call the storage driver to obtain the state of the first pin, and thereby determine whether another processor (e.g., the second processor) is accessing the memory based on the state of the first pin.

[0156] As an example, the first pin or the second pin is a GPIO pin; of course, the first pin or the second pin can also be other pins, which is not specifically limited in the embodiments of the present application.

[0157] Of course, the embodiments of the present application do not limit the specific manner in which the first processor calls the storage driver to obtain information about the memory access status of the other processor (e.g., the second processor). For example, in some embodiments, the first processor calls the storage driver to obtain a status flag bit from the status storage unit that indicates whether the other processor (e.g., the second processor) is accessing the memory, thereby obtaining information about whether the other processor (e.g., the second processor) is accessing the memory based on the status flag bit.

[0158] The example shown in FIG11 of the present application only takes the method in which the first processor calls the storage driver to obtain the state of the first pin, and obtains whether other processors are accessing the memory according to the state of the first pin as an example.

[0159] S1104: The first processor determines whether the state of the first pin is at the second level.

[0160] As an example, if the state of the first pin is the first level, the first processor can determine that the state of the second pin is the third level and thus determine that the second processor is accessing the memory; or, if the state of the first pin is the second level, the first processor can determine that the state of the second pin is the fourth level and thus determine that the second processor is not accessing the memory.

[0161] As an example, the first level is a high level, and the second level is a low level; or, the first level is a low level, and the second level is a high level.

[0162] As an example, the third level is a high level, and the fourth level is a low level; or, the fourth level is a low level, and the third level is a high level.

[0163] In some examples, at S1104, the first processor determines that the state of the first pin is the second level, and further determines that the second processor is not accessing the memory. In this case, the first processor can access the memory normally. In order to facilitate other processors (such as the second processor) to know that the first processor is accessing the memory during the process of the first processor accessing the memory, the first processor can notify other processors (such as the second processor) of its access to the memory by setting the pin state. For example, when the first processor determines that the state of the first pin is the second level at S1104, the first processor executes the following S1105-S1108:

[0164] S1105: The first processor sets the state of the third pin to the fifth level.

[0165] In some embodiments, the storage driver of the first processor includes a third pin, and the state of the third pin is used to indicate the first processor's access to the memory, such as whether the first processor is currently accessing the memory. Based on this, the first processor can set the state of the third pin to indicate that the first processor is currently accessing the memory before accessing the memory.

[0166] As an example, the state of the third pin at the sixth level indicates that the first processor is not accessing the memory, while the state of the third pin at the fifth level indicates that the first processor is accessing the memory. Based on this, after determining that the second processor is not accessing the memory and before the first processor accesses the memory, the first processor can adjust the state of the third pin from the sixth level to the fifth level to facilitate other processors to know that the first processor is accessing the memory, thereby preventing conflicts caused by multiple processors accessing the memory simultaneously and achieving more scientific and orderly memory sharing.

[0167] S1106: The first processor determines whether the state of the first pin is at the second level.

[0168] In some embodiments, in order to avoid a conflict caused by the first processor and the second processor accessing the memory at the same time after the first processor determines that the state of the first pin is the second level based on S1104 and further determines that the second processor does not access the memory, the first processor can again determine whether the state of the first pin is the second level to reconfirm that the second processor does not access the memory.

[0169] S1107: The first processor accesses the memory.

[0170] The specific operation of the first processor in response to the service request to access the memory is related to the purpose of the application accessing the memory through the service request. For example, assuming that the purpose of the application accessing the memory through the service request is to read the first data in the memory, the first processor reads the first data that the application wants to read from the memory in response to the service request. For another example, assuming that the purpose of the application accessing the memory through the service request is to write the second data to the memory, the first processor writes the second data that the application wants to write to the memory in response to the service request. For another example, assuming that the purpose of the application accessing the memory through the service request is to modify the third data in the memory, the first processor modifies the third data in the memory in response to the service request.

[0171] S1108: The first processor sets the state of the third pin to a sixth level.

[0172] Among them, the state of the third pin is the sixth level, which is used to indicate that the first processor has not accessed the memory. Based on this, other processors can know that the first processor has not accessed the memory, so that other processors can access the memory in time when they need to access the memory, thereby realizing more scientific and orderly memory sharing.

[0173] It should be noted that the above embodiment only uses the example of the first processor determining, based on S1104, that the state of the first pin is the second level, and then determining that the second processor has not accessed the memory. In other examples, as shown in FIG11 , if the first processor determines, based on S1104, that the state of the first pin is not the second level, but is the first level, the first processor may perform subsequent processing in any of the following three ways (way 1 to way 3):

[0174] Mode 1: re-execute S1104 and execute S1105 to S1108 when the state of the first pin is at the second level.

[0175] For example, the first processor may periodically execute S1104 according to a certain period T (eg, every 100 milliseconds) until it is determined that the state of the first pin is at the second level and then executes S1105 to S1108.

[0176] Based on this, the first processor may temporarily not access the memory, and access the memory again when ensuring that other second processors do not access the memory by re-executing S1104, so as to prevent conflicts caused by multiple processors accessing the memory at the same time and realize more scientific and orderly memory sharing.

[0177] Method 2: Execute S1109-S1110 and then re-execute S1104-S1108.

[0178] Among them, S1109-S1110 are as follows:

[0179] S1109: The first processor starts an interrupt monitoring function.

[0180] After the interrupt monitoring function is enabled, the second processor will proactively notify the first processor after terminating access to the memory. For example, after terminating access to the memory, the second processor can notify the first processor that the second processor has terminated access to the memory by adjusting the state of the second pin to the fourth level. Alternatively, after terminating access to the memory, the second processor can notify the first processor that the second processor has terminated access to the memory by sending a reminder or other means. The embodiments of the present application do not limit the specific method.

[0181] S1110: The interrupt detection function prompts that the state of the first pin is the second level.

[0182] Based on this, the first processor can temporarily not access the memory, and access the memory only when it is ensured that other second processors have not accessed the memory by starting the interrupt monitoring function. While responding to business requests to access the memory in a timely manner, it prevents conflicts caused by multiple processors accessing the memory at the same time, and realizes more scientific and orderly memory sharing.

[0183] Furthermore, compared with the method 1, the method 2 can avoid the waste of power consumption and processing resources of the terminal device caused by the first processor constantly obtaining access to the memory by the second processor.

[0184] Method 3: Execute S1111-S1112 and then re-execute S1104-S1108.

[0185] Among them, S1111-S1112 are as follows:

[0186] S1111: The first processor starts the waiting time.

[0187] Exemplarily, the waiting time is such as waiting for a preset time period, such as waiting for 5 milliseconds.

[0188] S1112: Waiting exceeds the preset time.

[0189] Based on this, the first processor can temporarily not access the memory, and access the memory only when it is sure that other second processors have not accessed the memory by waiting for more than a preset time and then judging again, so as to prevent conflicts caused by multiple processors accessing the memory at the same time and realize more scientific and orderly memory sharing.

[0190] Furthermore, compared with method 1, method 3 can avoid the waste of power consumption and processing resources of the terminal device caused by the first processor constantly obtaining access to the memory by the second processor.

[0191] Furthermore, it should be noted that the above embodiment uses only the example of the first processor determining, based on S1106, that the state of the first pin is the second level, and thereby determining that the second processor has not accessed the memory. In other examples, as shown in FIG11 , if the first processor determines, based on S1106, that the state of the first pin is not the second level, but is the first level, the first processor may also perform subsequent processing using any of the above-described methods 1 to 3, which will not be repeated here.

[0192] It can be understood that based on the method for accessing the memory provided by the present application, such as the method for accessing the memory shown in Figures 9 and 10, multiple processors of the terminal device (such as the first processor and the second processor) can ensure that in any usage scenario, any processor can normally store data, modify or read stored data, etc. by sharing the same memory. For example, compared with the architecture in which the MCU uses the memory configured for the AP to store MCU-related data, even if the AP and the memory configured for the AP are powered off in low-power mode, the storage of MCU-related data and the normal reading, modification, deletion, etc. of stored data can be carried out normally. In addition, any processor among the multiple processors (such as the first processor) can realize mutually exclusive access to the memory by multiple processors based on the acquired access conditions of other processors to the memory, such as whether other processors are accessing the memory, thereby realizing more scientific and orderly memory sharing.

[0193] Furthermore, the solution provided in the present application in which multiple processors of a terminal device (such as a first processor and a second processor) share the same memory can also reduce the production cost of the terminal device and provide support for the miniaturization of the terminal device.

[0194] Furthermore, because multiple processors in a terminal device (e.g., the first and second processors) share the same memory, when one processor writes data (e.g., data for Music A) to the memory, the other processors know that the data has been written to the memory. Consequently, when other processors receive a request to write the same data to the memory, they no longer need to write the same data repeatedly, but instead report a successful write to the application. This prevents data from being written repeatedly to applications that are shared by multiple processors (e.g., the AP and MCU).

[0195] The embodiments of the present application do not limit the specific processor mode adopted when the first processor determines based on S1104 that the state of the first pin is not the second level. The first processor can adopt any of the above-mentioned modes 1 to 3 for subsequent processing; and the embodiments of the present application do not limit the specific processor mode adopted when the first processor determines based on S1106 that the state of the first pin is not the second level. The first processor can adopt any of the above-mentioned modes 1 to 3 for subsequent processing, depending on the specific device capabilities, power consumption requirements, business needs, usage scenarios, etc.

[0196] Furthermore, it should be noted that the above embodiments only take the first processor executing S1106 after executing S1105, and then executing S1107-S1108 based on the execution result of S1106, or executing S1109-S1110 based on the execution result of S1106 and then executing S1107-S1108, or executing S1111-S1112 based on the execution result of S1106 and then executing S1107-S1108 as examples. This application does not limit whether the first processor executes S1106 after executing S1105. In other words, S1106 is not a required step. For example, in some embodiments, after executing S1105, the first processor may also directly execute S1107-S1108.

[0197] It should be understood that the various schemes of the embodiments of the present application can be reasonably combined and used, and the explanations or descriptions of the various terms appearing in the embodiments can be referenced or explained with each other in the various embodiments, without limitation to this.

[0198] It should also be understood that in the various embodiments of the present application, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0199] It is understandable that, in order to implement the functions of any of the above-mentioned embodiments, the terminal equipment and the like include hardware structures and / or software modules corresponding to the execution of each function. Those skilled in the art should easily realize that, in combination with the units and algorithm steps of each example described in the embodiments disclosed herein, the present application can be implemented in the form of hardware or a combination of hardware and computer software. Whether a function is executed in the form of hardware or computer software driving hardware depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0200] The embodiments of the present application can divide the terminal equipment, etc. into functional modules. For example, each functional module can be divided according to each function, or two or more functions can be integrated into one processing module. The above-mentioned integrated modules can be implemented in the form of hardware or in the form of software functional modules. It should be noted that the division of modules in the embodiments of the present application is schematic and is only a logical function division. There may be other division methods in actual implementation. It should also be understood that each module in the terminal equipment, etc. can be implemented in the form of software and / or hardware, and there is no specific limitation on this. In other words, the terminal equipment, etc. is presented in the form of functional modules. The "module" here can refer to a specific application integrated circuit ASIC, a circuit, a processor and memory that executes one or more software or firmware programs, an integrated logic circuit, and / or other devices that can provide the above-mentioned functions.

[0201] In an optional manner, when data transmission is implemented using software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the process or function described in the embodiment of the present application is implemented in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from one website, computer, server or data center to another website, computer, server or data center via a wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) method. The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server or data center that includes one or more available media. The available medium can be a magnetic medium (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a digital video disk (DVD)), or a semiconductor medium (e.g., a solid state disk (SSD)).

[0202] The steps of the method or algorithm described in conjunction with the embodiments of the present application can be implemented in hardware or by executing software instructions by a processor. The software instructions can be composed of corresponding software modules, which can be stored in random access memory (RAM), flash memory, read-only memory (ROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM) memory, registers, hard disks, mobile hard disks, compact disc read-only memory (CD-ROM) or any other form of storage medium known in the art. An exemplary storage medium is coupled to a processor so that the processor can read information from the storage medium and write information to the storage medium. Of course, the storage medium can also be an integral part of the processor. The processor and the storage medium can be located in an application specific integrated circuit (ASIC). In addition, the ASIC can be located in a terminal device. Of course, the processor and the storage medium can also exist as discrete components.

[0203] Through the description of the above implementation methods, technical personnel in the relevant field can clearly understand that for the convenience and simplicity of description, only the division of the above-mentioned functional modules is used as an example. In actual applications, the above-mentioned functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above.

Claims

1. A method for accessing a memory, characterized in that, The method is applied to a first processor in a terminal device. The terminal device further includes a second processor and a memory, and the first processor and the second processor share the memory. The method includes: Receiving a service request of an application, where the service request is used to request access to the memory; Obtaining first information from the second processor, where the first information is used to represent whether the second processor is accessing the memory; When the first information represents that the second processor is not accessing the memory, accessing the memory in response to the service request.

2. The method according to claim 1, characterized in that, The first processor includes a first pin, and the first pin is connected to a second pin of the second processor. The obtaining first information from the second processor includes: Obtaining the state of the first pin, where the state of the first pin is used to represent whether the second processor is accessing the memory.

3. The method according to claim 2, characterized in that, The state of the first pin includes a first level and a second level. The method further includes: If the state of the first pin is the first level, determining that the second processor is accessing the memory; If the state of the first pin is the second level, determining that the second processor is not accessing the memory.

4. The method according to claim 3, wherein When the state of the second pin is a third level, the state of the first pin is the first level; When the state of the second pin is a fourth level, the state of the first pin is the second level.

5. The method according to any one of claims 1-4, characterized in that, The first processor further includes a third pin, and the state of the third pin represents whether the first processor is accessing the memory.

6. The method according to claim 5, wherein When the first processor accesses the memory, the state of the third pin is a fifth level; when the first processor does not access the memory, the state of the third pin is a sixth level.

7. The method according to claim 6, wherein The method further includes: Before the first processor accesses the memory, adjusting the state of the third pin from the sixth level to the fifth level.

8. The method according to claim 7, wherein The adjusting the state of the third pin from the sixth level to the fifth level includes: After receiving the service request, obtaining second information from the second processor, where the second information is used to represent whether the second processor accesses the memory; When the second information represents that the second processor is not accessing the memory, adjusting the state of the third pin from the sixth level to the fifth level.

9. The method according to claim 8, wherein The obtaining first information from the second processor includes: When the second information represents that the second processor is accessing the memory, waiting for a preset duration and then obtaining the first information from the second processor.

10. The method according to any one of claims 1-9, characterized in that, The service request is used to request access to one or more of the following partitions in the memory: a partition corresponding to the first processor and not corresponding to the second processor, a partition corresponding to both the first processor and the second processor.

11. The method according to claim 10, characterized in that, The memory further includes a partition corresponding to the second processor and not corresponding to the first processor.

12. The method according to any one of claims 1-11, wherein the first processor accesses the memory for performing one or more of the following: reading data from the memory, writing data to the memory, and modifying data in the memory.

13. The method according to any one of claims 1-12, wherein the first processor is an application processor AP, and the second processor is a microprogram controller MCU; or the first processor is an MCU, and the second processor is an AP; wherein, the memory is an embedded multimedia card eMMC.

14. A chip, characterized in that, The chip includes: a processing module and one or more pins, and the processing module and the one or more pins are used to support the chip to implement the method according to any one of claims 1-13.

15. A terminal device, characterized in that, The terminal device includes: a first processor, a second processor, and a memory, the first processor and the second processor share the memory, and the first processor or the second processor is used to implement the method according to any one of claims 1-13.

16. A computer-readable storage medium, characterized in that, Computer program instructions are stored on the computer-readable storage medium, and when the computer program instructions are executed by a processing circuit, the method according to any one of claims 1-13 is implemented.

17. A computer program product comprising instructions, characterized in that, When the computer program product runs on a computer, the computer is caused to execute the method according to any one of claims 1-13.

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